diff options
Diffstat (limited to 'tests/long')
98 files changed, 8443 insertions, 3849 deletions
diff --git a/tests/long/00.gzip/ref/arm/linux/o3-timing/config.ini b/tests/long/00.gzip/ref/arm/linux/o3-timing/config.ini index 4ad2150c8..361881dae 100644 --- a/tests/long/00.gzip/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/00.gzip/ref/arm/linux/o3-timing/config.ini @@ -25,6 +25,8 @@ BTBEntries=4096 BTBTagSize=16 LFSTSize=1024 LQEntries=32 +LSQCheckLoads=true +LSQDepCheckShift=4 RASSize=16 SQEntries=32 SSITSize=1024 @@ -491,12 +493,12 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=gzip input.log 1 -cwd=build/ARM_SE/tests/fast/long/00.gzip/arm/linux/o3-timing +cwd=build/ARM_SE/tests/opt/long/00.gzip/arm/linux/o3-timing egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/arm/linux/gzip +executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/gzip gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/00.gzip/ref/arm/linux/o3-timing/simout b/tests/long/00.gzip/ref/arm/linux/o3-timing/simout index 0f161f8aa..0ab77604f 100755 --- a/tests/long/00.gzip/ref/arm/linux/o3-timing/simout +++ b/tests/long/00.gzip/ref/arm/linux/o3-timing/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Mar 18 2011 20:12:03 -M5 started Mar 18 2011 21:36:19 -M5 executing on zizzer -command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/00.gzip/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/fast/long/00.gzip/arm/linux/o3-timing +M5 compiled Mar 30 2011 17:47:57 +M5 started Mar 30 2011 17:54:33 +M5 executing on u200439-lin.austin.arm.com +command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/00.gzip/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/opt/long/00.gzip/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... spec_init @@ -42,4 +42,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 196536810500 because target called exit() +Exiting @ tick 196513140500 because target called exit() diff --git a/tests/long/00.gzip/ref/arm/linux/o3-timing/stats.txt b/tests/long/00.gzip/ref/arm/linux/o3-timing/stats.txt index 69e8f3745..838d97db1 100644 --- a/tests/long/00.gzip/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/00.gzip/ref/arm/linux/o3-timing/stats.txt @@ -1,142 +1,142 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 157384 # Simulator instruction rate (inst/s) -host_mem_usage 221236 # Number of bytes of host memory used -host_seconds 3827.32 # Real time elapsed on the host -host_tick_rate 51350965 # Simulator tick rate (ticks/s) +host_inst_rate 79580 # Simulator instruction rate (inst/s) +host_mem_usage 255900 # Number of bytes of host memory used +host_seconds 7569.27 # Real time elapsed on the host +host_tick_rate 25961971 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 602359870 # Number of instructions simulated -sim_seconds 0.196537 # Number of seconds simulated -sim_ticks 196536810500 # Number of ticks simulated +sim_insts 602359865 # Number of instructions simulated +sim_seconds 0.196513 # Number of seconds simulated +sim_ticks 196513140500 # Number of ticks simulated system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.BTBHits 75961485 # Number of BTB hits -system.cpu.BPredUnit.BTBLookups 82107435 # Number of BTB lookups -system.cpu.BPredUnit.RASInCorrect 1596 # Number of incorrect RAS predictions. -system.cpu.BPredUnit.condIncorrect 3833895 # Number of conditional branches incorrect -system.cpu.BPredUnit.condPredicted 81873360 # Number of conditional branches predicted -system.cpu.BPredUnit.lookups 88392158 # Number of BP lookups -system.cpu.BPredUnit.usedRAS 1389747 # Number of times the RAS was used to get a target. -system.cpu.commit.COM:branches 70826856 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 7927801 # number cycles where commit BW limit reached +system.cpu.BPredUnit.BTBHits 75744427 # Number of BTB hits +system.cpu.BPredUnit.BTBLookups 81879675 # Number of BTB lookups +system.cpu.BPredUnit.RASInCorrect 1640 # Number of incorrect RAS predictions. +system.cpu.BPredUnit.condIncorrect 3832102 # Number of conditional branches incorrect +system.cpu.BPredUnit.condPredicted 81880205 # Number of conditional branches predicted +system.cpu.BPredUnit.lookups 88398894 # Number of BP lookups +system.cpu.BPredUnit.usedRAS 1393010 # Number of times the RAS was used to get a target. +system.cpu.commit.COM:branches 70828614 # Number of branches committed +system.cpu.commit.COM:bw_lim_events 7897771 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle::samples 379302454 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::mean 1.588073 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::stdev 1.904864 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::samples 379244728 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::mean 1.588315 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::stdev 1.904338 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::0 123535993 32.57% 32.57% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::1 123034003 32.44% 65.01% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::2 59238565 15.62% 80.62% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::3 18407109 4.85% 85.48% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::4 17194886 4.53% 90.01% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::5 14352047 3.78% 93.79% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::6 7619076 2.01% 95.80% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::7 7992974 2.11% 97.91% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::8 7927801 2.09% 100.00% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::0 123478650 32.56% 32.56% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::1 123013107 32.44% 65.00% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::2 59170888 15.60% 80.60% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::3 18488020 4.87% 85.47% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::4 17225820 4.54% 90.01% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::5 14373715 3.79% 93.80% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::6 7590349 2.00% 95.81% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::7 8006408 2.11% 97.92% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::8 7897771 2.08% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::total 379302454 # Number of insts commited each cycle -system.cpu.commit.COM:count 602359921 # Number of instructions committed +system.cpu.commit.COM:committed_per_cycle::total 379244728 # Number of insts commited each cycle +system.cpu.commit.COM:count 602359916 # Number of instructions committed system.cpu.commit.COM:fp_insts 16 # Number of committed floating point instructions. system.cpu.commit.COM:function_calls 997573 # Number of function calls committed. -system.cpu.commit.COM:int_insts 533522695 # Number of committed integer instructions. -system.cpu.commit.COM:loads 148952608 # Number of loads committed +system.cpu.commit.COM:int_insts 533522691 # Number of committed integer instructions. +system.cpu.commit.COM:loads 148952607 # Number of loads committed system.cpu.commit.COM:membars 1328 # Number of memory barriers committed -system.cpu.commit.COM:refs 219173635 # Number of memory references committed +system.cpu.commit.COM:refs 219173633 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 3894768 # The number of times a branch was mispredicted -system.cpu.commit.commitCommittedInsts 602359921 # The number of committed instructions -system.cpu.commit.commitNonSpecStalls 6311 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 86755718 # The number of squashed insts skipped by commit -system.cpu.committedInsts 602359870 # Number of Instructions Simulated -system.cpu.committedInsts_total 602359870 # Number of Instructions Simulated -system.cpu.cpi 0.652556 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.652556 # CPI: Total CPI of All Threads -system.cpu.dcache.LoadLockedReq_accesses 1359 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_avg_miss_latency 10642.857143 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_hits 1345 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_miss_latency 149000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_rate 0.010302 # miss rate for LoadLockedReq accesses +system.cpu.commit.branchMispredicts 3891220 # The number of times a branch was mispredicted +system.cpu.commit.commitCommittedInsts 602359916 # The number of committed instructions +system.cpu.commit.commitNonSpecStalls 6310 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.commitSquashedInsts 86859726 # The number of squashed insts skipped by commit +system.cpu.committedInsts 602359865 # Number of Instructions Simulated +system.cpu.committedInsts_total 602359865 # Number of Instructions Simulated +system.cpu.cpi 0.652478 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.652478 # CPI: Total CPI of All Threads +system.cpu.dcache.LoadLockedReq_accesses 1356 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_avg_miss_latency 10607.142857 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_hits 1342 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_miss_latency 148500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_rate 0.010324 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_misses 14 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_mshr_hits 14 # number of LoadLockedReq MSHR hits -system.cpu.dcache.ReadReq_accesses 139417902 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 13041.209813 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7899.689585 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 139176030 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 3154303500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.001735 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 241872 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 46005 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 1547288500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.001405 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 195867 # number of ReadReq MSHR misses -system.cpu.dcache.StoreCondReq_accesses 1341 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_hits 1341 # number of StoreCondReq hits +system.cpu.dcache.ReadReq_accesses 139395234 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 13041.881358 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7904.223289 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 139153026 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 3158848000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.001738 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 242208 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 46247 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 1548919500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.001406 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 195961 # number of ReadReq MSHR misses +system.cpu.dcache.StoreCondReq_accesses 1340 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_hits 1340 # number of StoreCondReq hits system.cpu.dcache.WriteReq_accesses 69417531 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 17903.398328 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 10349.195917 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 67926226 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 26699427444 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.021483 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 1491305 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 1243450 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 2565099954 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.003570 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 247855 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles::no_mshrs 4339.606397 # average number of cycles each access was blocked +system.cpu.dcache.WriteReq_avg_miss_latency 17910.212192 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 10351.034278 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 67926304 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 26708191996 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.021482 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 1491227 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 1243368 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 2565597005 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.003571 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 247859 # number of WriteReq MSHR misses +system.cpu.dcache.avg_blocked_cycles::no_mshrs 4376.771337 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 466.744813 # Average number of references to valid blocks. -system.cpu.dcache.blocked::no_mshrs 2251 # number of cycles access was blocked +system.cpu.dcache.avg_refs 466.592209 # Average number of references to valid blocks. +system.cpu.dcache.blocked::no_mshrs 2191 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_mshrs 9768454 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_mshrs 9589506 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 208835433 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 17224.859864 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 9267.939056 # average overall mshr miss latency -system.cpu.dcache.demand_hits 207102256 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 29853730944 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.008299 # miss rate for demand accesses -system.cpu.dcache.demand_misses 1733177 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 1289455 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 4112388454 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_accesses 208812765 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 17229.974009 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 9270.687452 # average overall mshr miss latency +system.cpu.dcache.demand_hits 207079330 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 29867039996 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.008301 # miss rate for demand accesses +system.cpu.dcache.demand_misses 1733435 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 1289615 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 4114516505 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.002125 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 443722 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses 443820 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.999720 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 4094.852027 # Average occupied blocks per context -system.cpu.dcache.overall_accesses 208835433 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 17224.859864 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 9267.939056 # average overall mshr miss latency +system.cpu.dcache.occ_%::0 0.999719 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 4094.849519 # Average occupied blocks per context +system.cpu.dcache.overall_accesses 208812765 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 17229.974009 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 9270.687452 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 207102256 # number of overall hits -system.cpu.dcache.overall_miss_latency 29853730944 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.008299 # miss rate for overall accesses -system.cpu.dcache.overall_misses 1733177 # number of overall misses -system.cpu.dcache.overall_mshr_hits 1289455 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 4112388454 # number of overall MSHR miss cycles +system.cpu.dcache.overall_hits 207079330 # number of overall hits +system.cpu.dcache.overall_miss_latency 29867039996 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.008301 # miss rate for overall accesses +system.cpu.dcache.overall_misses 1733435 # number of overall misses +system.cpu.dcache.overall_mshr_hits 1289615 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 4114516505 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.002125 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 443722 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses 443820 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.replacements 439626 # number of replacements -system.cpu.dcache.sampled_refs 443722 # Sample count of references to valid blocks. +system.cpu.dcache.replacements 439722 # number of replacements +system.cpu.dcache.sampled_refs 443818 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4094.852027 # Cycle average of tags in use -system.cpu.dcache.total_refs 207104942 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 89209000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 394231 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 63976815 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 1279 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 5983185 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 722294449 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 163843845 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 138493802 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 12857426 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 4707 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 12987991 # Number of cycles decode is unblocking +system.cpu.dcache.tagsinuse 4094.849519 # Cycle average of tags in use +system.cpu.dcache.total_refs 207082021 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 89315000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 394264 # number of writebacks +system.cpu.decode.DECODE:BlockedCycles 64227537 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BranchMispred 1274 # Number of times decode detected a branch misprediction +system.cpu.decode.DECODE:BranchResolved 5983982 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 722350979 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 163737957 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 138388023 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 12871984 # Number of cycles decode is squashing +system.cpu.decode.DECODE:SquashedInsts 4747 # Number of squashed instructions handled by decode +system.cpu.decode.DECODE:UnblockCycles 12891210 # Number of cycles decode is unblocking system.cpu.dtb.accesses 0 # DTB accesses system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions @@ -158,140 +158,140 @@ system.cpu.dtb.read_misses 0 # DT system.cpu.dtb.write_accesses 0 # DTB write accesses system.cpu.dtb.write_hits 0 # DTB write hits system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.fetch.Branches 88392158 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 71392458 # Number of cache lines fetched -system.cpu.fetch.Cycles 153990332 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 937286 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 689759462 # Number of instructions fetch has processed -system.cpu.fetch.MiscStallCycles 1876 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.SquashCycles 4453848 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.224874 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 71392458 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 77351232 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 1.754784 # Number of inst fetches per cycle -system.cpu.fetch.rateDist::samples 392159879 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.871937 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.898017 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.Branches 88398894 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 71395519 # Number of cache lines fetched +system.cpu.fetch.Cycles 153789076 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 942755 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 689805737 # Number of instructions fetch has processed +system.cpu.fetch.MiscStallCycles 34 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.SquashCycles 4451587 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.224919 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 71395519 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 77137437 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 1.755114 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 392116711 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.872365 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.899483 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 238169672 60.73% 60.73% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 25123756 6.41% 67.14% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 18408287 4.69% 71.83% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 22743537 5.80% 77.63% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 11348841 2.89% 80.53% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 12044698 3.07% 83.60% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 4472652 1.14% 84.74% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 7314673 1.87% 86.60% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 52533763 13.40% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 238327790 60.78% 60.78% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 25111973 6.40% 67.18% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 18227974 4.65% 71.83% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 22524916 5.74% 77.58% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 11352449 2.90% 80.47% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 12221762 3.12% 83.59% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 4491606 1.15% 84.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 7291145 1.86% 86.59% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 52567096 13.41% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 392159879 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 392116711 # Number of instructions fetched each cycle (Total) system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.icache.ReadReq_accesses 71392458 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 35440.133038 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 34413.407821 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 71391556 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 31967000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_accesses 71395519 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 35429.359823 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 34341.412742 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 71394613 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 32099000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.000013 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 902 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 186 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 24640000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_misses 906 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 184 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 24794500 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000010 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 716 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses 722 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 99708.877095 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 99159.184722 # Average number of references to valid blocks. system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 71392458 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 35440.133038 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 34413.407821 # average overall mshr miss latency -system.cpu.icache.demand_hits 71391556 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 31967000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_accesses 71395519 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 35429.359823 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 34341.412742 # average overall mshr miss latency +system.cpu.icache.demand_hits 71394613 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 32099000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.000013 # miss rate for demand accesses -system.cpu.icache.demand_misses 902 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 186 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 24640000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_misses 906 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 184 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 24794500 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.000010 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 716 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses 722 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.304966 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 624.569528 # Average occupied blocks per context -system.cpu.icache.overall_accesses 71392458 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 35440.133038 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 34413.407821 # average overall mshr miss latency +system.cpu.icache.occ_%::0 0.307172 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 629.087764 # Average occupied blocks per context +system.cpu.icache.overall_accesses 71395519 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 35429.359823 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 34341.412742 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 71391556 # number of overall hits -system.cpu.icache.overall_miss_latency 31967000 # number of overall miss cycles +system.cpu.icache.overall_hits 71394613 # number of overall hits +system.cpu.icache.overall_miss_latency 32099000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000013 # miss rate for overall accesses -system.cpu.icache.overall_misses 902 # number of overall misses -system.cpu.icache.overall_mshr_hits 186 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 24640000 # number of overall MSHR miss cycles +system.cpu.icache.overall_misses 906 # number of overall misses +system.cpu.icache.overall_mshr_hits 184 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 24794500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.000010 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 716 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses 722 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.replacements 33 # number of replacements -system.cpu.icache.sampled_refs 716 # Sample count of references to valid blocks. +system.cpu.icache.replacements 31 # number of replacements +system.cpu.icache.sampled_refs 720 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 624.569528 # Cycle average of tags in use -system.cpu.icache.total_refs 71391556 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 629.087764 # Cycle average of tags in use +system.cpu.icache.total_refs 71394613 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 913743 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 73697015 # Number of branches executed -system.cpu.iew.EXEC:nop 61594 # number of nop insts executed -system.cpu.iew.EXEC:rate 1.622192 # Inst execution rate -system.cpu.iew.EXEC:refs 239145114 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 73370419 # Number of stores executed +system.cpu.idleCycles 909571 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 73704412 # Number of branches executed +system.cpu.iew.EXEC:nop 61098 # number of nop insts executed +system.cpu.iew.EXEC:rate 1.622472 # Inst execution rate +system.cpu.iew.EXEC:refs 239165331 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 73423365 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 736423030 # num instructions consuming a value -system.cpu.iew.WB:count 631861927 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.594969 # average fanout of values written-back +system.cpu.iew.WB:consumers 736448308 # num instructions consuming a value +system.cpu.iew.WB:count 631945179 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.594878 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 438148553 # num instructions producing a value -system.cpu.iew.WB:rate 1.607490 # insts written-back per cycle -system.cpu.iew.WB:sent 632828783 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 4309187 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 803250 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 176095139 # Number of dispatched load instructions +system.cpu.iew.WB:producers 438096934 # num instructions producing a value +system.cpu.iew.WB:rate 1.607895 # insts written-back per cycle +system.cpu.iew.WB:sent 632881856 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 4305441 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 811047 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 176106355 # Number of dispatched load instructions system.cpu.iew.iewDispNonSpecInsts 5819 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 2962571 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 82148484 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 689113035 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 165774695 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 6093175 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 637640921 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 25921 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewDispSquashedInsts 2956217 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 82187861 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 689217371 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 165741966 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 6134058 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 637674087 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 25252 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 3894 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 12857426 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 66942 # Number of cycles IEW is unblocking +system.cpu.iew.iewLSQFullEvents 3721 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 12871984 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 65726 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread.0.cacheBlocked 8942 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 25088282 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 91350 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.cacheBlocked 8982 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread.0.forwLoads 25082678 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 87734 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 610036 # Number of memory ordering violations -system.cpu.iew.lsq.thread.0.rescheduledLoads 15544 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 27142530 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 11927457 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 610036 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 629916 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 3679271 # Number of branches that were predicted taken incorrectly -system.cpu.int_regfile_reads 1724659056 # number of integer regfile reads -system.cpu.int_regfile_writes 495413856 # number of integer regfile writes -system.cpu.ipc 1.532435 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.532435 # IPC: Total IPC of All Threads +system.cpu.iew.lsq.thread.0.memOrderViolation 611520 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.rescheduledLoads 15892 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread.0.squashedLoads 27153747 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 11966835 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 611520 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 628522 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 3676919 # Number of branches that were predicted taken incorrectly +system.cpu.int_regfile_reads 1724767298 # number of integer regfile reads +system.cpu.int_regfile_writes 495432855 # number of integer regfile writes +system.cpu.ipc 1.532620 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.532620 # IPC: Total IPC of All Threads system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntAlu 400825580 62.27% 62.27% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntAlu 400863775 62.26% 62.26% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::IntMult 6585 0.00% 62.27% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 62.27% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 62.27% # Type of FU issued @@ -320,80 +320,80 @@ system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 3 0.00% 62.27% system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 62.27% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 62.27% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 62.27% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemRead 168279108 26.14% 88.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemWrite 74622820 11.59% 100.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemRead 168265891 26.14% 88.40% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemWrite 74671891 11.60% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::total 643734096 # Type of FU issued -system.cpu.iq.ISSUE:fu_busy_cnt 3962863 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.006156 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:FU_type_0::total 643808145 # Type of FU issued +system.cpu.iq.ISSUE:fu_busy_cnt 3945011 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.006128 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntAlu 103447 2.61% 2.61% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 2.61% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 2.61% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 2.61% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 2.61% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 2.61% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 2.61% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 2.61% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 2.61% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 2.61% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 2.61% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 2.61% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 2.61% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 2.61% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 2.61% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 2.61% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 2.61% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 2.61% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 2.61% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 2.61% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 2.61% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 2.61% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 2.61% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 2.61% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 2.61% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 2.61% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 2.61% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 2.61% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 2.61% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemRead 3410396 86.06% 88.67% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemWrite 449020 11.33% 100.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntAlu 107679 2.73% 2.73% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 2.73% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 2.73% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 2.73% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 2.73% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 2.73% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 2.73% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 2.73% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 2.73% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 2.73% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 2.73% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 2.73% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 2.73% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 2.73% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 2.73% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 2.73% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 2.73% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 2.73% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 2.73% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 2.73% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 2.73% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 2.73% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 2.73% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 2.73% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 2.73% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 2.73% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 2.73% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 2.73% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 2.73% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemRead 3407280 86.37% 89.10% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemWrite 430052 10.90% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:issued_per_cycle::samples 392159879 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::mean 1.641509 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.552773 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::samples 392116711 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::mean 1.641879 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.551770 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::0 108979156 27.79% 27.79% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::1 107509921 27.41% 55.20% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::2 76161777 19.42% 74.63% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::3 48539013 12.38% 87.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::4 26829140 6.84% 93.84% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::5 16734433 4.27% 98.11% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::6 5468015 1.39% 99.51% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::7 1020625 0.26% 99.77% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::8 917799 0.23% 100.00% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::0 108904518 27.77% 27.77% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::1 107421508 27.40% 55.17% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::2 76290088 19.46% 74.62% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::3 48454562 12.36% 86.98% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::4 26882762 6.86% 93.84% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::5 16851716 4.30% 98.14% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::6 5414053 1.38% 99.52% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::7 1011203 0.26% 99.77% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::8 886301 0.23% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::total 392159879 # Number of insts issued each cycle -system.cpu.iq.ISSUE:rate 1.637693 # Inst issue rate +system.cpu.iq.ISSUE:issued_per_cycle::total 392116711 # Number of insts issued each cycle +system.cpu.iq.ISSUE:rate 1.638079 # Inst issue rate system.cpu.iq.fp_alu_accesses 20 # Number of floating point alu accesses system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_writes 16 # Number of floating instruction queue writes -system.cpu.iq.int_alu_accesses 647696939 # Number of integer alu accesses -system.cpu.iq.int_inst_queue_reads 1683941472 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_wakeup_accesses 631861911 # Number of integer instruction queue wakeup accesses -system.cpu.iq.int_inst_queue_writes 776045363 # Number of integer instruction queue writes -system.cpu.iq.iqInstsAdded 689044280 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 643734096 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 7161 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 86384301 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 350574 # Number of squashed instructions issued +system.cpu.iq.int_alu_accesses 647753136 # Number of integer alu accesses +system.cpu.iq.int_inst_queue_reads 1684034505 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_wakeup_accesses 631945163 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_writes 776263645 # Number of integer instruction queue writes +system.cpu.iq.iqInstsAdded 689149113 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 643808145 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 7160 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 86496318 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 356529 # Number of squashed instructions issued system.cpu.iq.iqSquashedNonSpecRemoved 850 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 162192952 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedOperandsExamined 162226931 # Number of squashed operands that are examined and possibly removed from graph system.cpu.itb.accesses 0 # DTB accesses system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions @@ -415,106 +415,114 @@ system.cpu.itb.read_misses 0 # DT system.cpu.itb.write_accesses 0 # DTB write accesses system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.l2cache.ReadExReq_accesses 247857 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 34331.314168 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31234.317248 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_hits 189417 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_miss_latency 2006322000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_rate 0.235781 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 58440 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 1825333500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.235781 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 58440 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 196581 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 34342.701958 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31091.800820 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 163901 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 1122319500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.166242 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 32680 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_accesses 247858 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_avg_miss_latency 34335.577877 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31238.064273 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_hits 189420 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_miss_latency 2006502500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_rate 0.235772 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_misses 58438 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 1825490000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.235772 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_misses 58438 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_accesses 196680 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 34348.019439 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31098.694669 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 163962 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 1123798500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.166351 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 32718 # number of ReadReq misses system.cpu.l2cache.ReadReq_mshr_hits 6 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_miss_latency 1015893500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.166211 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 32674 # number of ReadReq MSHR misses -system.cpu.l2cache.Writeback_accesses 394231 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 394231 # number of Writeback hits -system.cpu.l2cache.avg_blocked_cycles::no_mshrs 5401.428571 # average number of cycles each access was blocked +system.cpu.l2cache.ReadReq_mshr_miss_latency 1017300500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.166321 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 32712 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_accesses 2 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 32000 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_hits 1 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_miss_rate 0.500000 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_misses 1 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 32000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_rate 0.500000 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_misses 1 # number of UpgradeReq MSHR misses +system.cpu.l2cache.Writeback_accesses 394264 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 394264 # number of Writeback hits +system.cpu.l2cache.avg_blocked_cycles::no_mshrs 6213.636364 # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 4.739445 # Average number of references to valid blocks. -system.cpu.l2cache.blocked::no_mshrs 350 # number of cycles access was blocked +system.cpu.l2cache.avg_refs 4.739861 # Average number of references to valid blocks. +system.cpu.l2cache.blocked::no_mshrs 330 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_mshrs 1890500 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_mshrs 2050500 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 444438 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 34335.398376 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31183.210045 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 353318 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 3128641500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.205023 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 91120 # number of demand (read+write) misses +system.cpu.l2cache.demand_accesses 444538 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 34340.043442 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31188.047175 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 353382 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 3130301000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.205058 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 91156 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 6 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 2841227000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.205009 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 91114 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 2842790500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.205044 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 91150 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.057195 # Average percentage of cache occupancy -system.cpu.l2cache.occ_%::1 0.487171 # Average percentage of cache occupancy -system.cpu.l2cache.occ_blocks::0 1874.172488 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 15963.624075 # Average occupied blocks per context -system.cpu.l2cache.overall_accesses 444438 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 34335.398376 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31183.210045 # average overall mshr miss latency +system.cpu.l2cache.occ_%::0 0.057260 # Average percentage of cache occupancy +system.cpu.l2cache.occ_%::1 0.487109 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 1876.282231 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 15961.603623 # Average occupied blocks per context +system.cpu.l2cache.overall_accesses 444538 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 34340.043442 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31188.047175 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 353318 # number of overall hits -system.cpu.l2cache.overall_miss_latency 3128641500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.205023 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 91120 # number of overall misses +system.cpu.l2cache.overall_hits 353382 # number of overall hits +system.cpu.l2cache.overall_miss_latency 3130301000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.205058 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 91156 # number of overall misses system.cpu.l2cache.overall_mshr_hits 6 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 2841227000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.205009 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 91114 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 2842790500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.205044 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 91150 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.replacements 72928 # number of replacements -system.cpu.l2cache.sampled_refs 88438 # Sample count of references to valid blocks. +system.cpu.l2cache.replacements 72953 # number of replacements +system.cpu.l2cache.sampled_refs 88472 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 17837.796563 # Cycle average of tags in use -system.cpu.l2cache.total_refs 419147 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 17837.885854 # Cycle average of tags in use +system.cpu.l2cache.total_refs 419345 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 58125 # number of writebacks -system.cpu.memDep0.conflictingLoads 25818022 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 23076545 # Number of conflicting stores. -system.cpu.memDep0.insertedLoads 176095139 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 82148484 # Number of stores inserted to the mem dependence unit. -system.cpu.misc_regfile_reads 922030590 # number of misc regfile reads -system.cpu.misc_regfile_writes 9368 # number of misc regfile writes -system.cpu.numCycles 393073622 # number of cpu cycles simulated +system.cpu.l2cache.writebacks 58134 # number of writebacks +system.cpu.memDep0.conflictingLoads 25914382 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 23086559 # Number of conflicting stores. +system.cpu.memDep0.insertedLoads 176106355 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 82187861 # Number of stores inserted to the mem dependence unit. +system.cpu.misc_regfile_reads 922126404 # number of misc regfile reads +system.cpu.misc_regfile_writes 2684 # number of misc regfile writes +system.cpu.numCycles 393026282 # number of cpu cycles simulated system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.rename.RENAME:BlockCycles 9403650 # Number of cycles rename is blocking -system.cpu.rename.RENAME:CommittedMaps 471025466 # Number of HB maps that are committed -system.cpu.rename.RENAME:IQFullEvents 50023577 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 176787767 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 1922723 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:RenameLookups 2034086698 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 711204835 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 553151366 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 138512795 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 12857426 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 54492155 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 82125897 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:BlockCycles 9628088 # Number of cycles rename is blocking +system.cpu.rename.RENAME:CommittedMaps 471021820 # Number of HB maps that are committed +system.cpu.rename.RENAME:IQFullEvents 50048668 # Number of times rename has blocked due to IQ full +system.cpu.rename.RENAME:IdleCycles 176696020 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 1915065 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:RenameLookups 2034394520 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 711291370 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 553214444 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 138291459 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 12871984 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 54521168 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 82192621 # Number of HB maps that are undone due to squashing system.cpu.rename.RENAME:fp_rename_lookups 96 # Number of floating rename lookups -system.cpu.rename.RENAME:int_rename_lookups 2034086602 # Number of integer rename lookups -system.cpu.rename.RENAME:serializeStallCycles 106086 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 6114 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 91032587 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 6112 # count of temporary serializing insts renamed -system.cpu.rob.rob_reads 1060489680 # The number of ROB reads -system.cpu.rob.rob_writes 1391088840 # The number of ROB writes -system.cpu.timesIdled 36977 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.rename.RENAME:int_rename_lookups 2034394424 # Number of integer rename lookups +system.cpu.rename.RENAME:serializeStallCycles 107992 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 6480 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 91409775 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 6477 # count of temporary serializing insts renamed +system.cpu.rob.rob_reads 1060565987 # The number of ROB reads +system.cpu.rob.rob_writes 1391311417 # The number of ROB writes +system.cpu.timesIdled 36947 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 48 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/00.gzip/ref/arm/linux/simple-atomic/config.ini b/tests/long/00.gzip/ref/arm/linux/simple-atomic/config.ini index e931d99dc..b07d285b7 100644 --- a/tests/long/00.gzip/ref/arm/linux/simple-atomic/config.ini +++ b/tests/long/00.gzip/ref/arm/linux/simple-atomic/config.ini @@ -61,7 +61,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=gzip input.log 1 -cwd=build/ARM_SE/tests/fast/long/00.gzip/arm/linux/simple-atomic +cwd=build/ARM_SE/tests/opt/long/00.gzip/arm/linux/simple-atomic egid=100 env= errout=cerr diff --git a/tests/long/00.gzip/ref/arm/linux/simple-atomic/simout b/tests/long/00.gzip/ref/arm/linux/simple-atomic/simout index cf49f4125..d9332d696 100755 --- a/tests/long/00.gzip/ref/arm/linux/simple-atomic/simout +++ b/tests/long/00.gzip/ref/arm/linux/simple-atomic/simout @@ -5,11 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Mar 11 2011 20:10:09 -M5 revision 4decc284606a 8095 default qtip tip ext/update_add_stats.patch -M5 started Mar 11 2011 20:23:27 +M5 compiled Mar 30 2011 17:47:57 +M5 started Mar 30 2011 17:54:33 M5 executing on u200439-lin.austin.arm.com -command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/00.gzip/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/fast/long/00.gzip/arm/linux/simple-atomic +command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/00.gzip/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/opt/long/00.gzip/arm/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... spec_init diff --git a/tests/long/00.gzip/ref/arm/linux/simple-atomic/stats.txt b/tests/long/00.gzip/ref/arm/linux/simple-atomic/stats.txt index 0eb8d8824..f0089af03 100644 --- a/tests/long/00.gzip/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/00.gzip/ref/arm/linux/simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1838558 # Simulator instruction rate (inst/s) -host_mem_usage 246240 # Number of bytes of host memory used -host_seconds 327.63 # Real time elapsed on the host -host_tick_rate 919312999 # Simulator tick rate (ticks/s) +host_inst_rate 1048186 # Simulator instruction rate (inst/s) +host_mem_usage 246964 # Number of bytes of host memory used +host_seconds 574.67 # Real time elapsed on the host +host_tick_rate 524112689 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 602359851 # Number of instructions simulated sim_seconds 0.301191 # Number of seconds simulated @@ -56,18 +56,18 @@ system.cpu.numCycles 602382741 # nu system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.num_busy_cycles 602382741 # Number of busy cycles -system.cpu.num_conditional_control_insts 67016068 # number of instructions that are conditional controls +system.cpu.num_conditional_control_insts 67017827 # number of instructions that are conditional controls system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses system.cpu.num_fp_insts 16 # number of float instructions system.cpu.num_fp_register_reads 16 # number of times the floating registers were read system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_func_calls 1993596 # number of times a function call or return occured +system.cpu.num_func_calls 1993546 # number of times a function call or return occured system.cpu.num_idle_cycles 0 # Number of idle cycles system.cpu.num_insts 602359851 # Number of instructions executed system.cpu.num_int_alu_accesses 533522639 # Number of integer alu accesses system.cpu.num_int_insts 533522639 # number of integer instructions system.cpu.num_int_register_reads 1694262461 # number of times the integer registers were read -system.cpu.num_int_register_writes 458085654 # number of times the integer registers were written +system.cpu.num_int_register_writes 458076290 # number of times the integer registers were written system.cpu.num_load_insts 148952594 # Number of load instructions system.cpu.num_mem_refs 219173607 # number of memory refs system.cpu.num_store_insts 70221013 # Number of store instructions diff --git a/tests/long/00.gzip/ref/arm/linux/simple-timing/config.ini b/tests/long/00.gzip/ref/arm/linux/simple-timing/config.ini index cd3bf6aae..5a251a60a 100644 --- a/tests/long/00.gzip/ref/arm/linux/simple-timing/config.ini +++ b/tests/long/00.gzip/ref/arm/linux/simple-timing/config.ini @@ -164,7 +164,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=gzip input.log 1 -cwd=build/ARM_SE/tests/fast/long/00.gzip/arm/linux/simple-timing +cwd=build/ARM_SE/tests/opt/long/00.gzip/arm/linux/simple-timing egid=100 env= errout=cerr diff --git a/tests/long/00.gzip/ref/arm/linux/simple-timing/simerr b/tests/long/00.gzip/ref/arm/linux/simple-timing/simerr index c1c8fcec5..eabe42249 100755 --- a/tests/long/00.gzip/ref/arm/linux/simple-timing/simerr +++ b/tests/long/00.gzip/ref/arm/linux/simple-timing/simerr @@ -1,7 +1,3 @@ warn: Sockets disabled, not accepting gdb connections For more information see: http://www.m5sim.org/warn/d946bea6 -warn: Complete acc isn't called on normal stores in O3. -For more information see: http://www.m5sim.org/warn/138d8573 -warn: Complete acc isn't called on normal stores in O3. -For more information see: http://www.m5sim.org/warn/138d8573 hack: be nice to actually delete the event here diff --git a/tests/long/00.gzip/ref/arm/linux/simple-timing/simout b/tests/long/00.gzip/ref/arm/linux/simple-timing/simout index 3d2816f3e..9680f68d5 100755 --- a/tests/long/00.gzip/ref/arm/linux/simple-timing/simout +++ b/tests/long/00.gzip/ref/arm/linux/simple-timing/simout @@ -5,11 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Mar 11 2011 20:10:09 -M5 revision 4decc284606a 8095 default qtip tip ext/update_add_stats.patch -M5 started Mar 11 2011 20:13:11 +M5 compiled Mar 30 2011 17:47:57 +M5 started Mar 30 2011 17:54:33 M5 executing on u200439-lin.austin.arm.com -command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/00.gzip/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/fast/long/00.gzip/arm/linux/simple-timing +command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/00.gzip/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/opt/long/00.gzip/arm/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... spec_init diff --git a/tests/long/00.gzip/ref/arm/linux/simple-timing/stats.txt b/tests/long/00.gzip/ref/arm/linux/simple-timing/stats.txt index bc2095464..9997800cb 100644 --- a/tests/long/00.gzip/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/00.gzip/ref/arm/linux/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 732997 # Simulator instruction rate (inst/s) -host_mem_usage 253960 # Number of bytes of host memory used -host_seconds 819.10 # Real time elapsed on the host -host_tick_rate 972728993 # Simulator tick rate (ticks/s) +host_inst_rate 590565 # Simulator instruction rate (inst/s) +host_mem_usage 254684 # Number of bytes of host memory used +host_seconds 1016.65 # Real time elapsed on the host +host_tick_rate 783712761 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 600398281 # Number of instructions simulated sim_seconds 0.796763 # Number of seconds simulated @@ -249,18 +249,18 @@ system.cpu.numCycles 1593525852 # nu system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.num_busy_cycles 1593525852 # Number of busy cycles -system.cpu.num_conditional_control_insts 67016068 # number of instructions that are conditional controls +system.cpu.num_conditional_control_insts 67017827 # number of instructions that are conditional controls system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses system.cpu.num_fp_insts 16 # number of float instructions system.cpu.num_fp_register_reads 16 # number of times the floating registers were read system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_func_calls 1993596 # number of times a function call or return occured +system.cpu.num_func_calls 1993546 # number of times a function call or return occured system.cpu.num_idle_cycles 0 # Number of idle cycles system.cpu.num_insts 600398281 # Number of instructions executed system.cpu.num_int_alu_accesses 533522639 # Number of integer alu accesses system.cpu.num_int_insts 533522639 # number of integer instructions system.cpu.num_int_register_reads 1840897552 # number of times the integer registers were read -system.cpu.num_int_register_writes 458086291 # number of times the integer registers were written +system.cpu.num_int_register_writes 458076290 # number of times the integer registers were written system.cpu.num_load_insts 148952594 # Number of load instructions system.cpu.num_mem_refs 219173607 # number of memory refs system.cpu.num_store_insts 70221013 # Number of store instructions diff --git a/tests/long/10.linux-boot/ref/arm/linux/realview-o3/config.ini b/tests/long/10.linux-boot/ref/arm/linux/realview-o3/config.ini index 55f3d08fb..5e6e6c0a7 100644 --- a/tests/long/10.linux-boot/ref/arm/linux/realview-o3/config.ini +++ b/tests/long/10.linux-boot/ref/arm/linux/realview-o3/config.ini @@ -11,7 +11,7 @@ children=bridge cpu diskmem intrctrl iobus iocache l2c membus physmem realview t boot_cpu_frequency=500 boot_osflags=earlyprintk mem=128MB console=ttyAMA0 lpj=19988480 norandmaps slram=slram0,0x8000000,+0x8000000 mtdparts=slram0:- rw loglevel=8 root=/dev/mtdblock0 init_param=0 -kernel=/dist/m5/system/binaries/vmlinux.arm +kernel=/chips/pd/randd/dist/binaries/vmlinux.arm load_addr_mask=268435455 machine_type=RealView_PBX mem_mode=timing @@ -47,6 +47,8 @@ BTBEntries=4096 BTBTagSize=16 LFSTSize=1024 LQEntries=32 +LSQCheckLoads=true +LSQDepCheckShift=4 RASSize=16 SQEntries=32 SSITSize=1024 @@ -493,7 +495,7 @@ type=ExeTracer [system.diskmem] type=PhysicalMemory -file=/dist/m5/system/disks/ael-arm.ext2 +file=/chips/pd/randd/dist/disks/ael-arm.ext2 latency=30000 latency_var=0 null=false diff --git a/tests/long/10.linux-boot/ref/arm/linux/realview-o3/simerr b/tests/long/10.linux-boot/ref/arm/linux/realview-o3/simerr index 63ac398c9..701e9297b 100755 --- a/tests/long/10.linux-boot/ref/arm/linux/realview-o3/simerr +++ b/tests/long/10.linux-boot/ref/arm/linux/realview-o3/simerr @@ -26,6 +26,8 @@ warn: instruction 'mcr icimvau' unimplemented For more information see: http://www.m5sim.org/warn/21b09adb warn: instruction 'mcr bpiall' unimplemented For more information see: http://www.m5sim.org/warn/21b09adb +warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors +For more information see: http://www.m5sim.org/warn/7998f2ea warn: instruction 'mcr bpiall' unimplemented For more information see: http://www.m5sim.org/warn/21b09adb warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors diff --git a/tests/long/10.linux-boot/ref/arm/linux/realview-o3/simout b/tests/long/10.linux-boot/ref/arm/linux/realview-o3/simout index 03f27ae2f..b0b26bf8a 100755 --- a/tests/long/10.linux-boot/ref/arm/linux/realview-o3/simout +++ b/tests/long/10.linux-boot/ref/arm/linux/realview-o3/simout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Mar 18 2011 02:37:41 -M5 started Mar 18 2011 02:38:20 -M5 executing on zizzer -command line: build/ARM_FS/m5.fast -d build/ARM_FS/tests/fast/long/10.linux-boot/arm/linux/realview-o3 -re tests/run.py build/ARM_FS/tests/fast/long/10.linux-boot/arm/linux/realview-o3 +M5 compiled Mar 31 2011 10:39:48 +M5 started Mar 31 2011 10:41:48 +M5 executing on u200439-lin.austin.arm.com +command line: build/ARM_FS/m5.opt -d build/ARM_FS/tests/opt/long/10.linux-boot/arm/linux/realview-o3 -re tests/run.py build/ARM_FS/tests/opt/long/10.linux-boot/arm/linux/realview-o3 Global frequency set at 1000000000000 ticks per second -info: kernel located at: /dist/m5/system/binaries/vmlinux.arm +info: kernel located at: /chips/pd/randd/dist/binaries/vmlinux.arm info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 83363125500 because m5_exit instruction encountered +Exiting @ tick 82667402500 because m5_exit instruction encountered diff --git a/tests/long/10.linux-boot/ref/arm/linux/realview-o3/stats.txt b/tests/long/10.linux-boot/ref/arm/linux/realview-o3/stats.txt index 2371efa42..22329b251 100644 --- a/tests/long/10.linux-boot/ref/arm/linux/realview-o3/stats.txt +++ b/tests/long/10.linux-boot/ref/arm/linux/realview-o3/stats.txt @@ -1,506 +1,504 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 136397 # Simulator instruction rate (inst/s) -host_mem_usage 350148 # Number of bytes of host memory used -host_seconds 380.99 # Real time elapsed on the host -host_tick_rate 218804000 # Simulator tick rate (ticks/s) +host_inst_rate 90803 # Simulator instruction rate (inst/s) +host_mem_usage 385116 # Number of bytes of host memory used +host_seconds 572.31 # Real time elapsed on the host +host_tick_rate 144444192 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 51966326 # Number of instructions simulated -sim_seconds 0.083363 # Number of seconds simulated -sim_ticks 83363125500 # Number of ticks simulated +sim_insts 51967991 # Number of instructions simulated +sim_seconds 0.082667 # Number of seconds simulated +sim_ticks 82667402500 # Number of ticks simulated system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.BTBHits 9109525 # Number of BTB hits -system.cpu.BPredUnit.BTBLookups 11661597 # Number of BTB lookups -system.cpu.BPredUnit.RASInCorrect 155432 # Number of incorrect RAS predictions. -system.cpu.BPredUnit.condIncorrect 643707 # Number of conditional branches incorrect -system.cpu.BPredUnit.condPredicted 11148181 # Number of conditional branches predicted -system.cpu.BPredUnit.lookups 13121145 # Number of BP lookups -system.cpu.BPredUnit.usedRAS 795550 # Number of times the RAS was used to get a target. -system.cpu.commit.COM:branches 8359370 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 811751 # number cycles where commit BW limit reached +system.cpu.BPredUnit.BTBHits 9197470 # Number of BTB hits +system.cpu.BPredUnit.BTBLookups 11720402 # Number of BTB lookups +system.cpu.BPredUnit.RASInCorrect 155471 # Number of incorrect RAS predictions. +system.cpu.BPredUnit.condIncorrect 664024 # Number of conditional branches incorrect +system.cpu.BPredUnit.condPredicted 11242806 # Number of conditional branches predicted +system.cpu.BPredUnit.lookups 13225964 # Number of BP lookups +system.cpu.BPredUnit.usedRAS 787685 # Number of times the RAS was used to get a target. +system.cpu.commit.COM:branches 8444335 # Number of branches committed +system.cpu.commit.COM:bw_lim_events 800394 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle::samples 94793091 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::mean 0.549507 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::stdev 1.345543 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::samples 93520933 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::mean 0.557000 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::stdev 1.350737 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::0 73158899 77.18% 77.18% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::1 10643869 11.23% 88.41% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::2 3426640 3.61% 92.02% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::3 1618432 1.71% 93.73% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::4 3558653 3.75% 97.48% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::5 736107 0.78% 98.26% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::6 543274 0.57% 98.83% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::7 295466 0.31% 99.14% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::8 811751 0.86% 100.00% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::0 71862945 76.84% 76.84% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::1 10613514 11.35% 88.19% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::2 3470472 3.71% 91.90% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::3 1669950 1.79% 93.69% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::4 3525302 3.77% 97.46% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::5 743125 0.79% 98.25% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::6 539739 0.58% 98.83% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::7 295492 0.32% 99.14% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::8 800394 0.86% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::total 94793091 # Number of insts commited each cycle -system.cpu.commit.COM:count 52089506 # Number of instructions committed +system.cpu.commit.COM:committed_per_cycle::total 93520933 # Number of insts commited each cycle +system.cpu.commit.COM:count 52091171 # Number of instructions committed system.cpu.commit.COM:fp_insts 6017 # Number of committed floating point instructions. -system.cpu.commit.COM:function_calls 529550 # Number of function calls committed. -system.cpu.commit.COM:int_insts 42498657 # Number of committed integer instructions. -system.cpu.commit.COM:loads 9209715 # Number of loads committed +system.cpu.commit.COM:function_calls 529543 # Number of function calls committed. +system.cpu.commit.COM:int_insts 42499828 # Number of committed integer instructions. +system.cpu.commit.COM:loads 9204456 # Number of loads committed system.cpu.commit.COM:membars 3 # Number of memory barriers committed -system.cpu.commit.COM:refs 16294715 # Number of memory references committed +system.cpu.commit.COM:refs 16289486 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 710936 # The number of times a branch was mispredicted -system.cpu.commit.commitCommittedInsts 52089506 # The number of committed instructions -system.cpu.commit.commitNonSpecStalls 2963004 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 16584310 # The number of squashed insts skipped by commit -system.cpu.committedInsts 51966326 # Number of Instructions Simulated -system.cpu.committedInsts_total 51966326 # Number of Instructions Simulated -system.cpu.cpi 3.208352 # CPI: Cycles Per Instruction -system.cpu.cpi_total 3.208352 # CPI: Total CPI of All Threads -system.cpu.dcache.LoadLockedReq_accesses::0 110398 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 110398 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_avg_miss_latency::0 14987.700535 # average LoadLockedReq miss latency +system.cpu.commit.branchMispredicts 640570 # The number of times a branch was mispredicted +system.cpu.commit.commitCommittedInsts 52091171 # The number of committed instructions +system.cpu.commit.commitNonSpecStalls 2963049 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.commitSquashedInsts 16156603 # The number of squashed insts skipped by commit +system.cpu.committedInsts 51967991 # Number of Instructions Simulated +system.cpu.committedInsts_total 51967991 # Number of Instructions Simulated +system.cpu.cpi 3.181474 # CPI: Cycles Per Instruction +system.cpu.cpi_total 3.181474 # CPI: Total CPI of All Threads +system.cpu.dcache.LoadLockedReq_accesses::0 111599 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 111599 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_avg_miss_latency::0 14959.817352 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 11878.197102 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_uncacheable_latency inf # average LoadLockedReq mshr uncacheable latency -system.cpu.dcache.LoadLockedReq_hits::0 103853 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 103853 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_miss_latency 98094500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_rate::0 0.059285 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_misses::0 6545 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 6545 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_mshr_hits 954 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_miss_latency 66411000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::0 0.050644 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 11849.393291 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_hits::0 105029 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 105029 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_miss_latency 98286000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_rate::0 0.058871 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_misses::0 6570 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 6570 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_mshr_hits 966 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_miss_latency 66404000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::0 0.050216 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_misses 5591 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_uncacheable_latency 312483000 # number of LoadLockedReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_accesses::0 9405887 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 9405887 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency::0 14818.902196 # average ReadReq miss latency +system.cpu.dcache.LoadLockedReq_mshr_misses 5604 # number of LoadLockedReq MSHR misses +system.cpu.dcache.ReadReq_accesses::0 9424637 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 9424637 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency::0 14817.536812 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 13268.493454 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 13267.620751 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_hits::0 8919589 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 8919589 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 7206402500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate::0 0.051701 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses::0 486298 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 486298 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 238048 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 3293903500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.026393 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_hits::0 8938243 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 8938243 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 7207161000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate::0 0.051609 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses::0 486394 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 486394 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 237639 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 3300387000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.026394 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 248250 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_uncacheable_latency 38193579000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.StoreCondReq_accesses::0 105006 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 105006 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_hits::0 105006 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 105006 # number of StoreCondReq hits -system.cpu.dcache.WriteReq_accesses::0 6670914 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 6670914 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency::0 39947.948992 # average WriteReq miss latency +system.cpu.dcache.ReadReq_mshr_misses 248755 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_uncacheable_latency 38192917500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.StoreCondReq_accesses::0 105021 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 105021 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_hits::0 105021 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 105021 # number of StoreCondReq hits +system.cpu.dcache.WriteReq_accesses::0 6670926 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6670926 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency::0 39939.840777 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 38533.384242 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 38522.323685 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.cpu.dcache.WriteReq_hits::0 4625272 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 4625272 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 81719202272 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate::0 0.306651 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses::0 2045642 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2045642 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 1875083 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 6572215483 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.025568 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_hits::0 4625068 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 4625068 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 81711242773 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate::0 0.306683 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses::0 2045858 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2045858 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 1875300 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 6570290483 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.025567 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 170559 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_uncacheable_latency 939908183 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.avg_blocked_cycles::no_mshrs 7476.302863 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 21020 # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 32.546615 # Average number of references to valid blocks. -system.cpu.dcache.blocked::no_mshrs 908 # number of cycles access was blocked +system.cpu.dcache.WriteReq_mshr_misses 170558 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_uncacheable_latency 939960187 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.avg_blocked_cycles::no_mshrs 7470.310989 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 21040 # average number of cycles each access was blocked +system.cpu.dcache.avg_refs 32.551220 # Average number of references to valid blocks. +system.cpu.dcache.blocked::no_mshrs 910 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 25 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_mshrs 6788483 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 525500 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_mshrs 6797983 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 526000 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses::0 16076801 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::0 16095563 # number of demand (read+write) accesses system.cpu.dcache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 16076801 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency::0 35121.529251 # average overall miss latency +system.cpu.dcache.demand_accesses::total 16095563 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency::0 35114.358197 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 23557.561998 # average overall mshr miss latency -system.cpu.dcache.demand_hits::0 13544861 # number of demand (read+write) hits +system.cpu.dcache.demand_avg_mshr_miss_latency 23540.117962 # average overall mshr miss latency +system.cpu.dcache.demand_hits::0 13563311 # number of demand (read+write) hits system.cpu.dcache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 13544861 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 88925604772 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate::0 0.157490 # miss rate for demand accesses +system.cpu.dcache.demand_hits::total 13563311 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 88918403773 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate::0 0.157326 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu.dcache.demand_misses::0 2531940 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::0 2532252 # number of demand (read+write) misses system.cpu.dcache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2531940 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 2113131 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 9866118983 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_misses::total 2532252 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 2112939 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 9870677483 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate::0 0.026051 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 418809 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses 419313 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.999517 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 511.752645 # Average occupied blocks per context -system.cpu.dcache.overall_accesses::0 16076801 # number of overall (read+write) accesses +system.cpu.dcache.occ_%::0 0.999513 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 511.750780 # Average occupied blocks per context +system.cpu.dcache.overall_accesses::0 16095563 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 16076801 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency::0 35121.529251 # average overall miss latency +system.cpu.dcache.overall_accesses::total 16095563 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency::0 35114.358197 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 23557.561998 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 23540.117962 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits::0 13544861 # number of overall hits +system.cpu.dcache.overall_hits::0 13563311 # number of overall hits system.cpu.dcache.overall_hits::1 0 # number of overall hits -system.cpu.dcache.overall_hits::total 13544861 # number of overall hits -system.cpu.dcache.overall_miss_latency 88925604772 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate::0 0.157490 # miss rate for overall accesses +system.cpu.dcache.overall_hits::total 13563311 # number of overall hits +system.cpu.dcache.overall_miss_latency 88918403773 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate::0 0.157326 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu.dcache.overall_misses::0 2531940 # number of overall misses +system.cpu.dcache.overall_misses::0 2532252 # number of overall misses system.cpu.dcache.overall_misses::1 0 # number of overall misses -system.cpu.dcache.overall_misses::total 2531940 # number of overall misses -system.cpu.dcache.overall_mshr_hits 2113131 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 9866118983 # number of overall MSHR miss cycles +system.cpu.dcache.overall_misses::total 2532252 # number of overall misses +system.cpu.dcache.overall_mshr_hits 2112939 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 9870677483 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate::0 0.026051 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 418809 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_latency 39133487183 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_misses 419313 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_uncacheable_latency 39132877687 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.replacements 422131 # number of replacements -system.cpu.dcache.sampled_refs 422643 # Sample count of references to valid blocks. +system.cpu.dcache.replacements 422673 # number of replacements +system.cpu.dcache.sampled_refs 423185 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 511.752645 # Cycle average of tags in use -system.cpu.dcache.total_refs 13755599 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 48259000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 390426 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 54881827 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 71596 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 1214700 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 77864847 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 24077327 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 14646912 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 2655366 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 235100 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 1186997 # Number of cycles decode is unblocking -system.cpu.dtb.accesses 35220915 # DTB accesses -system.cpu.dtb.align_faults 1535 # Number of TLB faults due to alignment restrictions +system.cpu.dcache.tagsinuse 511.750780 # Cycle average of tags in use +system.cpu.dcache.total_refs 13775188 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 48224000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 391306 # number of writebacks +system.cpu.decode.DECODE:BlockedCycles 53936427 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BranchMispred 70459 # Number of times decode detected a branch misprediction +system.cpu.decode.DECODE:BranchResolved 1223835 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 76423626 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 23928576 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 14469727 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 2568818 # Number of cycles decode is squashing +system.cpu.decode.DECODE:SquashedInsts 235907 # Number of squashed instructions handled by decode +system.cpu.decode.DECODE:UnblockCycles 1186175 # Number of cycles decode is unblocking +system.cpu.dtb.accesses 35245643 # DTB accesses +system.cpu.dtb.align_faults 1502 # Number of TLB faults due to alignment restrictions system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.flush_entries 2767 # Number of entries that have been flushed from TLB +system.cpu.dtb.flush_entries 2802 # Number of entries that have been flushed from TLB system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_asid 40 # Number of times TLB was flushed by ASID system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 33670 # Number of times TLB was flushed by MVA & ASID -system.cpu.dtb.hits 35140303 # DTB hits +system.cpu.dtb.hits 35173393 # DTB hits system.cpu.dtb.inst_accesses 0 # ITB inst accesses system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.misses 80612 # DTB misses -system.cpu.dtb.perms_faults 1012 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.misses 72250 # DTB misses +system.cpu.dtb.perms_faults 1115 # Number of TLB faults due to permissions restrictions system.cpu.dtb.prefetch_faults 1019 # Number of TLB faults due to prefetch -system.cpu.dtb.read_accesses 27731873 # DTB read accesses -system.cpu.dtb.read_hits 27661932 # DTB read hits -system.cpu.dtb.read_misses 69941 # DTB read misses -system.cpu.dtb.write_accesses 7489042 # DTB write accesses -system.cpu.dtb.write_hits 7478371 # DTB write hits -system.cpu.dtb.write_misses 10671 # DTB write misses -system.cpu.fetch.Branches 13121145 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 6614824 # Number of cache lines fetched -system.cpu.fetch.Cycles 16225603 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 267333 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 65526878 # Number of instructions fetch has processed -system.cpu.fetch.ItlbSquashes 4933 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.MiscStallCycles 21202 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.SquashCycles 1110741 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 8007 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.branchRate 0.078699 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 6613458 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 9905075 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 0.393021 # Number of inst fetches per cycle -system.cpu.fetch.rateDist::samples 97448429 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.824712 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.089384 # Number of instructions fetched each cycle (Total) +system.cpu.dtb.read_accesses 27745512 # DTB read accesses +system.cpu.dtb.read_hits 27683911 # DTB read hits +system.cpu.dtb.read_misses 61601 # DTB read misses +system.cpu.dtb.write_accesses 7500131 # DTB write accesses +system.cpu.dtb.write_hits 7489482 # DTB write hits +system.cpu.dtb.write_misses 10649 # DTB write misses +system.cpu.fetch.Branches 13225964 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 6550605 # Number of cache lines fetched +system.cpu.fetch.Cycles 16044931 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 257300 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 64080161 # Number of instructions fetch has processed +system.cpu.fetch.ItlbSquashes 3986 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.MiscStallCycles 17407 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.SquashCycles 1041050 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 7083 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.branchRate 0.079995 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 6549214 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 9985155 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 0.387578 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 96089723 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.820891 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.076577 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 81239523 83.37% 83.37% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1275012 1.31% 84.68% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1734122 1.78% 86.45% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 1277387 1.31% 87.77% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 4689721 4.81% 92.58% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 799978 0.82% 93.40% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 845081 0.87% 94.27% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 738625 0.76% 95.02% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 4848980 4.98% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 80061400 83.32% 83.32% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1246898 1.30% 84.62% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1750624 1.82% 86.44% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 1251283 1.30% 87.74% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 4759856 4.95% 92.69% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 798226 0.83% 93.53% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 841539 0.88% 94.40% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 741758 0.77% 95.17% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 4638139 4.83% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 97448429 # Number of instructions fetched each cycle (Total) -system.cpu.fp_regfile_reads 5433 # number of floating regfile reads -system.cpu.fp_regfile_writes 1933 # number of floating regfile writes -system.cpu.icache.ReadReq_accesses::0 6614731 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 6614731 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency::0 14762.027587 # average ReadReq miss latency +system.cpu.fetch.rateDist::total 96089723 # Number of instructions fetched each cycle (Total) +system.cpu.fp_regfile_reads 5467 # number of floating regfile reads +system.cpu.fp_regfile_writes 1929 # number of floating regfile writes +system.cpu.icache.ReadReq_accesses::0 6550512 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 6550512 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency::0 14752.246405 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 12010.787096 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 12017.726532 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu.icache.ReadReq_hits::0 6061711 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 6061711 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 8163696496 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate::0 0.083604 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses::0 553020 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 553020 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 43430 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 6120576996 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::0 0.077039 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_hits::0 6004197 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 6004197 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 8059373495 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate::0 0.083400 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses::0 546315 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 546315 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 44384 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 6032069496 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::0 0.076625 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 509590 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_uncacheable_latency 4968000 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.avg_blocked_cycles::no_mshrs 6801.619835 # average number of cycles each access was blocked +system.cpu.icache.ReadReq_mshr_misses 501931 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_uncacheable_latency 4957500 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.avg_blocked_cycles::no_mshrs 6823.818182 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 11.895551 # Average number of references to valid blocks. -system.cpu.icache.blocked::no_mshrs 121 # number of cycles access was blocked +system.cpu.icache.avg_refs 11.962625 # Average number of references to valid blocks. +system.cpu.icache.blocked::no_mshrs 88 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_mshrs 822996 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_mshrs 600496 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses::0 6614731 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::0 6550512 # number of demand (read+write) accesses system.cpu.icache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 6614731 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency::0 14762.027587 # average overall miss latency +system.cpu.icache.demand_accesses::total 6550512 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency::0 14752.246405 # average overall miss latency system.cpu.icache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu.icache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 12010.787096 # average overall mshr miss latency -system.cpu.icache.demand_hits::0 6061711 # number of demand (read+write) hits +system.cpu.icache.demand_avg_mshr_miss_latency 12017.726532 # average overall mshr miss latency +system.cpu.icache.demand_hits::0 6004197 # number of demand (read+write) hits system.cpu.icache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 6061711 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 8163696496 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate::0 0.083604 # miss rate for demand accesses +system.cpu.icache.demand_hits::total 6004197 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 8059373495 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate::0 0.083400 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu.icache.demand_misses::0 553020 # number of demand (read+write) misses +system.cpu.icache.demand_misses::0 546315 # number of demand (read+write) misses system.cpu.icache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 553020 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 43430 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 6120576996 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate::0 0.077039 # mshr miss rate for demand accesses +system.cpu.icache.demand_misses::total 546315 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 44384 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 6032069496 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate::0 0.076625 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 509590 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses 501931 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.969182 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 496.221044 # Average occupied blocks per context -system.cpu.icache.overall_accesses::0 6614731 # number of overall (read+write) accesses +system.cpu.icache.occ_%::0 0.970187 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 496.735661 # Average occupied blocks per context +system.cpu.icache.overall_accesses::0 6550512 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 6614731 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency::0 14762.027587 # average overall miss latency +system.cpu.icache.overall_accesses::total 6550512 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency::0 14752.246405 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu.icache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 12010.787096 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 12017.726532 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu.icache.overall_hits::0 6061711 # number of overall hits +system.cpu.icache.overall_hits::0 6004197 # number of overall hits system.cpu.icache.overall_hits::1 0 # number of overall hits -system.cpu.icache.overall_hits::total 6061711 # number of overall hits -system.cpu.icache.overall_miss_latency 8163696496 # number of overall miss cycles -system.cpu.icache.overall_miss_rate::0 0.083604 # miss rate for overall accesses +system.cpu.icache.overall_hits::total 6004197 # number of overall hits +system.cpu.icache.overall_miss_latency 8059373495 # number of overall miss cycles +system.cpu.icache.overall_miss_rate::0 0.083400 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu.icache.overall_misses::0 553020 # number of overall misses +system.cpu.icache.overall_misses::0 546315 # number of overall misses system.cpu.icache.overall_misses::1 0 # number of overall misses -system.cpu.icache.overall_misses::total 553020 # number of overall misses -system.cpu.icache.overall_mshr_hits 43430 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 6120576996 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate::0 0.077039 # mshr miss rate for overall accesses +system.cpu.icache.overall_misses::total 546315 # number of overall misses +system.cpu.icache.overall_mshr_hits 44384 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 6032069496 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate::0 0.076625 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 509590 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_latency 4968000 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_misses 501931 # number of overall MSHR misses +system.cpu.icache.overall_mshr_uncacheable_latency 4957500 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.replacements 509066 # number of replacements -system.cpu.icache.sampled_refs 509578 # Sample count of references to valid blocks. +system.cpu.icache.replacements 501401 # number of replacements +system.cpu.icache.sampled_refs 501913 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 496.221044 # Cycle average of tags in use -system.cpu.icache.total_refs 6061711 # Total number of references to valid blocks. -system.cpu.icache.warmup_cycle 6357615000 # Cycle when the warmup percentage was hit. -system.cpu.icache.writebacks 41956 # number of writebacks -system.cpu.idleCycles 69277823 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 10103883 # Number of branches executed -system.cpu.iew.EXEC:nop 231467 # number of nop insts executed -system.cpu.iew.EXEC:rate 0.472681 # Inst execution rate -system.cpu.iew.EXEC:refs 35943577 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 7792930 # Number of stores executed +system.cpu.icache.tagsinuse 496.735661 # Cycle average of tags in use +system.cpu.icache.total_refs 6004197 # Total number of references to valid blocks. +system.cpu.icache.warmup_cycle 6211908000 # Cycle when the warmup percentage was hit. +system.cpu.icache.writebacks 41188 # number of writebacks +system.cpu.idleCycles 69245083 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 10229161 # Number of branches executed +system.cpu.iew.EXEC:nop 166597 # number of nop insts executed +system.cpu.iew.EXEC:rate 0.475852 # Inst execution rate +system.cpu.iew.EXEC:refs 35984402 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 7799191 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 62506487 # num instructions consuming a value -system.cpu.iew.WB:count 60999387 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.509822 # average fanout of values written-back +system.cpu.iew.WB:consumers 62355336 # num instructions consuming a value +system.cpu.iew.WB:count 60877824 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.509736 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 31867154 # num instructions producing a value -system.cpu.iew.WB:rate 0.365866 # insts written-back per cycle -system.cpu.iew.WB:sent 78280633 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 793572 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 21409899 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 12831645 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 4013649 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 440829 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 8731029 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 70887049 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 28150647 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1185759 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 78808302 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 28695 # Number of times the IQ has become full, causing a stall +system.cpu.iew.WB:producers 31784768 # num instructions producing a value +system.cpu.iew.WB:rate 0.368209 # insts written-back per cycle +system.cpu.iew.WB:sent 78147343 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 710642 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 21410172 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 12850597 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 4002212 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 353192 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 8736302 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 70500878 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 28185211 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1060546 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 78674830 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 28770 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 45726 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 2655366 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 263937 # Number of cycles IEW is unblocking +system.cpu.iew.iewLSQFullEvents 45532 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 2568818 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 264100 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread.0.cacheBlocked 8278 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 328988 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 7892 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.cacheBlocked 8285 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread.0.forwLoads 330904 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 7460 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 280623 # Number of memory ordering violations -system.cpu.iew.lsq.thread.0.rescheduledLoads 17006286 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 3621930 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 1646029 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 280623 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 286587 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 506985 # Number of branches that were predicted taken incorrectly -system.cpu.int_regfile_reads 183036764 # number of integer regfile reads -system.cpu.int_regfile_writes 44051569 # number of integer regfile writes -system.cpu.ipc 0.311687 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.311687 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0::No_OpClass 2392951 2.99% 2.99% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntAlu 41025492 51.29% 54.28% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntMult 89631 0.11% 54.39% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 54.39% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 54.39% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 54.39% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 54.39% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 54.39% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 54.39% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 54.39% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 54.39% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 54.39% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAlu 14 0.00% 54.39% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdCmp 1 0.00% 54.39% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 54.39% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 54.39% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 54.39% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 54.39% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 54.39% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 9 0.00% 54.39% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 54.39% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 1 0.00% 54.39% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 54.39% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 1 0.00% 54.39% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 1 0.00% 54.39% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 54.39% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 882 0.00% 54.39% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 54.39% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 10 0.00% 54.39% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 54.39% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemRead 28522924 35.66% 90.05% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemWrite 7962144 9.95% 100.00% # Type of FU issued +system.cpu.iew.lsq.thread.0.memOrderViolation 280975 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.rescheduledLoads 17000760 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread.0.squashedLoads 3646141 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 1651272 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 280975 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 187196 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 523446 # Number of branches that were predicted taken incorrectly +system.cpu.int_regfile_reads 182828391 # number of integer regfile reads +system.cpu.int_regfile_writes 43909645 # number of integer regfile writes +system.cpu.ipc 0.314320 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.314320 # IPC: Total IPC of All Threads +system.cpu.iq.ISSUE:FU_type_0::No_OpClass 2392951 3.00% 3.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntAlu 40765047 51.13% 54.13% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntMult 71833 0.09% 54.22% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 54.22% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 54.22% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 54.22% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 54.22% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 54.22% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 54.22% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 54.22% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 54.22% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 54.22% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 54.22% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdCmp 1 0.00% 54.22% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 54.22% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdMisc 11 0.00% 54.22% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 54.22% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 54.22% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdShift 2 0.00% 54.22% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 9 0.00% 54.22% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 54.22% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 54.22% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 54.22% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 54.22% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 54.22% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 54.22% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 880 0.00% 54.22% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 54.22% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 10 0.00% 54.22% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 54.22% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemRead 28539771 35.79% 90.01% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemWrite 7964861 9.99% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::total 79994061 # Type of FU issued -system.cpu.iq.ISSUE:fu_busy_cnt 4819476 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.060248 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:FU_type_0::total 79735376 # Type of FU issued +system.cpu.iq.ISSUE:fu_busy_cnt 4820944 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.060462 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntAlu 5122 0.11% 0.11% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 0.11% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 0.11% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 0.11% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 0.11% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 0.11% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 0.11% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 0.11% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 0.11% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 0.11% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 0.11% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 0.11% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 0.11% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 0.11% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 0.11% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 0.11% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 0.11% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 0.11% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 0.11% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 0.11% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 0.11% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 0.11% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 0.11% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 0.11% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 0.11% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 0.11% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 0.11% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 0.11% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 0.11% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemRead 4502393 93.42% 93.53% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemWrite 311961 6.47% 100.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntAlu 4959 0.10% 0.10% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 0.10% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 0.10% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 0.10% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 0.10% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 0.10% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 0.10% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 0.10% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 0.10% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 0.10% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 0.10% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 0.10% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 0.10% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 0.10% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 0.10% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 0.10% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 0.10% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 0.10% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 0.10% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 0.10% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 0.10% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 0.10% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 0.10% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 0.10% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 0.10% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 0.10% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 0.10% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 0.10% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 0.10% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemRead 4503516 93.42% 93.52% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemWrite 312469 6.48% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:issued_per_cycle::samples 97448429 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::mean 0.820886 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.375646 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::samples 96089723 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::mean 0.829801 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.378962 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::0 61152445 62.75% 62.75% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::1 16744626 17.18% 79.94% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::2 7216759 7.41% 87.34% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::3 4112834 4.22% 91.56% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::4 5964384 6.12% 97.68% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::5 1312092 1.35% 99.03% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::6 631511 0.65% 99.68% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::7 239871 0.25% 99.92% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::8 73907 0.08% 100.00% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::0 59895094 62.33% 62.33% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::1 16672825 17.35% 79.68% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::2 7219542 7.51% 87.20% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::3 4124127 4.29% 91.49% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::4 5945369 6.19% 97.68% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::5 1307408 1.36% 99.04% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::6 617440 0.64% 99.68% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::7 235414 0.24% 99.92% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::8 72504 0.08% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::total 97448429 # Number of insts issued each cycle -system.cpu.iq.ISSUE:rate 0.479793 # Inst issue rate -system.cpu.iq.fp_alu_accesses 8478 # Number of floating point alu accesses -system.cpu.iq.fp_inst_queue_reads 16113 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_wakeup_accesses 6290 # Number of floating instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_writes 9126 # Number of floating instruction queue writes -system.cpu.iq.int_alu_accesses 82412108 # Number of integer alu accesses -system.cpu.iq.int_inst_queue_reads 262450164 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_wakeup_accesses 60993097 # Number of integer instruction queue wakeup accesses -system.cpu.iq.int_inst_queue_writes 88832185 # Number of integer instruction queue writes -system.cpu.iq.iqInstsAdded 66612352 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 79994061 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 4043230 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 17919898 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 129886 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 1080226 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 22542223 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.itb.accesses 6629825 # DTB accesses +system.cpu.iq.ISSUE:issued_per_cycle::total 96089723 # Number of insts issued each cycle +system.cpu.iq.ISSUE:rate 0.482266 # Inst issue rate +system.cpu.iq.fp_alu_accesses 8546 # Number of floating point alu accesses +system.cpu.iq.fp_inst_queue_reads 16333 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_wakeup_accesses 6331 # Number of floating instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_writes 9298 # Number of floating instruction queue writes +system.cpu.iq.int_alu_accesses 82154823 # Number of integer alu accesses +system.cpu.iq.int_inst_queue_reads 260564966 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_wakeup_accesses 60871493 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_writes 88267100 # Number of integer instruction queue writes +system.cpu.iq.iqInstsAdded 66302141 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 79735376 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 4032140 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 17675893 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 127840 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 1069091 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 22304285 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.itb.accesses 6563470 # DTB accesses system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.flush_entries 1593 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 1619 # Number of entries that have been flushed from TLB system.cpu.itb.flush_tlb 2 # Number of times complete TLB was flushed system.cpu.itb.flush_tlb_asid 40 # Number of times TLB was flushed by ASID system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 33670 # Number of times TLB was flushed by MVA & ASID -system.cpu.itb.hits 6621818 # DTB hits -system.cpu.itb.inst_accesses 6629825 # ITB inst accesses -system.cpu.itb.inst_hits 6621818 # ITB inst hits -system.cpu.itb.inst_misses 8007 # ITB inst misses -system.cpu.itb.misses 8007 # DTB misses -system.cpu.itb.perms_faults 6553 # Number of TLB faults due to permissions restrictions +system.cpu.itb.hits 6556387 # DTB hits +system.cpu.itb.inst_accesses 6563470 # ITB inst accesses +system.cpu.itb.inst_hits 6556387 # ITB inst hits +system.cpu.itb.inst_misses 7083 # ITB inst misses +system.cpu.itb.misses 7083 # DTB misses +system.cpu.itb.perms_faults 5304 # Number of TLB faults due to permissions restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.read_hits 0 # DTB read hits @@ -510,37 +508,37 @@ system.cpu.itb.write_hits 0 # DT system.cpu.itb.write_misses 0 # DTB write misses system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu.memDep0.conflictingLoads 3412 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 10055 # Number of conflicting stores. -system.cpu.memDep0.insertedLoads 12831645 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 8731029 # Number of stores inserted to the mem dependence unit. -system.cpu.misc_regfile_reads 85580617 # number of misc regfile reads -system.cpu.misc_regfile_writes 661928 # number of misc regfile writes -system.cpu.numCycles 166726252 # number of cpu cycles simulated +system.cpu.memDep0.conflictingLoads 3483 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 10121 # Number of conflicting stores. +system.cpu.memDep0.insertedLoads 12850597 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 8736302 # Number of stores inserted to the mem dependence unit. +system.cpu.misc_regfile_reads 84311208 # number of misc regfile reads +system.cpu.misc_regfile_writes 505887 # number of misc regfile writes +system.cpu.numCycles 165334806 # number of cpu cycles simulated system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.rename.RENAME:BlockCycles 33115020 # Number of cycles rename is blocking -system.cpu.rename.RENAME:CommittedMaps 36897186 # Number of HB maps that are committed -system.cpu.rename.RENAME:IQFullEvents 774970 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 25771675 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 2462995 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:ROBFullEvents 448472 # Number of times rename has blocked due to ROB full -system.cpu.rename.RENAME:RenameLookups 192653284 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 74465658 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 54282132 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 13171967 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 2655366 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 5478763 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 17384945 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:fp_rename_lookups 47581 # Number of floating rename lookups -system.cpu.rename.RENAME:int_rename_lookups 192605703 # Number of integer rename lookups -system.cpu.rename.RENAME:serializeStallCycles 17255638 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 861623 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 14920123 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 719344 # count of temporary serializing insts renamed -system.cpu.rob.rob_reads 161714856 # The number of ROB reads -system.cpu.rob.rob_writes 140047516 # The number of ROB writes -system.cpu.timesIdled 1095909 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.rename.RENAME:BlockCycles 33117946 # Number of cycles rename is blocking +system.cpu.rename.RENAME:CommittedMaps 36733346 # Number of HB maps that are committed +system.cpu.rename.RENAME:IQFullEvents 775449 # Number of times rename has blocked due to IQ full +system.cpu.rename.RENAME:IdleCycles 25568402 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 2466412 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:ROBFullEvents 439285 # Number of times rename has blocked due to ROB full +system.cpu.rename.RENAME:RenameLookups 190546876 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 73646302 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 53333432 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 13047340 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 2568818 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 5448397 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 16600085 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:fp_rename_lookups 49406 # Number of floating rename lookups +system.cpu.rename.RENAME:int_rename_lookups 190497470 # Number of integer rename lookups +system.cpu.rename.RENAME:serializeStallCycles 16338820 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 812667 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 14273675 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 662897 # count of temporary serializing insts renamed +system.cpu.rob.rob_reads 160028013 # The number of ROB reads +system.cpu.rob.rob_writes 139108925 # The number of ROB writes +system.cpu.timesIdled 1092643 # Number of times that the entire CPU went into an idle state and unscheduled itself system.iocache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.iocache.avg_refs no_value # Average number of references to valid blocks. @@ -608,143 +606,141 @@ system.iocache.tagsinuse 0 # Cy system.iocache.total_refs 0 # Total number of references to valid blocks. system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.iocache.writebacks 0 # number of writebacks -system.l2c.LoadLockedReq_avg_mshr_uncacheable_latency inf # average LoadLockedReq mshr uncacheable latency -system.l2c.LoadLockedReq_mshr_uncacheable_latency 234200000 # number of LoadLockedReq MSHR uncacheable cycles -system.l2c.ReadExReq_accesses::0 168831 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 168831 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_avg_miss_latency::0 52452.308619 # average ReadExReq miss latency +system.l2c.ReadExReq_accesses::0 168856 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 168856 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_avg_miss_latency::0 52453.278430 # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::1 inf # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::total inf # average ReadExReq miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency 40012.249340 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_hits::0 60866 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 60866 # number of ReadExReq hits -system.l2c.ReadExReq_miss_latency 5663013500 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_rate::0 0.639486 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_misses::0 107965 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 107965 # number of ReadExReq misses -system.l2c.ReadExReq_mshr_miss_latency 4319922500 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_rate::0 0.639486 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_avg_mshr_miss_latency 40012.348538 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_hits::0 60908 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 60908 # number of ReadExReq hits +system.l2c.ReadExReq_miss_latency 5662226500 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_rate::0 0.639290 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_misses::0 107948 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 107948 # number of ReadExReq misses +system.l2c.ReadExReq_mshr_miss_latency 4319253000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_rate::0 0.639290 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::1 inf # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::total inf # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_misses 107965 # number of ReadExReq MSHR misses -system.l2c.ReadReq_accesses::0 760970 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::1 118352 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 879322 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_avg_miss_latency::0 52680.502591 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::1 6692714.285714 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 6745394.788305 # average ReadReq miss latency -system.l2c.ReadReq_avg_mshr_miss_latency 40041.751725 # average ReadReq mshr miss latency +system.l2c.ReadExReq_mshr_misses 107948 # number of ReadExReq MSHR misses +system.l2c.ReadReq_accesses::0 753810 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::1 101430 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 855240 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_avg_miss_latency::0 52702.508435 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::1 6230167.630058 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 6282870.138493 # average ReadReq miss latency +system.l2c.ReadReq_avg_mshr_miss_latency 40041.091563 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_hits::0 740516 # number of ReadReq hits -system.l2c.ReadReq_hits::1 118191 # number of ReadReq hits -system.l2c.ReadReq_hits::total 858707 # number of ReadReq hits -system.l2c.ReadReq_miss_latency 1077527000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_rate::0 0.026879 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::1 0.001360 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.028239 # miss rate for ReadReq accesses -system.l2c.ReadReq_misses::0 20454 # number of ReadReq misses -system.l2c.ReadReq_misses::1 161 # number of ReadReq misses -system.l2c.ReadReq_misses::total 20615 # number of ReadReq misses -system.l2c.ReadReq_mshr_hits 41 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_miss_latency 823819000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_rate::0 0.027037 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::1 0.173837 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.200874 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_misses 20574 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_uncacheable_latency 28941133500 # number of ReadReq MSHR uncacheable cycles -system.l2c.UpgradeReq_accesses::0 1757 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 1757 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_avg_miss_latency::0 817.335660 # average UpgradeReq miss latency +system.l2c.ReadReq_hits::0 733359 # number of ReadReq hits +system.l2c.ReadReq_hits::1 101257 # number of ReadReq hits +system.l2c.ReadReq_hits::total 834616 # number of ReadReq hits +system.l2c.ReadReq_miss_latency 1077819000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_rate::0 0.027130 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::1 0.001706 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.028836 # miss rate for ReadReq accesses +system.l2c.ReadReq_misses::0 20451 # number of ReadReq misses +system.l2c.ReadReq_misses::1 173 # number of ReadReq misses +system.l2c.ReadReq_misses::total 20624 # number of ReadReq misses +system.l2c.ReadReq_mshr_hits 48 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_miss_latency 823885500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_rate::0 0.027296 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::1 0.202859 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.230155 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_misses 20576 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_uncacheable_latency 28941115500 # number of ReadReq MSHR uncacheable cycles +system.l2c.UpgradeReq_accesses::0 1732 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 1732 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_avg_miss_latency::0 396.713615 # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::1 inf # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::total inf # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency 40000.581734 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_hits::0 38 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 38 # number of UpgradeReq hits -system.l2c.UpgradeReq_miss_latency 1405000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_rate::0 0.978372 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_misses::0 1719 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 1719 # number of UpgradeReq misses -system.l2c.UpgradeReq_mshr_miss_latency 68761000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_rate::0 0.978372 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_hits::0 28 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 28 # number of UpgradeReq hits +system.l2c.UpgradeReq_miss_latency 676000 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_rate::0 0.983834 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_misses::0 1704 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 1704 # number of UpgradeReq misses +system.l2c.UpgradeReq_mshr_miss_latency 68160000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_rate::0 0.983834 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::1 inf # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::total inf # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_misses 1719 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses 1704 # number of UpgradeReq MSHR misses system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_mshr_uncacheable_latency 746054947 # number of WriteReq MSHR uncacheable cycles -system.l2c.Writeback_accesses::0 432382 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 432382 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_hits::0 432382 # number of Writeback hits -system.l2c.Writeback_hits::total 432382 # number of Writeback hits +system.l2c.WriteReq_mshr_uncacheable_latency 745824450 # number of WriteReq MSHR uncacheable cycles +system.l2c.Writeback_accesses::0 432494 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 432494 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_hits::0 432494 # number of Writeback hits +system.l2c.Writeback_hits::total 432494 # number of Writeback hits system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.l2c.avg_refs 8.321857 # Average number of references to valid blocks. +system.l2c.avg_refs 8.116644 # Average number of references to valid blocks. system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked::no_targets 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.demand_accesses::0 929801 # number of demand (read+write) accesses -system.l2c.demand_accesses::1 118352 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 1048153 # number of demand (read+write) accesses -system.l2c.demand_avg_miss_latency::0 52488.654327 # average overall miss latency -system.l2c.demand_avg_miss_latency::1 41866711.180124 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 41919199.834451 # average overall miss latency -system.l2c.demand_avg_mshr_miss_latency 40016.971503 # average overall mshr miss latency -system.l2c.demand_hits::0 801382 # number of demand (read+write) hits -system.l2c.demand_hits::1 118191 # number of demand (read+write) hits -system.l2c.demand_hits::total 919573 # number of demand (read+write) hits -system.l2c.demand_miss_latency 6740540500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_rate::0 0.138114 # miss rate for demand accesses -system.l2c.demand_miss_rate::1 0.001360 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.139475 # miss rate for demand accesses -system.l2c.demand_misses::0 128419 # number of demand (read+write) misses -system.l2c.demand_misses::1 161 # number of demand (read+write) misses -system.l2c.demand_misses::total 128580 # number of demand (read+write) misses -system.l2c.demand_mshr_hits 41 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_miss_latency 5143741500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_rate::0 0.138244 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::1 1.086074 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 1.224317 # mshr miss rate for demand accesses -system.l2c.demand_mshr_misses 128539 # number of demand (read+write) MSHR misses +system.l2c.demand_accesses::0 922666 # number of demand (read+write) accesses +system.l2c.demand_accesses::1 101430 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 1024096 # number of demand (read+write) accesses +system.l2c.demand_avg_miss_latency::0 52492.975023 # average overall miss latency +system.l2c.demand_avg_miss_latency::1 38959800.578035 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 39012293.553058 # average overall miss latency +system.l2c.demand_avg_mshr_miss_latency 40016.950142 # average overall mshr miss latency +system.l2c.demand_hits::0 794267 # number of demand (read+write) hits +system.l2c.demand_hits::1 101257 # number of demand (read+write) hits +system.l2c.demand_hits::total 895524 # number of demand (read+write) hits +system.l2c.demand_miss_latency 6740045500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_rate::0 0.139161 # miss rate for demand accesses +system.l2c.demand_miss_rate::1 0.001706 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.140866 # miss rate for demand accesses +system.l2c.demand_misses::0 128399 # number of demand (read+write) misses +system.l2c.demand_misses::1 173 # number of demand (read+write) misses +system.l2c.demand_misses::total 128572 # number of demand (read+write) misses +system.l2c.demand_mshr_hits 48 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_miss_latency 5143138500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_rate::0 0.139296 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::1 1.267120 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 1.406417 # mshr miss rate for demand accesses +system.l2c.demand_mshr_misses 128524 # number of demand (read+write) MSHR misses system.l2c.fast_writes 0 # number of fast writes performed system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.occ_%::0 0.099437 # Average percentage of cache occupancy -system.l2c.occ_%::1 0.480717 # Average percentage of cache occupancy -system.l2c.occ_blocks::0 6516.698147 # Average occupied blocks per context -system.l2c.occ_blocks::1 31504.278077 # Average occupied blocks per context -system.l2c.overall_accesses::0 929801 # number of overall (read+write) accesses -system.l2c.overall_accesses::1 118352 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 1048153 # number of overall (read+write) accesses -system.l2c.overall_avg_miss_latency::0 52488.654327 # average overall miss latency -system.l2c.overall_avg_miss_latency::1 41866711.180124 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 41919199.834451 # average overall miss latency -system.l2c.overall_avg_mshr_miss_latency 40016.971503 # average overall mshr miss latency +system.l2c.occ_%::0 0.099484 # Average percentage of cache occupancy +system.l2c.occ_%::1 0.481769 # Average percentage of cache occupancy +system.l2c.occ_blocks::0 6519.756785 # Average occupied blocks per context +system.l2c.occ_blocks::1 31573.183682 # Average occupied blocks per context +system.l2c.overall_accesses::0 922666 # number of overall (read+write) accesses +system.l2c.overall_accesses::1 101430 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 1024096 # number of overall (read+write) accesses +system.l2c.overall_avg_miss_latency::0 52492.975023 # average overall miss latency +system.l2c.overall_avg_miss_latency::1 38959800.578035 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 39012293.553058 # average overall miss latency +system.l2c.overall_avg_mshr_miss_latency 40016.950142 # average overall mshr miss latency system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.l2c.overall_hits::0 801382 # number of overall hits -system.l2c.overall_hits::1 118191 # number of overall hits -system.l2c.overall_hits::total 919573 # number of overall hits -system.l2c.overall_miss_latency 6740540500 # number of overall miss cycles -system.l2c.overall_miss_rate::0 0.138114 # miss rate for overall accesses -system.l2c.overall_miss_rate::1 0.001360 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.139475 # miss rate for overall accesses -system.l2c.overall_misses::0 128419 # number of overall misses -system.l2c.overall_misses::1 161 # number of overall misses -system.l2c.overall_misses::total 128580 # number of overall misses -system.l2c.overall_mshr_hits 41 # number of overall MSHR hits -system.l2c.overall_mshr_miss_latency 5143741500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_rate::0 0.138244 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::1 1.086074 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 1.224317 # mshr miss rate for overall accesses -system.l2c.overall_mshr_misses 128539 # number of overall MSHR misses -system.l2c.overall_mshr_uncacheable_latency 29687188447 # number of overall MSHR uncacheable cycles +system.l2c.overall_hits::0 794267 # number of overall hits +system.l2c.overall_hits::1 101257 # number of overall hits +system.l2c.overall_hits::total 895524 # number of overall hits +system.l2c.overall_miss_latency 6740045500 # number of overall miss cycles +system.l2c.overall_miss_rate::0 0.139161 # miss rate for overall accesses +system.l2c.overall_miss_rate::1 0.001706 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.140866 # miss rate for overall accesses +system.l2c.overall_misses::0 128399 # number of overall misses +system.l2c.overall_misses::1 173 # number of overall misses +system.l2c.overall_misses::total 128572 # number of overall misses +system.l2c.overall_mshr_hits 48 # number of overall MSHR hits +system.l2c.overall_mshr_miss_latency 5143138500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_rate::0 0.139296 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::1 1.267120 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 1.406417 # mshr miss rate for overall accesses +system.l2c.overall_mshr_misses 128524 # number of overall MSHR misses +system.l2c.overall_mshr_uncacheable_latency 29686939950 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.l2c.replacements 94739 # number of replacements -system.l2c.sampled_refs 127041 # Sample count of references to valid blocks. +system.l2c.replacements 94736 # number of replacements +system.l2c.sampled_refs 127028 # Sample count of references to valid blocks. system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.l2c.tagsinuse 38020.976224 # Cycle average of tags in use -system.l2c.total_refs 1057217 # Total number of references to valid blocks. +system.l2c.tagsinuse 38092.940467 # Cycle average of tags in use +system.l2c.total_refs 1031041 # Total number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.writebacks 87634 # number of writebacks +system.l2c.writebacks 87630 # number of writebacks ---------- End Simulation Statistics ---------- diff --git a/tests/long/10.linux-boot/ref/arm/linux/realview-o3/status b/tests/long/10.linux-boot/ref/arm/linux/realview-o3/status index f27ebe211..cffda2d37 100644 --- a/tests/long/10.linux-boot/ref/arm/linux/realview-o3/status +++ b/tests/long/10.linux-boot/ref/arm/linux/realview-o3/status @@ -1 +1 @@ -build/ARM_FS/tests/fast/long/10.linux-boot/arm/linux/realview-o3 FAILED! +build/ARM_FS/tests/opt/long/10.linux-boot/arm/linux/realview-o3 FAILED! diff --git a/tests/long/10.linux-boot/ref/arm/linux/realview-o3/system.terminal b/tests/long/10.linux-boot/ref/arm/linux/realview-o3/system.terminal Binary files differindex 5219ab85a..855723281 100644 --- a/tests/long/10.linux-boot/ref/arm/linux/realview-o3/system.terminal +++ b/tests/long/10.linux-boot/ref/arm/linux/realview-o3/system.terminal diff --git a/tests/long/10.mcf/ref/arm/linux/o3-timing/chair.cook.ppm b/tests/long/10.mcf/ref/arm/linux/o3-timing/chair.cook.ppm new file mode 100644 index 000000000..9ac19076f --- /dev/null +++ b/tests/long/10.mcf/ref/arm/linux/o3-timing/chair.cook.ppm @@ -0,0 +1,4 @@ +P6 +15 15 +255 +
!!! !!!$$$&&&'''&&&%%%
!!!%%%(((******)))(((!!! ###'''***+++,,,+++)))""" ###''')))++++++***)))!!! !!!%%%((()))))))))''' """%%%&&&'''&&&%%% %%% !!!"""#########"""(((---222666&&&...///===;;;999555111,,,((($$$DDDKKKRRRXXXBBB†††‘‘‘jjjWWWZZZUUUNNNGGG???888[[[dddkkkrrr]]]CCC===eeeaaarrrkkkddd[[[SSSKKKiiipppvvvvvvEEE ggg{{{uuunnnfff^^^VVVmmmsssxxx|||oooEEEDDD]]]vvvzzzuuuooohhhaaaZZZjjjooossswwwyyyzzzzzzyyywwwtttoookkkeee```ZZZeeeiiilllnnnpppppppppooonnnkkkhhhddd```\\\WWW
\ No newline at end of file diff --git a/tests/long/10.mcf/ref/arm/linux/o3-timing/config.ini b/tests/long/10.mcf/ref/arm/linux/o3-timing/config.ini index 4906aee98..24945daa3 100644 --- a/tests/long/10.mcf/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/10.mcf/ref/arm/linux/o3-timing/config.ini @@ -25,6 +25,8 @@ BTBEntries=4096 BTBTagSize=16 LFSTSize=1024 LQEntries=32 +LSQCheckLoads=true +LSQDepCheckShift=4 RASSize=16 SQEntries=32 SSITSize=1024 @@ -491,14 +493,14 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=mcf mcf.in -cwd=build/ARM_SE/tests/fast/long/10.mcf/arm/linux/o3-timing +cwd=build/ARM_SE/tests/opt/long/10.mcf/arm/linux/o3-timing egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/arm/linux/mcf +executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/mcf gid=100 -input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in +input=/chips/pd/randd/dist/cpu2000/data/mcf/smred/input/mcf.in max_stack_size=67108864 output=cout pid=100 diff --git a/tests/long/10.mcf/ref/arm/linux/o3-timing/mcf.out b/tests/long/10.mcf/ref/arm/linux/o3-timing/mcf.out new file mode 100644 index 000000000..095132477 --- /dev/null +++ b/tests/long/10.mcf/ref/arm/linux/o3-timing/mcf.out @@ -0,0 +1,999 @@ +() +500 +() +499 +() +498 +() +496 +() +495 +() +494 +() +493 +() +492 +() +491 +() +490 +() +489 +() +488 +() +487 +() +486 +() +484 +() +482 +() +481 +() +480 +() +479 +() +478 +() +477 +() +476 +() +475 +() +474 +() +473 +() +472 +() +471 +() +469 +() +468 +() +467 +() +466 +() +465 +() +464 +() +463 +() +462 +() +461 +() +460 +() +459 +() +458 +() +457 +() +455 +() +454 +() +452 +() +451 +() +450 +() +449 +() +448 +() +446 +() +445 +() +444 +() +443 +() +442 +() +440 +() +439 +() +438 +() +436 +() +435 +() +433 +() +432 +() +431 +() +428 +() +427 +() +425 +() +424 +() +423 +() +420 +() +419 +() +416 +() +414 +() +413 +() +412 +() +407 +() +406 +() +405 +() +404 +() +403 +() +402 +() +401 +() +400 +() +399 +() +398 +() +396 +() +395 +() +393 +() +392 +() +390 +() +389 +() +388 +() +387 +() +386 +() +385 +() +384 +() +383 +() +382 +() +381 +() +380 +() +379 +() +377 +() +375 +() +374 +() +373 +() +372 +() +371 +() +370 +() +369 +() +368 +() +366 +() +365 +() +364 +() +362 +() +361 +() +360 +() +359 +() +358 +() +357 +() +356 +() +355 +() +354 +() +352 +() +350 +() +347 +() +344 +() +342 +() +341 +() +340 +() +339 +() +338 +() +332 +() +325 +() +320 +*** +345 +() +319 +*** +497 +() +318 +*** +349 +() +317 +*** +408 +() +316 +*** +324 +() +315 +*** +328 +() +314 +*** +335 +() +313 +*** +378 +() +312 +*** +426 +() +311 +*** +411 +() +304 +*** +343 +() +303 +*** +417 +() +302 +*** +485 +() +301 +*** +363 +() +300 +*** +376 +() +299 +*** +333 +() +292 +*** +337 +() +291 +*** +409 +() +290 +*** +421 +() +289 +*** +437 +() +288 +*** +430 +() +287 +*** +348 +() +286 +*** +326 +() +284 +() +282 +*** +308 +() +279 +*** +297 +*** +305 +() +278 +() +277 +*** +307 +() +276 +*** +296 +() +273 +() +271 +() +265 +() +246 +*** +267 +() +245 +*** +280 +() +244 +*** +391 +() +243 +*** +330 +() +242 +*** +456 +() +241 +*** +346 +() +240 +*** +483 +() +239 +*** +260 +() +238 +*** +261 +() +237 +*** +262 +*** +294 +() +236 +*** +253 +() +229 +*** +397 +() +228 +*** +298 +() +227 +*** +415 +() +226 +*** +264 +() +224 +*** +232 +() +222 +*** +233 +() +217 +*** +250 +() +211 +*** +331 +() +210 +*** +394 +() +209 +*** +410 +() +208 +*** +321 +() +207 +*** +327 +() +206 +*** +309 +() +199 +*** +259 +() +198 +*** +219 +() +197 +*** +220 +() +195 +*** +429 +() +194 +*** +470 +() +193 +*** +274 +() +191 +*** +203 +() +190 +*** +263 +() +189 +215 +*** +230 +() +188 +*** +266 +*** +295 +() +182 +*** +329 +() +181 +*** +351 +() +180 +*** +441 +() +179 +*** +453 +() +178 +*** +418 +() +177 +*** +353 +() +176 +*** +422 +() +175 +*** +225 +*** +255 +() +174 +*** +269 +() +173 +*** +214 +() +172 +*** +186 +() +171 +*** +447 +() +170 +*** +270 +*** +306 +() +169 +*** +336 +() +168 +*** +285 +() +165 +*** +249 +() +146 +*** +154 +() +143 +*** +334 +() +142 +*** +216 +*** +257 +() +141 +*** +167 +*** +251 +() +140 +*** +162 +*** +293 +() +139 +*** +158 +() +137 +*** +166 +*** +201 +() +136 +*** +160 +() +134 +*** +221 +() +132 +*** +213 +() +131 +*** +187 +() +129 +*** +235 +() +128 +*** +153 +() +127 +*** +156 +() +126 +*** +159 +*** +218 +() +125 +*** +155 +() +124 +*** +157 +() +123 +*** +152 +() +116 +*** +135 +*** +163 +() +115 +*** +133 +*** +204 +*** +248 +() +114 +*** +192 +*** +212 +() +113 +*** +268 +() +112 +*** +367 +() +111 +*** +272 +() +110 +*** +434 +() +109 +*** +323 +() +108 +*** +281 +() +107 +*** +144 +*** +148 +() +106 +*** +275 +() +105 +*** +196 +*** +254 +() +104 +*** +138 +*** +161 +() +103 +*** +310 +() +102 +*** +223 +*** +252 +() +80 +() +70 +() +69 +() +68 +() +66 +() +64 +() +62 +*** +256 +() +61 +*** +93 +() +59 +*** +120 +() +58 +() +57 +*** +183 +() +55 +() +54 +() +52 +*** +147 +() +51 +*** +118 +() +50 +*** +83 +() +49 +*** +98 +() +48 +*** +99 +() +47 +() +46 +*** +184 +() +45 +*** +121 +() +44 +() +43 +*** +88 +() +42 +*** +122 +() +41 +*** +91 +() +40 +*** +96 +() +38 +*** +100 +() +37 +*** +149 +() +36 +*** +74 +() +35 +*** +258 +() +34 +*** +151 +() +33 +*** +85 +() +32 +() +31 +*** +94 +() +30 +*** +97 +() +29 +*** +90 +() +28 +*** +89 +() +27 +*** +92 +() +26 +*** +72 +*** +247 +() +25 +*** +86 +() +24 +*** +82 +() +23 +*** +87 +*** +117 +() +22 +*** +76 +*** +119 +() +21 +*** +84 +() +20 +*** +78 +() +19 +*** +73 +() +18 +*** +81 +() +17 +*** +65 +() +16 +*** +63 +*** +101 +() +15 +*** +71 +() +14 +*** +75 +() +13 +*** +322 +() +12 +*** +77 +() +11 +*** +283 +() +10 +*** +79 +() +9 +*** +145 +*** +150 +() +8 +*** +67 +() +7 +*** +60 +*** +231 +() +6 +*** +56 +*** +234 +() +5 +*** +164 +*** +202 +() +4 +*** +53 +() +3 +*** +130 +*** +185 +*** +200 +() +2 +*** +205 +() +1 +*** +39 +*** +95 diff --git a/tests/long/10.mcf/ref/arm/linux/o3-timing/simout b/tests/long/10.mcf/ref/arm/linux/o3-timing/simout index 800a14f70..9a7a71365 100755 --- a/tests/long/10.mcf/ref/arm/linux/o3-timing/simout +++ b/tests/long/10.mcf/ref/arm/linux/o3-timing/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Mar 18 2011 20:12:03 -M5 started Mar 18 2011 20:50:23 -M5 executing on zizzer -command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/10.mcf/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/fast/long/10.mcf/arm/linux/o3-timing +M5 compiled Mar 30 2011 17:47:57 +M5 started Mar 30 2011 17:54:33 +M5 executing on u200439-lin.austin.arm.com +command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/10.mcf/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/opt/long/10.mcf/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -27,4 +27,4 @@ simplex iterations : 2663 flow value : 3080014995 checksum : 68389 optimal -Exiting @ tick 44810819000 because target called exit() +Exiting @ tick 44794736000 because target called exit() diff --git a/tests/long/10.mcf/ref/arm/linux/o3-timing/stats.txt b/tests/long/10.mcf/ref/arm/linux/o3-timing/stats.txt index 59d8e7864..280797690 100644 --- a/tests/long/10.mcf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/10.mcf/ref/arm/linux/o3-timing/stats.txt @@ -1,142 +1,142 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 152339 # Simulator instruction rate (inst/s) -host_mem_usage 354000 # Number of bytes of host memory used -host_seconds 598.99 # Real time elapsed on the host -host_tick_rate 74810841 # Simulator tick rate (ticks/s) +host_inst_rate 64138 # Simulator instruction rate (inst/s) +host_mem_usage 388624 # Number of bytes of host memory used +host_seconds 1422.72 # Real time elapsed on the host +host_tick_rate 31485248 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 91249440 # Number of instructions simulated -sim_seconds 0.044811 # Number of seconds simulated -sim_ticks 44810819000 # Number of ticks simulated +sim_insts 91249905 # Number of instructions simulated +sim_seconds 0.044795 # Number of seconds simulated +sim_ticks 44794736000 # Number of ticks simulated system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.BTBHits 24834182 # Number of BTB hits -system.cpu.BPredUnit.BTBLookups 26488589 # Number of BTB lookups -system.cpu.BPredUnit.RASInCorrect 13381 # Number of incorrect RAS predictions. -system.cpu.BPredUnit.condIncorrect 1577083 # Number of conditional branches incorrect -system.cpu.BPredUnit.condPredicted 23759439 # Number of conditional branches predicted -system.cpu.BPredUnit.lookups 29547808 # Number of BP lookups -system.cpu.BPredUnit.usedRAS 61655 # Number of times the RAS was used to get a target. -system.cpu.commit.COM:branches 18706964 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 663516 # number cycles where commit BW limit reached +system.cpu.BPredUnit.BTBHits 24857865 # Number of BTB hits +system.cpu.BPredUnit.BTBLookups 26546272 # Number of BTB lookups +system.cpu.BPredUnit.RASInCorrect 12880 # Number of incorrect RAS predictions. +system.cpu.BPredUnit.condIncorrect 1596208 # Number of conditional branches incorrect +system.cpu.BPredUnit.condPredicted 23792873 # Number of conditional branches predicted +system.cpu.BPredUnit.lookups 29586235 # Number of BP lookups +system.cpu.BPredUnit.usedRAS 63032 # Number of times the RAS was used to get a target. +system.cpu.commit.COM:branches 18722470 # Number of branches committed +system.cpu.commit.COM:bw_lim_events 671558 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle::samples 84127548 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::mean 1.084806 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::stdev 1.485867 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::samples 84101876 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::mean 1.085142 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::stdev 1.487392 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::0 39814306 47.33% 47.33% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::1 21951452 26.09% 73.42% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::2 9558270 11.36% 84.78% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::3 7643193 9.09% 93.87% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::4 2705607 3.22% 97.08% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::5 250022 0.30% 97.38% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::6 904462 1.08% 98.45% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::7 636720 0.76% 99.21% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::8 663516 0.79% 100.00% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::0 39810013 47.34% 47.34% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::1 21942954 26.09% 73.43% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::2 9544341 11.35% 84.77% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::3 7643789 9.09% 93.86% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::4 2702545 3.21% 97.08% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::5 240327 0.29% 97.36% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::6 909211 1.08% 98.44% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::7 637138 0.76% 99.20% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::8 671558 0.80% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::total 84127548 # Number of insts commited each cycle -system.cpu.commit.COM:count 91262049 # Number of instructions committed +system.cpu.commit.COM:committed_per_cycle::total 84101876 # Number of insts commited each cycle +system.cpu.commit.COM:count 91262514 # Number of instructions committed system.cpu.commit.COM:fp_insts 48 # Number of committed floating point instructions. system.cpu.commit.COM:function_calls 56148 # Number of function calls committed. -system.cpu.commit.COM:int_insts 72532946 # Number of committed integer instructions. -system.cpu.commit.COM:loads 22575783 # Number of loads committed +system.cpu.commit.COM:int_insts 72533318 # Number of committed integer instructions. +system.cpu.commit.COM:loads 22575876 # Number of loads committed system.cpu.commit.COM:membars 3888 # Number of memory barriers committed -system.cpu.commit.COM:refs 27322443 # Number of memory references committed +system.cpu.commit.COM:refs 27322629 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 1596327 # The number of times a branch was mispredicted -system.cpu.commit.commitCommittedInsts 91262049 # The number of committed instructions -system.cpu.commit.commitNonSpecStalls 554313 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 37919647 # The number of squashed insts skipped by commit -system.cpu.committedInsts 91249440 # Number of Instructions Simulated -system.cpu.committedInsts_total 91249440 # Number of Instructions Simulated -system.cpu.cpi 0.982161 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.982161 # CPI: Total CPI of All Threads -system.cpu.dcache.LoadLockedReq_accesses 6690 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_avg_miss_latency 17714.285714 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_hits 6683 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_miss_latency 124000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_rate 0.001046 # miss rate for LoadLockedReq accesses +system.cpu.commit.branchMispredicts 1599456 # The number of times a branch was mispredicted +system.cpu.commit.commitCommittedInsts 91262514 # The number of committed instructions +system.cpu.commit.commitNonSpecStalls 554406 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.commitSquashedInsts 37771309 # The number of squashed insts skipped by commit +system.cpu.committedInsts 91249905 # Number of Instructions Simulated +system.cpu.committedInsts_total 91249905 # Number of Instructions Simulated +system.cpu.cpi 0.981803 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.981803 # CPI: Total CPI of All Threads +system.cpu.dcache.LoadLockedReq_accesses 6763 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_avg_miss_latency 17642.857143 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_hits 6756 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_miss_latency 123500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_rate 0.001035 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_misses 7 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_mshr_hits 7 # number of LoadLockedReq MSHR hits -system.cpu.dcache.ReadReq_accesses 24486290 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 5359.849313 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2292.924521 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 23465767 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 5469849500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.041677 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 1020523 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 105108 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 2098977500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.037385 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 915415 # number of ReadReq MSHR misses -system.cpu.dcache.StoreCondReq_accesses 5703 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_hits 5703 # number of StoreCondReq hits +system.cpu.dcache.ReadReq_accesses 24496209 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 5358.863391 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2291.343120 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 23475471 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 5469995500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.041669 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 1020738 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 105235 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 2097731500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.037373 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 915503 # number of ReadReq MSHR misses +system.cpu.dcache.StoreCondReq_accesses 5796 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_hits 5796 # number of StoreCondReq hits system.cpu.dcache.WriteReq_accesses 4734981 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 26966.662287 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 29146.815533 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 4581638 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 4135148895 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.032385 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 153343 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 118616 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 1012181463 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.007334 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 34727 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles::no_mshrs 2888.268241 # average number of cycles each access was blocked +system.cpu.dcache.WriteReq_avg_miss_latency 26966.230972 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 29153.525857 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 4581642 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 4134974891 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.032384 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 153339 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 118609 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 1012501953 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.007335 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 34730 # number of WriteReq MSHR misses +system.cpu.dcache.avg_blocked_cycles::no_mshrs 2888.334667 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 29.532208 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 29.539803 # Average number of references to valid blocks. system.cpu.dcache.blocked::no_mshrs 7497 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_mshrs 21653347 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_mshrs 21653845 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 29221271 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 8182.363570 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 3274.414733 # average overall mshr miss latency -system.cpu.dcache.demand_hits 28047405 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 9604998395 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.040172 # miss rate for demand accesses -system.cpu.dcache.demand_misses 1173866 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 223724 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 3111158963 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.032515 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 950142 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_accesses 29231190 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 8180.869220 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 3273.127173 # average overall mshr miss latency +system.cpu.dcache.demand_hits 28057113 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 9604970391 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.040165 # miss rate for demand accesses +system.cpu.dcache.demand_misses 1174077 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 223844 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 3110233453 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.032508 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 950233 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.852969 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 3493.759701 # Average occupied blocks per context -system.cpu.dcache.overall_accesses 29221271 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 8182.363570 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 3274.414733 # average overall mshr miss latency +system.cpu.dcache.occ_%::0 0.852828 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 3493.184851 # Average occupied blocks per context +system.cpu.dcache.overall_accesses 29231190 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 8180.869220 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 3273.127173 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 28047405 # number of overall hits -system.cpu.dcache.overall_miss_latency 9604998395 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.040172 # miss rate for overall accesses -system.cpu.dcache.overall_misses 1173866 # number of overall misses -system.cpu.dcache.overall_mshr_hits 223724 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 3111158963 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.032515 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 950142 # number of overall MSHR misses +system.cpu.dcache.overall_hits 28057113 # number of overall hits +system.cpu.dcache.overall_miss_latency 9604970391 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.040165 # miss rate for overall accesses +system.cpu.dcache.overall_misses 1174077 # number of overall misses +system.cpu.dcache.overall_mshr_hits 223844 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 3110233453 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.032508 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 950233 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.replacements 946046 # number of replacements -system.cpu.dcache.sampled_refs 950142 # Sample count of references to valid blocks. +system.cpu.dcache.replacements 946136 # number of replacements +system.cpu.dcache.sampled_refs 950232 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 3493.759701 # Cycle average of tags in use -system.cpu.dcache.total_refs 28059791 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 18895308000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 943121 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 17616091 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 8947 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 4756283 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 139877523 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 32952944 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 32754638 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 5463778 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 29965 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 803874 # Number of cycles decode is unblocking +system.cpu.dcache.tagsinuse 3493.184851 # Cycle average of tags in use +system.cpu.dcache.total_refs 28069666 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 18896443000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 943153 # number of writebacks +system.cpu.decode.DECODE:BlockedCycles 17588781 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BranchMispred 9537 # Number of times decode detected a branch misprediction +system.cpu.decode.DECODE:BranchResolved 4762375 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 139874563 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 32956661 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 32742845 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 5457924 # Number of cycles decode is squashing +system.cpu.decode.DECODE:SquashedInsts 30438 # Number of squashed instructions handled by decode +system.cpu.decode.DECODE:UnblockCycles 813588 # Number of cycles decode is unblocking system.cpu.dtb.accesses 0 # DTB accesses system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions @@ -158,243 +158,243 @@ system.cpu.dtb.read_misses 0 # DT system.cpu.dtb.write_accesses 0 # DTB write accesses system.cpu.dtb.write_hits 0 # DTB write hits system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.fetch.Branches 29547808 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 15301199 # Number of cache lines fetched -system.cpu.fetch.Cycles 34415849 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 249988 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 142060699 # Number of instructions fetch has processed -system.cpu.fetch.MiscStallCycles 19814 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.SquashCycles 1615180 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.329695 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 15301199 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 24895837 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 1.585116 # Number of inst fetches per cycle -system.cpu.fetch.rateDist::samples 89591325 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.597262 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.585030 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.Branches 29586235 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 15336543 # Number of cache lines fetched +system.cpu.fetch.Cycles 34444061 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 252596 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 142085293 # Number of instructions fetch has processed +system.cpu.fetch.MiscStallCycles 8 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.SquashCycles 1618878 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.330242 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 15336543 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 24920897 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 1.585960 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 89559799 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.598579 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.586276 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 55239268 61.66% 61.66% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 6349932 7.09% 68.74% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 6414208 7.16% 75.90% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 4426055 4.94% 80.84% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 3460419 3.86% 84.71% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1907279 2.13% 86.84% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 1921135 2.14% 88.98% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 3244772 3.62% 92.60% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 6628257 7.40% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 55181021 61.61% 61.61% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 6379280 7.12% 68.74% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 6413392 7.16% 75.90% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 4415439 4.93% 80.83% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 3489859 3.90% 84.72% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1871095 2.09% 86.81% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1928131 2.15% 88.97% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 3220363 3.60% 92.56% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 6661219 7.44% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 89591325 # Number of instructions fetched each cycle (Total) -system.cpu.fp_regfile_reads 83 # number of floating regfile reads -system.cpu.fp_regfile_writes 76 # number of floating regfile writes -system.cpu.icache.ReadReq_accesses 15301199 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 35691.320293 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 34369.469027 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 15300381 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 29195500 # number of ReadReq miss cycles +system.cpu.fetch.rateDist::total 89559799 # Number of instructions fetched each cycle (Total) +system.cpu.fp_regfile_reads 96 # number of floating regfile reads +system.cpu.fp_regfile_writes 96 # number of floating regfile writes +system.cpu.icache.ReadReq_accesses 15336543 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 35886.138614 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 34397.626113 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 15335735 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 28996000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.000053 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 818 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 140 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 23302500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_misses 808 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 134 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 23184000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000044 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 678 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses 674 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 22566.933628 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 22787.124814 # Average number of references to valid blocks. system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 15301199 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 35691.320293 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 34369.469027 # average overall mshr miss latency -system.cpu.icache.demand_hits 15300381 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 29195500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_accesses 15336543 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 35886.138614 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 34397.626113 # average overall mshr miss latency +system.cpu.icache.demand_hits 15335735 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 28996000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.000053 # miss rate for demand accesses -system.cpu.icache.demand_misses 818 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 140 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 23302500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_misses 808 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 134 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 23184000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.000044 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 678 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses 674 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.276968 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 567.230284 # Average occupied blocks per context -system.cpu.icache.overall_accesses 15301199 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 35691.320293 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 34369.469027 # average overall mshr miss latency +system.cpu.icache.occ_%::0 0.277518 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 568.356083 # Average occupied blocks per context +system.cpu.icache.overall_accesses 15336543 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 35886.138614 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 34397.626113 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 15300381 # number of overall hits -system.cpu.icache.overall_miss_latency 29195500 # number of overall miss cycles +system.cpu.icache.overall_hits 15335735 # number of overall hits +system.cpu.icache.overall_miss_latency 28996000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000053 # miss rate for overall accesses -system.cpu.icache.overall_misses 818 # number of overall misses -system.cpu.icache.overall_mshr_hits 140 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 23302500 # number of overall MSHR miss cycles +system.cpu.icache.overall_misses 808 # number of overall misses +system.cpu.icache.overall_mshr_hits 134 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 23184000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.000044 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 678 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses 674 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.replacements 2 # number of replacements -system.cpu.icache.sampled_refs 678 # Sample count of references to valid blocks. +system.cpu.icache.sampled_refs 673 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 567.230284 # Cycle average of tags in use -system.cpu.icache.total_refs 15300381 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 568.356083 # Cycle average of tags in use +system.cpu.icache.total_refs 15335735 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 30314 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 20925598 # Number of branches executed -system.cpu.iew.EXEC:nop 54439 # number of nop insts executed -system.cpu.iew.EXEC:rate 1.157971 # Inst execution rate -system.cpu.iew.EXEC:refs 30252486 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 5191190 # Number of stores executed +system.cpu.idleCycles 29674 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 20951910 # Number of branches executed +system.cpu.iew.EXEC:nop 39919 # number of nop insts executed +system.cpu.iew.EXEC:rate 1.157669 # Inst execution rate +system.cpu.iew.EXEC:refs 30258239 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 5196792 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 127253538 # num instructions consuming a value -system.cpu.iew.WB:count 102147077 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.488789 # average fanout of values written-back +system.cpu.iew.WB:consumers 127150055 # num instructions consuming a value +system.cpu.iew.WB:count 102173263 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.489247 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 62200099 # num instructions producing a value -system.cpu.iew.WB:rate 1.139759 # insts written-back per cycle -system.cpu.iew.WB:sent 102625765 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 1807591 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 317265 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 31522248 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 688638 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 326826 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 6607421 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 129183212 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 25061296 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 2026821 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 103779294 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 171143 # Number of times the IQ has become full, causing a stall +system.cpu.iew.WB:producers 62207806 # num instructions producing a value +system.cpu.iew.WB:rate 1.140461 # insts written-back per cycle +system.cpu.iew.WB:sent 102563540 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 1809783 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 316819 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 31496278 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 689079 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 358280 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 6614347 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 129035403 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 25061447 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 2046229 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 103714956 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 173808 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 178 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 5463778 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 193382 # Number of cycles IEW is unblocking +system.cpu.iew.iewLSQFullEvents 187 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 5457924 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 196064 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread.0.cacheBlocked 21870 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 400446 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 24865 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.cacheBlocked 21877 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread.0.forwLoads 398676 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 24099 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 14115 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.memOrderViolation 14224 # Number of memory ordering violations system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 8946464 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 1860761 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 14115 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 301414 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 1506177 # Number of branches that were predicted taken incorrectly -system.cpu.int_regfile_reads 259793995 # number of integer regfile reads -system.cpu.int_regfile_writes 80578248 # number of integer regfile writes -system.cpu.ipc 1.018163 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.018163 # IPC: Total IPC of All Threads +system.cpu.iew.lsq.thread.0.squashedLoads 8920401 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 1867594 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 14224 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 282853 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 1526930 # Number of branches that were predicted taken incorrectly +system.cpu.int_regfile_reads 259728905 # number of integer regfile reads +system.cpu.int_regfile_writes 80595216 # number of integer regfile writes +system.cpu.ipc 1.018534 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.018534 # IPC: Total IPC of All Threads system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntAlu 74302206 70.22% 70.22% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntMult 10686 0.01% 70.23% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 70.23% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 70.23% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 70.23% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 70.23% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 70.23% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 70.23% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 70.23% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 70.23% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 70.23% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 70.23% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 70.23% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 70.23% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 70.23% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 70.23% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 70.23% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 70.23% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 70.23% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 70.23% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 70.23% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 70.23% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 1 0.00% 70.23% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 21 0.00% 70.23% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 70.23% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 37 0.00% 70.24% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 70.24% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 4 0.00% 70.24% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 70.24% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemRead 26235832 24.80% 95.03% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemWrite 5257328 4.97% 100.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntAlu 74250134 70.21% 70.21% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntMult 10532 0.01% 70.22% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 70.22% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 70.22% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 70.22% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 70.22% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 70.22% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 70.22% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 70.22% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 70.22% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 70.22% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 70.22% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 70.22% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 70.22% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 70.22% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 70.22% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 70.22% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 70.22% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 70.22% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 70.22% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 70.22% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 70.22% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 1 0.00% 70.22% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 27 0.00% 70.22% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 70.22% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 46 0.00% 70.22% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 70.22% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 5 0.00% 70.22% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 70.22% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemRead 26236363 24.81% 95.02% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemWrite 5264077 4.98% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::total 105806115 # Type of FU issued -system.cpu.iq.ISSUE:fu_busy_cnt 187983 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.001777 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:FU_type_0::total 105761185 # Type of FU issued +system.cpu.iq.ISSUE:fu_busy_cnt 177153 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.001675 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntAlu 52416 27.88% 27.88% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntMult 27 0.01% 27.90% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 27.90% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 27.90% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 27.90% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 27.90% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 27.90% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 27.90% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 27.90% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 27.90% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 27.90% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 27.90% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 27.90% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 27.90% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 27.90% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 27.90% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 27.90% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 27.90% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 27.90% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 27.90% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 27.90% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 27.90% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 27.90% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 27.90% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 27.90% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 27.90% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 27.90% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 27.90% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 27.90% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemRead 77701 41.33% 69.23% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemWrite 57839 30.77% 100.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntAlu 40759 23.01% 23.01% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntMult 27 0.02% 23.02% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 23.02% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 23.02% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 23.02% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 23.02% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 23.02% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 23.02% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 23.02% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 23.02% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 23.02% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 23.02% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 23.02% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 23.02% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 23.02% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 23.02% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 23.02% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 23.02% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 23.02% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 23.02% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 23.02% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 23.02% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 23.02% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 23.02% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 23.02% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 23.02% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 23.02% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 23.02% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 23.02% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemRead 78448 44.28% 67.31% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemWrite 57919 32.69% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:issued_per_cycle::samples 89591325 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::mean 1.180986 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.458768 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::samples 89559799 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::mean 1.180900 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.457109 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::0 38472986 42.94% 42.94% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::1 23460608 26.19% 69.13% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::2 14306679 15.97% 85.10% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::3 6444522 7.19% 92.29% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::4 2370548 2.65% 94.94% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::5 2667663 2.98% 97.91% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::6 1626344 1.82% 99.73% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::7 115788 0.13% 99.86% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::8 126187 0.14% 100.00% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::0 38412400 42.89% 42.89% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::1 23501864 26.24% 69.13% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::2 14299372 15.97% 85.10% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::3 6452092 7.20% 92.30% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::4 2377583 2.65% 94.96% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::5 2675567 2.99% 97.94% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::6 1597319 1.78% 99.73% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::7 116596 0.13% 99.86% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::8 127006 0.14% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::total 89591325 # Number of insts issued each cycle -system.cpu.iq.ISSUE:rate 1.180587 # Inst issue rate -system.cpu.iq.fp_alu_accesses 94 # Number of floating point alu accesses -system.cpu.iq.fp_inst_queue_reads 184 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_wakeup_accesses 84 # Number of floating instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_writes 160 # Number of floating instruction queue writes -system.cpu.iq.int_alu_accesses 105994004 # Number of integer alu accesses -system.cpu.iq.int_inst_queue_reads 301419127 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_wakeup_accesses 102146993 # Number of integer instruction queue wakeup accesses -system.cpu.iq.int_inst_queue_writes 166681021 # Number of integer instruction queue writes -system.cpu.iq.iqInstsAdded 128435251 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 105806115 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 693522 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 37544982 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 27773 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 139209 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 69554944 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.ISSUE:issued_per_cycle::total 89559799 # Number of insts issued each cycle +system.cpu.iq.ISSUE:rate 1.180509 # Inst issue rate +system.cpu.iq.fp_alu_accesses 110 # Number of floating point alu accesses +system.cpu.iq.fp_inst_queue_reads 216 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_wakeup_accesses 99 # Number of floating instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_writes 196 # Number of floating instruction queue writes +system.cpu.iq.int_alu_accesses 105938228 # Number of integer alu accesses +system.cpu.iq.int_inst_queue_reads 301287282 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_wakeup_accesses 102173164 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_writes 166475031 # Number of integer instruction queue writes +system.cpu.iq.iqInstsAdded 128301553 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 105761185 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 693931 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 37472339 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 28176 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 139525 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 69343981 # Number of squashed operands that are examined and possibly removed from graph system.cpu.itb.accesses 0 # DTB accesses system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions @@ -416,107 +416,114 @@ system.cpu.itb.read_misses 0 # DT system.cpu.itb.write_accesses 0 # DTB write accesses system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.l2cache.ReadExReq_accesses 34763 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 34229.176697 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31038.826604 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_hits 20224 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_miss_latency 497658000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_rate 0.418232 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_accesses 34765 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_avg_miss_latency 34227.938648 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31038.585872 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_hits 20226 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_miss_latency 497640000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_rate 0.418208 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_misses 14539 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 451273500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.418232 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 451270000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.418208 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_misses 14539 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 916057 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 34296.259843 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31108.565737 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 915041 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 34845000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.001109 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 1016 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_hits 12 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_miss_latency 31233000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.001096 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 1004 # number of ReadReq MSHR misses -system.cpu.l2cache.Writeback_accesses 943121 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 943121 # number of Writeback hits +system.cpu.l2cache.ReadReq_accesses 916140 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 34309.334657 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31104.709419 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 915133 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 34549500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.001099 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 1007 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_hits 9 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_miss_latency 31042500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.001089 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 998 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_accesses 1 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31000 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_misses 1 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 31000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_misses 1 # number of UpgradeReq MSHR misses +system.cpu.l2cache.Writeback_accesses 943153 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 943153 # number of Writeback hits system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 104.841512 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 104.893699 # Average number of references to valid blocks. system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 950820 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 34233.558341 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31043.331403 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 935265 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 532503000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.016360 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 15555 # number of demand (read+write) misses -system.cpu.l2cache.demand_mshr_hits 12 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 482506500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.016347 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 15543 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_accesses 950905 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 34233.211115 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31042.833237 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 935359 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 532189500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.016349 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 15546 # number of demand (read+write) misses +system.cpu.l2cache.demand_mshr_hits 9 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_miss_latency 482312500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.016339 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 15537 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.012390 # Average percentage of cache occupancy -system.cpu.l2cache.occ_%::1 0.250098 # Average percentage of cache occupancy -system.cpu.l2cache.occ_blocks::0 405.999438 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 8195.227045 # Average occupied blocks per context -system.cpu.l2cache.overall_accesses 950820 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 34233.558341 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31043.331403 # average overall mshr miss latency +system.cpu.l2cache.occ_%::0 0.012381 # Average percentage of cache occupancy +system.cpu.l2cache.occ_%::1 0.250026 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 405.690928 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 8192.856570 # Average occupied blocks per context +system.cpu.l2cache.overall_accesses 950905 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 34233.211115 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31042.833237 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 935265 # number of overall hits -system.cpu.l2cache.overall_miss_latency 532503000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.016360 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 15555 # number of overall misses -system.cpu.l2cache.overall_mshr_hits 12 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 482506500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.016347 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 15543 # number of overall MSHR misses +system.cpu.l2cache.overall_hits 935359 # number of overall hits +system.cpu.l2cache.overall_miss_latency 532189500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.016349 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 15546 # number of overall misses +system.cpu.l2cache.overall_mshr_hits 9 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_miss_latency 482312500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.016339 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 15537 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.replacements 702 # number of replacements -system.cpu.l2cache.sampled_refs 15528 # Sample count of references to valid blocks. +system.cpu.l2cache.sampled_refs 15522 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 8601.226483 # Cycle average of tags in use -system.cpu.l2cache.total_refs 1627979 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 8598.547498 # Cycle average of tags in use +system.cpu.l2cache.total_refs 1628160 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 32 # number of writebacks -system.cpu.memDep0.conflictingLoads 745583 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 374535 # Number of conflicting stores. -system.cpu.memDep0.insertedLoads 31522248 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 6607421 # Number of stores inserted to the mem dependence unit. -system.cpu.misc_regfile_reads 197265421 # number of misc regfile reads -system.cpu.misc_regfile_writes 1603310 # number of misc regfile writes -system.cpu.numCycles 89621639 # number of cpu cycles simulated +system.cpu.memDep0.conflictingLoads 672298 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 377389 # Number of conflicting stores. +system.cpu.memDep0.insertedLoads 31496278 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 6614347 # Number of stores inserted to the mem dependence unit. +system.cpu.misc_regfile_reads 197340646 # number of misc regfile reads +system.cpu.misc_regfile_writes 11604 # number of misc regfile writes +system.cpu.numCycles 89589473 # number of cpu cycles simulated system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.rename.RENAME:BlockCycles 2572422 # Number of cycles rename is blocking -system.cpu.rename.RENAME:CommittedMaps 72121223 # Number of HB maps that are committed -system.cpu.rename.RENAME:IQFullEvents 2896922 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 35550108 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 1943384 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:BlockCycles 2558009 # Number of cycles rename is blocking +system.cpu.rename.RENAME:CommittedMaps 71576967 # Number of HB maps that are committed +system.cpu.rename.RENAME:IQFullEvents 2891853 # Number of times rename has blocked due to IQ full +system.cpu.rename.RENAME:IdleCycles 35560664 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 1952065 # Number of times rename has blocked due to LSQ full system.cpu.rename.RENAME:ROBFullEvents 58 # Number of times rename has blocked due to ROB full -system.cpu.rename.RENAME:RenameLookups 350234554 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 135614727 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 106518917 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 30912538 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 5463778 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 5897124 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 34397691 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:fp_rename_lookups 648 # Number of floating rename lookups -system.cpu.rename.RENAME:int_rename_lookups 350233906 # Number of integer rename lookups -system.cpu.rename.RENAME:serializeStallCycles 9195355 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 700993 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 13077041 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 701919 # count of temporary serializing insts renamed -system.cpu.rob.rob_reads 212639994 # The number of ROB reads -system.cpu.rob.rob_writes 263827329 # The number of ROB writes -system.cpu.timesIdled 1459 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.rename.RENAME:RenameLookups 350271207 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 135568411 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 105865304 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 30904016 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 5457924 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 5891977 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 34288334 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:fp_rename_lookups 787 # Number of floating rename lookups +system.cpu.rename.RENAME:int_rename_lookups 350270420 # Number of integer rename lookups +system.cpu.rename.RENAME:serializeStallCycles 9187209 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 701223 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 13035103 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 702184 # count of temporary serializing insts renamed +system.cpu.rob.rob_reads 212458407 # The number of ROB reads +system.cpu.rob.rob_writes 263525841 # The number of ROB writes +system.cpu.timesIdled 1433 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 442 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/10.mcf/ref/arm/linux/simple-atomic/chair.cook.ppm b/tests/long/10.mcf/ref/arm/linux/simple-atomic/chair.cook.ppm new file mode 100644 index 000000000..9ac19076f --- /dev/null +++ b/tests/long/10.mcf/ref/arm/linux/simple-atomic/chair.cook.ppm @@ -0,0 +1,4 @@ +P6 +15 15 +255 +
!!! !!!$$$&&&'''&&&%%%
!!!%%%(((******)))(((!!! ###'''***+++,,,+++)))""" ###''')))++++++***)))!!! !!!%%%((()))))))))''' """%%%&&&'''&&&%%% %%% !!!"""#########"""(((---222666&&&...///===;;;999555111,,,((($$$DDDKKKRRRXXXBBB†††‘‘‘jjjWWWZZZUUUNNNGGG???888[[[dddkkkrrr]]]CCC===eeeaaarrrkkkddd[[[SSSKKKiiipppvvvvvvEEE ggg{{{uuunnnfff^^^VVVmmmsssxxx|||oooEEEDDD]]]vvvzzzuuuooohhhaaaZZZjjjooossswwwyyyzzzzzzyyywwwtttoookkkeee```ZZZeeeiiilllnnnpppppppppooonnnkkkhhhddd```\\\WWW
\ No newline at end of file diff --git a/tests/long/10.mcf/ref/arm/linux/simple-atomic/config.ini b/tests/long/10.mcf/ref/arm/linux/simple-atomic/config.ini index febb3dd2f..2f887d410 100644 --- a/tests/long/10.mcf/ref/arm/linux/simple-atomic/config.ini +++ b/tests/long/10.mcf/ref/arm/linux/simple-atomic/config.ini @@ -61,7 +61,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=mcf mcf.in -cwd=build/ARM_SE/tests/fast/long/10.mcf/arm/linux/simple-atomic +cwd=build/ARM_SE/tests/opt/long/10.mcf/arm/linux/simple-atomic egid=100 env= errout=cerr diff --git a/tests/long/10.mcf/ref/arm/linux/simple-atomic/mcf.out b/tests/long/10.mcf/ref/arm/linux/simple-atomic/mcf.out new file mode 100644 index 000000000..095132477 --- /dev/null +++ b/tests/long/10.mcf/ref/arm/linux/simple-atomic/mcf.out @@ -0,0 +1,999 @@ +() +500 +() +499 +() +498 +() +496 +() +495 +() +494 +() +493 +() +492 +() +491 +() +490 +() +489 +() +488 +() +487 +() +486 +() +484 +() +482 +() +481 +() +480 +() +479 +() +478 +() +477 +() +476 +() +475 +() +474 +() +473 +() +472 +() +471 +() +469 +() +468 +() +467 +() +466 +() +465 +() +464 +() +463 +() +462 +() +461 +() +460 +() +459 +() +458 +() +457 +() +455 +() +454 +() +452 +() +451 +() +450 +() +449 +() +448 +() +446 +() +445 +() +444 +() +443 +() +442 +() +440 +() +439 +() +438 +() +436 +() +435 +() +433 +() +432 +() +431 +() +428 +() +427 +() +425 +() +424 +() +423 +() +420 +() +419 +() +416 +() +414 +() +413 +() +412 +() +407 +() +406 +() +405 +() +404 +() +403 +() +402 +() +401 +() +400 +() +399 +() +398 +() +396 +() +395 +() +393 +() +392 +() +390 +() +389 +() +388 +() +387 +() +386 +() +385 +() +384 +() +383 +() +382 +() +381 +() +380 +() +379 +() +377 +() +375 +() +374 +() +373 +() +372 +() +371 +() +370 +() +369 +() +368 +() +366 +() +365 +() +364 +() +362 +() +361 +() +360 +() +359 +() +358 +() +357 +() +356 +() +355 +() +354 +() +352 +() +350 +() +347 +() +344 +() +342 +() +341 +() +340 +() +339 +() +338 +() +332 +() +325 +() +320 +*** +345 +() +319 +*** +497 +() +318 +*** +349 +() +317 +*** +408 +() +316 +*** +324 +() +315 +*** +328 +() +314 +*** +335 +() +313 +*** +378 +() +312 +*** +426 +() +311 +*** +411 +() +304 +*** +343 +() +303 +*** +417 +() +302 +*** +485 +() +301 +*** +363 +() +300 +*** +376 +() +299 +*** +333 +() +292 +*** +337 +() +291 +*** +409 +() +290 +*** +421 +() +289 +*** +437 +() +288 +*** +430 +() +287 +*** +348 +() +286 +*** +326 +() +284 +() +282 +*** +308 +() +279 +*** +297 +*** +305 +() +278 +() +277 +*** +307 +() +276 +*** +296 +() +273 +() +271 +() +265 +() +246 +*** +267 +() +245 +*** +280 +() +244 +*** +391 +() +243 +*** +330 +() +242 +*** +456 +() +241 +*** +346 +() +240 +*** +483 +() +239 +*** +260 +() +238 +*** +261 +() +237 +*** +262 +*** +294 +() +236 +*** +253 +() +229 +*** +397 +() +228 +*** +298 +() +227 +*** +415 +() +226 +*** +264 +() +224 +*** +232 +() +222 +*** +233 +() +217 +*** +250 +() +211 +*** +331 +() +210 +*** +394 +() +209 +*** +410 +() +208 +*** +321 +() +207 +*** +327 +() +206 +*** +309 +() +199 +*** +259 +() +198 +*** +219 +() +197 +*** +220 +() +195 +*** +429 +() +194 +*** +470 +() +193 +*** +274 +() +191 +*** +203 +() +190 +*** +263 +() +189 +215 +*** +230 +() +188 +*** +266 +*** +295 +() +182 +*** +329 +() +181 +*** +351 +() +180 +*** +441 +() +179 +*** +453 +() +178 +*** +418 +() +177 +*** +353 +() +176 +*** +422 +() +175 +*** +225 +*** +255 +() +174 +*** +269 +() +173 +*** +214 +() +172 +*** +186 +() +171 +*** +447 +() +170 +*** +270 +*** +306 +() +169 +*** +336 +() +168 +*** +285 +() +165 +*** +249 +() +146 +*** +154 +() +143 +*** +334 +() +142 +*** +216 +*** +257 +() +141 +*** +167 +*** +251 +() +140 +*** +162 +*** +293 +() +139 +*** +158 +() +137 +*** +166 +*** +201 +() +136 +*** +160 +() +134 +*** +221 +() +132 +*** +213 +() +131 +*** +187 +() +129 +*** +235 +() +128 +*** +153 +() +127 +*** +156 +() +126 +*** +159 +*** +218 +() +125 +*** +155 +() +124 +*** +157 +() +123 +*** +152 +() +116 +*** +135 +*** +163 +() +115 +*** +133 +*** +204 +*** +248 +() +114 +*** +192 +*** +212 +() +113 +*** +268 +() +112 +*** +367 +() +111 +*** +272 +() +110 +*** +434 +() +109 +*** +323 +() +108 +*** +281 +() +107 +*** +144 +*** +148 +() +106 +*** +275 +() +105 +*** +196 +*** +254 +() +104 +*** +138 +*** +161 +() +103 +*** +310 +() +102 +*** +223 +*** +252 +() +80 +() +70 +() +69 +() +68 +() +66 +() +64 +() +62 +*** +256 +() +61 +*** +93 +() +59 +*** +120 +() +58 +() +57 +*** +183 +() +55 +() +54 +() +52 +*** +147 +() +51 +*** +118 +() +50 +*** +83 +() +49 +*** +98 +() +48 +*** +99 +() +47 +() +46 +*** +184 +() +45 +*** +121 +() +44 +() +43 +*** +88 +() +42 +*** +122 +() +41 +*** +91 +() +40 +*** +96 +() +38 +*** +100 +() +37 +*** +149 +() +36 +*** +74 +() +35 +*** +258 +() +34 +*** +151 +() +33 +*** +85 +() +32 +() +31 +*** +94 +() +30 +*** +97 +() +29 +*** +90 +() +28 +*** +89 +() +27 +*** +92 +() +26 +*** +72 +*** +247 +() +25 +*** +86 +() +24 +*** +82 +() +23 +*** +87 +*** +117 +() +22 +*** +76 +*** +119 +() +21 +*** +84 +() +20 +*** +78 +() +19 +*** +73 +() +18 +*** +81 +() +17 +*** +65 +() +16 +*** +63 +*** +101 +() +15 +*** +71 +() +14 +*** +75 +() +13 +*** +322 +() +12 +*** +77 +() +11 +*** +283 +() +10 +*** +79 +() +9 +*** +145 +*** +150 +() +8 +*** +67 +() +7 +*** +60 +*** +231 +() +6 +*** +56 +*** +234 +() +5 +*** +164 +*** +202 +() +4 +*** +53 +() +3 +*** +130 +*** +185 +*** +200 +() +2 +*** +205 +() +1 +*** +39 +*** +95 diff --git a/tests/long/10.mcf/ref/arm/linux/simple-atomic/simout b/tests/long/10.mcf/ref/arm/linux/simple-atomic/simout index 4df99b9a8..d4df9bd55 100755 --- a/tests/long/10.mcf/ref/arm/linux/simple-atomic/simout +++ b/tests/long/10.mcf/ref/arm/linux/simple-atomic/simout @@ -5,11 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Mar 11 2011 20:10:09 -M5 revision 4decc284606a 8095 default qtip tip ext/update_add_stats.patch -M5 started Mar 11 2011 20:10:13 +M5 compiled Mar 30 2011 17:47:57 +M5 started Mar 30 2011 17:54:34 M5 executing on u200439-lin.austin.arm.com -command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/10.mcf/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/fast/long/10.mcf/arm/linux/simple-atomic +command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/10.mcf/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/opt/long/10.mcf/arm/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/10.mcf/ref/arm/linux/simple-atomic/stats.txt b/tests/long/10.mcf/ref/arm/linux/simple-atomic/stats.txt index 60359959c..4aa89302d 100644 --- a/tests/long/10.mcf/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/10.mcf/ref/arm/linux/simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1915165 # Simulator instruction rate (inst/s) -host_mem_usage 378952 # Number of bytes of host memory used -host_seconds 47.65 # Real time elapsed on the host -host_tick_rate 1138365446 # Simulator tick rate (ticks/s) +host_inst_rate 950960 # Simulator instruction rate (inst/s) +host_mem_usage 379668 # Number of bytes of host memory used +host_seconds 95.96 # Real time elapsed on the host +host_tick_rate 565248287 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 91252969 # Number of instructions simulated sim_seconds 0.054241 # Number of seconds simulated @@ -56,18 +56,18 @@ system.cpu.numCycles 108481333 # nu system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.num_busy_cycles 108481333 # Number of busy cycles -system.cpu.num_conditional_control_insts 15112201 # number of instructions that are conditional controls +system.cpu.num_conditional_control_insts 15127614 # number of instructions that are conditional controls system.cpu.num_fp_alu_accesses 48 # Number of float alu accesses system.cpu.num_fp_insts 48 # number of float instructions system.cpu.num_fp_register_reads 54 # number of times the floating registers were read system.cpu.num_fp_register_writes 30 # number of times the floating registers were written -system.cpu.num_func_calls 97900 # number of times a function call or return occured +system.cpu.num_func_calls 96832 # number of times a function call or return occured system.cpu.num_idle_cycles 0 # Number of idle cycles system.cpu.num_insts 91252969 # Number of instructions executed system.cpu.num_int_alu_accesses 72525682 # Number of integer alu accesses system.cpu.num_int_insts 72525682 # number of integer instructions system.cpu.num_int_register_reads 234656737 # number of times the integer registers were read -system.cpu.num_int_register_writes 72596953 # number of times the integer registers were written +system.cpu.num_int_register_writes 70993656 # number of times the integer registers were written system.cpu.num_load_insts 22573967 # Number of load instructions system.cpu.num_mem_refs 27318811 # number of memory refs system.cpu.num_store_insts 4744844 # Number of store instructions diff --git a/tests/long/10.mcf/ref/arm/linux/simple-timing/chair.cook.ppm b/tests/long/10.mcf/ref/arm/linux/simple-timing/chair.cook.ppm new file mode 100644 index 000000000..9ac19076f --- /dev/null +++ b/tests/long/10.mcf/ref/arm/linux/simple-timing/chair.cook.ppm @@ -0,0 +1,4 @@ +P6 +15 15 +255 +
!!! !!!$$$&&&'''&&&%%%
!!!%%%(((******)))(((!!! ###'''***+++,,,+++)))""" ###''')))++++++***)))!!! !!!%%%((()))))))))''' """%%%&&&'''&&&%%% %%% !!!"""#########"""(((---222666&&&...///===;;;999555111,,,((($$$DDDKKKRRRXXXBBB†††‘‘‘jjjWWWZZZUUUNNNGGG???888[[[dddkkkrrr]]]CCC===eeeaaarrrkkkddd[[[SSSKKKiiipppvvvvvvEEE ggg{{{uuunnnfff^^^VVVmmmsssxxx|||oooEEEDDD]]]vvvzzzuuuooohhhaaaZZZjjjooossswwwyyyzzzzzzyyywwwtttoookkkeee```ZZZeeeiiilllnnnpppppppppooonnnkkkhhhddd```\\\WWW
\ No newline at end of file diff --git a/tests/long/10.mcf/ref/arm/linux/simple-timing/config.ini b/tests/long/10.mcf/ref/arm/linux/simple-timing/config.ini index faf8a693c..9fe66a752 100644 --- a/tests/long/10.mcf/ref/arm/linux/simple-timing/config.ini +++ b/tests/long/10.mcf/ref/arm/linux/simple-timing/config.ini @@ -164,7 +164,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=mcf mcf.in -cwd=build/ARM_SE/tests/fast/long/10.mcf/arm/linux/simple-timing +cwd=build/ARM_SE/tests/opt/long/10.mcf/arm/linux/simple-timing egid=100 env= errout=cerr diff --git a/tests/long/10.mcf/ref/arm/linux/simple-timing/mcf.out b/tests/long/10.mcf/ref/arm/linux/simple-timing/mcf.out new file mode 100644 index 000000000..095132477 --- /dev/null +++ b/tests/long/10.mcf/ref/arm/linux/simple-timing/mcf.out @@ -0,0 +1,999 @@ +() +500 +() +499 +() +498 +() +496 +() +495 +() +494 +() +493 +() +492 +() +491 +() +490 +() +489 +() +488 +() +487 +() +486 +() +484 +() +482 +() +481 +() +480 +() +479 +() +478 +() +477 +() +476 +() +475 +() +474 +() +473 +() +472 +() +471 +() +469 +() +468 +() +467 +() +466 +() +465 +() +464 +() +463 +() +462 +() +461 +() +460 +() +459 +() +458 +() +457 +() +455 +() +454 +() +452 +() +451 +() +450 +() +449 +() +448 +() +446 +() +445 +() +444 +() +443 +() +442 +() +440 +() +439 +() +438 +() +436 +() +435 +() +433 +() +432 +() +431 +() +428 +() +427 +() +425 +() +424 +() +423 +() +420 +() +419 +() +416 +() +414 +() +413 +() +412 +() +407 +() +406 +() +405 +() +404 +() +403 +() +402 +() +401 +() +400 +() +399 +() +398 +() +396 +() +395 +() +393 +() +392 +() +390 +() +389 +() +388 +() +387 +() +386 +() +385 +() +384 +() +383 +() +382 +() +381 +() +380 +() +379 +() +377 +() +375 +() +374 +() +373 +() +372 +() +371 +() +370 +() +369 +() +368 +() +366 +() +365 +() +364 +() +362 +() +361 +() +360 +() +359 +() +358 +() +357 +() +356 +() +355 +() +354 +() +352 +() +350 +() +347 +() +344 +() +342 +() +341 +() +340 +() +339 +() +338 +() +332 +() +325 +() +320 +*** +345 +() +319 +*** +497 +() +318 +*** +349 +() +317 +*** +408 +() +316 +*** +324 +() +315 +*** +328 +() +314 +*** +335 +() +313 +*** +378 +() +312 +*** +426 +() +311 +*** +411 +() +304 +*** +343 +() +303 +*** +417 +() +302 +*** +485 +() +301 +*** +363 +() +300 +*** +376 +() +299 +*** +333 +() +292 +*** +337 +() +291 +*** +409 +() +290 +*** +421 +() +289 +*** +437 +() +288 +*** +430 +() +287 +*** +348 +() +286 +*** +326 +() +284 +() +282 +*** +308 +() +279 +*** +297 +*** +305 +() +278 +() +277 +*** +307 +() +276 +*** +296 +() +273 +() +271 +() +265 +() +246 +*** +267 +() +245 +*** +280 +() +244 +*** +391 +() +243 +*** +330 +() +242 +*** +456 +() +241 +*** +346 +() +240 +*** +483 +() +239 +*** +260 +() +238 +*** +261 +() +237 +*** +262 +*** +294 +() +236 +*** +253 +() +229 +*** +397 +() +228 +*** +298 +() +227 +*** +415 +() +226 +*** +264 +() +224 +*** +232 +() +222 +*** +233 +() +217 +*** +250 +() +211 +*** +331 +() +210 +*** +394 +() +209 +*** +410 +() +208 +*** +321 +() +207 +*** +327 +() +206 +*** +309 +() +199 +*** +259 +() +198 +*** +219 +() +197 +*** +220 +() +195 +*** +429 +() +194 +*** +470 +() +193 +*** +274 +() +191 +*** +203 +() +190 +*** +263 +() +189 +215 +*** +230 +() +188 +*** +266 +*** +295 +() +182 +*** +329 +() +181 +*** +351 +() +180 +*** +441 +() +179 +*** +453 +() +178 +*** +418 +() +177 +*** +353 +() +176 +*** +422 +() +175 +*** +225 +*** +255 +() +174 +*** +269 +() +173 +*** +214 +() +172 +*** +186 +() +171 +*** +447 +() +170 +*** +270 +*** +306 +() +169 +*** +336 +() +168 +*** +285 +() +165 +*** +249 +() +146 +*** +154 +() +143 +*** +334 +() +142 +*** +216 +*** +257 +() +141 +*** +167 +*** +251 +() +140 +*** +162 +*** +293 +() +139 +*** +158 +() +137 +*** +166 +*** +201 +() +136 +*** +160 +() +134 +*** +221 +() +132 +*** +213 +() +131 +*** +187 +() +129 +*** +235 +() +128 +*** +153 +() +127 +*** +156 +() +126 +*** +159 +*** +218 +() +125 +*** +155 +() +124 +*** +157 +() +123 +*** +152 +() +116 +*** +135 +*** +163 +() +115 +*** +133 +*** +204 +*** +248 +() +114 +*** +192 +*** +212 +() +113 +*** +268 +() +112 +*** +367 +() +111 +*** +272 +() +110 +*** +434 +() +109 +*** +323 +() +108 +*** +281 +() +107 +*** +144 +*** +148 +() +106 +*** +275 +() +105 +*** +196 +*** +254 +() +104 +*** +138 +*** +161 +() +103 +*** +310 +() +102 +*** +223 +*** +252 +() +80 +() +70 +() +69 +() +68 +() +66 +() +64 +() +62 +*** +256 +() +61 +*** +93 +() +59 +*** +120 +() +58 +() +57 +*** +183 +() +55 +() +54 +() +52 +*** +147 +() +51 +*** +118 +() +50 +*** +83 +() +49 +*** +98 +() +48 +*** +99 +() +47 +() +46 +*** +184 +() +45 +*** +121 +() +44 +() +43 +*** +88 +() +42 +*** +122 +() +41 +*** +91 +() +40 +*** +96 +() +38 +*** +100 +() +37 +*** +149 +() +36 +*** +74 +() +35 +*** +258 +() +34 +*** +151 +() +33 +*** +85 +() +32 +() +31 +*** +94 +() +30 +*** +97 +() +29 +*** +90 +() +28 +*** +89 +() +27 +*** +92 +() +26 +*** +72 +*** +247 +() +25 +*** +86 +() +24 +*** +82 +() +23 +*** +87 +*** +117 +() +22 +*** +76 +*** +119 +() +21 +*** +84 +() +20 +*** +78 +() +19 +*** +73 +() +18 +*** +81 +() +17 +*** +65 +() +16 +*** +63 +*** +101 +() +15 +*** +71 +() +14 +*** +75 +() +13 +*** +322 +() +12 +*** +77 +() +11 +*** +283 +() +10 +*** +79 +() +9 +*** +145 +*** +150 +() +8 +*** +67 +() +7 +*** +60 +*** +231 +() +6 +*** +56 +*** +234 +() +5 +*** +164 +*** +202 +() +4 +*** +53 +() +3 +*** +130 +*** +185 +*** +200 +() +2 +*** +205 +() +1 +*** +39 +*** +95 diff --git a/tests/long/10.mcf/ref/arm/linux/simple-timing/simerr b/tests/long/10.mcf/ref/arm/linux/simple-timing/simerr index c1c8fcec5..eabe42249 100755 --- a/tests/long/10.mcf/ref/arm/linux/simple-timing/simerr +++ b/tests/long/10.mcf/ref/arm/linux/simple-timing/simerr @@ -1,7 +1,3 @@ warn: Sockets disabled, not accepting gdb connections For more information see: http://www.m5sim.org/warn/d946bea6 -warn: Complete acc isn't called on normal stores in O3. -For more information see: http://www.m5sim.org/warn/138d8573 -warn: Complete acc isn't called on normal stores in O3. -For more information see: http://www.m5sim.org/warn/138d8573 hack: be nice to actually delete the event here diff --git a/tests/long/10.mcf/ref/arm/linux/simple-timing/simout b/tests/long/10.mcf/ref/arm/linux/simple-timing/simout index fff5a35b0..4622f4ee0 100755 --- a/tests/long/10.mcf/ref/arm/linux/simple-timing/simout +++ b/tests/long/10.mcf/ref/arm/linux/simple-timing/simout @@ -5,11 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Mar 11 2011 20:10:09 -M5 revision 4decc284606a 8095 default qtip tip ext/update_add_stats.patch -M5 started Mar 11 2011 21:05:58 +M5 compiled Mar 30 2011 17:47:57 +M5 started Mar 30 2011 17:54:34 M5 executing on u200439-lin.austin.arm.com -command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/10.mcf/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/fast/long/10.mcf/arm/linux/simple-timing +command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/10.mcf/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/opt/long/10.mcf/arm/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/10.mcf/ref/arm/linux/simple-timing/stats.txt b/tests/long/10.mcf/ref/arm/linux/simple-timing/stats.txt index 33b349bfd..389bae1e3 100644 --- a/tests/long/10.mcf/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/10.mcf/ref/arm/linux/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 675901 # Simulator instruction rate (inst/s) -host_mem_usage 386672 # Number of bytes of host memory used -host_seconds 134.97 # Real time elapsed on the host -host_tick_rate 1097177206 # Simulator tick rate (ticks/s) +host_inst_rate 492863 # Simulator instruction rate (inst/s) +host_mem_usage 387392 # Number of bytes of host memory used +host_seconds 185.09 # Real time elapsed on the host +host_tick_rate 800055292 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 91226321 # Number of instructions simulated sim_seconds 0.148086 # Number of seconds simulated @@ -249,18 +249,18 @@ system.cpu.numCycles 296172478 # nu system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.num_busy_cycles 296172478 # Number of busy cycles -system.cpu.num_conditional_control_insts 15112201 # number of instructions that are conditional controls +system.cpu.num_conditional_control_insts 15127614 # number of instructions that are conditional controls system.cpu.num_fp_alu_accesses 48 # Number of float alu accesses system.cpu.num_fp_insts 48 # number of float instructions system.cpu.num_fp_register_reads 54 # number of times the floating registers were read system.cpu.num_fp_register_writes 30 # number of times the floating registers were written -system.cpu.num_func_calls 97900 # number of times a function call or return occured +system.cpu.num_func_calls 96832 # number of times a function call or return occured system.cpu.num_idle_cycles 0 # Number of idle cycles system.cpu.num_insts 91226321 # Number of instructions executed system.cpu.num_int_alu_accesses 72525682 # Number of integer alu accesses system.cpu.num_int_insts 72525682 # number of integer instructions system.cpu.num_int_register_reads 257193253 # number of times the integer registers were read -system.cpu.num_int_register_writes 72608963 # number of times the integer registers were written +system.cpu.num_int_register_writes 70993656 # number of times the integer registers were written system.cpu.num_load_insts 22573967 # Number of load instructions system.cpu.num_mem_refs 27318811 # number of memory refs system.cpu.num_store_insts 4744844 # Number of store instructions diff --git a/tests/long/20.parser/ref/arm/linux/o3-timing/config.ini b/tests/long/20.parser/ref/arm/linux/o3-timing/config.ini index 7cddc1030..6518c5843 100644 --- a/tests/long/20.parser/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/20.parser/ref/arm/linux/o3-timing/config.ini @@ -25,6 +25,8 @@ BTBEntries=4096 BTBTagSize=16 LFSTSize=1024 LQEntries=32 +LSQCheckLoads=true +LSQDepCheckShift=4 RASSize=16 SQEntries=32 SSITSize=1024 @@ -491,14 +493,14 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=parser 2.1.dict -batch -cwd=build/ARM_SE/tests/fast/long/20.parser/arm/linux/o3-timing +cwd=build/ARM_SE/tests/opt/long/20.parser/arm/linux/o3-timing egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/arm/linux/parser +executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/parser gid=100 -input=/dist/m5/cpu2000/data/parser/mdred/input/parser.in +input=/chips/pd/randd/dist/cpu2000/data/parser/mdred/input/parser.in max_stack_size=67108864 output=cout pid=100 diff --git a/tests/long/20.parser/ref/arm/linux/o3-timing/simout b/tests/long/20.parser/ref/arm/linux/o3-timing/simout index d3cedcd62..ce3065a66 100755 --- a/tests/long/20.parser/ref/arm/linux/o3-timing/simout +++ b/tests/long/20.parser/ref/arm/linux/o3-timing/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Mar 18 2011 20:12:03 -M5 started Mar 18 2011 21:12:45 -M5 executing on zizzer -command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/20.parser/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/fast/long/20.parser/arm/linux/o3-timing +M5 compiled Mar 30 2011 17:47:57 +M5 started Mar 30 2011 17:54:34 +M5 executing on u200439-lin.austin.arm.com +command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/20.parser/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/opt/long/20.parser/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -71,4 +71,4 @@ info: Increasing stack size by one page. about 2 million people attended the five best costumes got prizes No errors! -Exiting @ tick 334221751500 because target called exit() +Exiting @ tick 332731219000 because target called exit() diff --git a/tests/long/20.parser/ref/arm/linux/o3-timing/stats.txt b/tests/long/20.parser/ref/arm/linux/o3-timing/stats.txt index 3718b083f..f51506400 100644 --- a/tests/long/20.parser/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/20.parser/ref/arm/linux/o3-timing/stats.txt @@ -1,142 +1,142 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 115680 # Simulator instruction rate (inst/s) -host_mem_usage 225512 # Number of bytes of host memory used -host_seconds 4956.26 # Real time elapsed on the host -host_tick_rate 67434212 # Simulator tick rate (ticks/s) +host_inst_rate 59520 # Simulator instruction rate (inst/s) +host_mem_usage 261972 # Number of bytes of host memory used +host_seconds 9632.84 # Real time elapsed on the host +host_tick_rate 34541337 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 573342252 # Number of instructions simulated -sim_seconds 0.334222 # Number of seconds simulated -sim_ticks 334221751500 # Number of ticks simulated +sim_insts 573342397 # Number of instructions simulated +sim_seconds 0.332731 # Number of seconds simulated +sim_ticks 332731219000 # Number of ticks simulated system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.BTBHits 146248863 # Number of BTB hits -system.cpu.BPredUnit.BTBLookups 176289381 # Number of BTB lookups -system.cpu.BPredUnit.RASInCorrect 2732047 # Number of incorrect RAS predictions. -system.cpu.BPredUnit.condIncorrect 15792639 # Number of conditional branches incorrect -system.cpu.BPredUnit.condPredicted 173563787 # Number of conditional branches predicted -system.cpu.BPredUnit.lookups 218029317 # Number of BP lookups -system.cpu.BPredUnit.usedRAS 10847475 # Number of times the RAS was used to get a target. -system.cpu.commit.COM:branches 116606323 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 7009812 # number cycles where commit BW limit reached +system.cpu.BPredUnit.BTBHits 157170154 # Number of BTB hits +system.cpu.BPredUnit.BTBLookups 189971474 # Number of BTB lookups +system.cpu.BPredUnit.RASInCorrect 2546633 # Number of incorrect RAS predictions. +system.cpu.BPredUnit.condIncorrect 18809964 # Number of conditional branches incorrect +system.cpu.BPredUnit.condPredicted 186338321 # Number of conditional branches predicted +system.cpu.BPredUnit.lookups 233659814 # Number of BP lookups +system.cpu.BPredUnit.usedRAS 11860569 # Number of times the RAS was used to get a target. +system.cpu.commit.COM:branches 120192362 # Number of branches committed +system.cpu.commit.COM:bw_lim_events 6858146 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle::samples 605188855 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::mean 0.949598 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::stdev 1.450627 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::samples 603587786 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::mean 0.952117 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::stdev 1.448029 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::0 311994753 51.55% 51.55% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::1 161715098 26.72% 78.27% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::2 68890759 11.38% 89.66% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::3 25427565 4.20% 93.86% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::4 17265141 2.85% 96.71% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::5 5227008 0.86% 97.58% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::6 5978308 0.99% 98.56% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::7 1680411 0.28% 98.84% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::8 7009812 1.16% 100.00% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::0 310030081 51.36% 51.36% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::1 161983498 26.84% 78.20% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::2 68757792 11.39% 89.59% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::3 25709435 4.26% 93.85% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::4 17326011 2.87% 96.72% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::5 5210197 0.86% 97.59% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::6 6149685 1.02% 98.60% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::7 1562941 0.26% 98.86% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::8 6858146 1.14% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::total 605188855 # Number of insts commited each cycle -system.cpu.commit.COM:count 574686136 # Number of instructions committed +system.cpu.commit.COM:committed_per_cycle::total 603587786 # Number of insts commited each cycle +system.cpu.commit.COM:count 574686281 # Number of instructions committed system.cpu.commit.COM:fp_insts 16 # Number of committed floating point instructions. system.cpu.commit.COM:function_calls 9757362 # Number of function calls committed. -system.cpu.commit.COM:int_insts 473702069 # Number of committed integer instructions. -system.cpu.commit.COM:loads 126773148 # Number of loads committed +system.cpu.commit.COM:int_insts 473702185 # Number of committed integer instructions. +system.cpu.commit.COM:loads 126773177 # Number of loads committed system.cpu.commit.COM:membars 1488542 # Number of memory barriers committed -system.cpu.commit.COM:refs 184377217 # Number of memory references committed +system.cpu.commit.COM:refs 184377275 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 21479549 # The number of times a branch was mispredicted -system.cpu.commit.commitCommittedInsts 574686136 # The number of committed instructions -system.cpu.commit.commitNonSpecStalls 3877864 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 397226721 # The number of squashed insts skipped by commit -system.cpu.committedInsts 573342252 # Number of Instructions Simulated -system.cpu.committedInsts_total 573342252 # Number of Instructions Simulated -system.cpu.cpi 1.165872 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.165872 # CPI: Total CPI of All Threads -system.cpu.dcache.LoadLockedReq_accesses 2604331 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_avg_miss_latency 7833.333333 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_hits 2604295 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_miss_latency 282000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_rate 0.000014 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_misses 36 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_mshr_hits 36 # number of LoadLockedReq MSHR hits -system.cpu.dcache.ReadReq_accesses 142077585 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 10714.447779 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 6999.796046 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 141007026 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 11470448500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.007535 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 1070559 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 219878 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 5954593500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.005987 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 850681 # number of ReadReq MSHR misses -system.cpu.dcache.StoreCondReq_accesses 2232133 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_hits 2232133 # number of StoreCondReq hits +system.cpu.commit.branchMispredicts 20926821 # The number of times a branch was mispredicted +system.cpu.commit.commitCommittedInsts 574686281 # The number of committed instructions +system.cpu.commit.commitNonSpecStalls 3877893 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.commitSquashedInsts 381923221 # The number of squashed insts skipped by commit +system.cpu.committedInsts 573342397 # Number of Instructions Simulated +system.cpu.committedInsts_total 573342397 # Number of Instructions Simulated +system.cpu.cpi 1.160672 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.160672 # CPI: Total CPI of All Threads +system.cpu.dcache.LoadLockedReq_accesses 2604457 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_avg_miss_latency 7857.142857 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_hits 2604422 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_miss_latency 275000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_rate 0.000013 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_misses 35 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_mshr_hits 35 # number of LoadLockedReq MSHR hits +system.cpu.dcache.ReadReq_accesses 143454074 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 10689.937494 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7026.878867 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 142382969 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 11450045500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.007467 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 1071105 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 217572 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 5997673000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.005950 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 853533 # number of ReadReq MSHR misses +system.cpu.dcache.StoreCondReq_accesses 2232162 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_hits 2232162 # number of StoreCondReq hits system.cpu.dcache.WriteReq_accesses 54239306 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 15646.653056 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 13092.754811 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 52838909 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 21911526000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.025819 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 1400397 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 1056210 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 4506356000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.006346 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 344187 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_avg_miss_latency 15503.883790 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 12993.978894 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 52863588 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 21328972000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.025364 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 1375718 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 1033256 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 4449944000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.006314 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 342462 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 166.282010 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 167.338700 # Average number of references to valid blocks. system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 196316891 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 13509.740562 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 8754.899704 # average overall mshr miss latency -system.cpu.dcache.demand_hits 193845935 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 33381974500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.012587 # miss rate for demand accesses -system.cpu.dcache.demand_misses 2470956 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 1276088 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 10460949500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.006086 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 1194868 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_accesses 197693380 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 13396.562604 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 8735.502239 # average overall mshr miss latency +system.cpu.dcache.demand_hits 195246557 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 32779017500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.012377 # miss rate for demand accesses +system.cpu.dcache.demand_misses 2446823 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 1250828 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 10447617000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.006050 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 1195995 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.991141 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 4059.712057 # Average occupied blocks per context -system.cpu.dcache.overall_accesses 196316891 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 13509.740562 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 8754.899704 # average overall mshr miss latency +system.cpu.dcache.occ_%::0 0.991470 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 4061.060335 # Average occupied blocks per context +system.cpu.dcache.overall_accesses 197693380 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 13396.562604 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 8735.502239 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 193845935 # number of overall hits -system.cpu.dcache.overall_miss_latency 33381974500 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.012587 # miss rate for overall accesses -system.cpu.dcache.overall_misses 2470956 # number of overall misses -system.cpu.dcache.overall_mshr_hits 1276088 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 10460949500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.006086 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 1194868 # number of overall MSHR misses +system.cpu.dcache.overall_hits 195246557 # number of overall hits +system.cpu.dcache.overall_miss_latency 32779017500 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.012377 # miss rate for overall accesses +system.cpu.dcache.overall_misses 2446823 # number of overall misses +system.cpu.dcache.overall_mshr_hits 1250828 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 10447617000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.006050 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 1195995 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.replacements 1190756 # number of replacements -system.cpu.dcache.sampled_refs 1194852 # Sample count of references to valid blocks. +system.cpu.dcache.replacements 1191585 # number of replacements +system.cpu.dcache.sampled_refs 1195681 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4059.712057 # Cycle average of tags in use -system.cpu.dcache.total_refs 198682392 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 6636207000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 1064084 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 88183325 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 76234 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 32910143 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 1105509065 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 280452015 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 231095248 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 58620851 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 216396 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 5458266 # Number of cycles decode is unblocking +system.cpu.dcache.tagsinuse 4061.060335 # Cycle average of tags in use +system.cpu.dcache.total_refs 200083704 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 6358781000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 1064793 # number of writebacks +system.cpu.decode.DECODE:BlockedCycles 85842380 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BranchMispred 76871 # Number of times decode detected a branch misprediction +system.cpu.decode.DECODE:BranchResolved 34367828 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 1126968144 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 277630014 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 236143765 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 57332647 # Number of cycles decode is squashing +system.cpu.decode.DECODE:SquashedInsts 218235 # Number of squashed instructions handled by decode +system.cpu.decode.DECODE:UnblockCycles 3971626 # Number of cycles decode is unblocking system.cpu.dtb.accesses 0 # DTB accesses system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions @@ -158,242 +158,242 @@ system.cpu.dtb.read_misses 0 # DT system.cpu.dtb.write_accesses 0 # DTB write accesses system.cpu.dtb.write_hits 0 # DTB write hits system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.fetch.Branches 218029317 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 124225331 # Number of cache lines fetched -system.cpu.fetch.Cycles 240845488 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 2943984 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 985167776 # Number of instructions fetch has processed -system.cpu.fetch.MiscStallCycles 5168276 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.SquashCycles 21620484 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.326175 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 124225331 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 157096338 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 1.473824 # Number of inst fetches per cycle -system.cpu.fetch.rateDist::samples 663809705 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.722895 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.715589 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.Branches 233659814 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 132169265 # Number of cache lines fetched +system.cpu.fetch.Cycles 250543993 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 4563312 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 1003583241 # Number of instructions fetch has processed +system.cpu.fetch.MiscStallCycles 3753 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.SquashCycles 21196803 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.351124 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 132169265 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 169030723 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 1.508099 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 660920432 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.774764 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.719580 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 422975812 63.72% 63.72% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 19490823 2.94% 66.66% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 33888081 5.11% 71.76% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 39021858 5.88% 77.64% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 37073066 5.58% 83.22% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 16674783 2.51% 85.74% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 18304020 2.76% 88.49% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 13198645 1.99% 90.48% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 63182617 9.52% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 410388026 62.09% 62.09% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 20297992 3.07% 65.16% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 37708836 5.71% 70.87% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 39874346 6.03% 76.90% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 40511205 6.13% 83.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 16776062 2.54% 85.57% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 18545890 2.81% 88.38% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 14106044 2.13% 90.51% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 62712031 9.49% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 663809705 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 660920432 # Number of instructions fetched each cycle (Total) system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.icache.ReadReq_accesses 124225331 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 14458.321717 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 10724.096566 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 124210983 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 207448000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.000115 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 14348 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 1010 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 143038000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000107 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 13338 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_accesses 132169265 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 14331.781024 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 10612.450522 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 132154341 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 213887500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.000113 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 14924 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 1029 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 147460000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.000105 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 13895 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 9323.748912 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 9748.051560 # Average number of references to valid blocks. system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 124225331 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 14458.321717 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 10724.096566 # average overall mshr miss latency -system.cpu.icache.demand_hits 124210983 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 207448000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.000115 # miss rate for demand accesses -system.cpu.icache.demand_misses 14348 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 1010 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 143038000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.000107 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 13338 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_accesses 132169265 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 14331.781024 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 10612.450522 # average overall mshr miss latency +system.cpu.icache.demand_hits 132154341 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 213887500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.000113 # miss rate for demand accesses +system.cpu.icache.demand_misses 14924 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 1029 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 147460000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.000105 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 13895 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.515723 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 1056.199986 # Average occupied blocks per context -system.cpu.icache.overall_accesses 124225331 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 14458.321717 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 10724.096566 # average overall mshr miss latency +system.cpu.icache.occ_%::0 0.514415 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 1053.520934 # Average occupied blocks per context +system.cpu.icache.overall_accesses 132169265 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 14331.781024 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 10612.450522 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 124210983 # number of overall hits -system.cpu.icache.overall_miss_latency 207448000 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.000115 # miss rate for overall accesses -system.cpu.icache.overall_misses 14348 # number of overall misses -system.cpu.icache.overall_mshr_hits 1010 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 143038000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.000107 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 13338 # number of overall MSHR misses +system.cpu.icache.overall_hits 132154341 # number of overall hits +system.cpu.icache.overall_miss_latency 213887500 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.000113 # miss rate for overall accesses +system.cpu.icache.overall_misses 14924 # number of overall misses +system.cpu.icache.overall_mshr_hits 1029 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 147460000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.000105 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 13895 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.replacements 11505 # number of replacements -system.cpu.icache.sampled_refs 13322 # Sample count of references to valid blocks. +system.cpu.icache.replacements 11791 # number of replacements +system.cpu.icache.sampled_refs 13557 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1056.199986 # Cycle average of tags in use -system.cpu.icache.total_refs 124210983 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 1053.520934 # Cycle average of tags in use +system.cpu.icache.total_refs 132154335 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 4633799 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 138142297 # Number of branches executed -system.cpu.iew.EXEC:nop 12876339 # number of nop insts executed -system.cpu.iew.EXEC:rate 1.081001 # Inst execution rate -system.cpu.iew.EXEC:refs 219209030 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 66375463 # Number of stores executed +system.cpu.icache.writebacks 4 # number of writebacks +system.cpu.idleCycles 4542007 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 142399885 # Number of branches executed +system.cpu.iew.EXEC:nop 9420990 # number of nop insts executed +system.cpu.iew.EXEC:rate 1.051214 # Inst execution rate +system.cpu.iew.EXEC:refs 220838036 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 66554903 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 788336695 # num instructions consuming a value -system.cpu.iew.WB:count 685357565 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.485374 # average fanout of values written-back +system.cpu.iew.WB:consumers 782273717 # num instructions consuming a value +system.cpu.iew.WB:count 680637923 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.486169 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 382637953 # num instructions producing a value -system.cpu.iew.WB:rate 1.025304 # insts written-back per cycle -system.cpu.iew.WB:sent 714473572 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 25616212 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 2985344 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 194483391 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 2822926 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 7041770 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 112758143 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 971912060 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 152833567 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 22948891 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 722588050 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 111523 # Number of times the IQ has become full, causing a stall +system.cpu.iew.WB:producers 380317186 # num instructions producing a value +system.cpu.iew.WB:rate 1.022804 # insts written-back per cycle +system.cpu.iew.WB:sent 691183006 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 25100140 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 2947924 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 196892006 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 2816035 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 18822753 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 114373867 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 956606524 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 154283133 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 25300490 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 699543688 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 130928 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 15327 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 58620851 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 199342 # Number of cycles IEW is unblocking +system.cpu.iew.iewLSQFullEvents 7156 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 57332647 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 209223 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread.0.cacheBlocked 77 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 5719789 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 15891 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.cacheBlocked 75 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread.0.forwLoads 5626597 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 13730 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 94425 # Number of memory ordering violations -system.cpu.iew.lsq.thread.0.rescheduledLoads 23277 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 67710242 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 55154074 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 94425 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 10897628 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 14718584 # Number of branches that were predicted taken incorrectly -system.cpu.int_regfile_reads 1644594876 # number of integer regfile reads -system.cpu.int_regfile_writes 527674952 # number of integer regfile writes -system.cpu.ipc 0.857727 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.857727 # IPC: Total IPC of All Threads +system.cpu.iew.lsq.thread.0.memOrderViolation 241250 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.rescheduledLoads 24511 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread.0.squashedLoads 70118828 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 56769769 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 241250 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 6965983 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 18134157 # Number of branches that were predicted taken incorrectly +system.cpu.int_regfile_reads 1609052037 # number of integer regfile reads +system.cpu.int_regfile_writes 524399008 # number of integer regfile writes +system.cpu.ipc 0.861570 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.861570 # IPC: Total IPC of All Threads system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntAlu 513661883 68.90% 68.90% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntMult 386634 0.05% 68.95% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 68.95% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatAdd 106 0.00% 68.95% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 68.95% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 68.95% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 68.95% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 68.95% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 68.95% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 68.95% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 68.95% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 68.95% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 68.95% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 68.95% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 68.95% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 68.95% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 68.95% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 68.95% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 68.95% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 68.95% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 68.95% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 68.95% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 68.95% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 68.95% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 68.95% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 3 0.00% 68.95% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 68.95% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 68.95% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 68.95% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemRead 160948708 21.59% 90.54% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemWrite 70539607 9.46% 100.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntAlu 491156775 67.76% 67.76% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntMult 386013 0.05% 67.81% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatAdd 106 0.00% 67.81% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 3 0.00% 67.81% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemRead 162458896 22.41% 90.23% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemWrite 70842385 9.77% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::total 745536941 # Type of FU issued -system.cpu.iq.ISSUE:fu_busy_cnt 10587544 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.014201 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:FU_type_0::total 724844178 # Type of FU issued +system.cpu.iq.ISSUE:fu_busy_cnt 8619148 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.011891 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntAlu 2110928 19.94% 19.94% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 19.94% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 19.94% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 19.94% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 19.94% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 19.94% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 19.94% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 19.94% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 19.94% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 19.94% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 19.94% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 19.94% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 19.94% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 19.94% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 19.94% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 19.94% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 19.94% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 19.94% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 19.94% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 19.94% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 19.94% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 19.94% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 19.94% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 19.94% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 19.94% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 19.94% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 19.94% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 19.94% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 19.94% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemRead 5343659 50.47% 70.41% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemWrite 3132957 29.59% 100.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntAlu 25536 0.30% 0.30% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 0.30% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 0.30% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 0.30% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 0.30% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 0.30% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 0.30% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 0.30% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 0.30% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 0.30% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 0.30% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 0.30% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 0.30% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 0.30% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 0.30% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 0.30% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 0.30% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 0.30% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 0.30% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 0.30% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 0.30% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 0.30% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 0.30% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 0.30% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 0.30% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 0.30% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 0.30% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 0.30% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 0.30% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemRead 5445227 63.18% 63.47% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemWrite 3148385 36.53% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:issued_per_cycle::samples 663809705 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::mean 1.123118 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.406431 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::samples 660920432 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::mean 1.096719 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.355430 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::0 308965401 46.54% 46.54% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::1 144668555 21.79% 68.34% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::2 110038020 16.58% 84.91% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::3 52350888 7.89% 92.80% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::4 29088648 4.38% 97.18% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::5 8324547 1.25% 98.44% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::6 7676240 1.16% 99.59% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::7 1874333 0.28% 99.88% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::8 823073 0.12% 100.00% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::0 305964281 46.29% 46.29% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::1 148313904 22.44% 68.73% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::2 112740957 17.06% 85.79% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::3 49799071 7.53% 93.33% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::4 29063149 4.40% 97.72% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::5 8262993 1.25% 98.97% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::6 4169807 0.63% 99.61% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::7 1785416 0.27% 99.88% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::8 820854 0.12% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::total 663809705 # Number of insts issued each cycle -system.cpu.iq.ISSUE:rate 1.115333 # Inst issue rate +system.cpu.iq.ISSUE:issued_per_cycle::total 660920432 # Number of insts issued each cycle +system.cpu.iq.ISSUE:rate 1.089234 # Inst issue rate system.cpu.iq.fp_alu_accesses 126 # Number of floating point alu accesses system.cpu.iq.fp_inst_queue_reads 248 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_writes 340 # Number of floating instruction queue writes -system.cpu.iq.int_alu_accesses 756124359 # Number of integer alu accesses -system.cpu.iq.int_inst_queue_reads 2167725865 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_wakeup_accesses 685357549 # Number of integer instruction queue wakeup accesses -system.cpu.iq.int_inst_queue_writes 1330295825 # Number of integer instruction queue writes -system.cpu.iq.iqInstsAdded 954351941 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 745536941 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 4683780 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 371189493 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 2254982 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 805916 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 656102390 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.int_alu_accesses 733463200 # Number of integer alu accesses +system.cpu.iq.int_inst_queue_reads 2121563604 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_wakeup_accesses 680637907 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_writes 1319150008 # Number of integer instruction queue writes +system.cpu.iq.iqInstsAdded 942508573 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 724844178 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 4676961 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 371760121 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 2335916 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 799068 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 680735331 # Number of squashed operands that are examined and possibly removed from graph system.cpu.itb.accesses 0 # DTB accesses system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions @@ -415,115 +415,117 @@ system.cpu.itb.read_misses 0 # DT system.cpu.itb.write_accesses 0 # DTB write accesses system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.l2cache.ReadExReq_accesses 344509 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 34257.550447 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31005.397937 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_hits 231966 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_miss_latency 3855447500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_rate 0.326677 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 112543 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 3489440500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.326677 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 112543 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 863665 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 34190.772563 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31027.525161 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 739947 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 4230014000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.143248 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 123718 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_hits 13 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_miss_latency 3838260000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.143233 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 123705 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_accesses 16 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_hits 13 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_miss_rate 0.187500 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_misses 3 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 93000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_rate 0.187500 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_misses 3 # number of UpgradeReq MSHR misses -system.cpu.l2cache.Writeback_accesses 1064084 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 1064084 # number of Writeback hits +system.cpu.l2cache.ReadExReq_accesses 342473 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_avg_miss_latency 34244.416047 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31005.822429 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_hits 231351 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_miss_latency 3805308000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_rate 0.324469 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_misses 111122 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 3445429000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.324469 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_misses 111122 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_accesses 866749 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 34192.097787 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31026.522397 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 741784 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 4272815500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.144177 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 124965 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_hits 14 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_miss_latency 3876795000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.144161 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 124951 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_accesses 298 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_avg_miss_latency 4635.416667 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31057.291667 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_hits 202 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_miss_latency 445000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_rate 0.322148 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_misses 96 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 2981500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_rate 0.322148 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_misses 96 # number of UpgradeReq MSHR misses +system.cpu.l2cache.Writeback_accesses 1064797 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 1064797 # number of Writeback hits system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 6.437044 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 6.452091 # Average number of references to valid blocks. system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 1208174 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 34222.582229 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31016.984271 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 971913 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 8085461500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.195552 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 236261 # number of demand (read+write) misses -system.cpu.l2cache.demand_mshr_hits 13 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 7327700500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.195541 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 236248 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_accesses 1209222 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 34216.723072 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31016.778708 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 973135 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 8078123500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.195239 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 236087 # number of demand (read+write) misses +system.cpu.l2cache.demand_mshr_hits 14 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_miss_latency 7322224000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.195227 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 236073 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.213211 # Average percentage of cache occupancy -system.cpu.l2cache.occ_%::1 0.422279 # Average percentage of cache occupancy -system.cpu.l2cache.occ_blocks::0 6986.504420 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 13837.237986 # Average occupied blocks per context -system.cpu.l2cache.overall_accesses 1208174 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 34222.582229 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31016.984271 # average overall mshr miss latency +system.cpu.l2cache.occ_%::0 0.216648 # Average percentage of cache occupancy +system.cpu.l2cache.occ_%::1 0.421153 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 7099.133966 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 13800.334539 # Average occupied blocks per context +system.cpu.l2cache.overall_accesses 1209222 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 34216.723072 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31016.778708 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 971913 # number of overall hits -system.cpu.l2cache.overall_miss_latency 8085461500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.195552 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 236261 # number of overall misses -system.cpu.l2cache.overall_mshr_hits 13 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 7327700500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.195541 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 236248 # number of overall MSHR misses +system.cpu.l2cache.overall_hits 973135 # number of overall hits +system.cpu.l2cache.overall_miss_latency 8078123500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.195239 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 236087 # number of overall misses +system.cpu.l2cache.overall_mshr_hits 14 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_miss_latency 7322224000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.195227 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 236073 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.replacements 217136 # number of replacements -system.cpu.l2cache.sampled_refs 237363 # Sample count of references to valid blocks. +system.cpu.l2cache.replacements 217008 # number of replacements +system.cpu.l2cache.sampled_refs 237229 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 20823.742406 # Cycle average of tags in use -system.cpu.l2cache.total_refs 1527916 # Total number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 241420822000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 171788 # number of writebacks -system.cpu.memDep0.conflictingLoads 54696737 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 61739671 # Number of conflicting stores. -system.cpu.memDep0.insertedLoads 194483391 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 112758143 # Number of stores inserted to the mem dependence unit. -system.cpu.misc_regfile_reads 1214411471 # number of misc regfile reads -system.cpu.misc_regfile_writes 344749 # number of misc regfile writes -system.cpu.numCycles 668443504 # number of cpu cycles simulated +system.cpu.l2cache.tagsinuse 20899.468505 # Cycle average of tags in use +system.cpu.l2cache.total_refs 1530623 # Total number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 239794586000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.writebacks 171527 # number of writebacks +system.cpu.memDep0.conflictingLoads 54793834 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 61680450 # Number of conflicting stores. +system.cpu.memDep0.insertedLoads 196892006 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 114373867 # Number of stores inserted to the mem dependence unit. +system.cpu.misc_regfile_reads 1238278236 # number of misc regfile reads +system.cpu.misc_regfile_writes 4464328 # number of misc regfile writes +system.cpu.numCycles 665462439 # number of cpu cycles simulated system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.rename.RENAME:BlockCycles 12415646 # Number of cycles rename is blocking -system.cpu.rename.RENAME:CommittedMaps 448650778 # Number of HB maps that are committed -system.cpu.rename.RENAME:IQFullEvents 9472750 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 295422634 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 10451000 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:ROBFullEvents 22 # Number of times rename has blocked due to ROB full -system.cpu.rename.RENAME:RenameLookups 2625367121 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 1059917765 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 772660527 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 221340746 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 58620851 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 26319878 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 324009746 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:fp_rename_lookups 1198 # Number of floating rename lookups -system.cpu.rename.RENAME:int_rename_lookups 2625365923 # Number of integer rename lookups -system.cpu.rename.RENAME:serializeStallCycles 49689950 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 2845114 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 73898765 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 2845067 # count of temporary serializing insts renamed -system.cpu.rob.rob_reads 1570084762 # The number of ROB reads -system.cpu.rob.rob_writes 2002485622 # The number of ROB writes -system.cpu.timesIdled 109548 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.rename.RENAME:BlockCycles 11783884 # Number of cycles rename is blocking +system.cpu.rename.RENAME:CommittedMaps 448493735 # Number of HB maps that are committed +system.cpu.rename.RENAME:IQFullEvents 9081964 # Number of times rename has blocked due to IQ full +system.cpu.rename.RENAME:IdleCycles 293899856 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 10512591 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:ROBFullEvents 133 # Number of times rename has blocked due to ROB full +system.cpu.rename.RENAME:RenameLookups 2673538298 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 1068521543 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 798521782 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 223635059 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 57332647 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 24492193 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 350028044 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:fp_rename_lookups 1141 # Number of floating rename lookups +system.cpu.rename.RENAME:int_rename_lookups 2673537157 # Number of integer rename lookups +system.cpu.rename.RENAME:serializeStallCycles 49776793 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 2837350 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 62579735 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 2837280 # count of temporary serializing insts renamed +system.cpu.rob.rob_reads 1553332004 # The number of ROB reads +system.cpu.rob.rob_writes 1970603439 # The number of ROB writes +system.cpu.timesIdled 108463 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 548 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/20.parser/ref/arm/linux/simple-atomic/config.ini b/tests/long/20.parser/ref/arm/linux/simple-atomic/config.ini index a151096ae..2b400c946 100644 --- a/tests/long/20.parser/ref/arm/linux/simple-atomic/config.ini +++ b/tests/long/20.parser/ref/arm/linux/simple-atomic/config.ini @@ -61,7 +61,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=parser 2.1.dict -batch -cwd=build/ARM_SE/tests/fast/long/20.parser/arm/linux/simple-atomic +cwd=build/ARM_SE/tests/opt/long/20.parser/arm/linux/simple-atomic egid=100 env= errout=cerr diff --git a/tests/long/20.parser/ref/arm/linux/simple-atomic/simout b/tests/long/20.parser/ref/arm/linux/simple-atomic/simout index b7bee7747..1ad3a878c 100755 --- a/tests/long/20.parser/ref/arm/linux/simple-atomic/simout +++ b/tests/long/20.parser/ref/arm/linux/simple-atomic/simout @@ -5,11 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Mar 11 2011 20:10:09 -M5 revision 4decc284606a 8095 default qtip tip ext/update_add_stats.patch -M5 started Mar 11 2011 20:56:42 +M5 compiled Mar 30 2011 17:47:57 +M5 started Mar 30 2011 17:56:20 M5 executing on u200439-lin.austin.arm.com -command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/20.parser/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/fast/long/20.parser/arm/linux/simple-atomic +command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/20.parser/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/opt/long/20.parser/arm/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/20.parser/ref/arm/linux/simple-atomic/stats.txt b/tests/long/20.parser/ref/arm/linux/simple-atomic/stats.txt index ebf53733b..818f8fd56 100644 --- a/tests/long/20.parser/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/20.parser/ref/arm/linux/simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1809145 # Simulator instruction rate (inst/s) -host_mem_usage 249796 # Number of bytes of host memory used -host_seconds 315.60 # Real time elapsed on the host -host_tick_rate 920461558 # Simulator tick rate (ticks/s) +host_inst_rate 1096990 # Simulator instruction rate (inst/s) +host_mem_usage 250472 # Number of bytes of host memory used +host_seconds 520.49 # Real time elapsed on the host +host_tick_rate 558129819 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 570968176 # Number of instructions simulated sim_seconds 0.290499 # Number of seconds simulated @@ -56,18 +56,18 @@ system.cpu.numCycles 580997945 # nu system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.num_busy_cycles 580997945 # Number of busy cycles -system.cpu.num_conditional_control_insts 92286726 # number of instructions that are conditional controls +system.cpu.num_conditional_control_insts 95872736 # number of instructions that are conditional controls system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses system.cpu.num_fp_insts 16 # number of float instructions system.cpu.num_fp_register_reads 16 # number of times the floating registers were read system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_func_calls 16003168 # number of times a function call or return occured +system.cpu.num_func_calls 15725605 # number of times a function call or return occured system.cpu.num_idle_cycles 0 # Number of idle cycles system.cpu.num_insts 570968176 # Number of instructions executed system.cpu.num_int_alu_accesses 470727703 # Number of integer alu accesses system.cpu.num_int_insts 470727703 # number of integer instructions system.cpu.num_int_register_reads 1385336079 # number of times the integer registers were read -system.cpu.num_int_register_writes 425457618 # number of times the integer registers were written +system.cpu.num_int_register_writes 425113002 # number of times the integer registers were written system.cpu.num_load_insts 126029556 # Number of load instructions system.cpu.num_mem_refs 182890035 # number of memory refs system.cpu.num_store_insts 56860479 # Number of store instructions diff --git a/tests/long/20.parser/ref/arm/linux/simple-timing/config.ini b/tests/long/20.parser/ref/arm/linux/simple-timing/config.ini index 043ad11cc..75a3e24c1 100644 --- a/tests/long/20.parser/ref/arm/linux/simple-timing/config.ini +++ b/tests/long/20.parser/ref/arm/linux/simple-timing/config.ini @@ -164,7 +164,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=parser 2.1.dict -batch -cwd=build/ARM_SE/tests/fast/long/20.parser/arm/linux/simple-timing +cwd=build/ARM_SE/tests/opt/long/20.parser/arm/linux/simple-timing egid=100 env= errout=cerr diff --git a/tests/long/20.parser/ref/arm/linux/simple-timing/simerr b/tests/long/20.parser/ref/arm/linux/simple-timing/simerr index cdafa164c..eabe42249 100755 --- a/tests/long/20.parser/ref/arm/linux/simple-timing/simerr +++ b/tests/long/20.parser/ref/arm/linux/simple-timing/simerr @@ -1,5 +1,3 @@ warn: Sockets disabled, not accepting gdb connections For more information see: http://www.m5sim.org/warn/d946bea6 -warn: Complete acc isn't called on normal stores in O3. -For more information see: http://www.m5sim.org/warn/138d8573 hack: be nice to actually delete the event here diff --git a/tests/long/20.parser/ref/arm/linux/simple-timing/simout b/tests/long/20.parser/ref/arm/linux/simple-timing/simout index 3a9b66fdf..697084dd6 100755 --- a/tests/long/20.parser/ref/arm/linux/simple-timing/simout +++ b/tests/long/20.parser/ref/arm/linux/simple-timing/simout @@ -5,11 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Mar 11 2011 20:10:09 -M5 revision 4decc284606a 8095 default qtip tip ext/update_add_stats.patch -M5 started Mar 11 2011 20:33:09 +M5 compiled Mar 30 2011 17:47:57 +M5 started Mar 30 2011 17:57:49 M5 executing on u200439-lin.austin.arm.com -command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/20.parser/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/fast/long/20.parser/arm/linux/simple-timing +command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/20.parser/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/opt/long/20.parser/arm/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/20.parser/ref/arm/linux/simple-timing/stats.txt b/tests/long/20.parser/ref/arm/linux/simple-timing/stats.txt index 54e168a67..3b54b12a7 100644 --- a/tests/long/20.parser/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/20.parser/ref/arm/linux/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 827470 # Simulator instruction rate (inst/s) -host_mem_usage 257480 # Number of bytes of host memory used -host_seconds 687.68 # Real time elapsed on the host -host_tick_rate 1050246633 # Simulator tick rate (ticks/s) +host_inst_rate 577686 # Simulator instruction rate (inst/s) +host_mem_usage 258200 # Number of bytes of host memory used +host_seconds 985.02 # Real time elapsed on the host +host_tick_rate 733214267 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 569034848 # Number of instructions simulated sim_seconds 0.722234 # Number of seconds simulated @@ -249,18 +249,18 @@ system.cpu.numCycles 1444468728 # nu system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.num_busy_cycles 1444468728 # Number of busy cycles -system.cpu.num_conditional_control_insts 92286726 # number of instructions that are conditional controls +system.cpu.num_conditional_control_insts 95872736 # number of instructions that are conditional controls system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses system.cpu.num_fp_insts 16 # number of float instructions system.cpu.num_fp_register_reads 16 # number of times the floating registers were read system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_func_calls 16003168 # number of times a function call or return occured +system.cpu.num_func_calls 15725605 # number of times a function call or return occured system.cpu.num_idle_cycles 0 # Number of idle cycles system.cpu.num_insts 569034848 # Number of instructions executed system.cpu.num_int_alu_accesses 470727703 # Number of integer alu accesses system.cpu.num_int_insts 470727703 # number of integer instructions system.cpu.num_int_register_reads 1511252780 # number of times the integer registers were read -system.cpu.num_int_register_writes 425461081 # number of times the integer registers were written +system.cpu.num_int_register_writes 425113002 # number of times the integer registers were written system.cpu.num_load_insts 126029556 # Number of load instructions system.cpu.num_mem_refs 182890035 # number of memory refs system.cpu.num_store_insts 56860479 # Number of store instructions diff --git a/tests/long/30.eon/ref/arm/linux/o3-timing/config.ini b/tests/long/30.eon/ref/arm/linux/o3-timing/config.ini index fbefef88a..66031e1a3 100644 --- a/tests/long/30.eon/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/30.eon/ref/arm/linux/o3-timing/config.ini @@ -25,6 +25,8 @@ BTBEntries=4096 BTBTagSize=16 LFSTSize=1024 LQEntries=32 +LSQCheckLoads=true +LSQDepCheckShift=4 RASSize=16 SQEntries=32 SSITSize=1024 @@ -491,12 +493,12 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook -cwd=build/ARM_SE/tests/fast/long/30.eon/arm/linux/o3-timing +cwd=build/ARM_SE/tests/opt/long/30.eon/arm/linux/o3-timing egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/arm/linux/eon +executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/eon gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/30.eon/ref/arm/linux/o3-timing/simout b/tests/long/30.eon/ref/arm/linux/o3-timing/simout index 0ca6ba2b5..556348771 100755 --- a/tests/long/30.eon/ref/arm/linux/o3-timing/simout +++ b/tests/long/30.eon/ref/arm/linux/o3-timing/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Mar 18 2011 20:12:03 -M5 started Mar 18 2011 21:17:10 -M5 executing on zizzer -command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/30.eon/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/fast/long/30.eon/arm/linux/o3-timing +M5 compiled Mar 30 2011 17:47:57 +M5 started Mar 30 2011 18:04:19 +M5 executing on u200439-lin.austin.arm.com +command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/30.eon/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/opt/long/30.eon/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. @@ -17,4 +17,4 @@ info: Increasing stack size by one page. info: Increasing stack size by one page. info: Increasing stack size by one page. OO-style eon Time= 0.150000 -Exiting @ tick 151690547000 because target called exit() +Exiting @ tick 151737379000 because target called exit() diff --git a/tests/long/30.eon/ref/arm/linux/o3-timing/stats.txt b/tests/long/30.eon/ref/arm/linux/o3-timing/stats.txt index 72ade1ee4..b033858f5 100644 --- a/tests/long/30.eon/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/30.eon/ref/arm/linux/o3-timing/stats.txt @@ -1,142 +1,142 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 139716 # Simulator instruction rate (inst/s) -host_mem_usage 230084 # Number of bytes of host memory used -host_seconds 2498.39 # Real time elapsed on the host -host_tick_rate 60715238 # Simulator tick rate (ticks/s) +host_inst_rate 74668 # Simulator instruction rate (inst/s) +host_mem_usage 264768 # Number of bytes of host memory used +host_seconds 4674.91 # Real time elapsed on the host +host_tick_rate 32457846 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 349065980 # Number of instructions simulated -sim_seconds 0.151691 # Number of seconds simulated -sim_ticks 151690547000 # Number of ticks simulated +sim_insts 349065985 # Number of instructions simulated +sim_seconds 0.151737 # Number of seconds simulated +sim_ticks 151737379000 # Number of ticks simulated system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.BTBHits 20064052 # Number of BTB hits -system.cpu.BPredUnit.BTBLookups 26320164 # Number of BTB lookups -system.cpu.BPredUnit.RASInCorrect 70860 # Number of incorrect RAS predictions. -system.cpu.BPredUnit.condIncorrect 3397653 # Number of conditional branches incorrect -system.cpu.BPredUnit.condPredicted 19939350 # Number of conditional branches predicted -system.cpu.BPredUnit.lookups 36470167 # Number of BP lookups -system.cpu.BPredUnit.usedRAS 7288898 # Number of times the RAS was used to get a target. -system.cpu.commit.COM:branches 30506634 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 7586748 # number cycles where commit BW limit reached +system.cpu.BPredUnit.BTBHits 20189650 # Number of BTB hits +system.cpu.BPredUnit.BTBLookups 26438081 # Number of BTB lookups +system.cpu.BPredUnit.RASInCorrect 72569 # Number of incorrect RAS predictions. +system.cpu.BPredUnit.condIncorrect 3421912 # Number of conditional branches incorrect +system.cpu.BPredUnit.condPredicted 20033400 # Number of conditional branches predicted +system.cpu.BPredUnit.lookups 36581771 # Number of BP lookups +system.cpu.BPredUnit.usedRAS 7288333 # Number of times the RAS was used to get a target. +system.cpu.commit.COM:branches 30521887 # Number of branches committed +system.cpu.commit.COM:bw_lim_events 7594485 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle::samples 297315049 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::mean 1.174063 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::stdev 1.830157 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::samples 297396946 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::mean 1.173740 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::stdev 1.829368 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::0 153879250 51.76% 51.76% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::1 68550967 23.06% 74.81% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::2 27297315 9.18% 83.99% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::3 16153153 5.43% 89.43% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::4 11239863 3.78% 93.21% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::5 6593648 2.22% 95.43% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::6 3258875 1.10% 96.52% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::7 2755230 0.93% 97.45% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::8 7586748 2.55% 100.00% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::0 153798947 51.72% 51.72% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::1 68683080 23.09% 74.81% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::2 27481761 9.24% 84.05% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::3 16045950 5.40% 89.45% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::4 11196284 3.76% 93.21% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::5 6591467 2.22% 95.43% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::6 3251010 1.09% 96.52% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::7 2753962 0.93% 97.45% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::8 7594485 2.55% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::total 297315049 # Number of insts commited each cycle -system.cpu.commit.COM:count 349066592 # Number of instructions committed +system.cpu.commit.COM:committed_per_cycle::total 297396946 # Number of insts commited each cycle +system.cpu.commit.COM:count 349066597 # Number of instructions committed system.cpu.commit.COM:fp_insts 114216705 # Number of committed floating point instructions. system.cpu.commit.COM:function_calls 6225112 # Number of function calls committed. -system.cpu.commit.COM:int_insts 287529371 # Number of committed integer instructions. -system.cpu.commit.COM:loads 94648996 # Number of loads committed +system.cpu.commit.COM:int_insts 287529375 # Number of committed integer instructions. +system.cpu.commit.COM:loads 94648997 # Number of loads committed system.cpu.commit.COM:membars 11033 # Number of memory barriers committed -system.cpu.commit.COM:refs 177024837 # Number of memory references committed +system.cpu.commit.COM:refs 177024839 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 3383925 # The number of times a branch was mispredicted -system.cpu.commit.commitCommittedInsts 349066592 # The number of committed instructions -system.cpu.commit.commitNonSpecStalls 3555475 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 29789757 # The number of squashed insts skipped by commit -system.cpu.committedInsts 349065980 # Number of Instructions Simulated -system.cpu.committedInsts_total 349065980 # Number of Instructions Simulated -system.cpu.cpi 0.869122 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.869122 # CPI: Total CPI of All Threads -system.cpu.dcache.LoadLockedReq_accesses 11409 # number of LoadLockedReq accesses(hits+misses) +system.cpu.commit.branchMispredicts 3392850 # The number of times a branch was mispredicted +system.cpu.commit.commitCommittedInsts 349066597 # The number of committed instructions +system.cpu.commit.commitNonSpecStalls 3555476 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.commitSquashedInsts 29812251 # The number of squashed insts skipped by commit +system.cpu.committedInsts 349065985 # Number of Instructions Simulated +system.cpu.committedInsts_total 349065985 # Number of Instructions Simulated +system.cpu.cpi 0.869391 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.869391 # CPI: Total CPI of All Threads +system.cpu.dcache.LoadLockedReq_accesses 11420 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_avg_miss_latency 38000 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_hits 11407 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits 11418 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_miss_latency 76000 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_rate 0.000175 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_misses 2 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_mshr_hits 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.ReadReq_accesses 95593398 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 33910.477454 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 30796.467863 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 95590382 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 102274000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_accesses 95511418 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 33945.089582 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 30823.853743 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 95508404 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 102310500 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.000032 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 3016 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 1289 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 53185500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_misses 3014 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 1291 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 53109500 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.000018 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 1727 # number of ReadReq MSHR misses -system.cpu.dcache.StoreCondReq_accesses 11146 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_hits 11146 # number of StoreCondReq hits +system.cpu.dcache.ReadReq_mshr_misses 1723 # number of ReadReq MSHR misses +system.cpu.dcache.StoreCondReq_accesses 11147 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_hits 11147 # number of StoreCondReq hits system.cpu.dcache.WriteReq_accesses 82052672 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 32102.269728 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35439.570120 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 82033727 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 608177500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_avg_miss_latency 32101.461896 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35437.632135 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 82033724 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 608258500 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.000231 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 18945 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 16107 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 100577500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_misses 18948 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 16110 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 100572000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.000035 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 2838 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets 26227.272727 # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 38940.524331 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 38956.714348 # Average number of references to valid blocks. system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 11 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 288500 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 177646070 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 32350.598789 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 33683.023001 # average overall mshr miss latency -system.cpu.dcache.demand_hits 177624109 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 710451500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_accesses 177564090 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 32354.475913 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 33694.694146 # average overall mshr miss latency +system.cpu.dcache.demand_hits 177542128 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 710569000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.000124 # miss rate for demand accesses -system.cpu.dcache.demand_misses 21961 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 17396 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 153763000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_misses 21962 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 17401 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 153681500 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.000026 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 4565 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses 4561 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.753135 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 3084.839186 # Average occupied blocks per context -system.cpu.dcache.overall_accesses 177646070 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 32350.598789 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 33683.023001 # average overall mshr miss latency +system.cpu.dcache.occ_%::0 0.753211 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 3085.152893 # Average occupied blocks per context +system.cpu.dcache.overall_accesses 177564090 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 32354.475913 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 33694.694146 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 177624109 # number of overall hits -system.cpu.dcache.overall_miss_latency 710451500 # number of overall miss cycles +system.cpu.dcache.overall_hits 177542128 # number of overall hits +system.cpu.dcache.overall_miss_latency 710569000 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.000124 # miss rate for overall accesses -system.cpu.dcache.overall_misses 21961 # number of overall misses -system.cpu.dcache.overall_mshr_hits 17396 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 153763000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_misses 21962 # number of overall misses +system.cpu.dcache.overall_mshr_hits 17401 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 153681500 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.000026 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 4565 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses 4561 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.replacements 1402 # number of replacements -system.cpu.dcache.sampled_refs 4562 # Sample count of references to valid blocks. +system.cpu.dcache.replacements 1400 # number of replacements +system.cpu.dcache.sampled_refs 4558 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 3084.839186 # Cycle average of tags in use -system.cpu.dcache.total_refs 177646672 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 3085.152893 # Cycle average of tags in use +system.cpu.dcache.total_refs 177564704 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 1023 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 139700611 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 71034 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 7228761 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 408720937 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 85085390 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 69907941 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 5944542 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 201754 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 2621106 # Number of cycles decode is unblocking +system.cpu.dcache.writebacks 1021 # number of writebacks +system.cpu.decode.DECODE:BlockedCycles 139649394 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BranchMispred 71446 # Number of times decode detected a branch misprediction +system.cpu.decode.DECODE:BranchResolved 7239931 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 408881420 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 85142692 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 69995506 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 5956648 # Number of cycles decode is squashing +system.cpu.decode.DECODE:SquashedInsts 202337 # Number of squashed instructions handled by decode +system.cpu.decode.DECODE:UnblockCycles 2609353 # Number of cycles decode is unblocking system.cpu.dtb.accesses 0 # DTB accesses system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions @@ -158,243 +158,243 @@ system.cpu.dtb.read_misses 0 # DT system.cpu.dtb.write_accesses 0 # DTB write accesses system.cpu.dtb.write_hits 0 # DTB write hits system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.fetch.Branches 36470167 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 38697287 # Number of cache lines fetched -system.cpu.fetch.Cycles 74568068 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 438780 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 318859916 # Number of instructions fetch has processed -system.cpu.fetch.MiscStallCycles 20920 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.SquashCycles 3516150 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.120212 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 38697287 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 27352950 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 1.051021 # Number of inst fetches per cycle -system.cpu.fetch.rateDist::samples 303259590 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.373282 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.757488 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.Branches 36581771 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 38750811 # Number of cache lines fetched +system.cpu.fetch.Cycles 74679621 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 443401 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 319036670 # Number of instructions fetch has processed +system.cpu.fetch.MiscStallCycles 16 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.SquashCycles 3525453 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.120543 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 38750811 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 27477983 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 1.051279 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 303353593 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.373711 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.756892 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 229247017 75.59% 75.59% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 9043835 2.98% 78.58% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 5596121 1.85% 80.42% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 6435084 2.12% 82.54% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 5316543 1.75% 84.30% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 4702041 1.55% 85.85% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 3588760 1.18% 87.03% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 4030820 1.33% 88.36% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 35299369 11.64% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 229229916 75.57% 75.57% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 9045346 2.98% 78.55% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 5665347 1.87% 80.41% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 6451006 2.13% 82.54% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 5318728 1.75% 84.29% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 4703234 1.55% 85.84% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 3636973 1.20% 87.04% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 4046277 1.33% 88.38% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 35256766 11.62% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 303259590 # Number of instructions fetched each cycle (Total) -system.cpu.fp_regfile_reads 185391890 # number of floating regfile reads -system.cpu.fp_regfile_writes 131539425 # number of floating regfile writes -system.cpu.icache.ReadReq_accesses 38697287 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 11752.678794 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 8359.038302 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 38681235 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 188654000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.000415 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 16052 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 413 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 130727000 # number of ReadReq MSHR miss cycles +system.cpu.fetch.rateDist::total 303353593 # Number of instructions fetched each cycle (Total) +system.cpu.fp_regfile_reads 185399370 # number of floating regfile reads +system.cpu.fp_regfile_writes 131540962 # number of floating regfile writes +system.cpu.icache.ReadReq_accesses 38750811 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 11739.616414 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 8345.912955 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 38734752 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 188526500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.000414 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 16059 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 412 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 130588500 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000404 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 15639 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses 15647 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 2473.857316 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 2476.013296 # Average number of references to valid blocks. system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 38697287 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 11752.678794 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 8359.038302 # average overall mshr miss latency -system.cpu.icache.demand_hits 38681235 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 188654000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.000415 # miss rate for demand accesses -system.cpu.icache.demand_misses 16052 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 413 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 130727000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_accesses 38750811 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 11739.616414 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 8345.912955 # average overall mshr miss latency +system.cpu.icache.demand_hits 38734752 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 188526500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.000414 # miss rate for demand accesses +system.cpu.icache.demand_misses 16059 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 412 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 130588500 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.000404 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 15639 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses 15647 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.893029 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 1828.923459 # Average occupied blocks per context -system.cpu.icache.overall_accesses 38697287 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 11752.678794 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 8359.038302 # average overall mshr miss latency +system.cpu.icache.occ_%::0 0.891809 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 1826.425729 # Average occupied blocks per context +system.cpu.icache.overall_accesses 38750811 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 11739.616414 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 8345.912955 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 38681235 # number of overall hits -system.cpu.icache.overall_miss_latency 188654000 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.000415 # miss rate for overall accesses -system.cpu.icache.overall_misses 16052 # number of overall misses -system.cpu.icache.overall_mshr_hits 413 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 130727000 # number of overall MSHR miss cycles +system.cpu.icache.overall_hits 38734752 # number of overall hits +system.cpu.icache.overall_miss_latency 188526500 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.000414 # miss rate for overall accesses +system.cpu.icache.overall_misses 16059 # number of overall misses +system.cpu.icache.overall_mshr_hits 412 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 130588500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.000404 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 15639 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses 15647 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.replacements 13772 # number of replacements -system.cpu.icache.sampled_refs 15636 # Sample count of references to valid blocks. +system.cpu.icache.replacements 13782 # number of replacements +system.cpu.icache.sampled_refs 15644 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1828.923459 # Cycle average of tags in use -system.cpu.icache.total_refs 38681233 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 1826.425729 # Cycle average of tags in use +system.cpu.icache.total_refs 38734752 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 121505 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 31578601 # Number of branches executed -system.cpu.iew.EXEC:nop 55958 # number of nop insts executed -system.cpu.iew.EXEC:rate 1.199464 # Inst execution rate -system.cpu.iew.EXEC:refs 183601400 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 84386759 # Number of stores executed +system.cpu.idleCycles 121166 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 31598497 # Number of branches executed +system.cpu.iew.EXEC:nop 47916 # number of nop insts executed +system.cpu.iew.EXEC:rate 1.198862 # Inst execution rate +system.cpu.iew.EXEC:refs 183613240 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 84389722 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 302383263 # num instructions consuming a value -system.cpu.iew.WB:count 361678841 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.513536 # average fanout of values written-back +system.cpu.iew.WB:consumers 302337892 # num instructions consuming a value +system.cpu.iew.WB:count 361679600 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.513512 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 155284641 # num instructions producing a value -system.cpu.iew.WB:rate 1.192160 # insts written-back per cycle -system.cpu.iew.WB:sent 362172156 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 3565736 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 6223 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 104097603 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 3634765 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 5762936 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 89132401 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 378858680 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 99214641 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 3439356 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 363894705 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 99 # Number of times the IQ has become full, causing a stall +system.cpu.iew.WB:producers 155254133 # num instructions producing a value +system.cpu.iew.WB:rate 1.191795 # insts written-back per cycle +system.cpu.iew.WB:sent 362096434 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 3575174 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 6232 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 104118233 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 3634513 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 5773715 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 89143121 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 378881196 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 99223518 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 3473693 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 363824242 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 103 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewLSQFullEvents 34 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 5944542 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 242 # Number of cycles IEW is unblocking +system.cpu.iew.iewSquashCycles 5956648 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 247 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread.0.cacheBlocked 169 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 3534064 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 41128 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.forwLoads 3624729 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 41298 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 165865 # Number of memory ordering violations -system.cpu.iew.lsq.thread.0.rescheduledLoads 275 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 9448606 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 6756560 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 165865 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 371765 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 3193971 # Number of branches that were predicted taken incorrectly -system.cpu.int_regfile_reads 845234199 # number of integer regfile reads -system.cpu.int_regfile_writes 184410543 # number of integer regfile writes -system.cpu.ipc 1.150586 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.150586 # IPC: Total IPC of All Threads +system.cpu.iew.lsq.thread.0.memOrderViolation 165832 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.rescheduledLoads 270 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread.0.squashedLoads 9469235 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 6767279 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 165832 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 360118 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 3215056 # Number of branches that were predicted taken incorrectly +system.cpu.int_regfile_reads 845155916 # number of integer regfile reads +system.cpu.int_regfile_writes 184404890 # number of integer regfile writes +system.cpu.ipc 1.150231 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.150231 # IPC: Total IPC of All Threads system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntAlu 125195241 34.08% 34.08% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntMult 2147341 0.58% 34.67% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 34.67% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatAdd 3 0.00% 34.67% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 34.67% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 34.67% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 34.67% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 34.67% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 34.67% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 34.67% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 34.67% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 34.67% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdCmp 1 0.00% 34.67% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 34.67% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 34.67% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 34.67% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 34.67% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 34.67% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 34.67% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 34.67% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 6684288 1.82% 36.49% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 36.49% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 8300579 2.26% 38.75% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 3402180 0.93% 39.67% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 1567163 0.43% 40.10% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 20208124 5.50% 45.60% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 7197502 1.96% 47.56% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 7077300 1.93% 49.49% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 175286 0.05% 49.53% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemRead 100094621 27.25% 76.78% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemWrite 85284432 23.22% 100.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntAlu 125135876 34.07% 34.07% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntMult 2147375 0.58% 34.65% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 34.65% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatAdd 3 0.00% 34.65% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 34.65% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 34.65% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 34.65% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 34.65% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 34.65% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 34.65% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 34.65% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 34.65% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 34.65% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 34.65% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 34.65% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 34.65% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 34.65% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 34.65% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 34.65% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 34.65% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 6684118 1.82% 36.47% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 36.47% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 8302383 2.26% 38.73% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 3402331 0.93% 39.66% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 1567187 0.43% 40.09% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 20210889 5.50% 45.59% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 7197544 1.96% 47.55% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 7077346 1.93% 49.48% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 175286 0.05% 49.52% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemRead 100106815 27.25% 76.78% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemWrite 85290782 23.22% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::total 367334061 # Type of FU issued -system.cpu.iq.ISSUE:fu_busy_cnt 12197832 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.033206 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:FU_type_0::total 367297935 # Type of FU issued +system.cpu.iq.ISSUE:fu_busy_cnt 12277552 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.033427 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntAlu 5508 0.05% 0.05% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntMult 5040 0.04% 0.09% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 0.09% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 0.09% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 0.09% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 0.09% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 0.09% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 0.09% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 0.09% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 0.09% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 0.09% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 0.09% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 0.09% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 0.09% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 0.09% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 0.09% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 0.09% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 0.09% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 0.09% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 0.09% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 66 0.00% 0.09% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 0.09% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 0.09% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 1308 0.01% 0.10% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 3 0.00% 0.10% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 233645 1.92% 2.01% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMult 627 0.01% 2.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 321940 2.64% 4.66% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 4.66% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemRead 7433926 60.94% 65.60% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemWrite 4195769 34.40% 100.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntAlu 1371 0.01% 0.01% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntMult 5040 0.04% 0.05% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 0.05% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 0.05% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 0.05% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 0.05% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 0.05% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 0.05% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 0.05% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 0.05% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 0.05% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 0.05% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 0.05% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 0.05% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 0.05% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 0.05% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 0.05% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 0.05% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 0.05% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 0.05% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 66 0.00% 0.05% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 0.05% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 0.05% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 1306 0.01% 0.06% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 3 0.00% 0.06% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 233643 1.90% 1.97% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatMult 626 0.01% 1.97% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 321940 2.62% 4.59% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 4.59% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemRead 7517293 61.23% 65.82% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemWrite 4196264 34.18% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:issued_per_cycle::samples 303259590 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::mean 1.211286 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.642583 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::samples 303353593 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::mean 1.210791 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.640692 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::0 151189237 49.85% 49.85% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::1 63508236 20.94% 70.80% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::2 27984122 9.23% 80.02% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::3 21601335 7.12% 87.15% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::4 21428973 7.07% 94.21% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::5 10561255 3.48% 97.70% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::6 4840954 1.60% 99.29% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::7 1678139 0.55% 99.85% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::8 467339 0.15% 100.00% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::0 151157606 49.83% 49.83% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::1 63646504 20.98% 70.81% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::2 27917034 9.20% 80.01% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::3 21656943 7.14% 87.15% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::4 21437631 7.07% 94.22% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::5 10744150 3.54% 97.76% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::6 4648214 1.53% 99.29% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::7 1678112 0.55% 99.85% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::8 467399 0.15% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::total 303259590 # Number of insts issued each cycle -system.cpu.iq.ISSUE:rate 1.210801 # Inst issue rate -system.cpu.iq.fp_alu_accesses 125152178 # Number of floating point alu accesses -system.cpu.iq.fp_inst_queue_reads 243612430 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_wakeup_accesses 116468066 # Number of floating instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_writes 124271782 # Number of floating instruction queue writes -system.cpu.iq.int_alu_accesses 254379715 # Number of integer alu accesses -system.cpu.iq.int_inst_queue_reads 807715135 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_wakeup_accesses 245210775 # Number of integer instruction queue wakeup accesses -system.cpu.iq.int_inst_queue_writes 282420664 # Number of integer instruction queue writes -system.cpu.iq.iqInstsAdded 375156709 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 367334061 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 3646013 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 27828461 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 1202021 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 90538 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 56356812 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.ISSUE:issued_per_cycle::total 303353593 # Number of insts issued each cycle +system.cpu.iq.ISSUE:rate 1.210308 # Inst issue rate +system.cpu.iq.fp_alu_accesses 125160042 # Number of floating point alu accesses +system.cpu.iq.fp_inst_queue_reads 243629757 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_wakeup_accesses 116471069 # Number of floating instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_writes 124289037 # Number of floating instruction queue writes +system.cpu.iq.int_alu_accesses 254415445 # Number of integer alu accesses +system.cpu.iq.int_inst_queue_reads 807801978 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_wakeup_accesses 245208531 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_writes 282487868 # Number of integer instruction queue writes +system.cpu.iq.iqInstsAdded 375187519 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 367297935 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 3645761 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 27882412 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 1204720 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 90285 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 56560737 # Number of squashed operands that are examined and possibly removed from graph system.cpu.itb.accesses 0 # DTB accesses system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions @@ -417,26 +417,26 @@ system.cpu.itb.write_accesses 0 # DT system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses system.cpu.l2cache.ReadExReq_accesses 2835 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 34417.287895 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31254.348598 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 34415.690451 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31254.703585 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_hits 18 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_miss_latency 96953500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 96949000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_rate 0.993651 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_misses 2817 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 88043500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 88044500 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.993651 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_misses 2817 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 17363 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 34335.562731 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31152.310924 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 13027 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 148879000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.249726 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 4336 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_hits 52 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_miss_latency 133456500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.246732 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 4284 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_accesses 17366 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 34342.074861 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31154.898293 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 13038 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 148632500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.249223 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 4328 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_hits 51 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_miss_latency 133249500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.246286 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 4277 # number of ReadReq MSHR misses system.cpu.l2cache.UpgradeReq_accesses 3 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31000 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses @@ -444,86 +444,86 @@ system.cpu.l2cache.UpgradeReq_misses 3 # nu system.cpu.l2cache.UpgradeReq_mshr_miss_latency 93000 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_misses 3 # number of UpgradeReq MSHR misses -system.cpu.l2cache.Writeback_accesses 1023 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 1023 # number of Writeback hits +system.cpu.l2cache.Writeback_accesses 1021 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 1021 # number of Writeback hits system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 2.520377 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 2.526863 # Average number of references to valid blocks. system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 20198 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 34367.747798 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31192.789748 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 13045 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 245832500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.354144 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 7153 # number of demand (read+write) misses -system.cpu.l2cache.demand_mshr_hits 52 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 221500000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.351569 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 7101 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_accesses 20201 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 34371.098670 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31194.530589 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 13056 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 245581500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.353695 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 7145 # number of demand (read+write) misses +system.cpu.l2cache.demand_mshr_hits 51 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_miss_latency 221294000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.351171 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 7094 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.103835 # Average percentage of cache occupancy -system.cpu.l2cache.occ_%::1 0.011338 # Average percentage of cache occupancy -system.cpu.l2cache.occ_blocks::0 3402.462231 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 371.534678 # Average occupied blocks per context -system.cpu.l2cache.overall_accesses 20198 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 34367.747798 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31192.789748 # average overall mshr miss latency +system.cpu.l2cache.occ_%::0 0.103738 # Average percentage of cache occupancy +system.cpu.l2cache.occ_%::1 0.011318 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 3399.287353 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 370.862974 # Average occupied blocks per context +system.cpu.l2cache.overall_accesses 20201 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 34371.098670 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31194.530589 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 13045 # number of overall hits -system.cpu.l2cache.overall_miss_latency 245832500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.354144 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 7153 # number of overall misses -system.cpu.l2cache.overall_mshr_hits 52 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 221500000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.351569 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 7101 # number of overall MSHR misses +system.cpu.l2cache.overall_hits 13056 # number of overall hits +system.cpu.l2cache.overall_miss_latency 245581500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.353695 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 7145 # number of overall misses +system.cpu.l2cache.overall_mshr_hits 51 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_miss_latency 221294000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.351171 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 7094 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.replacements 53 # number of replacements -system.cpu.l2cache.sampled_refs 5202 # Sample count of references to valid blocks. +system.cpu.l2cache.sampled_refs 5193 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 3773.996909 # Cycle average of tags in use -system.cpu.l2cache.total_refs 13111 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 3770.150327 # Cycle average of tags in use +system.cpu.l2cache.total_refs 13122 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.memDep0.conflictingLoads 11713930 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 25106151 # Number of conflicting stores. -system.cpu.memDep0.insertedLoads 104097603 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 89132401 # Number of stores inserted to the mem dependence unit. -system.cpu.misc_regfile_reads 963036910 # number of misc regfile reads -system.cpu.misc_regfile_writes 43097542 # number of misc regfile writes -system.cpu.numCycles 303381095 # number of cpu cycles simulated +system.cpu.memDep0.conflictingLoads 11875967 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 25086687 # Number of conflicting stores. +system.cpu.memDep0.insertedLoads 104118233 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 89143121 # Number of stores inserted to the mem dependence unit. +system.cpu.misc_regfile_reads 963294655 # number of misc regfile reads +system.cpu.misc_regfile_writes 34422261 # number of misc regfile writes +system.cpu.numCycles 303474759 # number of cpu cycles simulated system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.rename.RENAME:BlockCycles 825170 # Number of cycles rename is blocking -system.cpu.rename.RENAME:CommittedMaps 344460462 # Number of HB maps that are committed -system.cpu.rename.RENAME:IQFullEvents 48323 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 92021425 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 4815329 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:BlockCycles 833030 # Number of cycles rename is blocking +system.cpu.rename.RENAME:CommittedMaps 340927172 # Number of HB maps that are committed +system.cpu.rename.RENAME:IQFullEvents 47966 # Number of times rename has blocked due to IQ full +system.cpu.rename.RENAME:IdleCycles 92085018 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 4772387 # Number of times rename has blocked due to LSQ full system.cpu.rename.RENAME:ROBFullEvents 1 # Number of times rename has blocked due to ROB full -system.cpu.rename.RENAME:RenameLookups 1568557063 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 396913119 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 386168908 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 66099997 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 5944542 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 17924907 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 41708443 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:fp_rename_lookups 797945883 # Number of floating rename lookups -system.cpu.rename.RENAME:int_rename_lookups 770611180 # Number of integer rename lookups -system.cpu.rename.RENAME:serializeStallCycles 120443549 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 12410013 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 58864418 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 3692672 # count of temporary serializing insts renamed -system.cpu.rob.rob_reads 668582127 # The number of ROB reads -system.cpu.rob.rob_writes 763657860 # The number of ROB writes -system.cpu.timesIdled 2620 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.rename.RENAME:RenameLookups 1568873073 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 396996902 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 382623172 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 66169446 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 5956648 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 17891726 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 41695997 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:fp_rename_lookups 798025803 # Number of floating rename lookups +system.cpu.rename.RENAME:int_rename_lookups 770847270 # Number of integer rename lookups +system.cpu.rename.RENAME:serializeStallCycles 120417725 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 12413036 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 58729283 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 3692499 # count of temporary serializing insts renamed +system.cpu.rob.rob_reads 668678786 # The number of ROB reads +system.cpu.rob.rob_writes 763715026 # The number of ROB writes +system.cpu.timesIdled 2617 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 191 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/30.eon/ref/arm/linux/simple-atomic/config.ini b/tests/long/30.eon/ref/arm/linux/simple-atomic/config.ini index 392543608..50c83e5cc 100644 --- a/tests/long/30.eon/ref/arm/linux/simple-atomic/config.ini +++ b/tests/long/30.eon/ref/arm/linux/simple-atomic/config.ini @@ -61,7 +61,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook -cwd=build/ARM_SE/tests/fast/long/30.eon/arm/linux/simple-atomic +cwd=build/ARM_SE/tests/opt/long/30.eon/arm/linux/simple-atomic egid=100 env= errout=cerr diff --git a/tests/long/30.eon/ref/arm/linux/simple-atomic/simout b/tests/long/30.eon/ref/arm/linux/simple-atomic/simout index ec0472b91..6a6041ffa 100755 --- a/tests/long/30.eon/ref/arm/linux/simple-atomic/simout +++ b/tests/long/30.eon/ref/arm/linux/simple-atomic/simout @@ -5,11 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Mar 11 2011 20:10:09 -M5 revision 4decc284606a 8095 default qtip tip ext/update_add_stats.patch -M5 started Mar 11 2011 20:29:05 +M5 compiled Mar 30 2011 17:47:57 +M5 started Mar 30 2011 18:05:11 M5 executing on u200439-lin.austin.arm.com -command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/30.eon/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/fast/long/30.eon/arm/linux/simple-atomic +command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/30.eon/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/opt/long/30.eon/arm/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/long/30.eon/ref/arm/linux/simple-atomic/stats.txt b/tests/long/30.eon/ref/arm/linux/simple-atomic/stats.txt index d8a1a1d08..9bfaf4046 100644 --- a/tests/long/30.eon/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/30.eon/ref/arm/linux/simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1495798 # Simulator instruction rate (inst/s) -host_mem_usage 254688 # Number of bytes of host memory used -host_seconds 233.36 # Real time elapsed on the host -host_tick_rate 909925289 # Simulator tick rate (ticks/s) +host_inst_rate 854402 # Simulator instruction rate (inst/s) +host_mem_usage 255368 # Number of bytes of host memory used +host_seconds 408.55 # Real time elapsed on the host +host_tick_rate 519751077 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 349065408 # Number of instructions simulated sim_seconds 0.212344 # Number of seconds simulated @@ -56,18 +56,18 @@ system.cpu.numCycles 424688097 # nu system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.num_busy_cycles 424688097 # Number of busy cycles -system.cpu.num_conditional_control_insts 16255902 # number of instructions that are conditional controls +system.cpu.num_conditional_control_insts 16271154 # number of instructions that are conditional controls system.cpu.num_fp_alu_accesses 114216705 # Number of float alu accesses system.cpu.num_fp_insts 114216705 # number of float instructions system.cpu.num_fp_register_reads 180262959 # number of times the floating registers were read system.cpu.num_fp_register_writes 126152315 # number of times the floating registers were written -system.cpu.num_func_calls 12435295 # number of times a function call or return occured +system.cpu.num_func_calls 12433363 # number of times a function call or return occured system.cpu.num_idle_cycles 0 # Number of idle cycles system.cpu.num_insts 349065408 # Number of instructions executed system.cpu.num_int_alu_accesses 287528428 # Number of integer alu accesses system.cpu.num_int_insts 287528428 # number of integer instructions system.cpu.num_int_register_reads 1216522338 # number of times the integer registers were read -system.cpu.num_int_register_writes 216261597 # number of times the integer registers were written +system.cpu.num_int_register_writes 207564016 # number of times the integer registers were written system.cpu.num_load_insts 94648758 # Number of load instructions system.cpu.num_mem_refs 177024357 # number of memory refs system.cpu.num_store_insts 82375599 # Number of store instructions diff --git a/tests/long/30.eon/ref/arm/linux/simple-timing/config.ini b/tests/long/30.eon/ref/arm/linux/simple-timing/config.ini index 8ca4edc2e..52b5d655c 100644 --- a/tests/long/30.eon/ref/arm/linux/simple-timing/config.ini +++ b/tests/long/30.eon/ref/arm/linux/simple-timing/config.ini @@ -164,7 +164,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook -cwd=build/ARM_SE/tests/fast/long/30.eon/arm/linux/simple-timing +cwd=build/ARM_SE/tests/opt/long/30.eon/arm/linux/simple-timing egid=100 env= errout=cerr diff --git a/tests/long/30.eon/ref/arm/linux/simple-timing/simerr b/tests/long/30.eon/ref/arm/linux/simple-timing/simerr index fc990d9e5..0de362399 100755 --- a/tests/long/30.eon/ref/arm/linux/simple-timing/simerr +++ b/tests/long/30.eon/ref/arm/linux/simple-timing/simerr @@ -1,20 +1,12 @@ warn: Sockets disabled, not accepting gdb connections For more information see: http://www.m5sim.org/warn/d946bea6 -warn: Complete acc isn't called on normal stores in O3. -For more information see: http://www.m5sim.org/warn/138d8573 -warn: Complete acc isn't called on normal stores in O3. -For more information see: http://www.m5sim.org/warn/138d8573 getting pixel output filename pixels_out.cook opening control file chair.control.cook opening camera file chair.camera opening surfaces file chair.surfaces reading data processing 8parts -Grid measure is warn: Complete acc isn't called on normal stores in O3. -For more information see: http://www.m5sim.org/warn/138d8573 -warn: Complete acc isn't called on normal stores in O3. -For more information see: http://www.m5sim.org/warn/138d8573 -6 by 3.0001 by 6 +Grid measure is 6 by 3.0001 by 6 cell dimension is 0.863065 Creating grid for list of length 21 Grid size = 7 by 4 by 7 diff --git a/tests/long/30.eon/ref/arm/linux/simple-timing/simout b/tests/long/30.eon/ref/arm/linux/simple-timing/simout index 3a8c991e1..b2eb72faf 100755 --- a/tests/long/30.eon/ref/arm/linux/simple-timing/simout +++ b/tests/long/30.eon/ref/arm/linux/simple-timing/simout @@ -5,11 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Mar 11 2011 20:10:09 -M5 revision 4decc284606a 8095 default qtip tip ext/update_add_stats.patch -M5 started Mar 11 2011 20:10:13 +M5 compiled Mar 30 2011 17:47:57 +M5 started Mar 30 2011 18:11:41 M5 executing on u200439-lin.austin.arm.com -command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/30.eon/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/fast/long/30.eon/arm/linux/simple-timing +command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/30.eon/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/opt/long/30.eon/arm/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/long/30.eon/ref/arm/linux/simple-timing/stats.txt b/tests/long/30.eon/ref/arm/linux/simple-timing/stats.txt index 5afa5e2b9..91b489221 100644 --- a/tests/long/30.eon/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/30.eon/ref/arm/linux/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 633525 # Simulator instruction rate (inst/s) -host_mem_usage 262364 # Number of bytes of host memory used -host_seconds 550.39 # Real time elapsed on the host -host_tick_rate 955417914 # Simulator tick rate (ticks/s) +host_inst_rate 469608 # Simulator instruction rate (inst/s) +host_mem_usage 263124 # Number of bytes of host memory used +host_seconds 742.51 # Real time elapsed on the host +host_tick_rate 708215535 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 348687131 # Number of instructions simulated sim_seconds 0.525854 # Number of seconds simulated @@ -249,18 +249,18 @@ system.cpu.numCycles 1051708950 # nu system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.num_busy_cycles 1051708950 # Number of busy cycles -system.cpu.num_conditional_control_insts 16255901 # number of instructions that are conditional controls +system.cpu.num_conditional_control_insts 16271153 # number of instructions that are conditional controls system.cpu.num_fp_alu_accesses 114216705 # Number of float alu accesses system.cpu.num_fp_insts 114216705 # number of float instructions system.cpu.num_fp_register_reads 180262959 # number of times the floating registers were read system.cpu.num_fp_register_writes 126152315 # number of times the floating registers were written -system.cpu.num_func_calls 12435295 # number of times a function call or return occured +system.cpu.num_func_calls 12433363 # number of times a function call or return occured system.cpu.num_idle_cycles 0 # Number of idle cycles system.cpu.num_insts 348687131 # Number of instructions executed system.cpu.num_int_alu_accesses 287528427 # Number of integer alu accesses system.cpu.num_int_insts 287528427 # number of integer instructions system.cpu.num_int_register_reads 1352596558 # number of times the integer registers were read -system.cpu.num_int_register_writes 216551028 # number of times the integer registers were written +system.cpu.num_int_register_writes 207564015 # number of times the integer registers were written system.cpu.num_load_insts 94648758 # Number of load instructions system.cpu.num_mem_refs 177024357 # number of memory refs system.cpu.num_store_insts 82375599 # Number of store instructions diff --git a/tests/long/40.perlbmk/ref/arm/linux/o3-timing/config.ini b/tests/long/40.perlbmk/ref/arm/linux/o3-timing/config.ini index ac8aa026d..67cc175e5 100644 --- a/tests/long/40.perlbmk/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/40.perlbmk/ref/arm/linux/o3-timing/config.ini @@ -25,6 +25,8 @@ BTBEntries=4096 BTBTagSize=16 LFSTSize=1024 LQEntries=32 +LSQCheckLoads=true +LSQDepCheckShift=4 RASSize=16 SQEntries=32 SSITSize=1024 @@ -491,12 +493,12 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=perlbmk -I. -I lib lgred.makerand.pl -cwd=build/ARM_SE/tests/fast/long/40.perlbmk/arm/linux/o3-timing +cwd=build/ARM_SE/tests/opt/long/40.perlbmk/arm/linux/o3-timing egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/arm/linux/perlbmk +executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/perlbmk gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/40.perlbmk/ref/arm/linux/o3-timing/simout b/tests/long/40.perlbmk/ref/arm/linux/o3-timing/simout index 84182c35c..166a55741 100755 --- a/tests/long/40.perlbmk/ref/arm/linux/o3-timing/simout +++ b/tests/long/40.perlbmk/ref/arm/linux/o3-timing/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Mar 18 2011 20:12:03 -M5 started Mar 18 2011 21:04:48 -M5 executing on zizzer -command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/40.perlbmk/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/fast/long/40.perlbmk/arm/linux/o3-timing +M5 compiled Mar 30 2011 17:47:57 +M5 started Mar 30 2011 18:12:10 +M5 executing on u200439-lin.austin.arm.com +command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/40.perlbmk/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/opt/long/40.perlbmk/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. @@ -1389,4 +1389,4 @@ info: Increasing stack size by one page. 2000: 760651391 1000: 4031656975 0: 2206428413 -Exiting @ tick 856846060000 because target called exit() +Exiting @ tick 869122614500 because target called exit() diff --git a/tests/long/40.perlbmk/ref/arm/linux/o3-timing/stats.txt b/tests/long/40.perlbmk/ref/arm/linux/o3-timing/stats.txt index cda6b5767..13935d49e 100644 --- a/tests/long/40.perlbmk/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/40.perlbmk/ref/arm/linux/o3-timing/stats.txt @@ -1,142 +1,142 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 120907 # Simulator instruction rate (inst/s) -host_mem_usage 227772 # Number of bytes of host memory used -host_seconds 15593.28 # Real time elapsed on the host -host_tick_rate 54949698 # Simulator tick rate (ticks/s) +host_inst_rate 81390 # Simulator instruction rate (inst/s) +host_mem_usage 261920 # Number of bytes of host memory used +host_seconds 23164.20 # Real time elapsed on the host +host_tick_rate 37520082 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 1885343186 # Number of instructions simulated -sim_seconds 0.856846 # Number of seconds simulated -sim_ticks 856846060000 # Number of ticks simulated +sim_insts 1885343131 # Number of instructions simulated +sim_seconds 0.869123 # Number of seconds simulated +sim_ticks 869122614500 # Number of ticks simulated system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.BTBHits 305871415 # Number of BTB hits -system.cpu.BPredUnit.BTBLookups 427428565 # Number of BTB lookups -system.cpu.BPredUnit.RASInCorrect 4211226 # Number of incorrect RAS predictions. -system.cpu.BPredUnit.condIncorrect 36020935 # Number of conditional branches incorrect -system.cpu.BPredUnit.condPredicted 415846626 # Number of conditional branches predicted -system.cpu.BPredUnit.lookups 551391601 # Number of BP lookups -system.cpu.BPredUnit.usedRAS 57603360 # Number of times the RAS was used to get a target. -system.cpu.commit.COM:branches 291323460 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 56939437 # number cycles where commit BW limit reached +system.cpu.BPredUnit.BTBHits 306717434 # Number of BTB hits +system.cpu.BPredUnit.BTBLookups 430322374 # Number of BTB lookups +system.cpu.BPredUnit.RASInCorrect 4126641 # Number of incorrect RAS predictions. +system.cpu.BPredUnit.condIncorrect 38509304 # Number of conditional branches incorrect +system.cpu.BPredUnit.condPredicted 414146262 # Number of conditional branches predicted +system.cpu.BPredUnit.lookups 547821195 # Number of BP lookups +system.cpu.BPredUnit.usedRAS 52353944 # Number of times the RAS was used to get a target. +system.cpu.commit.COM:branches 291352101 # Number of branches committed +system.cpu.commit.COM:bw_lim_events 58391194 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle::samples 1535085949 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::mean 1.228175 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::stdev 1.842995 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::samples 1569639960 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::mean 1.201138 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::stdev 1.832019 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::0 710902830 46.31% 46.31% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::1 422912424 27.55% 73.86% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::2 179951323 11.72% 85.58% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::3 73924591 4.82% 90.40% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::4 52811288 3.44% 93.84% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::5 15756065 1.03% 94.86% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::6 17991551 1.17% 96.04% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::7 3896440 0.25% 96.29% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::8 56939437 3.71% 100.00% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::0 741490044 47.24% 47.24% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::1 428382990 27.29% 74.53% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::2 179836279 11.46% 85.99% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::3 75300710 4.80% 90.79% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::4 51350508 3.27% 94.06% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::5 14363186 0.92% 94.97% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::6 16626388 1.06% 96.03% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::7 3898661 0.25% 96.28% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::8 58391194 3.72% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::total 1535085949 # Number of insts commited each cycle -system.cpu.commit.COM:count 1885354202 # Number of instructions committed +system.cpu.commit.COM:committed_per_cycle::total 1569639960 # Number of insts commited each cycle +system.cpu.commit.COM:count 1885354147 # Number of instructions committed system.cpu.commit.COM:fp_insts 52289415 # Number of committed floating point instructions. system.cpu.commit.COM:function_calls 41577833 # Number of function calls committed. -system.cpu.commit.COM:int_insts 1660589612 # Number of committed integer instructions. -system.cpu.commit.COM:loads 631390749 # Number of loads committed +system.cpu.commit.COM:int_insts 1660589568 # Number of committed integer instructions. +system.cpu.commit.COM:loads 631390738 # Number of loads committed system.cpu.commit.COM:membars 9986 # Number of memory barriers committed -system.cpu.commit.COM:refs 908389613 # Number of memory references committed +system.cpu.commit.COM:refs 908389591 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 41574667 # The number of times a branch was mispredicted -system.cpu.commit.commitCommittedInsts 1885354202 # The number of committed instructions -system.cpu.commit.commitNonSpecStalls 211799 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 1130143872 # The number of squashed insts skipped by commit -system.cpu.committedInsts 1885343186 # Number of Instructions Simulated -system.cpu.committedInsts_total 1885343186 # Number of Instructions Simulated -system.cpu.cpi 0.908955 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.908955 # CPI: Total CPI of All Threads -system.cpu.dcache.LoadLockedReq_accesses 16574 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_avg_miss_latency 36166.666667 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_hits 16571 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_miss_latency 108500 # number of LoadLockedReq miss cycles +system.cpu.commit.branchMispredicts 44034324 # The number of times a branch was mispredicted +system.cpu.commit.commitCommittedInsts 1885354147 # The number of committed instructions +system.cpu.commit.commitNonSpecStalls 211788 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.commitSquashedInsts 1159545124 # The number of squashed insts skipped by commit +system.cpu.committedInsts 1885343131 # Number of Instructions Simulated +system.cpu.committedInsts_total 1885343131 # Number of Instructions Simulated +system.cpu.cpi 0.921978 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.921978 # CPI: Total CPI of All Threads +system.cpu.dcache.LoadLockedReq_accesses 16563 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_avg_miss_latency 36000 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_hits 16560 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_miss_latency 108000 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_rate 0.000181 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_misses 3 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_mshr_hits 3 # number of LoadLockedReq MSHR hits -system.cpu.dcache.ReadReq_accesses 710900650 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 34447.466761 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34122.014006 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 708969387 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 66527118000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.002717 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 1931263 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 468894 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 49898975500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.002057 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 1462369 # number of ReadReq MSHR misses -system.cpu.dcache.StoreCondReq_accesses 13552 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_hits 13552 # number of StoreCondReq hits -system.cpu.dcache.WriteReq_accesses 276935679 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 35080.855979 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 32457.559426 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 276128837 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 28304708000 # number of WriteReq miss cycles +system.cpu.dcache.ReadReq_accesses 719743327 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 34434.084402 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34107.861435 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 717811546 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 66519110000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.002684 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 1931781 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 469020 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 49891649500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.002032 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 1462761 # number of ReadReq MSHR misses +system.cpu.dcache.StoreCondReq_accesses 13541 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_hits 13541 # number of StoreCondReq hits +system.cpu.dcache.WriteReq_accesses 276935678 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 35082.855730 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 32466.582320 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 276128872 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 28305058500 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.002913 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 806842 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 734105 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 2360865500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_misses 806806 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 734090 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 2360840000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.000263 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 72737 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 72716 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 14875 # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 641.733949 # Average number of references to valid blocks. +system.cpu.dcache.avg_blocked_cycles::no_targets 14000 # average number of cycles each access was blocked +system.cpu.dcache.avg_refs 647.337915 # Average number of references to valid blocks. system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 4 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 59500 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 56000 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 987836329 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 34634.108626 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 34043.148160 # average overall mshr miss latency -system.cpu.dcache.demand_hits 985098224 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 94831826000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.002772 # miss rate for demand accesses -system.cpu.dcache.demand_misses 2738105 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 1202999 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 52259841000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.001554 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 1535106 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_accesses 996679005 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 34625.216763 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 34030.134935 # average overall mshr miss latency +system.cpu.dcache.demand_hits 993940418 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 94824168500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.002748 # miss rate for demand accesses +system.cpu.dcache.demand_misses 2738587 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 1203110 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 52252489500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.001541 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 1535477 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.999728 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 4094.887061 # Average occupied blocks per context -system.cpu.dcache.overall_accesses 987836329 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 34634.108626 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 34043.148160 # average overall mshr miss latency +system.cpu.dcache.occ_%::0 0.999735 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 4094.913997 # Average occupied blocks per context +system.cpu.dcache.overall_accesses 996679005 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 34625.216763 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 34030.134935 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 985098224 # number of overall hits -system.cpu.dcache.overall_miss_latency 94831826000 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.002772 # miss rate for overall accesses -system.cpu.dcache.overall_misses 2738105 # number of overall misses -system.cpu.dcache.overall_mshr_hits 1202999 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 52259841000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.001554 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 1535106 # number of overall MSHR misses +system.cpu.dcache.overall_hits 993940418 # number of overall hits +system.cpu.dcache.overall_miss_latency 94824168500 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.002748 # miss rate for overall accesses +system.cpu.dcache.overall_misses 2738587 # number of overall misses +system.cpu.dcache.overall_mshr_hits 1203110 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 52252489500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.001541 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 1535477 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.replacements 1531008 # number of replacements -system.cpu.dcache.sampled_refs 1535104 # Sample count of references to valid blocks. +system.cpu.dcache.replacements 1531378 # number of replacements +system.cpu.dcache.sampled_refs 1535474 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4094.887061 # Cycle average of tags in use -system.cpu.dcache.total_refs 985128352 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 336577000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 107051 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 147664711 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 10715 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 87011249 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 3347721217 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 741403203 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 643451103 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 155800890 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 20615 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 2566930 # Number of cycles decode is unblocking +system.cpu.dcache.tagsinuse 4094.913997 # Cycle average of tags in use +system.cpu.dcache.total_refs 993970537 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 333433000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 106994 # number of writebacks +system.cpu.decode.DECODE:BlockedCycles 146923379 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BranchMispred 10558 # Number of times decode detected a branch misprediction +system.cpu.decode.DECODE:BranchResolved 87779592 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 3387651447 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 772293047 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 647864668 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 162682073 # Number of cycles decode is squashing +system.cpu.decode.DECODE:SquashedInsts 19702 # Number of squashed instructions handled by decode +system.cpu.decode.DECODE:UnblockCycles 2558864 # Number of cycles decode is unblocking system.cpu.dtb.accesses 0 # DTB accesses system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions @@ -158,243 +158,243 @@ system.cpu.dtb.read_misses 0 # DT system.cpu.dtb.write_accesses 0 # DTB write accesses system.cpu.dtb.write_hits 0 # DTB write hits system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.fetch.Branches 551391601 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 362185761 # Number of cache lines fetched -system.cpu.fetch.Cycles 665483414 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 16434136 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 2595927696 # Number of instructions fetch has processed -system.cpu.fetch.MiscStallCycles 41205 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.SquashCycles 42962333 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.321757 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 362185761 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 363474775 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 1.514816 # Number of inst fetches per cycle -system.cpu.fetch.rateDist::samples 1690886837 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.036253 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.984064 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.Branches 547821195 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 367105078 # Number of cache lines fetched +system.cpu.fetch.Cycles 665860659 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 19277172 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 2595469256 # Number of instructions fetch has processed +system.cpu.fetch.MiscStallCycles 1285897 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.SquashCycles 45421845 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.315158 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 367105078 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 359071378 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 1.493155 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 1732322031 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.998705 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.975519 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 1025439720 60.65% 60.65% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 44027477 2.60% 63.25% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 104237585 6.16% 69.41% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 62717330 3.71% 73.12% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 88060980 5.21% 78.33% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 56164505 3.32% 81.65% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 31149333 1.84% 83.49% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 50263393 2.97% 86.47% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 228826514 13.53% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 1066497771 61.56% 61.56% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 40398523 2.33% 63.90% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 108471254 6.26% 70.16% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 62827060 3.63% 73.79% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 83015606 4.79% 78.58% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 56381906 3.25% 81.83% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 33027713 1.91% 83.74% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 49177401 2.84% 86.58% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 232524797 13.42% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1690886837 # Number of instructions fetched each cycle (Total) -system.cpu.fp_regfile_reads 71543856 # number of floating regfile reads -system.cpu.fp_regfile_writes 49528271 # number of floating regfile writes -system.cpu.icache.ReadReq_accesses 362185761 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 9513.703009 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 6161.539130 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 362162299 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 223210500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.000065 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 23462 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 449 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 141795500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000064 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 23013 # number of ReadReq MSHR misses +system.cpu.fetch.rateDist::total 1732322031 # Number of instructions fetched each cycle (Total) +system.cpu.fp_regfile_reads 71543247 # number of floating regfile reads +system.cpu.fp_regfile_writes 49528299 # number of floating regfile writes +system.cpu.icache.ReadReq_accesses 367105078 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 9381.938291 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 6050.959331 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 367080252 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 232916000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.000068 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 24826 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 434 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 147595000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.000066 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 24392 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 15738.659728 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 15051.057895 # Average number of references to valid blocks. system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 362185761 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 9513.703009 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 6161.539130 # average overall mshr miss latency -system.cpu.icache.demand_hits 362162299 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 223210500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.000065 # miss rate for demand accesses -system.cpu.icache.demand_misses 23462 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 449 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 141795500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.000064 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 23013 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_accesses 367105078 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 9381.938291 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 6050.959331 # average overall mshr miss latency +system.cpu.icache.demand_hits 367080252 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 232916000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.000068 # miss rate for demand accesses +system.cpu.icache.demand_misses 24826 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 434 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 147595000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.000066 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 24392 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.754539 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 1545.296100 # Average occupied blocks per context -system.cpu.icache.overall_accesses 362185761 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 9513.703009 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 6161.539130 # average overall mshr miss latency +system.cpu.icache.occ_%::0 0.752702 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 1541.532802 # Average occupied blocks per context +system.cpu.icache.overall_accesses 367105078 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 9381.938291 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 6050.959331 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 362162299 # number of overall hits -system.cpu.icache.overall_miss_latency 223210500 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.000065 # miss rate for overall accesses -system.cpu.icache.overall_misses 23462 # number of overall misses -system.cpu.icache.overall_mshr_hits 449 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 141795500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.000064 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 23013 # number of overall MSHR misses +system.cpu.icache.overall_hits 367080252 # number of overall hits +system.cpu.icache.overall_miss_latency 232916000 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.000068 # miss rate for overall accesses +system.cpu.icache.overall_misses 24826 # number of overall misses +system.cpu.icache.overall_mshr_hits 434 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 147595000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.000066 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 24392 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.replacements 21424 # number of replacements -system.cpu.icache.sampled_refs 23011 # Sample count of references to valid blocks. +system.cpu.icache.replacements 22805 # number of replacements +system.cpu.icache.sampled_refs 24389 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1545.296100 # Cycle average of tags in use -system.cpu.icache.total_refs 362162299 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 1541.532802 # Cycle average of tags in use +system.cpu.icache.total_refs 367080251 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 22805284 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 354837598 # Number of branches executed -system.cpu.iew.EXEC:nop 98250 # number of nop insts executed -system.cpu.iew.EXEC:rate 1.389523 # Inst execution rate -system.cpu.iew.EXEC:refs 1168779203 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 410575996 # Number of stores executed +system.cpu.idleCycles 5923199 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 358605233 # Number of branches executed +system.cpu.iew.EXEC:nop 1350849 # number of nop insts executed +system.cpu.iew.EXEC:rate 1.388402 # Inst execution rate +system.cpu.iew.EXEC:refs 1176236253 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 407328146 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 2421323747 # num instructions consuming a value -system.cpu.iew.WB:count 2344814753 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.534499 # average fanout of values written-back +system.cpu.iew.WB:consumers 2464876715 # num instructions consuming a value +system.cpu.iew.WB:count 2378604713 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.531444 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 1294194313 # num instructions producing a value -system.cpu.iew.WB:rate 1.368282 # insts written-back per cycle -system.cpu.iew.WB:sent 2351424737 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 45254697 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 17472224 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 920596247 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 229114 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 5701638 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 478927516 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 3015512989 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 758203207 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 66026694 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 2381213830 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 1233247 # Number of times the IQ has become full, causing a stall +system.cpu.iew.WB:producers 1309943730 # num instructions producing a value +system.cpu.iew.WB:rate 1.368394 # insts written-back per cycle +system.cpu.iew.WB:sent 2386121679 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 46494560 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 11036637 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 946299703 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 229756 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 7912481 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 478952600 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 3044913804 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 768908107 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 79753358 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 2413383308 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 10292588 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 293 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 155800890 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 2569235 # Number of cycles IEW is unblocking +system.cpu.iew.iewLSQFullEvents 325 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 162682073 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 10344235 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread.0.cacheBlocked 24 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 34849398 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 1378004 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.cacheBlocked 25 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread.0.forwLoads 36704375 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 1640 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 2578924 # Number of memory ordering violations -system.cpu.iew.lsq.thread.0.rescheduledLoads 5 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 289205497 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 201928652 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 2578924 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 7840428 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 37414269 # Number of branches that were predicted taken incorrectly -system.cpu.int_regfile_reads 5603494067 # number of integer regfile reads -system.cpu.int_regfile_writes 1718225433 # number of integer regfile writes -system.cpu.ipc 1.100164 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.100164 # IPC: Total IPC of All Threads +system.cpu.iew.lsq.thread.0.memOrderViolation 2659902 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.rescheduledLoads 95 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread.0.squashedLoads 314908964 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 201953747 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 2659902 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 7823566 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 38670994 # Number of branches that were predicted taken incorrectly +system.cpu.int_regfile_reads 5694776843 # number of integer regfile reads +system.cpu.int_regfile_writes 1751148890 # number of integer regfile writes +system.cpu.ipc 1.084624 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.084624 # IPC: Total IPC of All Threads system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntAlu 1176897350 48.09% 48.09% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntMult 11209556 0.46% 48.55% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 48.55% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 48.55% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 48.55% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 48.55% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 48.55% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 48.55% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 48.55% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAdd 8683 0.00% 48.55% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 48.55% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 48.55% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 48.55% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 48.55% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 48.55% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 48.55% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 48.55% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 48.55% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 48.55% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 48.55% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 1375289 0.06% 48.61% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 48.61% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 6876474 0.28% 48.89% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 5501174 0.22% 49.11% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 49.11% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 23385811 0.96% 50.07% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 50.07% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 50.07% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 50.07% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemRead 790636932 32.31% 82.37% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemWrite 431349255 17.63% 100.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntAlu 1205851764 48.37% 48.37% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntMult 11238449 0.45% 48.82% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 48.82% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 48.82% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 48.82% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 48.82% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 48.82% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 48.82% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 48.82% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdAdd 8633 0.00% 48.82% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 48.82% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 48.82% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 48.82% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 48.82% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 48.82% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 48.82% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 48.82% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 48.82% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 48.82% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 48.82% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 1375289 0.06% 48.87% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 48.87% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 6876474 0.28% 49.15% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 5501201 0.22% 49.37% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 49.37% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 23385525 0.94% 50.31% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 50.31% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 50.31% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 50.31% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemRead 797167964 31.97% 82.28% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemWrite 441731367 17.72% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::total 2447240524 # Type of FU issued -system.cpu.iq.ISSUE:fu_busy_cnt 85394641 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.034894 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:FU_type_0::total 2493136666 # Type of FU issued +system.cpu.iq.ISSUE:fu_busy_cnt 86890569 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.034852 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntAlu 17844 0.02% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntMult 24113 0.03% 0.05% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 0.05% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 0.05% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 0.05% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 0.05% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 0.05% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 0.05% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 0.05% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 0.05% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 0.05% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 0.05% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 0.05% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 0.05% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 0.05% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 0.05% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 0.05% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 0.05% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 0.05% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 0.05% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 0.05% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 0.05% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 0.05% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 0.05% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 0.05% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 0.05% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 0.05% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 0.05% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 0.05% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemRead 55081470 64.50% 64.55% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemWrite 30271214 35.45% 100.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntAlu 482 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntMult 24113 0.03% 0.03% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 0.03% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 0.03% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 0.03% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 0.03% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 0.03% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 0.03% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 0.03% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 0.03% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 0.03% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 0.03% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 0.03% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 0.03% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 0.03% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 0.03% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 0.03% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 0.03% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 0.03% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 0.03% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 0.03% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 0.03% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 0.03% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 0.03% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 0.03% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 0.03% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 0.03% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 0.03% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 0.03% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemRead 55140629 63.46% 63.49% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemWrite 31725345 36.51% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:issued_per_cycle::samples 1690886837 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::mean 1.447312 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.581356 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::samples 1732322031 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::mean 1.439188 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.577350 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::0 652913002 38.61% 38.61% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::1 347943808 20.58% 59.19% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::2 308699944 18.26% 77.45% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::3 176613135 10.45% 87.89% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::4 115002206 6.80% 94.69% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::5 60495189 3.58% 98.27% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::6 19163759 1.13% 99.41% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::7 5856252 0.35% 99.75% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::8 4199542 0.25% 100.00% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::0 668978981 38.62% 38.62% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::1 360959007 20.84% 59.45% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::2 315091353 18.19% 77.64% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::3 182075740 10.51% 88.15% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::4 118045462 6.81% 94.97% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::5 56433729 3.26% 98.23% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::6 19322035 1.12% 99.34% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::7 5840762 0.34% 99.68% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::8 5574962 0.32% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::total 1690886837 # Number of insts issued each cycle -system.cpu.iq.ISSUE:rate 1.428051 # Inst issue rate -system.cpu.iq.fp_alu_accesses 67428170 # Number of floating point alu accesses -system.cpu.iq.fp_inst_queue_reads 127980204 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_wakeup_accesses 59166521 # Number of floating instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_writes 84999921 # Number of floating instruction queue writes -system.cpu.iq.int_alu_accesses 2465206995 # Number of integer alu accesses -system.cpu.iq.int_inst_queue_reads 6542850406 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_wakeup_accesses 2285648232 # Number of integer instruction queue wakeup accesses -system.cpu.iq.int_inst_queue_writes 4061650965 # Number of integer instruction queue writes -system.cpu.iq.iqInstsAdded 3015173249 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 2447240524 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 241490 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 1129860503 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 68084 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 29691 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 1732452415 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.ISSUE:issued_per_cycle::total 1732322031 # Number of insts issued each cycle +system.cpu.iq.ISSUE:rate 1.434284 # Inst issue rate +system.cpu.iq.fp_alu_accesses 66051736 # Number of floating point alu accesses +system.cpu.iq.fp_inst_queue_reads 126602345 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_wakeup_accesses 59166260 # Number of floating instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_writes 83365842 # Number of floating instruction queue writes +system.cpu.iq.int_alu_accesses 2513975499 # Number of integer alu accesses +system.cpu.iq.int_inst_queue_reads 6687198013 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_wakeup_accesses 2319438453 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_writes 4119676810 # Number of integer instruction queue writes +system.cpu.iq.iqInstsAdded 3043320801 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 2493136666 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 242154 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 1158104053 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 8314426 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 30366 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 1709199023 # Number of squashed operands that are examined and possibly removed from graph system.cpu.itb.accesses 0 # DTB accesses system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions @@ -416,109 +416,115 @@ system.cpu.itb.read_misses 0 # DT system.cpu.itb.write_accesses 0 # DTB write accesses system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.l2cache.ReadExReq_accesses 72735 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 34498.577525 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31001.142520 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_hits 6653 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_miss_latency 2279735000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_rate 0.908531 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 66082 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 2048617500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.908531 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 66082 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 1485380 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 34263.370250 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31000.336529 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 70915 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 48464338000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.952258 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 1414465 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_hits 26 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_miss_latency 43848085000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.952241 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 1414439 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_accesses 2 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses 72713 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_avg_miss_latency 34498.933176 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31001.414866 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_hits 6629 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_miss_latency 2279827500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_rate 0.908833 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_misses 66084 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 2048697500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.908833 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_misses 66084 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_accesses 1487150 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 34256.254935 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31000.334021 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 72547 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 48459001000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.951217 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 1414603 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_hits 23 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_miss_latency 43852452500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.951202 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 1414580 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_accesses 3 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31000 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_hits 2 # number of UpgradeReq hits -system.cpu.l2cache.Writeback_accesses 107051 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 107051 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_miss_rate 0.333333 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_misses 1 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 31000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_rate 0.333333 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_misses 1 # number of UpgradeReq MSHR misses +system.cpu.l2cache.Writeback_accesses 106994 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 106994 # number of Writeback hits system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.052408 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 0.053475 # Average number of references to valid blocks. system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 1558115 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 34273.868374 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31000.372504 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 77568 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 50744073000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.950217 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 1480547 # number of demand (read+write) misses -system.cpu.l2cache.demand_mshr_hits 26 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 45896702500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.950200 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 1480521 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_accesses 1559863 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 34267.085819 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31000.382261 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 79176 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 50738828500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.949242 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 1480687 # number of demand (read+write) misses +system.cpu.l2cache.demand_mshr_hits 23 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_miss_latency 45901150000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.949227 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 1480664 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.884259 # Average percentage of cache occupancy -system.cpu.l2cache.occ_%::1 0.091385 # Average percentage of cache occupancy -system.cpu.l2cache.occ_blocks::0 28975.398232 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 2994.491803 # Average occupied blocks per context -system.cpu.l2cache.overall_accesses 1558115 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 34273.868374 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31000.372504 # average overall mshr miss latency +system.cpu.l2cache.occ_%::0 0.884291 # Average percentage of cache occupancy +system.cpu.l2cache.occ_%::1 0.091352 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 28976.452018 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 2993.413242 # Average occupied blocks per context +system.cpu.l2cache.overall_accesses 1559863 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 34267.085819 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31000.382261 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 77568 # number of overall hits -system.cpu.l2cache.overall_miss_latency 50744073000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.950217 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 1480547 # number of overall misses -system.cpu.l2cache.overall_mshr_hits 26 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 45896702500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.950200 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 1480521 # number of overall MSHR misses +system.cpu.l2cache.overall_hits 79176 # number of overall hits +system.cpu.l2cache.overall_miss_latency 50738828500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.949242 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 1480687 # number of overall misses +system.cpu.l2cache.overall_mshr_hits 23 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_miss_latency 45901150000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.949227 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 1480664 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.replacements 1479423 # number of replacements -system.cpu.l2cache.sampled_refs 1512143 # Sample count of references to valid blocks. +system.cpu.l2cache.replacements 1479500 # number of replacements +system.cpu.l2cache.sampled_refs 1512220 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 31969.890035 # Cycle average of tags in use -system.cpu.l2cache.total_refs 79248 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 31969.865261 # Cycle average of tags in use +system.cpu.l2cache.total_refs 80866 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 66099 # number of writebacks -system.cpu.memDep0.conflictingLoads 68608597 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 90712102 # Number of conflicting stores. -system.cpu.memDep0.insertedLoads 920596247 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 478927516 # Number of stores inserted to the mem dependence unit. -system.cpu.misc_regfile_reads 3922986795 # number of misc regfile reads -system.cpu.misc_regfile_writes 14227477 # number of misc regfile writes -system.cpu.numCycles 1713692121 # number of cpu cycles simulated +system.cpu.memDep0.conflictingLoads 75887530 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 97070199 # Number of conflicting stores. +system.cpu.memDep0.insertedLoads 946299703 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 478952600 # Number of stores inserted to the mem dependence unit. +system.cpu.misc_regfile_reads 3932819873 # number of misc regfile reads +system.cpu.misc_regfile_writes 13780016 # number of misc regfile writes +system.cpu.numCycles 1738245230 # number of cpu cycles simulated system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.rename.RENAME:BlockCycles 26481185 # Number of cycles rename is blocking -system.cpu.rename.RENAME:CommittedMaps 1523914787 # Number of HB maps that are committed -system.cpu.rename.RENAME:IQFullEvents 14530739 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 769489537 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 9665417 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:ROBFullEvents 4 # Number of times rename has blocked due to ROB full -system.cpu.rename.RENAME:RenameLookups 8794817078 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 3244153999 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 2590050394 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 617757360 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 155800890 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 32816862 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 1066135604 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:fp_rename_lookups 420246695 # Number of floating rename lookups -system.cpu.rename.RENAME:int_rename_lookups 8374570383 # Number of integer rename lookups -system.cpu.rename.RENAME:serializeStallCycles 88541003 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 8494560 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 86318102 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 244150 # count of temporary serializing insts renamed -system.cpu.rob.rob_reads 4493626241 # The number of ROB reads -system.cpu.rob.rob_writes 6186797097 # The number of ROB writes -system.cpu.timesIdled 1346446 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.rename.RENAME:BlockCycles 26815429 # Number of cycles rename is blocking +system.cpu.rename.RENAME:CommittedMaps 1523726473 # Number of HB maps that are committed +system.cpu.rename.RENAME:IQFullEvents 13358705 # Number of times rename has blocked due to IQ full +system.cpu.rename.RENAME:IdleCycles 804669593 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 12419294 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:ROBFullEvents 3 # Number of times rename has blocked due to ROB full +system.cpu.rename.RENAME:RenameLookups 8858159876 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 3258876297 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 2595747724 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 616670755 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 162682073 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 32941123 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 1072021248 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:fp_rename_lookups 417025150 # Number of floating rename lookups +system.cpu.rename.RENAME:int_rename_lookups 8441134726 # Number of integer rename lookups +system.cpu.rename.RENAME:serializeStallCycles 88543058 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 8500262 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 93807403 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 250407 # count of temporary serializing insts renamed +system.cpu.rob.rob_reads 4556129692 # The number of ROB reads +system.cpu.rob.rob_writes 6252480772 # The number of ROB writes +system.cpu.timesIdled 1346475 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 1411 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/40.perlbmk/ref/arm/linux/simple-atomic/config.ini b/tests/long/40.perlbmk/ref/arm/linux/simple-atomic/config.ini index 161aadfee..4c80bccfd 100644 --- a/tests/long/40.perlbmk/ref/arm/linux/simple-atomic/config.ini +++ b/tests/long/40.perlbmk/ref/arm/linux/simple-atomic/config.ini @@ -61,7 +61,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=perlbmk -I. -I lib lgred.makerand.pl -cwd=build/ARM_SE/tests/fast/long/40.perlbmk/arm/linux/simple-atomic +cwd=build/ARM_SE/tests/opt/long/40.perlbmk/arm/linux/simple-atomic egid=100 env= errout=cerr diff --git a/tests/long/40.perlbmk/ref/arm/linux/simple-atomic/simout b/tests/long/40.perlbmk/ref/arm/linux/simple-atomic/simout index 467c19c32..47a67193a 100755 --- a/tests/long/40.perlbmk/ref/arm/linux/simple-atomic/simout +++ b/tests/long/40.perlbmk/ref/arm/linux/simple-atomic/simout @@ -5,11 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Mar 11 2011 20:10:09 -M5 revision 4decc284606a 8095 default qtip tip ext/update_add_stats.patch -M5 started Mar 11 2011 20:44:47 +M5 compiled Mar 30 2011 17:47:57 +M5 started Mar 30 2011 18:14:25 M5 executing on u200439-lin.austin.arm.com -command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/40.perlbmk/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/fast/long/40.perlbmk/arm/linux/simple-atomic +command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/40.perlbmk/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/opt/long/40.perlbmk/arm/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/long/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt b/tests/long/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt index b4eaa4e1c..a5bf8162c 100644 --- a/tests/long/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1687648 # Simulator instruction rate (inst/s) -host_mem_usage 251592 # Number of bytes of host memory used -host_seconds 1117.14 # Real time elapsed on the host -host_tick_rate 846460115 # Simulator tick rate (ticks/s) +host_inst_rate 1065231 # Simulator instruction rate (inst/s) +host_mem_usage 252312 # Number of bytes of host memory used +host_seconds 1769.89 # Real time elapsed on the host +host_tick_rate 534279231 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1885336367 # Number of instructions simulated sim_seconds 0.945613 # Number of seconds simulated @@ -56,18 +56,18 @@ system.cpu.numCycles 1891226263 # nu system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.num_busy_cycles 1891226263 # Number of busy cycles -system.cpu.num_conditional_control_insts 223597262 # number of instructions that are conditional controls +system.cpu.num_conditional_control_insts 223625914 # number of instructions that are conditional controls system.cpu.num_fp_alu_accesses 52289415 # Number of float alu accesses system.cpu.num_fp_insts 52289415 # number of float instructions system.cpu.num_fp_register_reads 60540850 # number of times the floating registers were read system.cpu.num_fp_register_writes 46777010 # number of times the floating registers were written -system.cpu.num_func_calls 84508263 # number of times a function call or return occured +system.cpu.num_func_calls 80344203 # number of times a function call or return occured system.cpu.num_idle_cycles 0 # Number of idle cycles system.cpu.num_insts 1885336367 # Number of instructions executed system.cpu.num_int_alu_accesses 1660575345 # Number of integer alu accesses system.cpu.num_int_insts 1660575345 # number of integer instructions system.cpu.num_int_register_reads 4913858688 # number of times the integer registers were read -system.cpu.num_int_register_writes 1405410845 # number of times the integer registers were written +system.cpu.num_int_register_writes 1404936302 # number of times the integer registers were written system.cpu.num_load_insts 631387182 # Number of load instructions system.cpu.num_mem_refs 908382480 # number of memory refs system.cpu.num_store_insts 276995298 # Number of store instructions diff --git a/tests/long/40.perlbmk/ref/arm/linux/simple-timing/config.ini b/tests/long/40.perlbmk/ref/arm/linux/simple-timing/config.ini index 734b01f7e..53d197f66 100644 --- a/tests/long/40.perlbmk/ref/arm/linux/simple-timing/config.ini +++ b/tests/long/40.perlbmk/ref/arm/linux/simple-timing/config.ini @@ -164,7 +164,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=perlbmk -I. -I lib lgred.makerand.pl -cwd=build/ARM_SE/tests/fast/long/40.perlbmk/arm/linux/simple-timing +cwd=build/ARM_SE/tests/opt/long/40.perlbmk/arm/linux/simple-timing egid=100 env= errout=cerr diff --git a/tests/long/40.perlbmk/ref/arm/linux/simple-timing/simerr b/tests/long/40.perlbmk/ref/arm/linux/simple-timing/simerr index d834843e9..805a6606f 100755 --- a/tests/long/40.perlbmk/ref/arm/linux/simple-timing/simerr +++ b/tests/long/40.perlbmk/ref/arm/linux/simple-timing/simerr @@ -1,11 +1,5 @@ warn: Sockets disabled, not accepting gdb connections For more information see: http://www.m5sim.org/warn/d946bea6 -warn: Complete acc isn't called on normal stores in O3. -For more information see: http://www.m5sim.org/warn/138d8573 -warn: Complete acc isn't called on normal stores in O3. -For more information see: http://www.m5sim.org/warn/138d8573 -warn: Complete acc isn't called on normal stores in O3. -For more information see: http://www.m5sim.org/warn/138d8573 warn: fcntl64(3, 2) passed through to host For more information see: http://www.m5sim.org/warn/a55e2c46 hack: be nice to actually delete the event here diff --git a/tests/long/40.perlbmk/ref/arm/linux/simple-timing/simout b/tests/long/40.perlbmk/ref/arm/linux/simple-timing/simout index 871cc997a..5f6cb9527 100755 --- a/tests/long/40.perlbmk/ref/arm/linux/simple-timing/simout +++ b/tests/long/40.perlbmk/ref/arm/linux/simple-timing/simout @@ -5,11 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Mar 11 2011 20:10:09 -M5 revision 4decc284606a 8095 default qtip tip ext/update_add_stats.patch -M5 started Mar 11 2011 20:10:25 +M5 compiled Mar 30 2011 17:47:57 +M5 started Mar 30 2011 18:18:27 M5 executing on u200439-lin.austin.arm.com -command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/40.perlbmk/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/fast/long/40.perlbmk/arm/linux/simple-timing +command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/40.perlbmk/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/opt/long/40.perlbmk/arm/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/long/40.perlbmk/ref/arm/linux/simple-timing/stats.txt b/tests/long/40.perlbmk/ref/arm/linux/simple-timing/stats.txt index ae9492554..3345b6b66 100644 --- a/tests/long/40.perlbmk/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/40.perlbmk/ref/arm/linux/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 678497 # Simulator instruction rate (inst/s) -host_mem_usage 259312 # Number of bytes of host memory used -host_seconds 2762.35 # Real time elapsed on the host -host_tick_rate 857930242 # Simulator tick rate (ticks/s) +host_inst_rate 561445 # Simulator instruction rate (inst/s) +host_mem_usage 260040 # Number of bytes of host memory used +host_seconds 3338.25 # Real time elapsed on the host +host_tick_rate 709922934 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1874244950 # Number of instructions simulated sim_seconds 2.369902 # Number of seconds simulated @@ -249,18 +249,18 @@ system.cpu.numCycles 4739803920 # nu system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.num_busy_cycles 4739803920 # Number of busy cycles -system.cpu.num_conditional_control_insts 223597262 # number of instructions that are conditional controls +system.cpu.num_conditional_control_insts 223625914 # number of instructions that are conditional controls system.cpu.num_fp_alu_accesses 52289415 # Number of float alu accesses system.cpu.num_fp_insts 52289415 # number of float instructions system.cpu.num_fp_register_reads 60540850 # number of times the floating registers were read system.cpu.num_fp_register_writes 46777010 # number of times the floating registers were written -system.cpu.num_func_calls 84508263 # number of times a function call or return occured +system.cpu.num_func_calls 80344203 # number of times a function call or return occured system.cpu.num_idle_cycles 0 # Number of idle cycles system.cpu.num_insts 1874244950 # Number of instructions executed system.cpu.num_int_alu_accesses 1660575345 # Number of integer alu accesses system.cpu.num_int_insts 1660575345 # number of integer instructions system.cpu.num_int_register_reads 5538311924 # number of times the integer registers were read -system.cpu.num_int_register_writes 1405482554 # number of times the integer registers were written +system.cpu.num_int_register_writes 1404936302 # number of times the integer registers were written system.cpu.num_load_insts 631387182 # Number of load instructions system.cpu.num_mem_refs 908382480 # number of memory refs system.cpu.num_store_insts 276995298 # Number of store instructions diff --git a/tests/long/50.vortex/ref/arm/linux/o3-timing/config.ini b/tests/long/50.vortex/ref/arm/linux/o3-timing/config.ini index 63a46ba4a..dfd9d4d58 100644 --- a/tests/long/50.vortex/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/50.vortex/ref/arm/linux/o3-timing/config.ini @@ -25,6 +25,8 @@ BTBEntries=4096 BTBTagSize=16 LFSTSize=1024 LQEntries=32 +LSQCheckLoads=true +LSQDepCheckShift=4 RASSize=16 SQEntries=32 SSITSize=1024 @@ -491,12 +493,12 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=vortex lendian.raw -cwd=build/ARM_SE/tests/fast/long/50.vortex/arm/linux/o3-timing +cwd=build/ARM_SE/tests/opt/long/50.vortex/arm/linux/o3-timing egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/arm/linux/vortex +executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/vortex gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/50.vortex/ref/arm/linux/o3-timing/simout b/tests/long/50.vortex/ref/arm/linux/o3-timing/simout index 1da31b60d..3d6783bda 100755 --- a/tests/long/50.vortex/ref/arm/linux/o3-timing/simout +++ b/tests/long/50.vortex/ref/arm/linux/o3-timing/simout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Mar 18 2011 20:12:03 -M5 started Mar 18 2011 20:43:38 -M5 executing on zizzer -command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/50.vortex/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/fast/long/50.vortex/arm/linux/o3-timing +M5 compiled Mar 30 2011 17:47:57 +M5 started Mar 30 2011 18:24:14 +M5 executing on u200439-lin.austin.arm.com +command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/50.vortex/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/opt/long/50.vortex/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. -Exiting @ tick 39814499000 because target called exit() +Exiting @ tick 39891736000 because target called exit() diff --git a/tests/long/50.vortex/ref/arm/linux/o3-timing/smred.out b/tests/long/50.vortex/ref/arm/linux/o3-timing/smred.out new file mode 100644 index 000000000..726b45c60 --- /dev/null +++ b/tests/long/50.vortex/ref/arm/linux/o3-timing/smred.out @@ -0,0 +1,258 @@ + CREATE Db Header and Db Primal ... + NEW DB [ 3] Created. + +VORTEX INPUT PARAMETERS:: + MESSAGE FileName: smred.msg + OUTPUT FileName: smred.out + DISK CACHE FileName: NULL + PART DB FileName: parts.db + DRAW DB FileName: draw.db + PERSON DB FileName: emp.db + PERSONS Data FileName: ./input/persons.250 + PARTS Count : 100 + OUTER Loops : 1 + INNER Loops : 1 + LOOKUP Parts : 25 + DELETE Parts : 10 + STUFF Parts : 10 + DEPTH Traverse: 5 + % DECREASE Parts : 0 + % INCREASE LookUps : 0 + % INCREASE Deletes : 0 + % INCREASE Stuffs : 0 + FREEZE_PACKETS : 1 + ALLOC_CHUNKS : 10000 + EXTEND_CHUNKS : 5000 + DELETE Draw objects : True + DELETE Part objects : False + QUE_BUG : 1000 + VOID_BOUNDARY : 67108864 + VOID_RESERVE : 1048576 + + COMMIT_DBS : False + + + + BMT TEST :: files... + EdbName := PartLib + EdbFileName := parts.db + DrwName := DrawLib + DrwFileName := draw.db + EmpName := PersonLib + EmpFileName := emp.db + + Swap to DiskCache := False + Freeze the cache := True + + + BMT TEST :: parms... + DeBug modulo := 1000 + Create Parts count:= 100 + Outer Loops := 1 + Inner Loops := 1 + Look Ups := 25 + Delete Parts := 10 + Stuff Parts := 10 + Traverse Limit := 5 + Delete Draws := True + Delete Parts := False + Delete ALL Parts := after every <mod 0>Outer Loop + + INITIALIZE LIBRARY :: + + INITIALIZE SCHEMA :: + Primal_CreateDb Accessed !!! + CREATE Db Header and Db Primal ... + NEW DB [ 4] Created. + PartLibCreate:: Db[ 4]; VpartsDir= 1 + + Part Count= 1 + + Initialize the Class maps + LIST HEADS loaded ... DbListHead_Class = 207 + DbListNode_Class = 206 + +...NOTE... ShellLoadCode:: Class[ 228] will NOT be Activated. + + +...NOTE... ShellLoadCode:: Class[ 229] will NOT be Activated. + + Primal_CreateDb Accessed !!! + CREATE Db Header and Db Primal ... + NEW DB [ 5] Created. + DrawLibCreate:: Db[ 5]; VpartsDir= 1 + + Initialize the Class maps of this schema. + Primal_CreateDb Accessed !!! + CREATE Db Header and Db Primal ... + NEW DB [ 6] Created. + + ***NOTE*** Persons Library Extended! + + Create <131072> Persons. + ItNum 0. Person[ 6: 5]. Name= Riddell , Robert V. ; + + LAST Person Read:: + ItNum 250. Person[ 6: 503]. Name= Gonzales , Warren X. ; + + BUILD <Query0> for <Part2> class:: + + if (link[1].length >= 5) :: + + Build Query2 for <Address> class:: + + if (State == CA || State == T*) + + Build Query1 for <Person> class:: + + if (LastName >= H* && LastName <= P* && Query0(Residence)) :: + + BUILD <Query3> for <DrawObj> class:: + + if (Id >= 3000 + && (Id >= 3000 && Id <= 3001) + && Id >= 3002) + + BUILD <Query4> for <NamedDrawObj> class:: + + if (Nam == Pre* + || (Nam == ??Mid??? || == Pre??Mid?? || == ??Post + || == Pre??Post || == ??Mid???Post || == Pre??Mid???Post) + && Id <= 7) + SEED := 1008; Swap = False; RgnEntries = 135 + + OUTER LOOP [ 1] : NewParts = 100 LookUps = 25 StuffParts = 10. + + Create 100 New Parts + Create Part 1. Token[ 4: 2]. + + < 100> Parts Created. CurrentId= 100 + + Connect each instantiated Part TO 3 unique Parts + Connect Part 1. Token[ 4: 2] + Connect Part 25. Token[ 4: 26] FromList= 26. + Connect Part 12. Token[ 4: 13] FromList= 13. + Connect Part 59. Token[ 4: 60] FromList= 60. + + SET <DrawObjs> entries:: + 1. [ 5: 5] := <1 >; @[: 6] + Iteration count = 100 + + SET <NamedDrawObjs> entries:: + 1. [ 5: 39] := <14 >; + Iteration count = 12 + + SET <LibRectangles> entries:: + 1. [ 5: 23] := <8 >; @[: 24] + Iteration count = 12 + + LIST <DbRectangles> entries:: + 1. [ 5: 23] + Iteration count = 12 + + SET <PersonNames > entries:: + Iteration count = 250 + + COMMIT All Image copies:: Release=<True>; Max Parts= 100 + < 100> Part images' Committed. + < 0> are Named. + < 50> Point images' Committed. + < 81> Person images' Committed. + + COMMIT Parts(* 100) + + Commit TestObj_Class in <Primal> DB. + ItNum 0. Token[ 0: 0]. TestObj Committed. + < 0> TestObj images' Committed. + + Commit CartesianPoint_Class in <Primal> DB. + ItNum 0. Token[ 0: 0]. CartesianPoint Committed. + < 0> CartesianPoint images' Committed. + + BEGIN Inner Loop Sequence::. + + INNER LOOP [ 1: 1] : + + LOOK UP 25 Random Parts and Export each Part. + + LookUp for 26 parts; Asserts = 8 + <Part2 > Asserts = 2; NULL Asserts = 3. + <DrawObj > Asserts = 0; NULL Asserts = 5. + <NamedObj > Asserts = 0; NULL Asserts = 0. + <Person > Asserts = 0; NULL Asserts = 5. + <TestObj > Asserts = 60; NULL Asserts = 0. + + DELETE 10 Random Parts. + + PartDelete :: Token[ 4: 91]. + PartDisconnect:: Token[ 4: 91] id:= 90 for each link. + DisConnect link [ 0]:= 50; PartToken[ 51: 51]. + DisConnect link [ 1]:= 17; PartToken[ 18: 18]. + DisConnect link [ 2]:= 72; PartToken[ 73: 73]. + DeleteFromList:: Vchunk[ 4: 91]. (* 1) + DisConnect FromList[ 0]:= 56; Token[ 57: 57]. + Vlists[ 89] := 100; + + Delete for 11 parts; + + Traverse Count= 0 + + TRAVERSE PartId[ 6] and all Connections to 5 Levels + SEED In Traverse Part [ 4: 65] @ Level = 4. + + Traverse Count= 357 + Traverse Asserts = 5. True Tests = 1 + < 5> DrawObj objects DELETED. + < 2> are Named. + < 2> Point objects DELETED. + + CREATE 10 Additional Parts + + Create 10 New Parts + Create Part 101. Token[ 4: 102]. + + < 10> Parts Created. CurrentId= 110 + + Connect each instantiated Part TO 3 unique Parts + + COMMIT All Image copies:: Release=<True>; Max Parts= 110 + < 81> Part images' Committed. + < 0> are Named. + < 38> Point images' Committed. + < 31> Person images' Committed. + + COMMIT Parts(* 100) + + Commit TestObj_Class in <Primal> DB. + ItNum 0. Token[ 3: 4]. TestObj Committed. + < 15> TestObj images' Committed. + + Commit CartesianPoint_Class in <Primal> DB. + ItNum 0. Token[ 3: 3]. CartesianPoint Committed. + < 16> CartesianPoint images' Committed. + + DELETE All TestObj objects; + + Delete TestObj_Class in <Primal> DB. + ItNum 0. Token[ 3: 4]. TestObj Deleted. + < 15> TestObj objects Deleted. + + Commit CartesianPoint_Class in <Primal> DB. + ItNum 0. Token[ 3: 3]. CartesianPoint Deleted. + < 16> CartesianPoint objects Deleted. + + DELETE TestObj and Point objects... + + END INNER LOOP [ 1: 1]. + + DELETE All TestObj objects; + + Delete TestObj_Class in <Primal> DB. + < 0> TestObj objects Deleted. + + Commit CartesianPoint_Class in <Primal> DB. + < 0> CartesianPoint objects Deleted. + + DELETE TestObj and Point objects... + STATUS= -201 +V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1! diff --git a/tests/long/50.vortex/ref/arm/linux/o3-timing/stats.txt b/tests/long/50.vortex/ref/arm/linux/o3-timing/stats.txt index 3f79167d8..bb67506e5 100644 --- a/tests/long/50.vortex/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/50.vortex/ref/arm/linux/o3-timing/stats.txt @@ -1,142 +1,146 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 141424 # Simulator instruction rate (inst/s) -host_mem_usage 230092 # Number of bytes of host memory used -host_seconds 711.57 # Real time elapsed on the host -host_tick_rate 55953326 # Simulator tick rate (ticks/s) +host_inst_rate 65034 # Simulator instruction rate (inst/s) +host_mem_usage 264616 # Number of bytes of host memory used +host_seconds 1547.38 # Real time elapsed on the host +host_tick_rate 25780112 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 100632680 # Number of instructions simulated -sim_seconds 0.039814 # Number of seconds simulated -sim_ticks 39814499000 # Number of ticks simulated +sim_insts 100633305 # Number of instructions simulated +sim_seconds 0.039892 # Number of seconds simulated +sim_ticks 39891736000 # Number of ticks simulated system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.BTBHits 9474553 # Number of BTB hits -system.cpu.BPredUnit.BTBLookups 14867699 # Number of BTB lookups -system.cpu.BPredUnit.RASInCorrect 120437 # Number of incorrect RAS predictions. -system.cpu.BPredUnit.condIncorrect 705175 # Number of conditional branches incorrect -system.cpu.BPredUnit.condPredicted 11698396 # Number of conditional branches predicted -system.cpu.BPredUnit.lookups 17816526 # Number of BP lookups -system.cpu.BPredUnit.usedRAS 1920156 # Number of times the RAS was used to get a target. -system.cpu.commit.COM:branches 13645681 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 2731708 # number cycles where commit BW limit reached +system.cpu.BPredUnit.BTBHits 9865367 # Number of BTB hits +system.cpu.BPredUnit.BTBLookups 15339513 # Number of BTB lookups +system.cpu.BPredUnit.RASInCorrect 176572 # Number of incorrect RAS predictions. +system.cpu.BPredUnit.condIncorrect 830445 # Number of conditional branches incorrect +system.cpu.BPredUnit.condPredicted 11914381 # Number of conditional branches predicted +system.cpu.BPredUnit.lookups 18227498 # Number of BP lookups +system.cpu.BPredUnit.usedRAS 1851553 # Number of times the RAS was used to get a target. +system.cpu.commit.COM:branches 13669912 # Number of branches committed +system.cpu.commit.COM:bw_lim_events 2877364 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle::samples 76749449 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::mean 1.311257 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::stdev 1.867212 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::samples 76617428 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::mean 1.313524 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::stdev 1.896154 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::0 33503516 43.65% 43.65% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::1 22762482 29.66% 73.31% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::2 6689783 8.72% 82.03% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::3 4895670 6.38% 88.41% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::4 3997632 5.21% 93.62% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::5 1356419 1.77% 95.38% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::6 502786 0.66% 96.04% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::7 309453 0.40% 96.44% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::8 2731708 3.56% 100.00% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::0 34018334 44.40% 44.40% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::1 22269182 29.07% 73.47% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::2 6570057 8.58% 82.04% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::3 4759391 6.21% 88.25% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::4 3903161 5.09% 93.35% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::5 1377879 1.80% 95.15% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::6 463983 0.61% 95.75% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::7 378077 0.49% 96.24% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::8 2877364 3.76% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::total 76749449 # Number of insts commited each cycle -system.cpu.commit.COM:count 100638232 # Number of instructions committed +system.cpu.commit.COM:committed_per_cycle::total 76617428 # Number of insts commited each cycle +system.cpu.commit.COM:count 100638857 # Number of instructions committed system.cpu.commit.COM:fp_insts 56 # Number of committed floating point instructions. system.cpu.commit.COM:function_calls 1679850 # Number of function calls committed. -system.cpu.commit.COM:int_insts 91477423 # Number of committed integer instructions. -system.cpu.commit.COM:loads 27308268 # Number of loads committed +system.cpu.commit.COM:int_insts 91477923 # Number of committed integer instructions. +system.cpu.commit.COM:loads 27308393 # Number of loads committed system.cpu.commit.COM:membars 15920 # Number of memory barriers committed -system.cpu.commit.COM:refs 47865165 # Number of memory references committed +system.cpu.commit.COM:refs 47865415 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 701341 # The number of times a branch was mispredicted -system.cpu.commit.commitCommittedInsts 100638232 # The number of committed instructions -system.cpu.commit.commitNonSpecStalls 700789 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 12187883 # The number of squashed insts skipped by commit -system.cpu.committedInsts 100632680 # Number of Instructions Simulated -system.cpu.committedInsts_total 100632680 # Number of Instructions Simulated -system.cpu.cpi 0.791284 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.791284 # CPI: Total CPI of All Threads -system.cpu.dcache.LoadLockedReq_accesses 18554 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_avg_miss_latency 12851.851852 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_hits 18527 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_miss_latency 347000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_rate 0.001455 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_misses 27 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_mshr_hits 27 # number of LoadLockedReq MSHR hits -system.cpu.dcache.ReadReq_accesses 26941109 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 22340.076347 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 18819.128231 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 26838682 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 2288227000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.003802 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 102427 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 47963 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 1024965000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.002022 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 54464 # number of ReadReq MSHR misses -system.cpu.dcache.StoreCondReq_accesses 17078 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_hits 17078 # number of StoreCondReq hits +system.cpu.commit.branchMispredicts 800437 # The number of times a branch was mispredicted +system.cpu.commit.commitCommittedInsts 100638857 # The number of committed instructions +system.cpu.commit.commitNonSpecStalls 700914 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.commitSquashedInsts 13588852 # The number of squashed insts skipped by commit +system.cpu.committedInsts 100633305 # Number of Instructions Simulated +system.cpu.committedInsts_total 100633305 # Number of Instructions Simulated +system.cpu.cpi 0.792814 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.792814 # CPI: Total CPI of All Threads +system.cpu.dcache.LoadLockedReq_accesses 18795 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_avg_miss_latency 13515.151515 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 35500 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_hits 18762 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_miss_latency 446000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_rate 0.001756 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_misses 33 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_mshr_hits 32 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_miss_latency 35500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_rate 0.000053 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_misses 1 # number of LoadLockedReq MSHR misses +system.cpu.dcache.ReadReq_accesses 26949457 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 22750.430442 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 18884.806074 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 26845494 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 2365203000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.003858 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 103963 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 49303 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 1032243500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.002028 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 54660 # number of ReadReq MSHR misses +system.cpu.dcache.StoreCondReq_accesses 17203 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_hits 17203 # number of StoreCondReq hits system.cpu.dcache.WriteReq_accesses 19849901 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 32476.175857 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 34166.852204 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 18297799 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 50406337500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.078192 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 1552102 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 1445205 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 3652334000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_avg_miss_latency 32591.489503 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 34153.863424 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 18304057 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 50381358500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.077877 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 1545844 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 1438944 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 3651048000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.005385 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 106897 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 106900 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets 22000 # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 279.970622 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 279.703475 # Average number of references to valid blocks. system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 22000 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 46791010 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 31848.679896 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 28986.551893 # average overall mshr miss latency -system.cpu.dcache.demand_hits 45136481 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 52694564500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.035360 # miss rate for demand accesses -system.cpu.dcache.demand_misses 1654529 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 1493168 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 4677299000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.003449 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 161361 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_accesses 46799358 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 31971.352710 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 28987.939465 # average overall mshr miss latency +system.cpu.dcache.demand_hits 45149551 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 52746561500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.035253 # miss rate for demand accesses +system.cpu.dcache.demand_misses 1649807 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 1488247 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 4683291500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.003452 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 161560 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.994972 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 4075.403467 # Average occupied blocks per context -system.cpu.dcache.overall_accesses 46791010 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 31848.679896 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 28986.551893 # average overall mshr miss latency +system.cpu.dcache.occ_%::0 0.994984 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 4075.453819 # Average occupied blocks per context +system.cpu.dcache.overall_accesses 46799358 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 31971.352710 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 28987.939465 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 45136481 # number of overall hits -system.cpu.dcache.overall_miss_latency 52694564500 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.035360 # miss rate for overall accesses -system.cpu.dcache.overall_misses 1654529 # number of overall misses -system.cpu.dcache.overall_mshr_hits 1493168 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 4677299000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.003449 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 161361 # number of overall MSHR misses +system.cpu.dcache.overall_hits 45149551 # number of overall hits +system.cpu.dcache.overall_miss_latency 52746561500 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.035253 # miss rate for overall accesses +system.cpu.dcache.overall_misses 1649807 # number of overall misses +system.cpu.dcache.overall_mshr_hits 1488247 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 4683291500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.003452 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 161560 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.replacements 157250 # number of replacements -system.cpu.dcache.sampled_refs 161346 # Sample count of references to valid blocks. +system.cpu.dcache.replacements 157452 # number of replacements +system.cpu.dcache.sampled_refs 161548 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4075.403467 # Cycle average of tags in use -system.cpu.dcache.total_refs 45172140 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 327456000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 123257 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 29986169 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 91538 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 3619762 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 118267772 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 24869566 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 21242565 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 1889316 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 325053 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 651148 # Number of cycles decode is unblocking +system.cpu.dcache.tagsinuse 4075.453819 # Cycle average of tags in use +system.cpu.dcache.total_refs 45185537 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 327416000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 123381 # number of writebacks +system.cpu.decode.DECODE:BlockedCycles 28767889 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BranchMispred 93628 # Number of times decode detected a branch misprediction +system.cpu.decode.DECODE:BranchResolved 3727749 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 120621461 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 25476849 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 21756774 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 2130394 # Number of cycles decode is squashing +system.cpu.decode.DECODE:SquashedInsts 323992 # Number of squashed instructions handled by decode +system.cpu.decode.DECODE:UnblockCycles 615915 # Number of cycles decode is unblocking system.cpu.dtb.accesses 0 # DTB accesses system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions @@ -158,243 +162,243 @@ system.cpu.dtb.read_misses 0 # DT system.cpu.dtb.write_accesses 0 # DTB write accesses system.cpu.dtb.write_hits 0 # DTB write hits system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.fetch.Branches 17816526 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 11383853 # Number of cache lines fetched -system.cpu.fetch.Cycles 22263353 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 149960 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 87185179 # Number of instructions fetch has processed -system.cpu.fetch.MiscStallCycles 32417 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.SquashCycles 799636 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.223744 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 11383853 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 11394709 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 1.094892 # Number of inst fetches per cycle -system.cpu.fetch.rateDist::samples 78638764 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.535218 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.823911 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.Branches 18227498 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 11770565 # Number of cache lines fetched +system.cpu.fetch.Cycles 22825886 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 173702 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 89192210 # Number of instructions fetch has processed +system.cpu.fetch.MiscStallCycles 72 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.SquashCycles 899278 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.228462 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 11770565 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 11716920 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 1.117928 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 78747821 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.567287 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.842624 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 56390222 71.71% 71.71% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 2286086 2.91% 74.61% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 2538611 3.23% 77.84% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 2175303 2.77% 80.61% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 1609869 2.05% 82.66% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1746559 2.22% 84.88% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 986099 1.25% 86.13% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1498585 1.91% 88.04% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 9407430 11.96% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 55936810 71.03% 71.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 2349634 2.98% 74.02% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 2668515 3.39% 77.41% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 2236984 2.84% 80.25% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 1645406 2.09% 82.34% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1774436 2.25% 84.59% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 998371 1.27% 85.86% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1522539 1.93% 87.79% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 9615126 12.21% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 78638764 # Number of instructions fetched each cycle (Total) -system.cpu.fp_regfile_reads 366 # number of floating regfile reads -system.cpu.fp_regfile_writes 320 # number of floating regfile writes -system.cpu.icache.ReadReq_accesses 11383853 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 12943.379124 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 9472.145833 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 11359030 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 321293500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.002181 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 24823 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 823 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 227331500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.002108 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 24000 # number of ReadReq MSHR misses +system.cpu.fetch.rateDist::total 78747821 # Number of instructions fetched each cycle (Total) +system.cpu.fp_regfile_reads 90 # number of floating regfile reads +system.cpu.fp_regfile_writes 71 # number of floating regfile writes +system.cpu.icache.ReadReq_accesses 11770565 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 12757.129371 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 9282.013745 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 11745142 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 324324500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.002160 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 25423 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 832 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 228254000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.002089 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 24591 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 473.568957 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 477.833279 # Average number of references to valid blocks. system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 11383853 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 12943.379124 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 9472.145833 # average overall mshr miss latency -system.cpu.icache.demand_hits 11359030 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 321293500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.002181 # miss rate for demand accesses -system.cpu.icache.demand_misses 24823 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 823 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 227331500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.002108 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 24000 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_accesses 11770565 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 12757.129371 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 9282.013745 # average overall mshr miss latency +system.cpu.icache.demand_hits 11745142 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 324324500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.002160 # miss rate for demand accesses +system.cpu.icache.demand_misses 25423 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 832 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 228254000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.002089 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 24591 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.878234 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 1798.623677 # Average occupied blocks per context -system.cpu.icache.overall_accesses 11383853 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 12943.379124 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 9472.145833 # average overall mshr miss latency +system.cpu.icache.occ_%::0 0.875696 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 1793.424749 # Average occupied blocks per context +system.cpu.icache.overall_accesses 11770565 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 12757.129371 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 9282.013745 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 11359030 # number of overall hits -system.cpu.icache.overall_miss_latency 321293500 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.002181 # miss rate for overall accesses -system.cpu.icache.overall_misses 24823 # number of overall misses -system.cpu.icache.overall_mshr_hits 823 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 227331500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.002108 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 24000 # number of overall MSHR misses +system.cpu.icache.overall_hits 11745142 # number of overall hits +system.cpu.icache.overall_miss_latency 324324500 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.002160 # miss rate for overall accesses +system.cpu.icache.overall_misses 25423 # number of overall misses +system.cpu.icache.overall_mshr_hits 832 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 228254000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.002089 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 24591 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.replacements 21955 # number of replacements -system.cpu.icache.sampled_refs 23986 # Sample count of references to valid blocks. +system.cpu.icache.replacements 22549 # number of replacements +system.cpu.icache.sampled_refs 24580 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1798.623677 # Cycle average of tags in use -system.cpu.icache.total_refs 11359025 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 1793.424749 # Cycle average of tags in use +system.cpu.icache.total_refs 11745142 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 990235 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 14607903 # Number of branches executed -system.cpu.iew.EXEC:nop 89799 # number of nop insts executed -system.cpu.iew.EXEC:rate 1.318459 # Inst execution rate -system.cpu.iew.EXEC:refs 48979606 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 20848536 # Number of stores executed +system.cpu.idleCycles 1035652 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 14732348 # Number of branches executed +system.cpu.iew.EXEC:nop 77233 # number of nop insts executed +system.cpu.iew.EXEC:rate 1.323750 # Inst execution rate +system.cpu.iew.EXEC:refs 49299625 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 21011299 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 107968668 # num instructions consuming a value -system.cpu.iew.WB:count 104398441 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.491185 # average fanout of values written-back +system.cpu.iew.WB:consumers 107738460 # num instructions consuming a value +system.cpu.iew.WB:count 105037825 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.490563 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 53032589 # num instructions producing a value -system.cpu.iew.WB:rate 1.311061 # insts written-back per cycle -system.cpu.iew.WB:sent 104647568 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 769833 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 1011566 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 29423654 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 740403 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 542722 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 21756532 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 112900513 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 28131070 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 777005 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 104987577 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 5988 # Number of times the IQ has become full, causing a stall +system.cpu.iew.WB:producers 52852456 # num instructions producing a value +system.cpu.iew.WB:rate 1.316536 # insts written-back per cycle +system.cpu.iew.WB:sent 105209239 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 874742 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 976865 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 29744817 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 738677 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 687790 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 22207815 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 114301833 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 28288326 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 931089 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 105613393 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 6026 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 6373 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 1889316 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 50994 # Number of cycles IEW is unblocking +system.cpu.iew.iewLSQFullEvents 6915 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 2130394 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 55938 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread.0.cacheBlocked 7 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 986302 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 2227 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.forwLoads 1108085 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 2818 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 8960 # Number of memory ordering violations -system.cpu.iew.lsq.thread.0.rescheduledLoads 42 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 2115374 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 1199623 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 8960 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 250530 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 519303 # Number of branches that were predicted taken incorrectly -system.cpu.int_regfile_reads 251243405 # number of integer regfile reads -system.cpu.int_regfile_writes 77636795 # number of integer regfile writes -system.cpu.ipc 1.263769 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.263769 # IPC: Total IPC of All Threads +system.cpu.iew.lsq.thread.0.memOrderViolation 8523 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.rescheduledLoads 41 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread.0.squashedLoads 2436412 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 1650781 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 8523 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 227397 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 647345 # Number of branches that were predicted taken incorrectly +system.cpu.int_regfile_reads 252839831 # number of integer regfile reads +system.cpu.int_regfile_writes 78127707 # number of integer regfile writes +system.cpu.ipc 1.261330 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.261330 # IPC: Total IPC of All Threads system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntAlu 56346023 53.27% 53.27% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntMult 90776 0.09% 53.36% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 53.36% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatAdd 60 0.00% 53.36% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 53.36% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 53.36% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 53.36% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 53.36% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 53.36% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAdd 4 0.00% 53.36% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 53.36% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 53.36% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 53.36% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 53.36% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 53.36% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 53.36% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 53.36% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 53.36% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 53.36% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 53.36% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 53.36% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 53.36% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 53.36% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 53.36% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 53.36% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 7 0.00% 53.36% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 53.36% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 53.36% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 53.36% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemRead 28386719 26.84% 80.20% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemWrite 20941000 19.80% 100.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntAlu 56712642 53.23% 53.23% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntMult 95301 0.09% 53.32% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 53.32% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatAdd 11 0.00% 53.32% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 53.32% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 53.32% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 53.32% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 53.32% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 53.32% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdAdd 1 0.00% 53.32% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 53.32% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 53.32% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 53.32% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 53.32% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 53.32% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 53.32% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 53.32% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 53.32% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 53.32% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 53.32% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 53.32% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 53.32% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 53.32% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 53.32% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 53.32% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 8 0.00% 53.32% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 53.32% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 53.32% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 53.32% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemRead 28583241 26.83% 80.15% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemWrite 21153285 19.85% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::total 105764589 # Type of FU issued -system.cpu.iq.ISSUE:fu_busy_cnt 1807941 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.017094 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:FU_type_0::total 106544489 # Type of FU issued +system.cpu.iq.ISSUE:fu_busy_cnt 1792992 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.016829 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntAlu 62929 3.48% 3.48% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 3.48% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 3.48% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 3.48% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 3.48% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 3.48% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 3.48% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 3.48% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 3.48% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 3.48% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 3.48% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 3.48% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 3.48% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 3.48% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 3.48% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 3.48% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 3.48% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 3.48% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 3.48% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 3.48% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 3.48% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 3.48% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 3.48% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 3.48% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 3.48% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 3.48% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 3.48% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 3.48% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 3.48% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemRead 1498776 82.90% 86.38% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemWrite 246236 13.62% 100.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntAlu 49061 2.74% 2.74% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 2.74% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 2.74% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 2.74% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 2.74% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 2.74% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 2.74% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 2.74% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 2.74% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 2.74% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 2.74% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 2.74% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 2.74% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 2.74% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 2.74% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 2.74% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 2.74% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 2.74% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 2.74% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 2.74% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 2.74% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 2.74% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 2.74% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 2.74% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 2.74% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 2.74% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 2.74% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 2.74% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 2.74% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemRead 1439096 80.26% 83.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemWrite 304835 17.00% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:issued_per_cycle::samples 78638764 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::mean 1.344942 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.522879 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::samples 78747821 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::mean 1.352983 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.550711 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::0 29814112 37.91% 37.91% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::1 21100770 26.83% 64.75% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::2 12756983 16.22% 80.97% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::3 6513032 8.28% 89.25% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::4 4951047 6.30% 95.55% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::5 1996772 2.54% 98.08% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::6 869647 1.11% 99.19% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::7 486381 0.62% 99.81% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::8 150020 0.19% 100.00% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::0 30449549 38.67% 38.67% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::1 20272773 25.74% 64.41% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::2 12837785 16.30% 80.71% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::3 6496976 8.25% 88.96% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::4 4874072 6.19% 95.15% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::5 2197331 2.79% 97.94% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::6 925872 1.18% 99.12% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::7 480661 0.61% 99.73% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::8 212802 0.27% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::total 78638764 # Number of insts issued each cycle -system.cpu.iq.ISSUE:rate 1.328217 # Inst issue rate -system.cpu.iq.fp_alu_accesses 124 # Number of floating point alu accesses -system.cpu.iq.fp_inst_queue_reads 244 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_wakeup_accesses 101 # Number of floating instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_writes 368 # Number of floating instruction queue writes -system.cpu.iq.int_alu_accesses 107572406 # Number of integer alu accesses -system.cpu.iq.int_inst_queue_reads 292071724 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_wakeup_accesses 104398340 # Number of integer instruction queue wakeup accesses -system.cpu.iq.int_inst_queue_writes 124776670 # Number of integer instruction queue writes -system.cpu.iq.iqInstsAdded 112053311 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 105764589 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 757403 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 11959480 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 96092 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 56614 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 19388799 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.ISSUE:issued_per_cycle::total 78747821 # Number of insts issued each cycle +system.cpu.iq.ISSUE:rate 1.335421 # Inst issue rate +system.cpu.iq.fp_alu_accesses 82 # Number of floating point alu accesses +system.cpu.iq.fp_inst_queue_reads 160 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_wakeup_accesses 68 # Number of floating instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_writes 144 # Number of floating instruction queue writes +system.cpu.iq.int_alu_accesses 108337399 # Number of integer alu accesses +system.cpu.iq.int_inst_queue_reads 293735316 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_wakeup_accesses 105037757 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_writes 127630070 # Number of integer instruction queue writes +system.cpu.iq.iqInstsAdded 113468820 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 106544489 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 755780 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 13400232 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 105692 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 54866 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 21923544 # Number of squashed operands that are examined and possibly removed from graph system.cpu.itb.accesses 0 # DTB accesses system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions @@ -416,115 +420,115 @@ system.cpu.itb.read_misses 0 # DT system.cpu.itb.write_accesses 0 # DTB write accesses system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.l2cache.ReadExReq_accesses 106884 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 34404.892788 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31241.062378 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_hits 4284 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_miss_latency 3529942000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_rate 0.959919 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_accesses 106889 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_avg_miss_latency 34386.744639 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31232.309942 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_hits 4289 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_miss_latency 3528080000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_rate 0.959874 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_misses 102600 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 3205333000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.959919 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 3204435000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.959874 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_misses 102600 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 78447 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 34190.010219 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31051.927909 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 46154 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 1104098000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.411654 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 32293 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_hits 56 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_miss_latency 1001021000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.410940 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 32237 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_accesses 14 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses 79238 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 34336.176999 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31108.810299 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 46944 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 1108852500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.407557 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 32294 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_hits 59 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_miss_latency 1002792500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.406812 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 32235 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_accesses 12 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_hits 5 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_miss_rate 0.642857 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_misses 9 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 279000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_rate 0.642857 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_misses 9 # number of UpgradeReq MSHR misses -system.cpu.l2cache.Writeback_accesses 123257 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 123257 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_hits 4 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_miss_rate 0.666667 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_misses 8 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 248000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_rate 0.666667 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_misses 8 # number of UpgradeReq MSHR misses +system.cpu.l2cache.Writeback_accesses 123381 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 123381 # number of Writeback hits system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.508488 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 0.515289 # Average number of references to valid blocks. system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 185331 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 34353.450513 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31195.843871 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 50438 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 4634040000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.727849 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 134893 # number of demand (read+write) misses -system.cpu.l2cache.demand_mshr_hits 56 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 4206354000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.727547 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 134837 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_accesses 186127 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 34374.638605 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31202.784885 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 51233 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 4636932500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.724742 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 134894 # number of demand (read+write) misses +system.cpu.l2cache.demand_mshr_hits 59 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_miss_latency 4207227500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.724425 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 134835 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.070607 # Average percentage of cache occupancy -system.cpu.l2cache.occ_%::1 0.488287 # Average percentage of cache occupancy -system.cpu.l2cache.occ_blocks::0 2313.642919 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 16000.187006 # Average occupied blocks per context -system.cpu.l2cache.overall_accesses 185331 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 34353.450513 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31195.843871 # average overall mshr miss latency +system.cpu.l2cache.occ_%::0 0.070082 # Average percentage of cache occupancy +system.cpu.l2cache.occ_%::1 0.488463 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 2296.436358 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 16005.968558 # Average occupied blocks per context +system.cpu.l2cache.overall_accesses 186127 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 34374.638605 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31202.784885 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 50438 # number of overall hits -system.cpu.l2cache.overall_miss_latency 4634040000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.727849 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 134893 # number of overall misses -system.cpu.l2cache.overall_mshr_hits 56 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 4206354000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.727547 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 134837 # number of overall MSHR misses +system.cpu.l2cache.overall_hits 51233 # number of overall hits +system.cpu.l2cache.overall_miss_latency 4636932500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.724742 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 134894 # number of overall misses +system.cpu.l2cache.overall_mshr_hits 59 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_miss_latency 4207227500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.724425 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 134835 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.replacements 114587 # number of replacements -system.cpu.l2cache.sampled_refs 133431 # Sample count of references to valid blocks. +system.cpu.l2cache.replacements 114581 # number of replacements +system.cpu.l2cache.sampled_refs 133428 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 18313.829925 # Cycle average of tags in use -system.cpu.l2cache.total_refs 67848 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 18302.404916 # Cycle average of tags in use +system.cpu.l2cache.total_refs 68754 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 88456 # number of writebacks -system.cpu.memDep0.conflictingLoads 17365346 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 14593147 # Number of conflicting stores. -system.cpu.memDep0.insertedLoads 29423654 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 21756532 # Number of stores inserted to the mem dependence unit. -system.cpu.misc_regfile_reads 143746938 # number of misc regfile reads -system.cpu.misc_regfile_writes 1948150 # number of misc regfile writes -system.cpu.numCycles 79628999 # number of cpu cycles simulated +system.cpu.l2cache.writebacks 88457 # number of writebacks +system.cpu.memDep0.conflictingLoads 15454792 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 13946617 # Number of conflicting stores. +system.cpu.memDep0.insertedLoads 29744817 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 22207815 # Number of stores inserted to the mem dependence unit. +system.cpu.misc_regfile_reads 146355256 # number of misc regfile reads +system.cpu.misc_regfile_writes 34410 # number of misc regfile writes +system.cpu.numCycles 79783473 # number of cpu cycles simulated system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.rename.RENAME:BlockCycles 3301986 # Number of cycles rename is blocking -system.cpu.rename.RENAME:CommittedMaps 76545782 # Number of HB maps that are committed -system.cpu.rename.RENAME:IQFullEvents 219694 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 26561955 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 3507385 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:ROBFullEvents 2 # Number of times rename has blocked due to ROB full -system.cpu.rename.RENAME:RenameLookups 309490180 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 116073660 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 89787248 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 20074378 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 1889316 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 4839366 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 13241430 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:fp_rename_lookups 84864 # Number of floating rename lookups -system.cpu.rename.RENAME:int_rename_lookups 309405316 # Number of integer rename lookups -system.cpu.rename.RENAME:serializeStallCycles 21971763 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 760740 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 13287175 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 761380 # count of temporary serializing insts renamed -system.cpu.rob.rob_reads 186818557 # The number of ROB reads -system.cpu.rob.rob_writes 227542910 # The number of ROB writes -system.cpu.timesIdled 60754 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.rename.RENAME:BlockCycles 2921057 # Number of cycles rename is blocking +system.cpu.rename.RENAME:CommittedMaps 75878617 # Number of HB maps that are committed +system.cpu.rename.RENAME:IQFullEvents 205954 # Number of times rename has blocked due to IQ full +system.cpu.rename.RENAME:IdleCycles 27124909 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 2993782 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:ROBFullEvents 3 # Number of times rename has blocked due to ROB full +system.cpu.rename.RENAME:RenameLookups 315599119 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 118180992 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 90551096 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 20607135 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 2130394 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 4279204 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 14672443 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:fp_rename_lookups 83429 # Number of floating rename lookups +system.cpu.rename.RENAME:int_rename_lookups 315515690 # Number of integer rename lookups +system.cpu.rename.RENAME:serializeStallCycles 21685122 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 759000 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 12013897 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 759711 # count of temporary serializing insts renamed +system.cpu.rob.rob_reads 187942474 # The number of ROB reads +system.cpu.rob.rob_writes 230588533 # The number of ROB writes +system.cpu.timesIdled 60808 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 1946 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/50.vortex/ref/arm/linux/simple-atomic/config.ini b/tests/long/50.vortex/ref/arm/linux/simple-atomic/config.ini index 8908b70ed..262e03017 100644 --- a/tests/long/50.vortex/ref/arm/linux/simple-atomic/config.ini +++ b/tests/long/50.vortex/ref/arm/linux/simple-atomic/config.ini @@ -61,7 +61,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=vortex lendian.raw -cwd=build/ARM_SE/tests/fast/long/50.vortex/arm/linux/simple-atomic +cwd=build/ARM_SE/tests/opt/long/50.vortex/arm/linux/simple-atomic egid=100 env= errout=cerr diff --git a/tests/long/50.vortex/ref/arm/linux/simple-atomic/simout b/tests/long/50.vortex/ref/arm/linux/simple-atomic/simout index e76d85acc..66dafc4ae 100755 --- a/tests/long/50.vortex/ref/arm/linux/simple-atomic/simout +++ b/tests/long/50.vortex/ref/arm/linux/simple-atomic/simout @@ -5,11 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Mar 11 2011 20:10:09 -M5 revision 4decc284606a 8095 default qtip tip ext/update_add_stats.patch -M5 started Mar 11 2011 20:12:03 +M5 compiled Mar 30 2011 17:47:57 +M5 started Mar 30 2011 18:44:05 M5 executing on u200439-lin.austin.arm.com -command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/50.vortex/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/fast/long/50.vortex/arm/linux/simple-atomic +command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/50.vortex/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/opt/long/50.vortex/arm/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/long/50.vortex/ref/arm/linux/simple-atomic/smred.out b/tests/long/50.vortex/ref/arm/linux/simple-atomic/smred.out new file mode 100644 index 000000000..726b45c60 --- /dev/null +++ b/tests/long/50.vortex/ref/arm/linux/simple-atomic/smred.out @@ -0,0 +1,258 @@ + CREATE Db Header and Db Primal ... + NEW DB [ 3] Created. + +VORTEX INPUT PARAMETERS:: + MESSAGE FileName: smred.msg + OUTPUT FileName: smred.out + DISK CACHE FileName: NULL + PART DB FileName: parts.db + DRAW DB FileName: draw.db + PERSON DB FileName: emp.db + PERSONS Data FileName: ./input/persons.250 + PARTS Count : 100 + OUTER Loops : 1 + INNER Loops : 1 + LOOKUP Parts : 25 + DELETE Parts : 10 + STUFF Parts : 10 + DEPTH Traverse: 5 + % DECREASE Parts : 0 + % INCREASE LookUps : 0 + % INCREASE Deletes : 0 + % INCREASE Stuffs : 0 + FREEZE_PACKETS : 1 + ALLOC_CHUNKS : 10000 + EXTEND_CHUNKS : 5000 + DELETE Draw objects : True + DELETE Part objects : False + QUE_BUG : 1000 + VOID_BOUNDARY : 67108864 + VOID_RESERVE : 1048576 + + COMMIT_DBS : False + + + + BMT TEST :: files... + EdbName := PartLib + EdbFileName := parts.db + DrwName := DrawLib + DrwFileName := draw.db + EmpName := PersonLib + EmpFileName := emp.db + + Swap to DiskCache := False + Freeze the cache := True + + + BMT TEST :: parms... + DeBug modulo := 1000 + Create Parts count:= 100 + Outer Loops := 1 + Inner Loops := 1 + Look Ups := 25 + Delete Parts := 10 + Stuff Parts := 10 + Traverse Limit := 5 + Delete Draws := True + Delete Parts := False + Delete ALL Parts := after every <mod 0>Outer Loop + + INITIALIZE LIBRARY :: + + INITIALIZE SCHEMA :: + Primal_CreateDb Accessed !!! + CREATE Db Header and Db Primal ... + NEW DB [ 4] Created. + PartLibCreate:: Db[ 4]; VpartsDir= 1 + + Part Count= 1 + + Initialize the Class maps + LIST HEADS loaded ... DbListHead_Class = 207 + DbListNode_Class = 206 + +...NOTE... ShellLoadCode:: Class[ 228] will NOT be Activated. + + +...NOTE... ShellLoadCode:: Class[ 229] will NOT be Activated. + + Primal_CreateDb Accessed !!! + CREATE Db Header and Db Primal ... + NEW DB [ 5] Created. + DrawLibCreate:: Db[ 5]; VpartsDir= 1 + + Initialize the Class maps of this schema. + Primal_CreateDb Accessed !!! + CREATE Db Header and Db Primal ... + NEW DB [ 6] Created. + + ***NOTE*** Persons Library Extended! + + Create <131072> Persons. + ItNum 0. Person[ 6: 5]. Name= Riddell , Robert V. ; + + LAST Person Read:: + ItNum 250. Person[ 6: 503]. Name= Gonzales , Warren X. ; + + BUILD <Query0> for <Part2> class:: + + if (link[1].length >= 5) :: + + Build Query2 for <Address> class:: + + if (State == CA || State == T*) + + Build Query1 for <Person> class:: + + if (LastName >= H* && LastName <= P* && Query0(Residence)) :: + + BUILD <Query3> for <DrawObj> class:: + + if (Id >= 3000 + && (Id >= 3000 && Id <= 3001) + && Id >= 3002) + + BUILD <Query4> for <NamedDrawObj> class:: + + if (Nam == Pre* + || (Nam == ??Mid??? || == Pre??Mid?? || == ??Post + || == Pre??Post || == ??Mid???Post || == Pre??Mid???Post) + && Id <= 7) + SEED := 1008; Swap = False; RgnEntries = 135 + + OUTER LOOP [ 1] : NewParts = 100 LookUps = 25 StuffParts = 10. + + Create 100 New Parts + Create Part 1. Token[ 4: 2]. + + < 100> Parts Created. CurrentId= 100 + + Connect each instantiated Part TO 3 unique Parts + Connect Part 1. Token[ 4: 2] + Connect Part 25. Token[ 4: 26] FromList= 26. + Connect Part 12. Token[ 4: 13] FromList= 13. + Connect Part 59. Token[ 4: 60] FromList= 60. + + SET <DrawObjs> entries:: + 1. [ 5: 5] := <1 >; @[: 6] + Iteration count = 100 + + SET <NamedDrawObjs> entries:: + 1. [ 5: 39] := <14 >; + Iteration count = 12 + + SET <LibRectangles> entries:: + 1. [ 5: 23] := <8 >; @[: 24] + Iteration count = 12 + + LIST <DbRectangles> entries:: + 1. [ 5: 23] + Iteration count = 12 + + SET <PersonNames > entries:: + Iteration count = 250 + + COMMIT All Image copies:: Release=<True>; Max Parts= 100 + < 100> Part images' Committed. + < 0> are Named. + < 50> Point images' Committed. + < 81> Person images' Committed. + + COMMIT Parts(* 100) + + Commit TestObj_Class in <Primal> DB. + ItNum 0. Token[ 0: 0]. TestObj Committed. + < 0> TestObj images' Committed. + + Commit CartesianPoint_Class in <Primal> DB. + ItNum 0. Token[ 0: 0]. CartesianPoint Committed. + < 0> CartesianPoint images' Committed. + + BEGIN Inner Loop Sequence::. + + INNER LOOP [ 1: 1] : + + LOOK UP 25 Random Parts and Export each Part. + + LookUp for 26 parts; Asserts = 8 + <Part2 > Asserts = 2; NULL Asserts = 3. + <DrawObj > Asserts = 0; NULL Asserts = 5. + <NamedObj > Asserts = 0; NULL Asserts = 0. + <Person > Asserts = 0; NULL Asserts = 5. + <TestObj > Asserts = 60; NULL Asserts = 0. + + DELETE 10 Random Parts. + + PartDelete :: Token[ 4: 91]. + PartDisconnect:: Token[ 4: 91] id:= 90 for each link. + DisConnect link [ 0]:= 50; PartToken[ 51: 51]. + DisConnect link [ 1]:= 17; PartToken[ 18: 18]. + DisConnect link [ 2]:= 72; PartToken[ 73: 73]. + DeleteFromList:: Vchunk[ 4: 91]. (* 1) + DisConnect FromList[ 0]:= 56; Token[ 57: 57]. + Vlists[ 89] := 100; + + Delete for 11 parts; + + Traverse Count= 0 + + TRAVERSE PartId[ 6] and all Connections to 5 Levels + SEED In Traverse Part [ 4: 65] @ Level = 4. + + Traverse Count= 357 + Traverse Asserts = 5. True Tests = 1 + < 5> DrawObj objects DELETED. + < 2> are Named. + < 2> Point objects DELETED. + + CREATE 10 Additional Parts + + Create 10 New Parts + Create Part 101. Token[ 4: 102]. + + < 10> Parts Created. CurrentId= 110 + + Connect each instantiated Part TO 3 unique Parts + + COMMIT All Image copies:: Release=<True>; Max Parts= 110 + < 81> Part images' Committed. + < 0> are Named. + < 38> Point images' Committed. + < 31> Person images' Committed. + + COMMIT Parts(* 100) + + Commit TestObj_Class in <Primal> DB. + ItNum 0. Token[ 3: 4]. TestObj Committed. + < 15> TestObj images' Committed. + + Commit CartesianPoint_Class in <Primal> DB. + ItNum 0. Token[ 3: 3]. CartesianPoint Committed. + < 16> CartesianPoint images' Committed. + + DELETE All TestObj objects; + + Delete TestObj_Class in <Primal> DB. + ItNum 0. Token[ 3: 4]. TestObj Deleted. + < 15> TestObj objects Deleted. + + Commit CartesianPoint_Class in <Primal> DB. + ItNum 0. Token[ 3: 3]. CartesianPoint Deleted. + < 16> CartesianPoint objects Deleted. + + DELETE TestObj and Point objects... + + END INNER LOOP [ 1: 1]. + + DELETE All TestObj objects; + + Delete TestObj_Class in <Primal> DB. + < 0> TestObj objects Deleted. + + Commit CartesianPoint_Class in <Primal> DB. + < 0> CartesianPoint objects Deleted. + + DELETE TestObj and Point objects... + STATUS= -201 +V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1! diff --git a/tests/long/50.vortex/ref/arm/linux/simple-atomic/stats.txt b/tests/long/50.vortex/ref/arm/linux/simple-atomic/stats.txt index a0efd159d..c99f59463 100644 --- a/tests/long/50.vortex/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/50.vortex/ref/arm/linux/simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1751644 # Simulator instruction rate (inst/s) -host_mem_usage 253996 # Number of bytes of host memory used -host_seconds 57.45 # Real time elapsed on the host -host_tick_rate 938757926 # Simulator tick rate (ticks/s) +host_inst_rate 1067183 # Simulator instruction rate (inst/s) +host_mem_usage 254708 # Number of bytes of host memory used +host_seconds 94.30 # Real time elapsed on the host +host_tick_rate 571936208 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 100632437 # Number of instructions simulated sim_seconds 0.053932 # Number of seconds simulated @@ -56,18 +56,18 @@ system.cpu.numCycles 107864325 # nu system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.num_busy_cycles 107864325 # Number of busy cycles -system.cpu.num_conditional_control_insts 8896554 # number of instructions that are conditional controls +system.cpu.num_conditional_control_insts 8920660 # number of instructions that are conditional controls system.cpu.num_fp_alu_accesses 56 # Number of float alu accesses system.cpu.num_fp_insts 56 # number of float instructions system.cpu.num_fp_register_reads 36 # number of times the floating registers were read system.cpu.num_fp_register_writes 20 # number of times the floating registers were written -system.cpu.num_func_calls 3336597 # number of times a function call or return occured +system.cpu.num_func_calls 3287514 # number of times a function call or return occured system.cpu.num_idle_cycles 0 # Number of idle cycles system.cpu.num_insts 100632437 # Number of instructions executed system.cpu.num_int_alu_accesses 91472788 # Number of integer alu accesses system.cpu.num_int_insts 91472788 # number of integer instructions system.cpu.num_int_register_reads 261951567 # number of times the integer registers were read -system.cpu.num_int_register_writes 75074702 # number of times the integer registers were written +system.cpu.num_int_register_writes 73126599 # number of times the integer registers were written system.cpu.num_load_insts 27307109 # Number of load instructions system.cpu.num_mem_refs 47862848 # number of memory refs system.cpu.num_store_insts 20555739 # Number of store instructions diff --git a/tests/long/50.vortex/ref/arm/linux/simple-timing/config.ini b/tests/long/50.vortex/ref/arm/linux/simple-timing/config.ini index be517e6da..c681e2402 100644 --- a/tests/long/50.vortex/ref/arm/linux/simple-timing/config.ini +++ b/tests/long/50.vortex/ref/arm/linux/simple-timing/config.ini @@ -164,7 +164,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=vortex lendian.raw -cwd=build/ARM_SE/tests/fast/long/50.vortex/arm/linux/simple-timing +cwd=build/ARM_SE/tests/opt/long/50.vortex/arm/linux/simple-timing egid=100 env= errout=cerr diff --git a/tests/long/50.vortex/ref/arm/linux/simple-timing/simerr b/tests/long/50.vortex/ref/arm/linux/simple-timing/simerr index e391217dd..eabe42249 100755 --- a/tests/long/50.vortex/ref/arm/linux/simple-timing/simerr +++ b/tests/long/50.vortex/ref/arm/linux/simple-timing/simerr @@ -1,11 +1,3 @@ warn: Sockets disabled, not accepting gdb connections For more information see: http://www.m5sim.org/warn/d946bea6 -warn: Complete acc isn't called on normal stores in O3. -For more information see: http://www.m5sim.org/warn/138d8573 -warn: Complete acc isn't called on normal stores in O3. -For more information see: http://www.m5sim.org/warn/138d8573 -warn: Complete acc isn't called on normal stores in O3. -For more information see: http://www.m5sim.org/warn/138d8573 -warn: Complete acc isn't called on normal stores in O3. -For more information see: http://www.m5sim.org/warn/138d8573 hack: be nice to actually delete the event here diff --git a/tests/long/50.vortex/ref/arm/linux/simple-timing/simout b/tests/long/50.vortex/ref/arm/linux/simple-timing/simout index 1c30be5f8..b08e3aaf1 100755 --- a/tests/long/50.vortex/ref/arm/linux/simple-timing/simout +++ b/tests/long/50.vortex/ref/arm/linux/simple-timing/simout @@ -5,11 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Mar 11 2011 20:10:09 -M5 revision 4decc284606a 8095 default qtip tip ext/update_add_stats.patch -M5 started Mar 11 2011 20:26:17 +M5 compiled Mar 30 2011 17:47:57 +M5 started Mar 30 2011 18:45:50 M5 executing on u200439-lin.austin.arm.com -command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/50.vortex/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/fast/long/50.vortex/arm/linux/simple-timing +command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/50.vortex/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/opt/long/50.vortex/arm/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/long/50.vortex/ref/arm/linux/simple-timing/smred.out b/tests/long/50.vortex/ref/arm/linux/simple-timing/smred.out new file mode 100644 index 000000000..726b45c60 --- /dev/null +++ b/tests/long/50.vortex/ref/arm/linux/simple-timing/smred.out @@ -0,0 +1,258 @@ + CREATE Db Header and Db Primal ... + NEW DB [ 3] Created. + +VORTEX INPUT PARAMETERS:: + MESSAGE FileName: smred.msg + OUTPUT FileName: smred.out + DISK CACHE FileName: NULL + PART DB FileName: parts.db + DRAW DB FileName: draw.db + PERSON DB FileName: emp.db + PERSONS Data FileName: ./input/persons.250 + PARTS Count : 100 + OUTER Loops : 1 + INNER Loops : 1 + LOOKUP Parts : 25 + DELETE Parts : 10 + STUFF Parts : 10 + DEPTH Traverse: 5 + % DECREASE Parts : 0 + % INCREASE LookUps : 0 + % INCREASE Deletes : 0 + % INCREASE Stuffs : 0 + FREEZE_PACKETS : 1 + ALLOC_CHUNKS : 10000 + EXTEND_CHUNKS : 5000 + DELETE Draw objects : True + DELETE Part objects : False + QUE_BUG : 1000 + VOID_BOUNDARY : 67108864 + VOID_RESERVE : 1048576 + + COMMIT_DBS : False + + + + BMT TEST :: files... + EdbName := PartLib + EdbFileName := parts.db + DrwName := DrawLib + DrwFileName := draw.db + EmpName := PersonLib + EmpFileName := emp.db + + Swap to DiskCache := False + Freeze the cache := True + + + BMT TEST :: parms... + DeBug modulo := 1000 + Create Parts count:= 100 + Outer Loops := 1 + Inner Loops := 1 + Look Ups := 25 + Delete Parts := 10 + Stuff Parts := 10 + Traverse Limit := 5 + Delete Draws := True + Delete Parts := False + Delete ALL Parts := after every <mod 0>Outer Loop + + INITIALIZE LIBRARY :: + + INITIALIZE SCHEMA :: + Primal_CreateDb Accessed !!! + CREATE Db Header and Db Primal ... + NEW DB [ 4] Created. + PartLibCreate:: Db[ 4]; VpartsDir= 1 + + Part Count= 1 + + Initialize the Class maps + LIST HEADS loaded ... DbListHead_Class = 207 + DbListNode_Class = 206 + +...NOTE... ShellLoadCode:: Class[ 228] will NOT be Activated. + + +...NOTE... ShellLoadCode:: Class[ 229] will NOT be Activated. + + Primal_CreateDb Accessed !!! + CREATE Db Header and Db Primal ... + NEW DB [ 5] Created. + DrawLibCreate:: Db[ 5]; VpartsDir= 1 + + Initialize the Class maps of this schema. + Primal_CreateDb Accessed !!! + CREATE Db Header and Db Primal ... + NEW DB [ 6] Created. + + ***NOTE*** Persons Library Extended! + + Create <131072> Persons. + ItNum 0. Person[ 6: 5]. Name= Riddell , Robert V. ; + + LAST Person Read:: + ItNum 250. Person[ 6: 503]. Name= Gonzales , Warren X. ; + + BUILD <Query0> for <Part2> class:: + + if (link[1].length >= 5) :: + + Build Query2 for <Address> class:: + + if (State == CA || State == T*) + + Build Query1 for <Person> class:: + + if (LastName >= H* && LastName <= P* && Query0(Residence)) :: + + BUILD <Query3> for <DrawObj> class:: + + if (Id >= 3000 + && (Id >= 3000 && Id <= 3001) + && Id >= 3002) + + BUILD <Query4> for <NamedDrawObj> class:: + + if (Nam == Pre* + || (Nam == ??Mid??? || == Pre??Mid?? || == ??Post + || == Pre??Post || == ??Mid???Post || == Pre??Mid???Post) + && Id <= 7) + SEED := 1008; Swap = False; RgnEntries = 135 + + OUTER LOOP [ 1] : NewParts = 100 LookUps = 25 StuffParts = 10. + + Create 100 New Parts + Create Part 1. Token[ 4: 2]. + + < 100> Parts Created. CurrentId= 100 + + Connect each instantiated Part TO 3 unique Parts + Connect Part 1. Token[ 4: 2] + Connect Part 25. Token[ 4: 26] FromList= 26. + Connect Part 12. Token[ 4: 13] FromList= 13. + Connect Part 59. Token[ 4: 60] FromList= 60. + + SET <DrawObjs> entries:: + 1. [ 5: 5] := <1 >; @[: 6] + Iteration count = 100 + + SET <NamedDrawObjs> entries:: + 1. [ 5: 39] := <14 >; + Iteration count = 12 + + SET <LibRectangles> entries:: + 1. [ 5: 23] := <8 >; @[: 24] + Iteration count = 12 + + LIST <DbRectangles> entries:: + 1. [ 5: 23] + Iteration count = 12 + + SET <PersonNames > entries:: + Iteration count = 250 + + COMMIT All Image copies:: Release=<True>; Max Parts= 100 + < 100> Part images' Committed. + < 0> are Named. + < 50> Point images' Committed. + < 81> Person images' Committed. + + COMMIT Parts(* 100) + + Commit TestObj_Class in <Primal> DB. + ItNum 0. Token[ 0: 0]. TestObj Committed. + < 0> TestObj images' Committed. + + Commit CartesianPoint_Class in <Primal> DB. + ItNum 0. Token[ 0: 0]. CartesianPoint Committed. + < 0> CartesianPoint images' Committed. + + BEGIN Inner Loop Sequence::. + + INNER LOOP [ 1: 1] : + + LOOK UP 25 Random Parts and Export each Part. + + LookUp for 26 parts; Asserts = 8 + <Part2 > Asserts = 2; NULL Asserts = 3. + <DrawObj > Asserts = 0; NULL Asserts = 5. + <NamedObj > Asserts = 0; NULL Asserts = 0. + <Person > Asserts = 0; NULL Asserts = 5. + <TestObj > Asserts = 60; NULL Asserts = 0. + + DELETE 10 Random Parts. + + PartDelete :: Token[ 4: 91]. + PartDisconnect:: Token[ 4: 91] id:= 90 for each link. + DisConnect link [ 0]:= 50; PartToken[ 51: 51]. + DisConnect link [ 1]:= 17; PartToken[ 18: 18]. + DisConnect link [ 2]:= 72; PartToken[ 73: 73]. + DeleteFromList:: Vchunk[ 4: 91]. (* 1) + DisConnect FromList[ 0]:= 56; Token[ 57: 57]. + Vlists[ 89] := 100; + + Delete for 11 parts; + + Traverse Count= 0 + + TRAVERSE PartId[ 6] and all Connections to 5 Levels + SEED In Traverse Part [ 4: 65] @ Level = 4. + + Traverse Count= 357 + Traverse Asserts = 5. True Tests = 1 + < 5> DrawObj objects DELETED. + < 2> are Named. + < 2> Point objects DELETED. + + CREATE 10 Additional Parts + + Create 10 New Parts + Create Part 101. Token[ 4: 102]. + + < 10> Parts Created. CurrentId= 110 + + Connect each instantiated Part TO 3 unique Parts + + COMMIT All Image copies:: Release=<True>; Max Parts= 110 + < 81> Part images' Committed. + < 0> are Named. + < 38> Point images' Committed. + < 31> Person images' Committed. + + COMMIT Parts(* 100) + + Commit TestObj_Class in <Primal> DB. + ItNum 0. Token[ 3: 4]. TestObj Committed. + < 15> TestObj images' Committed. + + Commit CartesianPoint_Class in <Primal> DB. + ItNum 0. Token[ 3: 3]. CartesianPoint Committed. + < 16> CartesianPoint images' Committed. + + DELETE All TestObj objects; + + Delete TestObj_Class in <Primal> DB. + ItNum 0. Token[ 3: 4]. TestObj Deleted. + < 15> TestObj objects Deleted. + + Commit CartesianPoint_Class in <Primal> DB. + ItNum 0. Token[ 3: 3]. CartesianPoint Deleted. + < 16> CartesianPoint objects Deleted. + + DELETE TestObj and Point objects... + + END INNER LOOP [ 1: 1]. + + DELETE All TestObj objects; + + Delete TestObj_Class in <Primal> DB. + < 0> TestObj objects Deleted. + + Commit CartesianPoint_Class in <Primal> DB. + < 0> CartesianPoint objects Deleted. + + DELETE TestObj and Point objects... + STATUS= -201 +V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1! diff --git a/tests/long/50.vortex/ref/arm/linux/simple-timing/stats.txt b/tests/long/50.vortex/ref/arm/linux/simple-timing/stats.txt index 310405f1b..0bdccd82b 100644 --- a/tests/long/50.vortex/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/50.vortex/ref/arm/linux/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 759848 # Simulator instruction rate (inst/s) -host_mem_usage 261720 # Number of bytes of host memory used -host_seconds 131.33 # Real time elapsed on the host -host_tick_rate 1013599729 # Simulator tick rate (ticks/s) +host_inst_rate 558313 # Simulator instruction rate (inst/s) +host_mem_usage 262448 # Number of bytes of host memory used +host_seconds 178.74 # Real time elapsed on the host +host_tick_rate 744762819 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 99791663 # Number of instructions simulated sim_seconds 0.133117 # Number of seconds simulated @@ -249,18 +249,18 @@ system.cpu.numCycles 266234884 # nu system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.num_busy_cycles 266234884 # Number of busy cycles -system.cpu.num_conditional_control_insts 8896554 # number of instructions that are conditional controls +system.cpu.num_conditional_control_insts 8920660 # number of instructions that are conditional controls system.cpu.num_fp_alu_accesses 56 # Number of float alu accesses system.cpu.num_fp_insts 56 # number of float instructions system.cpu.num_fp_register_reads 36 # number of times the floating registers were read system.cpu.num_fp_register_writes 20 # number of times the floating registers were written -system.cpu.num_func_calls 3336597 # number of times a function call or return occured +system.cpu.num_func_calls 3287514 # number of times a function call or return occured system.cpu.num_idle_cycles 0 # Number of idle cycles system.cpu.num_insts 99791663 # Number of instructions executed system.cpu.num_int_alu_accesses 91472788 # Number of integer alu accesses system.cpu.num_int_insts 91472788 # number of integer instructions system.cpu.num_int_register_reads 288972903 # number of times the integer registers were read -system.cpu.num_int_register_writes 75127954 # number of times the integer registers were written +system.cpu.num_int_register_writes 73126599 # number of times the integer registers were written system.cpu.num_load_insts 27307109 # Number of load instructions system.cpu.num_mem_refs 47862848 # number of memory refs system.cpu.num_store_insts 20555739 # Number of store instructions diff --git a/tests/long/60.bzip2/ref/arm/linux/o3-timing/config.ini b/tests/long/60.bzip2/ref/arm/linux/o3-timing/config.ini index 45dd167de..ed32bdd50 100644 --- a/tests/long/60.bzip2/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/60.bzip2/ref/arm/linux/o3-timing/config.ini @@ -25,6 +25,8 @@ BTBEntries=4096 BTBTagSize=16 LFSTSize=1024 LQEntries=32 +LSQCheckLoads=true +LSQDepCheckShift=4 RASSize=16 SQEntries=32 SSITSize=1024 @@ -491,12 +493,12 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=bzip2 input.source 1 -cwd=build/ARM_SE/tests/fast/long/60.bzip2/arm/linux/o3-timing +cwd=build/ARM_SE/tests/opt/long/60.bzip2/arm/linux/o3-timing egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/arm/linux/bzip2 +executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/bzip2 gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/60.bzip2/ref/arm/linux/o3-timing/simout b/tests/long/60.bzip2/ref/arm/linux/o3-timing/simout index 023672bd1..cc554e99a 100755 --- a/tests/long/60.bzip2/ref/arm/linux/o3-timing/simout +++ b/tests/long/60.bzip2/ref/arm/linux/o3-timing/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Mar 18 2011 20:12:03 -M5 started Mar 18 2011 20:43:37 -M5 executing on zizzer -command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/60.bzip2/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/fast/long/60.bzip2/arm/linux/o3-timing +M5 compiled Mar 30 2011 17:47:57 +M5 started Mar 30 2011 18:48:59 +M5 executing on u200439-lin.austin.arm.com +command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/60.bzip2/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/opt/long/60.bzip2/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... spec_init @@ -28,4 +28,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 642564184000 because target called exit() +Exiting @ tick 642890553000 because target called exit() diff --git a/tests/long/60.bzip2/ref/arm/linux/o3-timing/stats.txt b/tests/long/60.bzip2/ref/arm/linux/o3-timing/stats.txt index 205768a76..341e94b76 100644 --- a/tests/long/60.bzip2/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/60.bzip2/ref/arm/linux/o3-timing/stats.txt @@ -1,142 +1,142 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 146692 # Simulator instruction rate (inst/s) -host_mem_usage 221392 # Number of bytes of host memory used -host_seconds 11746.21 # Real time elapsed on the host -host_tick_rate 54703941 # Simulator tick rate (ticks/s) +host_inst_rate 101524 # Simulator instruction rate (inst/s) +host_mem_usage 255996 # Number of bytes of host memory used +host_seconds 16972.10 # Real time elapsed on the host +host_tick_rate 37879250 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 1723073879 # Number of instructions simulated -sim_seconds 0.642564 # Number of seconds simulated -sim_ticks 642564184000 # Number of ticks simulated +sim_insts 1723073854 # Number of instructions simulated +sim_seconds 0.642891 # Number of seconds simulated +sim_ticks 642890553000 # Number of ticks simulated system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.BTBHits 223408375 # Number of BTB hits -system.cpu.BPredUnit.BTBLookups 259871172 # Number of BTB lookups -system.cpu.BPredUnit.RASInCorrect 422 # Number of incorrect RAS predictions. -system.cpu.BPredUnit.condIncorrect 18003899 # Number of conditional branches incorrect -system.cpu.BPredUnit.condPredicted 242860493 # Number of conditional branches predicted -system.cpu.BPredUnit.lookups 296348291 # Number of BP lookups -system.cpu.BPredUnit.usedRAS 17775010 # Number of times the RAS was used to get a target. -system.cpu.commit.COM:branches 213462249 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 57892406 # number cycles where commit BW limit reached +system.cpu.BPredUnit.BTBHits 223193937 # Number of BTB hits +system.cpu.BPredUnit.BTBLookups 259593204 # Number of BTB lookups +system.cpu.BPredUnit.RASInCorrect 340 # Number of incorrect RAS predictions. +system.cpu.BPredUnit.condIncorrect 18005065 # Number of conditional branches incorrect +system.cpu.BPredUnit.condPredicted 242843937 # Number of conditional branches predicted +system.cpu.BPredUnit.lookups 296310364 # Number of BP lookups +system.cpu.BPredUnit.usedRAS 17771313 # Number of times the RAS was used to get a target. +system.cpu.commit.COM:branches 213462366 # Number of branches committed +system.cpu.commit.COM:bw_lim_events 57604302 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle::samples 1166021349 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::mean 1.477738 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::stdev 2.107067 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::samples 1166659925 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::mean 1.476929 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::stdev 2.106061 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::0 510165620 43.75% 43.75% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::1 303741868 26.05% 69.80% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::2 123389035 10.58% 80.38% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::3 73903803 6.34% 86.72% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::4 37047511 3.18% 89.90% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::5 32051525 2.75% 92.65% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::6 15551434 1.33% 93.98% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::7 12278147 1.05% 95.04% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::8 57892406 4.96% 100.00% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::0 510754561 43.78% 43.78% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::1 303447125 26.01% 69.79% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::2 123940356 10.62% 80.41% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::3 73811223 6.33% 86.74% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::4 36743344 3.15% 89.89% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::5 32005168 2.74% 92.63% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::6 15998188 1.37% 94.00% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::7 12355658 1.06% 95.06% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::8 57604302 4.94% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::total 1166021349 # Number of insts commited each cycle -system.cpu.commit.COM:count 1723073897 # Number of instructions committed +system.cpu.commit.COM:committed_per_cycle::total 1166659925 # Number of insts commited each cycle +system.cpu.commit.COM:count 1723073872 # Number of instructions committed system.cpu.commit.COM:fp_insts 36 # Number of committed floating point instructions. system.cpu.commit.COM:function_calls 13665177 # Number of function calls committed. -system.cpu.commit.COM:int_insts 1536941877 # Number of committed integer instructions. -system.cpu.commit.COM:loads 485926777 # Number of loads committed +system.cpu.commit.COM:int_insts 1536941857 # Number of committed integer instructions. +system.cpu.commit.COM:loads 485926772 # Number of loads committed system.cpu.commit.COM:membars 62 # Number of memory barriers committed -system.cpu.commit.COM:refs 660773829 # Number of memory references committed +system.cpu.commit.COM:refs 660773819 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 18003533 # The number of times a branch was mispredicted -system.cpu.commit.commitCommittedInsts 1723073897 # The number of committed instructions -system.cpu.commit.commitNonSpecStalls 463 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 488491112 # The number of squashed insts skipped by commit -system.cpu.committedInsts 1723073879 # Number of Instructions Simulated -system.cpu.committedInsts_total 1723073879 # Number of Instructions Simulated -system.cpu.cpi 0.745835 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.745835 # CPI: Total CPI of All Threads -system.cpu.dcache.LoadLockedReq_accesses 77 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_avg_miss_latency 38333.333333 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_hits 74 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_miss_latency 115000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_rate 0.038961 # miss rate for LoadLockedReq accesses +system.cpu.commit.branchMispredicts 18004568 # The number of times a branch was mispredicted +system.cpu.commit.commitCommittedInsts 1723073872 # The number of committed instructions +system.cpu.commit.commitNonSpecStalls 458 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.commitSquashedInsts 488146148 # The number of squashed insts skipped by commit +system.cpu.committedInsts 1723073854 # Number of Instructions Simulated +system.cpu.committedInsts_total 1723073854 # Number of Instructions Simulated +system.cpu.cpi 0.746214 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.746214 # CPI: Total CPI of All Threads +system.cpu.dcache.LoadLockedReq_accesses 65 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_avg_miss_latency 27333.333333 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_hits 62 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_miss_latency 82000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_rate 0.046154 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_misses 3 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_mshr_hits 3 # number of LoadLockedReq MSHR hits -system.cpu.dcache.ReadReq_accesses 502016934 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 15157.913551 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 11504.970685 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 493884953 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 123263865000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.016199 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 8131981 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 482230 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 88010161000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.015238 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 7649751 # number of ReadReq MSHR misses -system.cpu.dcache.StoreCondReq_accesses 68 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_hits 68 # number of StoreCondReq hits +system.cpu.dcache.ReadReq_accesses 501584612 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 15160.364798 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 11507.023204 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 493452712 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 123282570500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.016212 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 8131900 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 482613 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 88020523000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.015250 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 7649287 # number of ReadReq MSHR misses +system.cpu.dcache.StoreCondReq_accesses 63 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_hits 63 # number of StoreCondReq hits system.cpu.dcache.WriteReq_accesses 172586047 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 23727.454668 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 20867.425320 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 168020006 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 108340530838 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.026457 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 4566041 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 2674070 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 39480563550 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.010962 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 1891971 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles::no_mshrs 3133.925265 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 19555.555556 # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 69.369565 # Average number of references to valid blocks. -system.cpu.dcache.blocked::no_mshrs 25102 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 9 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_mshrs 78667792 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 176000 # number of cycles access was blocked +system.cpu.dcache.WriteReq_avg_miss_latency 23758.689113 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 20868.683162 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 168021895 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 108438268431 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.026446 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 4564152 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 2672149 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 39483611148 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.010963 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 1892003 # number of WriteReq MSHR misses +system.cpu.dcache.avg_blocked_cycles::no_mshrs 3136.287441 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 20750 # average number of cycles each access was blocked +system.cpu.dcache.avg_refs 69.327600 # Average number of references to valid blocks. +system.cpu.dcache.blocked::no_mshrs 24979 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 8 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_mshrs 78341324 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 166000 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 674602981 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 18239.407353 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 13361.395831 # average overall mshr miss latency -system.cpu.dcache.demand_hits 661904959 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 231604395838 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.018823 # miss rate for demand accesses -system.cpu.dcache.demand_misses 12698022 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 3156300 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 127490724550 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.014144 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 9541722 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_accesses 674170659 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 18251.409094 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 13363.406222 # average overall mshr miss latency +system.cpu.dcache.demand_hits 661474607 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 231720838931 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.018832 # miss rate for demand accesses +system.cpu.dcache.demand_misses 12696052 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 3154762 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 127504134148 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.014153 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 9541290 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.997821 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 4087.076226 # Average occupied blocks per context -system.cpu.dcache.overall_accesses 674602981 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 18239.407353 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 13361.395831 # average overall mshr miss latency +system.cpu.dcache.occ_%::0 0.997826 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 4087.096656 # Average occupied blocks per context +system.cpu.dcache.overall_accesses 674170659 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 18251.409094 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 13363.406222 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 661904959 # number of overall hits -system.cpu.dcache.overall_miss_latency 231604395838 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.018823 # miss rate for overall accesses -system.cpu.dcache.overall_misses 12698022 # number of overall misses -system.cpu.dcache.overall_mshr_hits 3156300 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 127490724550 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.014144 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 9541722 # number of overall MSHR misses +system.cpu.dcache.overall_hits 661474607 # number of overall hits +system.cpu.dcache.overall_miss_latency 231720838931 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.018832 # miss rate for overall accesses +system.cpu.dcache.overall_misses 12696052 # number of overall misses +system.cpu.dcache.overall_mshr_hits 3154762 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 127504134148 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.014153 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 9541290 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.replacements 9537626 # number of replacements -system.cpu.dcache.sampled_refs 9541722 # Sample count of references to valid blocks. +system.cpu.dcache.replacements 9537194 # number of replacements +system.cpu.dcache.sampled_refs 9541290 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4087.076226 # Cycle average of tags in use -system.cpu.dcache.total_refs 661905101 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 5039888000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 3122150 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 126134544 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 631 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 46158003 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 2344918841 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 578373170 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 449937268 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 70475039 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 2244 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 11576366 # Number of cycles decode is unblocking +system.cpu.dcache.tagsinuse 4087.096656 # Cycle average of tags in use +system.cpu.dcache.total_refs 661474732 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 5035189000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 3122149 # number of writebacks +system.cpu.decode.DECODE:BlockedCycles 127119222 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BranchMispred 630 # Number of times decode detected a branch misprediction +system.cpu.decode.DECODE:BranchResolved 46145837 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 2344585205 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 578307676 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 449658106 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 70439042 # Number of cycles decode is squashing +system.cpu.decode.DECODE:SquashedInsts 2261 # Number of squashed instructions handled by decode +system.cpu.decode.DECODE:UnblockCycles 11574920 # Number of cycles decode is unblocking system.cpu.dtb.accesses 0 # DTB accesses system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions @@ -158,142 +158,142 @@ system.cpu.dtb.read_misses 0 # DT system.cpu.dtb.write_accesses 0 # DTB write accesses system.cpu.dtb.write_hits 0 # DTB write hits system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.fetch.Branches 296348291 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 276432138 # Number of cache lines fetched -system.cpu.fetch.Cycles 470132828 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 5100693 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 2155880694 # Number of instructions fetch has processed -system.cpu.fetch.MiscStallCycles 236 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.SquashCycles 18543154 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.230598 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 276432138 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 241183385 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 1.677561 # Number of inst fetches per cycle -system.cpu.fetch.rateDist::samples 1236496387 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.931778 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.884875 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.Branches 296310364 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 276394619 # Number of cache lines fetched +system.cpu.fetch.Cycles 469857260 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 5099612 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 2155595751 # Number of instructions fetch has processed +system.cpu.fetch.MiscStallCycles 63 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.SquashCycles 18544487 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.230452 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 276394619 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 240965250 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 1.676487 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 1237098966 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.930612 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.884681 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 766363617 61.98% 61.98% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 33302617 2.69% 64.67% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 59273636 4.79% 69.47% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 61386146 4.96% 74.43% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 46873479 3.79% 78.22% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 54969771 4.45% 82.67% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 53004501 4.29% 86.95% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 18322602 1.48% 88.44% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 143000018 11.56% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 767241756 62.02% 62.02% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 33244799 2.69% 64.71% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 58987586 4.77% 69.47% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 61314807 4.96% 74.43% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 46983054 3.80% 78.23% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 54993105 4.45% 82.67% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 53020195 4.29% 86.96% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 18334456 1.48% 88.44% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 142979208 11.56% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1236496387 # Number of instructions fetched each cycle (Total) -system.cpu.fp_regfile_reads 41 # number of floating regfile reads -system.cpu.fp_regfile_writes 33 # number of floating regfile writes -system.cpu.icache.ReadReq_accesses 276432138 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 34722.162741 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 34464.838256 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 276431204 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 32430500 # number of ReadReq miss cycles +system.cpu.fetch.rateDist::total 1237098966 # Number of instructions fetched each cycle (Total) +system.cpu.fp_regfile_reads 39 # number of floating regfile reads +system.cpu.fp_regfile_writes 31 # number of floating regfile writes +system.cpu.icache.ReadReq_accesses 276394619 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 34658.288770 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 34406.030856 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 276393684 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 32405500 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.000003 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 934 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 223 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 24504500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_misses 935 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 222 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 24531500 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000003 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 711 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses 713 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 388792.129395 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 387648.925666 # Average number of references to valid blocks. system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 276432138 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 34722.162741 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 34464.838256 # average overall mshr miss latency -system.cpu.icache.demand_hits 276431204 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 32430500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_accesses 276394619 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 34658.288770 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 34406.030856 # average overall mshr miss latency +system.cpu.icache.demand_hits 276393684 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 32405500 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.000003 # miss rate for demand accesses -system.cpu.icache.demand_misses 934 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 223 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 24504500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_misses 935 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 222 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 24531500 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.000003 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 711 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses 713 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.280397 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 574.252402 # Average occupied blocks per context -system.cpu.icache.overall_accesses 276432138 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 34722.162741 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 34464.838256 # average overall mshr miss latency +system.cpu.icache.occ_%::0 0.281945 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 577.423416 # Average occupied blocks per context +system.cpu.icache.overall_accesses 276394619 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 34658.288770 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 34406.030856 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 276431204 # number of overall hits -system.cpu.icache.overall_miss_latency 32430500 # number of overall miss cycles +system.cpu.icache.overall_hits 276393684 # number of overall hits +system.cpu.icache.overall_miss_latency 32405500 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000003 # miss rate for overall accesses -system.cpu.icache.overall_misses 934 # number of overall misses -system.cpu.icache.overall_mshr_hits 223 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 24504500 # number of overall MSHR miss cycles +system.cpu.icache.overall_misses 935 # number of overall misses +system.cpu.icache.overall_mshr_hits 222 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 24531500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.000003 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 711 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses 713 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.replacements 8 # number of replacements -system.cpu.icache.sampled_refs 711 # Sample count of references to valid blocks. +system.cpu.icache.sampled_refs 713 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 574.252402 # Cycle average of tags in use -system.cpu.icache.total_refs 276431204 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 577.423416 # Cycle average of tags in use +system.cpu.icache.total_refs 276393684 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 48631982 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 233424980 # Number of branches executed -system.cpu.iew.EXEC:nop 482 # number of nop insts executed -system.cpu.iew.EXEC:rate 1.517936 # Inst execution rate -system.cpu.iew.EXEC:refs 747978494 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 187773804 # Number of stores executed +system.cpu.idleCycles 48682141 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 233410057 # Number of branches executed +system.cpu.iew.EXEC:nop 371 # number of nop insts executed +system.cpu.iew.EXEC:rate 1.517006 # Inst execution rate +system.cpu.iew.EXEC:refs 747857641 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 187754946 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 2256428952 # num instructions consuming a value -system.cpu.iew.WB:count 1928922171 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.551030 # average fanout of values written-back +system.cpu.iew.WB:consumers 2256424150 # num instructions consuming a value +system.cpu.iew.WB:count 1928710637 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.551017 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 1243359181 # num instructions producing a value -system.cpu.iew.WB:rate 1.500957 # insts written-back per cycle -system.cpu.iew.WB:sent 1935148462 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 19351048 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 24037939 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 626206356 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 572 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 5915627 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 225279083 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 2211459502 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 560204690 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 21122432 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 1950742523 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 1443603 # Number of times the IQ has become full, causing a stall +system.cpu.iew.WB:producers 1243327288 # num instructions producing a value +system.cpu.iew.WB:rate 1.500030 # insts written-back per cycle +system.cpu.iew.WB:sent 1934940770 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 19351943 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 24201668 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 626078428 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 573 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 5945884 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 225252424 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 2211114719 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 560102695 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 21129397 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 1950537549 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 1433857 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 76182 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 70475039 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 2501364 # Number of cycles IEW is unblocking +system.cpu.iew.iewLSQFullEvents 76087 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 70439042 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 2509999 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread.0.cacheBlocked 185277 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 54176834 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 572517 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.cacheBlocked 185300 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread.0.forwLoads 54506765 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 584812 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 735122 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.memOrderViolation 734835 # Number of memory ordering violations system.cpu.iew.lsq.thread.0.rescheduledLoads 2 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 140279578 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 50432031 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 735122 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 3222127 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 16128921 # Number of branches that were predicted taken incorrectly -system.cpu.int_regfile_reads 5041119538 # number of integer regfile reads -system.cpu.int_regfile_writes 1533310252 # number of integer regfile writes -system.cpu.ipc 1.340780 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.340780 # IPC: Total IPC of All Threads +system.cpu.iew.lsq.thread.0.squashedLoads 140151655 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 50405377 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 734835 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 3232685 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 16119258 # Number of branches that were predicted taken incorrectly +system.cpu.int_regfile_reads 5040549881 # number of integer regfile reads +system.cpu.int_regfile_writes 1533135931 # number of integer regfile writes +system.cpu.ipc 1.340099 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.340099 # IPC: Total IPC of All Threads system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntAlu 1212671548 61.50% 61.50% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntMult 1140441 0.06% 61.56% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntAlu 1212590834 61.50% 61.50% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntMult 1140241 0.06% 61.56% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 61.56% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::FloatAdd 2 0.00% 61.56% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 61.56% # Type of FU issued @@ -315,86 +315,86 @@ system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 61.56% # Ty system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 61.56% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 61.56% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 61.56% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 7 0.00% 61.56% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 6 0.00% 61.56% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 1 0.00% 61.56% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 8 0.00% 61.56% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 7 0.00% 61.56% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 61.56% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 61.56% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 61.56% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemRead 568624535 28.84% 90.39% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemWrite 189428413 9.61% 100.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemRead 568540639 28.84% 90.39% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemWrite 189395216 9.61% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::total 1971864955 # Type of FU issued -system.cpu.iq.ISSUE:fu_busy_cnt 20980180 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.010640 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:FU_type_0::total 1971666946 # Type of FU issued +system.cpu.iq.ISSUE:fu_busy_cnt 20875026 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.010588 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntAlu 466922 2.23% 2.23% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntMult 1 0.00% 2.23% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 2.23% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 2.23% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 2.23% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 2.23% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 2.23% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 2.23% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 2.23% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 2.23% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 2.23% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 2.23% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 2.23% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 2.23% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 2.23% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 2.23% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 2.23% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 2.23% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 2.23% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 2.23% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 2.23% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 2.23% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 2.23% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 2.23% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 2.23% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 2.23% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 2.23% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 2.23% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 2.23% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemRead 19229106 91.65% 93.88% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemWrite 1284151 6.12% 100.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntAlu 491210 2.35% 2.35% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntMult 2 0.00% 2.35% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 2.35% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 2.35% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 2.35% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 2.35% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 2.35% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 2.35% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 2.35% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 2.35% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 2.35% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 2.35% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 2.35% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 2.35% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 2.35% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 2.35% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 2.35% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 2.35% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 2.35% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 2.35% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 2.35% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 2.35% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 2.35% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 2.35% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 2.35% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 2.35% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 2.35% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 2.35% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 2.35% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemRead 19087912 91.44% 93.79% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemWrite 1295902 6.21% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:issued_per_cycle::samples 1236496387 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::mean 1.594720 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.635591 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::samples 1237098966 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::mean 1.593783 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.635374 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::0 417933228 33.80% 33.80% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::1 278405850 22.52% 56.32% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::2 219666046 17.77% 74.08% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::3 150452877 12.17% 86.25% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::4 89712597 7.26% 93.50% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::5 51644953 4.18% 97.68% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::6 17725773 1.43% 99.11% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::7 8301913 0.67% 99.79% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::8 2653150 0.21% 100.00% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::0 418606363 33.84% 33.84% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::1 277983689 22.47% 56.31% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::2 220653980 17.84% 74.14% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::3 149807025 12.11% 86.25% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::4 89527255 7.24% 93.49% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::5 51723580 4.18% 97.67% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::6 17902939 1.45% 99.12% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::7 8343412 0.67% 99.79% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::8 2550723 0.21% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::total 1236496387 # Number of insts issued each cycle -system.cpu.iq.ISSUE:rate 1.534372 # Inst issue rate -system.cpu.iq.fp_alu_accesses 65 # Number of floating point alu accesses -system.cpu.iq.fp_inst_queue_reads 124 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_wakeup_accesses 53 # Number of floating instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_writes 108 # Number of floating instruction queue writes -system.cpu.iq.int_alu_accesses 1992845070 # Number of integer alu accesses -system.cpu.iq.int_inst_queue_reads 5201866882 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_wakeup_accesses 1928922118 # Number of integer instruction queue wakeup accesses -system.cpu.iq.int_inst_queue_writes 2697398990 # Number of integer instruction queue writes -system.cpu.iq.iqInstsAdded 2211458379 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 1971864955 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 641 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 485334084 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 660529 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 178 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 844272367 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.ISSUE:issued_per_cycle::total 1237098966 # Number of insts issued each cycle +system.cpu.iq.ISSUE:rate 1.533439 # Inst issue rate +system.cpu.iq.fp_alu_accesses 63 # Number of floating point alu accesses +system.cpu.iq.fp_inst_queue_reads 120 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_wakeup_accesses 51 # Number of floating instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_writes 94 # Number of floating instruction queue writes +system.cpu.iq.int_alu_accesses 1992541909 # Number of integer alu accesses +system.cpu.iq.int_inst_queue_reads 5201971393 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_wakeup_accesses 1928710586 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_writes 2696699928 # Number of integer instruction queue writes +system.cpu.iq.iqInstsAdded 2211113711 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 1971666946 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 637 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 484979968 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 663629 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 179 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 843902514 # Number of squashed operands that are examined and possibly removed from graph system.cpu.itb.accesses 0 # DTB accesses system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions @@ -416,107 +416,107 @@ system.cpu.itb.read_misses 0 # DT system.cpu.itb.write_accesses 0 # DTB write accesses system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.l2cache.ReadExReq_accesses 1891974 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 34486.894931 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31341.697108 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_hits 979846 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_miss_latency 31456462500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_rate 0.482104 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 912128 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 28587639500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.482104 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 912128 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 7650459 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 34316.020010 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31128.460219 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 5630454 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 69318532000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.264037 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 2020005 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_accesses 1892006 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_avg_miss_latency 34501.539320 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31341.195670 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_hits 979915 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_miss_latency 31468543500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_rate 0.482076 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_misses 912091 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 28586022500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.482076 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_misses 912091 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_accesses 7649997 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 34318.289104 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31128.516872 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 5630330 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 69311516000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.264009 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 2019667 # number of ReadReq misses system.cpu.l2cache.ReadReq_mshr_hits 10 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_miss_latency 62879334000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.264036 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 2019995 # number of ReadReq MSHR misses -system.cpu.l2cache.Writeback_accesses 3122150 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 3122150 # number of Writeback hits -system.cpu.l2cache.avg_blocked_cycles::no_mshrs 3879.110251 # average number of cycles each access was blocked +system.cpu.l2cache.ReadReq_mshr_miss_latency 62868927000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.264008 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 2019657 # number of ReadReq MSHR misses +system.cpu.l2cache.Writeback_accesses 3122149 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 3122149 # number of Writeback hits +system.cpu.l2cache.avg_blocked_cycles::no_mshrs 3935.335196 # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 2.653657 # Average number of references to valid blocks. -system.cpu.l2cache.blocked::no_mshrs 3619 # number of cycles access was blocked +system.cpu.l2cache.avg_refs 2.653954 # Average number of references to valid blocks. +system.cpu.l2cache.blocked::no_mshrs 3580 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_mshrs 14038500 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_mshrs 14088500 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 9542433 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 34369.175784 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31194.794182 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 6610300 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 100774994500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.307273 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 2932133 # number of demand (read+write) misses +system.cpu.l2cache.demand_accesses 9542003 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 34375.299564 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31194.683001 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 6610245 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 100780059500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.307248 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 2931758 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 10 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 91466973500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.307272 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 2932123 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 91454949500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.307247 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 2931748 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.488260 # Average percentage of cache occupancy -system.cpu.l2cache.occ_%::1 0.329752 # Average percentage of cache occupancy -system.cpu.l2cache.occ_blocks::0 15999.295959 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 10805.300698 # Average occupied blocks per context -system.cpu.l2cache.overall_accesses 9542433 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 34369.175784 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31194.794182 # average overall mshr miss latency +system.cpu.l2cache.occ_%::0 0.487988 # Average percentage of cache occupancy +system.cpu.l2cache.occ_%::1 0.329914 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 15990.396178 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 10810.627507 # Average occupied blocks per context +system.cpu.l2cache.overall_accesses 9542003 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 34375.299564 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31194.683001 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 6610300 # number of overall hits -system.cpu.l2cache.overall_miss_latency 100774994500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.307273 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 2932133 # number of overall misses +system.cpu.l2cache.overall_hits 6610245 # number of overall hits +system.cpu.l2cache.overall_miss_latency 100780059500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.307248 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 2931758 # number of overall misses system.cpu.l2cache.overall_mshr_hits 10 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 91466973500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.307272 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 2932123 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 91454949500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.307247 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 2931748 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.replacements 2919711 # number of replacements -system.cpu.l2cache.sampled_refs 2947033 # Sample count of references to valid blocks. +system.cpu.l2cache.replacements 2919341 # number of replacements +system.cpu.l2cache.sampled_refs 2946667 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 26804.596658 # Cycle average of tags in use -system.cpu.l2cache.total_refs 7820415 # Total number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 143356933000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 1216362 # number of writebacks -system.cpu.memDep0.conflictingLoads 94435755 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 90423649 # Number of conflicting stores. -system.cpu.memDep0.insertedLoads 626206356 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 225279083 # Number of stores inserted to the mem dependence unit. -system.cpu.misc_regfile_reads 2884410167 # number of misc regfile reads -system.cpu.misc_regfile_writes 896 # number of misc regfile writes -system.cpu.numCycles 1285128369 # number of cpu cycles simulated +system.cpu.l2cache.tagsinuse 26801.023686 # Cycle average of tags in use +system.cpu.l2cache.total_refs 7820318 # Total number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 143319905000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.writebacks 1216305 # number of writebacks +system.cpu.memDep0.conflictingLoads 95681801 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 90040335 # Number of conflicting stores. +system.cpu.memDep0.insertedLoads 626078428 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 225252424 # Number of stores inserted to the mem dependence unit. +system.cpu.misc_regfile_reads 2884001509 # number of misc regfile reads +system.cpu.misc_regfile_writes 130 # number of misc regfile writes +system.cpu.numCycles 1285781107 # number of cpu cycles simulated system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.rename.RENAME:BlockCycles 66687922 # Number of cycles rename is blocking -system.cpu.rename.RENAME:CommittedMaps 1360917734 # Number of HB maps that are committed -system.cpu.rename.RENAME:IQFullEvents 14597587 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 600232966 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 40535929 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:ROBFullEvents 10237 # Number of times rename has blocked due to ROB full -system.cpu.rename.RENAME:RenameLookups 6332213633 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 2292978845 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 1803334951 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 438824808 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 70475039 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 60261068 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 442417214 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:fp_rename_lookups 432 # Number of floating rename lookups -system.cpu.rename.RENAME:int_rename_lookups 6332213201 # Number of integer rename lookups -system.cpu.rename.RENAME:serializeStallCycles 14584 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 629 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 117068052 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 624 # count of temporary serializing insts renamed -system.cpu.rob.rob_reads 3319693353 # The number of ROB reads -system.cpu.rob.rob_writes 4493611781 # The number of ROB writes -system.cpu.timesIdled 1545196 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.rename.RENAME:BlockCycles 67172415 # Number of cycles rename is blocking +system.cpu.rename.RENAME:CommittedMaps 1360917377 # Number of HB maps that are committed +system.cpu.rename.RENAME:IQFullEvents 14851346 # Number of times rename has blocked due to IQ full +system.cpu.rename.RENAME:IdleCycles 600335413 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 40774846 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:ROBFullEvents 10242 # Number of times rename has blocked due to ROB full +system.cpu.rename.RENAME:RenameLookups 6331353991 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 2292668273 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 1803116545 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 438383597 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 70439042 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 60752889 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 442199165 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:fp_rename_lookups 393 # Number of floating rename lookups +system.cpu.rename.RENAME:int_rename_lookups 6331353598 # Number of integer rename lookups +system.cpu.rename.RENAME:serializeStallCycles 15610 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 650 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 118137729 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 645 # count of temporary serializing insts renamed +system.cpu.rob.rob_reads 3320275044 # The number of ROB reads +system.cpu.rob.rob_writes 4492885352 # The number of ROB writes +system.cpu.timesIdled 1544733 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 46 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/60.bzip2/ref/arm/linux/simple-atomic/config.ini b/tests/long/60.bzip2/ref/arm/linux/simple-atomic/config.ini index 17d22d770..b27b25e6d 100644 --- a/tests/long/60.bzip2/ref/arm/linux/simple-atomic/config.ini +++ b/tests/long/60.bzip2/ref/arm/linux/simple-atomic/config.ini @@ -61,7 +61,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=bzip2 input.source 1 -cwd=build/ARM_SE/tests/fast/long/60.bzip2/arm/linux/simple-atomic +cwd=build/ARM_SE/tests/opt/long/60.bzip2/arm/linux/simple-atomic egid=100 env= errout=cerr diff --git a/tests/long/60.bzip2/ref/arm/linux/simple-atomic/simout b/tests/long/60.bzip2/ref/arm/linux/simple-atomic/simout index 1571face8..d37b6d85d 100755 --- a/tests/long/60.bzip2/ref/arm/linux/simple-atomic/simout +++ b/tests/long/60.bzip2/ref/arm/linux/simple-atomic/simout @@ -5,11 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Mar 11 2011 20:10:09 -M5 revision 4decc284606a 8095 default qtip tip ext/update_add_stats.patch -M5 started Mar 11 2011 20:10:25 +M5 compiled Mar 30 2011 17:47:57 +M5 started Mar 30 2011 18:50:12 M5 executing on u200439-lin.austin.arm.com -command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/60.bzip2/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/fast/long/60.bzip2/arm/linux/simple-atomic +command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/60.bzip2/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/opt/long/60.bzip2/arm/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... spec_init diff --git a/tests/long/60.bzip2/ref/arm/linux/simple-atomic/stats.txt b/tests/long/60.bzip2/ref/arm/linux/simple-atomic/stats.txt index bb05b8971..0c882577d 100644 --- a/tests/long/60.bzip2/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/60.bzip2/ref/arm/linux/simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1831754 # Simulator instruction rate (inst/s) -host_mem_usage 246412 # Number of bytes of host memory used -host_seconds 940.67 # Real time elapsed on the host -host_tick_rate 915878288 # Simulator tick rate (ticks/s) +host_inst_rate 1075067 # Simulator instruction rate (inst/s) +host_mem_usage 247128 # Number of bytes of host memory used +host_seconds 1602.76 # Real time elapsed on the host +host_tick_rate 537533999 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1723073862 # Number of instructions simulated sim_seconds 0.861538 # Number of seconds simulated @@ -56,18 +56,18 @@ system.cpu.numCycles 1723076411 # nu system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.num_busy_cycles 1723076411 # Number of busy cycles -system.cpu.num_conditional_control_insts 177497944 # number of instructions that are conditional controls +system.cpu.num_conditional_control_insts 177498066 # number of instructions that are conditional controls system.cpu.num_fp_alu_accesses 36 # Number of float alu accesses system.cpu.num_fp_insts 36 # number of float instructions system.cpu.num_fp_register_reads 24 # number of times the floating registers were read system.cpu.num_fp_register_writes 16 # number of times the floating registers were written -system.cpu.num_func_calls 27330236 # number of times a function call or return occured +system.cpu.num_func_calls 27330134 # number of times a function call or return occured system.cpu.num_idle_cycles 0 # Number of idle cycles system.cpu.num_insts 1723073862 # Number of instructions executed system.cpu.num_int_alu_accesses 1536941850 # Number of integer alu accesses system.cpu.num_int_insts 1536941850 # number of integer instructions system.cpu.num_int_register_reads 4663954117 # number of times the integer registers were read -system.cpu.num_int_register_writes 1329730844 # number of times the integer registers were written +system.cpu.num_int_register_writes 1329729952 # number of times the integer registers were written system.cpu.num_load_insts 485926770 # Number of load instructions system.cpu.num_mem_refs 660773816 # number of memory refs system.cpu.num_store_insts 174847046 # Number of store instructions diff --git a/tests/long/60.bzip2/ref/arm/linux/simple-timing/config.ini b/tests/long/60.bzip2/ref/arm/linux/simple-timing/config.ini index 8dc825ce6..b26c9b5f5 100644 --- a/tests/long/60.bzip2/ref/arm/linux/simple-timing/config.ini +++ b/tests/long/60.bzip2/ref/arm/linux/simple-timing/config.ini @@ -164,7 +164,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=bzip2 input.source 1 -cwd=build/ARM_SE/tests/fast/long/60.bzip2/arm/linux/simple-timing +cwd=build/ARM_SE/tests/opt/long/60.bzip2/arm/linux/simple-timing egid=100 env= errout=cerr diff --git a/tests/long/60.bzip2/ref/arm/linux/simple-timing/simerr b/tests/long/60.bzip2/ref/arm/linux/simple-timing/simerr index cdafa164c..eabe42249 100755 --- a/tests/long/60.bzip2/ref/arm/linux/simple-timing/simerr +++ b/tests/long/60.bzip2/ref/arm/linux/simple-timing/simerr @@ -1,5 +1,3 @@ warn: Sockets disabled, not accepting gdb connections For more information see: http://www.m5sim.org/warn/d946bea6 -warn: Complete acc isn't called on normal stores in O3. -For more information see: http://www.m5sim.org/warn/138d8573 hack: be nice to actually delete the event here diff --git a/tests/long/60.bzip2/ref/arm/linux/simple-timing/simout b/tests/long/60.bzip2/ref/arm/linux/simple-timing/simout index ffc182a84..50181b6ce 100755 --- a/tests/long/60.bzip2/ref/arm/linux/simple-timing/simout +++ b/tests/long/60.bzip2/ref/arm/linux/simple-timing/simout @@ -5,11 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Mar 11 2011 20:10:09 -M5 revision 4decc284606a 8095 default qtip tip ext/update_add_stats.patch -M5 started Mar 11 2011 20:27:01 +M5 compiled Mar 30 2011 17:47:57 +M5 started Mar 30 2011 19:14:16 M5 executing on u200439-lin.austin.arm.com -command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/60.bzip2/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/fast/long/60.bzip2/arm/linux/simple-timing +command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/60.bzip2/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/opt/long/60.bzip2/arm/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... spec_init diff --git a/tests/long/60.bzip2/ref/arm/linux/simple-timing/stats.txt b/tests/long/60.bzip2/ref/arm/linux/simple-timing/stats.txt index f32aabd92..b09cdeb30 100644 --- a/tests/long/60.bzip2/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/60.bzip2/ref/arm/linux/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 781303 # Simulator instruction rate (inst/s) -host_mem_usage 254132 # Number of bytes of host memory used -host_seconds 2197.96 # Real time elapsed on the host -host_tick_rate 1106217790 # Simulator tick rate (ticks/s) +host_inst_rate 536583 # Simulator instruction rate (inst/s) +host_mem_usage 254860 # Number of bytes of host memory used +host_seconds 3200.38 # Real time elapsed on the host +host_tick_rate 759728459 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1717270343 # Number of instructions simulated sim_seconds 2.431420 # Number of seconds simulated @@ -249,18 +249,18 @@ system.cpu.numCycles 4862839908 # nu system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.num_busy_cycles 4862839908 # Number of busy cycles -system.cpu.num_conditional_control_insts 177497944 # number of instructions that are conditional controls +system.cpu.num_conditional_control_insts 177498066 # number of instructions that are conditional controls system.cpu.num_fp_alu_accesses 36 # Number of float alu accesses system.cpu.num_fp_insts 36 # number of float instructions system.cpu.num_fp_register_reads 24 # number of times the floating registers were read system.cpu.num_fp_register_writes 16 # number of times the floating registers were written -system.cpu.num_func_calls 27330236 # number of times a function call or return occured +system.cpu.num_func_calls 27330134 # number of times a function call or return occured system.cpu.num_idle_cycles 0 # Number of idle cycles system.cpu.num_insts 1717270343 # Number of instructions executed system.cpu.num_int_alu_accesses 1536941850 # Number of integer alu accesses system.cpu.num_int_insts 1536941850 # number of integer instructions system.cpu.num_int_register_reads 5142795796 # number of times the integer registers were read -system.cpu.num_int_register_writes 1329730906 # number of times the integer registers were written +system.cpu.num_int_register_writes 1329729952 # number of times the integer registers were written system.cpu.num_load_insts 485926770 # Number of load instructions system.cpu.num_mem_refs 660773816 # number of memory refs system.cpu.num_store_insts 174847046 # Number of store instructions diff --git a/tests/long/70.twolf/ref/arm/linux/o3-timing/config.ini b/tests/long/70.twolf/ref/arm/linux/o3-timing/config.ini index 40d053507..28d94254f 100644 --- a/tests/long/70.twolf/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/70.twolf/ref/arm/linux/o3-timing/config.ini @@ -25,6 +25,8 @@ BTBEntries=4096 BTBTagSize=16 LFSTSize=1024 LQEntries=32 +LSQCheckLoads=true +LSQDepCheckShift=4 RASSize=16 SQEntries=32 SSITSize=1024 @@ -491,12 +493,12 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=twolf smred -cwd=build/ARM_SE/tests/fast/long/70.twolf/arm/linux/o3-timing +cwd=build/ARM_SE/tests/opt/long/70.twolf/arm/linux/o3-timing egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/arm/linux/twolf +executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/twolf gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/70.twolf/ref/arm/linux/o3-timing/simout b/tests/long/70.twolf/ref/arm/linux/o3-timing/simout index 40d08ca97..0ed791575 100755 --- a/tests/long/70.twolf/ref/arm/linux/o3-timing/simout +++ b/tests/long/70.twolf/ref/arm/linux/o3-timing/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Mar 18 2011 20:12:03 -M5 started Mar 18 2011 20:55:41 -M5 executing on zizzer -command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/70.twolf/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/fast/long/70.twolf/arm/linux/o3-timing +M5 compiled Mar 30 2011 17:47:57 +M5 started Mar 30 2011 19:17:05 +M5 executing on u200439-lin.austin.arm.com +command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/70.twolf/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/opt/long/70.twolf/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -25,4 +25,4 @@ info: Increasing stack size by one page. 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 -122 123 124 Exiting @ tick 124689161500 because target called exit() +122 123 124 Exiting @ tick 125793203000 because target called exit() diff --git a/tests/long/70.twolf/ref/arm/linux/o3-timing/smred.out b/tests/long/70.twolf/ref/arm/linux/o3-timing/smred.out new file mode 100644 index 000000000..00387ae5c --- /dev/null +++ b/tests/long/70.twolf/ref/arm/linux/o3-timing/smred.out @@ -0,0 +1,276 @@ + +TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988 +Standard Cell Placement and Global Routing Program +Authors: Carl Sechen, Bill Swartz + Yale University + + +NOTE: Restart file .rs2 not used + +TimberWolf will perform a global route step +rowSep: 1.000000 +feedThruWidth: 4 + +****************** +BLOCK DATA +block:1 desire:85 +block:2 desire:85 +Total Desired Length: 170 +total cell length: 168 +total block length: 168 +block x-span:84 block y-span:78 +implicit feed thru range: -84 +Using default value of bin.penalty.control:1.000000 +numBins automatically set to:5 +binWidth = average_cell_width + 0 sigma= 17 +average_cell_width is:16 +standard deviation of cell length is:23.6305 +TimberWolfSC starting from the beginning + + + +THIS IS THE ROUTE COST OF THE ORIGINAL PLACEMENT: 645 +The number of nets with 1 pin is 4 +The number of nets with 2 pin is 9 +The number of nets with 3 pin is 0 +The number of nets with 4 pin is 2 +The number of nets with 5 pin is 0 +The number of nets with 6 pin is 0 +The number of nets with 7 pin is 0 +The number of nets with 8 pin is 0 +The number of nets with 9 pin is 0 +The number of nets with 10 pin or more is 0 + +New Cost Function: Initial Horizontal Cost:242 +New Cost Function: FEEDS:0 MISSING_ROWS:-46 + +bdxlen:86 bdylen:78 +l:0 t:78 r:86 b:0 + + + +THIS IS THE ROUTE COST OF THE CURRENT PLACEMENT: 645 + + + +THIS IS THE PENALTY OF THE CURRENT PLACEMENT: 44 + +The rand generator seed was at utemp() : 1 + + + tempfile[0][0] = 0.982500 tempfile[0][1] = 90.000000 + tempfile[1][0] = 0.915000 tempfile[1][1] = 20.000000 + tempfile[2][0] = 0.700000 tempfile[2][1] = 10.000000 + tempfile[3][0] = 0.100000 tempfile[3][1] = 0.000000 + + I T fds Wire Penalty P_lim Epct binC rowC acc s/p early FDs MRs + 1 500 0 929 592 160 30.0 1.0 3.0 84.2 34.7 0.0 0 40 + 2 491 0 876 106 726 0.0 0.8 2.5 80.0 18.5 0.0 0 46 + 3 482 0 822 273 372 0.0 0.5 1.5 80.8 21.2 0.0 0 46 + 4 474 0 826 53 247 0.0 0.5 0.9 65.0 21.9 0.0 0 48 + 5 465 8 987 73 190 0.0 0.5 0.5 50.0 38.3 0.0 0 46 + 6 457 8 851 67 226 0.0 0.5 0.5 53.8 42.9 0.0 0 52 + 7 449 8 1067 108 190 0.0 0.5 0.5 46.2 53.8 0.0 0 50 + 8 441 8 918 106 171 0.0 0.5 0.5 47.1 40.4 0.0 0 48 + 9 434 8 812 101 197 0.0 0.5 0.5 53.6 21.0 0.0 0 48 + 10 426 8 1038 121 181 0.0 0.5 0.5 43.6 27.1 0.0 0 48 + 11 419 8 898 93 187 0.0 0.5 0.5 45.3 47.8 0.0 0 50 + 12 411 4 857 94 240 0.0 0.5 0.5 62.7 51.6 0.0 0 44 + 13 404 8 1043 88 185 0.0 0.5 0.5 54.0 52.8 0.0 0 50 + 14 397 8 767 94 154 0.0 0.5 0.5 33.8 35.0 0.0 0 50 + 15 390 8 862 89 183 0.0 0.5 0.5 55.6 29.0 0.0 0 46 + 16 383 4 798 79 173 0.0 0.5 0.5 57.5 35.3 0.0 0 52 + 17 376 8 827 100 152 0.0 0.5 0.5 35.3 81.8 0.0 0 50 + 18 370 8 878 101 208 0.0 0.5 0.5 44.7 46.2 0.0 0 48 + 19 363 4 921 67 167 0.0 0.5 0.5 57.1 34.7 0.0 0 48 + 20 357 8 933 93 154 0.0 0.5 0.5 46.5 43.6 0.0 0 52 + 21 351 8 930 89 147 0.0 0.5 0.5 39.4 36.5 0.0 0 52 + 22 345 8 951 79 142 0.0 0.5 0.5 32.8 51.3 0.0 0 50 + 23 339 8 1046 87 207 0.0 0.5 0.5 52.8 61.0 0.0 0 48 + 24 333 4 989 96 185 0.0 0.5 0.5 45.3 43.3 0.0 0 42 + 25 327 4 577 86 157 0.0 0.5 0.5 31.1 55.3 0.0 0 52 + 26 321 8 776 97 174 0.0 0.5 0.5 47.9 62.5 0.0 0 52 + 27 315 8 850 81 188 0.0 0.5 0.5 45.0 55.2 0.0 0 50 + 28 310 8 898 97 148 0.0 0.5 0.5 43.0 45.8 0.0 0 48 + 29 304 8 889 65 173 0.0 0.5 0.5 32.5 41.3 0.0 0 50 + 30 299 8 858 81 153 0.0 0.5 0.5 44.3 29.2 0.0 0 46 + 31 294 8 871 82 187 0.0 0.5 0.5 45.7 47.7 0.0 0 48 + 32 289 8 782 109 173 0.0 0.5 0.5 35.2 57.4 0.0 0 48 + 33 284 8 743 98 189 0.0 0.6 0.5 41.8 64.3 0.0 0 52 + 34 279 8 943 90 147 0.0 0.5 0.5 38.6 32.8 0.0 0 48 + 35 274 8 907 57 166 0.0 0.5 0.5 33.6 51.0 0.0 0 48 + 36 269 8 900 70 148 0.0 0.5 0.5 45.0 41.4 0.0 0 50 + 37 264 4 875 106 133 0.0 0.5 0.5 31.7 55.3 0.0 0 52 + 38 260 8 1023 145 149 0.0 0.6 0.5 28.7 65.0 0.0 0 52 + 39 255 8 801 151 173 0.0 0.9 0.5 41.7 41.2 0.0 0 48 + 40 251 8 741 104 159 0.0 0.8 0.5 36.2 47.5 0.0 0 48 + 41 246 8 828 108 149 0.0 0.5 0.5 34.6 50.9 0.0 0 50 + 42 242 8 947 128 132 0.0 0.7 0.5 34.2 39.0 0.0 0 50 + 43 238 8 917 101 142 0.0 0.8 0.5 34.4 50.9 0.0 0 48 + 44 234 8 761 86 129 0.0 0.5 0.5 42.0 36.4 0.0 0 52 + 45 229 8 979 106 137 0.0 0.5 0.5 29.2 55.3 0.0 0 50 + 46 225 8 806 74 130 0.0 0.7 0.5 33.1 65.4 0.0 0 52 + 47 221 8 971 125 114 0.0 0.5 0.5 31.9 45.6 0.0 0 52 + 48 218 8 869 125 104 0.0 0.9 0.5 30.0 56.0 0.0 0 48 + 49 214 8 999 153 140 0.0 0.8 0.5 30.4 46.4 0.0 0 52 + 50 210 8 798 192 139 0.0 1.0 0.5 28.9 50.0 0.0 0 52 + 51 206 8 860 125 157 0.0 1.2 0.5 31.5 26.9 0.0 0 52 + 52 203 8 893 186 127 5.9 0.9 0.5 26.4 42.3 0.0 0 46 + 53 199 8 863 126 141 0.0 1.2 0.5 32.5 44.4 0.0 0 44 + 54 196 8 788 97 133 0.0 0.9 0.5 37.5 40.0 0.0 0 50 + 55 192 8 926 119 116 0.0 0.6 0.5 26.1 55.3 0.0 0 52 + 56 189 8 789 162 107 0.0 0.8 0.5 25.2 40.4 0.0 0 48 + 57 186 8 878 107 128 0.0 1.1 0.5 23.1 34.0 0.0 0 52 + 58 182 8 775 105 122 0.0 0.8 0.5 25.5 57.4 0.0 0 50 + 59 179 8 747 94 129 0.0 0.7 0.5 34.3 37.3 0.0 0 50 + 60 176 8 845 96 138 0.0 0.6 0.5 28.3 41.7 0.0 0 52 + 61 173 8 961 121 110 0.0 0.6 0.5 29.0 52.6 0.0 0 48 + 62 170 4 911 110 109 0.0 0.9 0.5 33.5 33.3 0.0 0 48 + 63 167 8 656 109 109 0.0 0.8 0.5 21.9 44.7 0.0 0 52 + 64 164 8 934 117 105 0.0 0.8 0.5 15.5 50.0 0.0 0 52 + 65 161 8 972 125 95 0.0 0.8 0.5 24.4 50.0 0.0 0 50 + 66 158 8 894 125 101 0.0 0.9 0.5 27.2 35.9 0.0 0 52 + 67 155 8 798 146 129 0.0 1.0 0.5 22.8 58.7 0.0 0 52 + 68 153 8 901 183 92 0.0 1.1 0.5 23.6 34.5 0.0 0 52 + 69 150 8 977 197 103 0.0 1.4 0.5 23.6 36.8 0.0 0 52 + 70 147 8 905 262 93 0.0 1.5 0.5 20.3 63.4 0.0 0 52 + 71 145 8 995 148 122 0.0 1.9 0.5 20.9 35.3 0.0 0 52 + 72 142 8 934 230 99 0.0 1.6 0.5 20.0 65.9 0.0 0 52 + 73 140 8 862 173 100 0.0 1.8 0.5 26.8 46.8 0.0 0 52 + 74 137 8 924 139 90 0.0 1.7 0.5 16.8 42.5 0.0 0 52 + 75 135 8 888 168 113 0.0 1.6 0.5 22.9 40.4 0.0 0 52 + 76 133 8 712 212 84 0.0 1.6 0.5 13.4 46.9 0.0 0 52 + 77 130 8 868 210 91 0.0 1.7 0.5 17.7 51.2 0.0 0 52 + 78 128 8 952 307 92 0.0 1.9 0.5 19.7 44.9 0.0 0 50 + 79 126 8 801 157 107 0.0 2.2 0.5 15.8 39.0 0.0 0 52 + 80 123 8 849 147 93 0.0 2.1 0.5 15.6 51.4 0.0 0 52 + 81 121 8 799 154 86 0.0 1.9 0.5 12.2 50.0 0.0 0 52 + 82 119 8 941 213 82 0.0 1.8 0.5 19.5 41.2 0.0 0 50 + 83 117 8 751 268 94 0.0 2.0 0.5 20.8 42.6 0.0 0 50 + 84 115 8 828 198 102 0.0 2.2 0.5 15.5 59.5 0.0 0 52 + 85 113 8 898 266 123 0.0 2.2 0.5 13.2 85.2 0.0 0 52 + 86 111 8 943 190 93 0.0 2.4 0.5 19.5 45.1 0.0 0 52 + 87 109 8 864 183 65 0.0 2.4 0.5 14.9 31.8 0.0 0 52 + 88 107 8 793 203 93 0.0 2.4 0.5 11.8 35.3 0.0 0 52 + 89 105 8 752 162 74 1.2 2.4 0.5 13.1 21.4 0.0 0 52 + 90 103 8 801 149 77 0.0 2.3 0.5 9.7 58.3 0.0 0 52 + 91 102 8 901 230 99 0.0 2.2 0.5 16.0 25.5 0.0 0 52 + 92 100 8 826 201 87 0.0 2.4 0.5 12.8 45.7 0.0 0 52 + 93 98 8 810 196 83 0.0 2.5 0.5 14.0 24.4 0.0 0 52 + 94 96 8 857 209 68 1.0 2.5 0.5 11.5 27.0 5.1 0 52 + 95 95 8 771 174 91 0.0 2.6 0.5 10.5 26.5 0.0 0 52 + 96 93 8 955 210 59 0.0 2.6 0.5 10.0 36.7 0.7 0 52 + 97 91 8 833 206 53 0.0 2.7 0.5 10.2 19.4 1.4 0 52 + 98 90 8 888 229 86 0.0 2.8 0.5 8.1 36.0 0.0 0 52 + 99 88 8 794 186 91 1.0 2.9 0.5 8.3 25.0 0.5 0 52 +100 81 8 756 170 72 1.0 2.9 0.5 6.0 23.8 7.0 0 52 +101 74 8 791 176 67 0.0 2.9 0.5 4.4 58.3 4.0 0 52 +102 67 8 813 213 43 0.0 3.0 0.5 7.0 150.0 4.2 0 52 +103 62 8 779 245 39 0.0 3.1 0.5 3.2 16.7 13.0 0 52 +104 56 8 767 303 63 0.0 3.2 0.5 4.1 20.0 0.7 0 52 +105 52 8 757 270 57 0.0 3.5 0.5 6.4 3.7 0.5 0 52 +106 47 8 763 283 41 0.0 3.7 0.5 4.5 0.0 0.0 0 52 +107 43 8 768 283 36 0.0 3.7 0.5 2.9 18.2 3.6 0 52 +108 39 8 804 283 25 0.0 3.7 0.5 3.1 0.0 6.2 0 52 +109 36 8 781 283 24 0.0 3.7 0.5 3.6 6.7 6.7 0 52 +110 33 8 738 298 42 0.0 3.7 0.5 3.3 15.4 3.5 0 52 +111 30 8 761 298 36 0.0 3.7 0.5 2.2 0.0 4.3 0 52 +112 27 8 769 298 37 0.0 3.7 0.5 0.9 0.0 2.2 0 52 +113 25 8 745 298 31 0.0 3.7 0.5 1.5 0.0 6.6 0 52 +114 23 8 753 298 16 0.0 3.7 0.5 1.3 0.0 2.8 0 52 +115 21 8 745 298 11 0.0 3.7 0.5 1.5 0.0 14.0 0 52 +116 19 8 747 298 21 0.0 3.7 0.5 2.1 0.0 5.8 0 52 +117 13 8 737 298 12 0.0 3.7 0.5 1.0 0.0 10.0 0 52 +118 9 8 736 298 4 0.0 3.7 0.5 1.5 0.0 18.5 0 52 +119 0 8 739 298 0 0.0 3.7 0.5 1.8 0.0 18.0 0 52 +120 0 8 732 298 0 0.0 3.7 0.5 1.2 0.0 21.8 0 52 +121 0 8 732 19 -1 0.0 0.0 0.5 0.0 100.0 54.8 + +Initial Wiring Cost: 645 Final Wiring Cost: 732 +############## Percent Wire Cost Reduction: -13 + + +Initial Wire Length: 645 Final Wire Length: 732 +************** Percent Wire Length Reduction: -13 + + +Initial Horiz. Wire: 216 Final Horiz. Wire: 147 +$$$$$$$$$$$ Percent H-Wire Length Reduction: 32 + + +Initial Vert. Wire: 429 Final Vert. Wire: 585 +@@@@@@@@@@@ Percent V-Wire Length Reduction: -36 + +Before Feeds are Added: +BLOCK TOTAL CELL LENGTHS OVER/UNDER TARGET + 1 82 -20 + 2 86 -16 + +LONGEST Block is:2 Its length is:86 +BLOCK TOTAL CELL LENGTHS OVER/UNDER TARGET + 1 86 -16 + 2 86 -16 + +LONGEST Block is:1 Its length is:86 +Added: 1 feed-through cells + +Removed the cell overlaps --- Will do neighbor interchanges only now + +TOTAL INTERCONNECT LENGTH: 994 +OVERLAP PENALTY: 0 + +initialRowControl: 1.650 +finalRowControl: 0.300 +iter T Wire accept + 122 0.001 976 16% + 123 0.001 971 0% + 124 0.001 971 0% +Total Feed-Alignment Movement (Pass 1): 0 +Total Feed-Alignment Movement (Pass 2): 0 +Total Feed-Alignment Movement (Pass 3): 0 +Total Feed-Alignment Movement (Pass 4): 0 +Total Feed-Alignment Movement (Pass 5): 0 +Total Feed-Alignment Movement (Pass 6): 0 +Total Feed-Alignment Movement (Pass 7): 0 +Total Feed-Alignment Movement (Pass 8): 0 + +The rand generator seed was at globroute() : 987654321 + + +Total Number of Net Segments: 9 +Number of Switchable Net Segments: 0 + +Number of channels: 3 + + + +THIS IS THE ORIGINAL NUMBER OF TRACKS: 5 + + +no. of accepted flips: 0 +no. of attempted flips: 0 +THIS IS THE NUMBER OF TRACKS: 5 + + + +FINAL NUMBER OF ROUTING TRACKS: 5 + +MAX OF CHANNEL: 1 is: 0 +MAX OF CHANNEL: 2 is: 4 +MAX OF CHANNEL: 3 is: 1 +FINAL TOTAL INTERCONNECT LENGTH: 978 +FINAL OVERLAP PENALTY: 0 FINAL VALUE OF TOTAL COST IS: 978 +MAX NUMBER OF ATTEMPTED FLIPS PER T: 55 + + +cost_scale_factor:3.90616 + +Number of Feed Thrus: 0 +Number of Implicit Feed Thrus: 0 + +Statistics: +Number of Standard Cells: 10 +Number of Pads: 0 +Number of Nets: 15 +Number of Pins: 46 +Usage statistics not available diff --git a/tests/long/70.twolf/ref/arm/linux/o3-timing/stats.txt b/tests/long/70.twolf/ref/arm/linux/o3-timing/stats.txt index 9197fbb30..983eb9eea 100644 --- a/tests/long/70.twolf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/70.twolf/ref/arm/linux/o3-timing/stats.txt @@ -1,142 +1,142 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 93351 # Simulator instruction rate (inst/s) -host_mem_usage 225124 # Number of bytes of host memory used -host_seconds 2021.07 # Real time elapsed on the host -host_tick_rate 61694693 # Simulator tick rate (ticks/s) +host_inst_rate 53498 # Simulator instruction rate (inst/s) +host_mem_usage 259788 # Number of bytes of host memory used +host_seconds 3526.69 # Real time elapsed on the host +host_tick_rate 35668914 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 188669147 # Number of instructions simulated -sim_seconds 0.124689 # Number of seconds simulated -sim_ticks 124689161500 # Number of ticks simulated +sim_insts 188669132 # Number of instructions simulated +sim_seconds 0.125793 # Number of seconds simulated +sim_ticks 125793203000 # Number of ticks simulated system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.BTBHits 82388478 # Number of BTB hits -system.cpu.BPredUnit.BTBLookups 87434288 # Number of BTB lookups -system.cpu.BPredUnit.RASInCorrect 36044 # Number of incorrect RAS predictions. -system.cpu.BPredUnit.condIncorrect 9641646 # Number of conditional branches incorrect -system.cpu.BPredUnit.condPredicted 85843084 # Number of conditional branches predicted -system.cpu.BPredUnit.lookups 110166863 # Number of BP lookups -system.cpu.BPredUnit.usedRAS 4949514 # Number of times the RAS was used to get a target. -system.cpu.commit.COM:branches 40244076 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 1787959 # number cycles where commit BW limit reached +system.cpu.BPredUnit.BTBHits 83359858 # Number of BTB hits +system.cpu.BPredUnit.BTBLookups 88566677 # Number of BTB lookups +system.cpu.BPredUnit.RASInCorrect 111813 # Number of incorrect RAS predictions. +system.cpu.BPredUnit.condIncorrect 9866046 # Number of conditional branches incorrect +system.cpu.BPredUnit.condPredicted 86389460 # Number of conditional branches predicted +system.cpu.BPredUnit.lookups 110931092 # Number of BP lookups +system.cpu.BPredUnit.usedRAS 4559844 # Number of times the RAS was used to get a target. +system.cpu.commit.COM:branches 40284207 # Number of branches committed +system.cpu.commit.COM:bw_lim_events 1785335 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle::samples 222534164 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::mean 0.847886 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::stdev 1.274260 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::samples 224388172 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::mean 0.840880 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::stdev 1.269231 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::0 117100961 52.62% 52.62% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::1 58370166 26.23% 78.85% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::2 31670521 14.23% 93.08% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::3 7201653 3.24% 96.32% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::4 3053342 1.37% 97.69% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::5 1898242 0.85% 98.54% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::6 800122 0.36% 98.90% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::7 651198 0.29% 99.20% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::8 1787959 0.80% 100.00% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::0 118836869 52.96% 52.96% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::1 58355167 26.01% 78.97% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::2 31951737 14.24% 93.21% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::3 7144506 3.18% 96.39% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::4 2914461 1.30% 97.69% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::5 1962763 0.87% 98.56% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::6 824316 0.37% 98.93% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::7 613018 0.27% 99.20% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::8 1785335 0.80% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::total 222534164 # Number of insts commited each cycle -system.cpu.commit.COM:count 188683535 # Number of instructions committed +system.cpu.commit.COM:committed_per_cycle::total 224388172 # Number of insts commited each cycle +system.cpu.commit.COM:count 188683520 # Number of instructions committed system.cpu.commit.COM:fp_insts 1752310 # Number of committed floating point instructions. system.cpu.commit.COM:function_calls 1848934 # Number of function calls committed. -system.cpu.commit.COM:int_insts 150271162 # Number of committed integer instructions. -system.cpu.commit.COM:loads 29852012 # Number of loads committed +system.cpu.commit.COM:int_insts 150271150 # Number of committed integer instructions. +system.cpu.commit.COM:loads 29852009 # Number of loads committed system.cpu.commit.COM:membars 22408 # Number of memory barriers committed -system.cpu.commit.COM:refs 42499173 # Number of memory references committed +system.cpu.commit.COM:refs 42499167 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 9542849 # The number of times a branch was mispredicted -system.cpu.commit.commitCommittedInsts 188683535 # The number of committed instructions -system.cpu.commit.commitNonSpecStalls 1635922 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 177752777 # The number of squashed insts skipped by commit -system.cpu.committedInsts 188669147 # Number of Instructions Simulated -system.cpu.committedInsts_total 188669147 # Number of Instructions Simulated -system.cpu.cpi 1.321776 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.321776 # CPI: Total CPI of All Threads -system.cpu.dcache.LoadLockedReq_accesses 26639 # number of LoadLockedReq accesses(hits+misses) +system.cpu.commit.branchMispredicts 9726959 # The number of times a branch was mispredicted +system.cpu.commit.commitCommittedInsts 188683520 # The number of committed instructions +system.cpu.commit.commitNonSpecStalls 1635919 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.commitSquashedInsts 179794570 # The number of squashed insts skipped by commit +system.cpu.committedInsts 188669132 # Number of Instructions Simulated +system.cpu.committedInsts_total 188669132 # Number of Instructions Simulated +system.cpu.cpi 1.333479 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.333479 # CPI: Total CPI of All Threads +system.cpu.dcache.LoadLockedReq_accesses 26643 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_avg_miss_latency 32000 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_hits 26637 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits 26641 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_miss_latency 64000 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_rate 0.000075 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_misses 2 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_mshr_hits 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.ReadReq_accesses 38457824 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 33236.876215 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 32051.677852 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 38456281 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 51284500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_accesses 38482154 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 33506.489293 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 32275.510204 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 38480613 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 51633500 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.000040 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 1543 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 798 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 23878500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_misses 1541 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 806 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 23722500 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.000019 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 745 # number of ReadReq MSHR misses -system.cpu.dcache.StoreCondReq_accesses 24934 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_hits 24934 # number of StoreCondReq hits -system.cpu.dcache.WriteReq_accesses 12364290 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 31170.308568 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35114.010989 # average WriteReq mshr miss latency +system.cpu.dcache.ReadReq_mshr_misses 735 # number of ReadReq MSHR misses +system.cpu.dcache.StoreCondReq_accesses 24931 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_hits 24931 # number of StoreCondReq hits +system.cpu.dcache.WriteReq_accesses 12364287 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 31178.656598 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35098.901099 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_hits 12356739 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 235367000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.000611 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 7551 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 6459 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 38344500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_miss_latency 235336500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.000610 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 7548 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 6456 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 38328000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.000088 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 1092 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 27688.944475 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 27853.817187 # Average number of references to valid blocks. system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 50822114 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 31520.947878 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 33872.074034 # average overall mshr miss latency -system.cpu.dcache.demand_hits 50813020 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 286651500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_accesses 50846441 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 31573.330399 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 33963.054187 # average overall mshr miss latency +system.cpu.dcache.demand_hits 50837352 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 286970000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.000179 # miss rate for demand accesses -system.cpu.dcache.demand_misses 9094 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 7257 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 62223000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_misses 9089 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 7262 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 62050500 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.000036 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 1837 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses 1827 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.341673 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 1399.491436 # Average occupied blocks per context -system.cpu.dcache.overall_accesses 50822114 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 31520.947878 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 33872.074034 # average overall mshr miss latency +system.cpu.dcache.occ_%::0 0.338856 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 1387.955871 # Average occupied blocks per context +system.cpu.dcache.overall_accesses 50846441 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 31573.330399 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 33963.054187 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 50813020 # number of overall hits -system.cpu.dcache.overall_miss_latency 286651500 # number of overall miss cycles +system.cpu.dcache.overall_hits 50837352 # number of overall hits +system.cpu.dcache.overall_miss_latency 286970000 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.000179 # miss rate for overall accesses -system.cpu.dcache.overall_misses 9094 # number of overall misses -system.cpu.dcache.overall_mshr_hits 7257 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 62223000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_misses 9089 # number of overall misses +system.cpu.dcache.overall_mshr_hits 7262 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 62050500 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.000036 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 1837 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses 1827 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.replacements 46 # number of replacements -system.cpu.dcache.sampled_refs 1837 # Sample count of references to valid blocks. +system.cpu.dcache.replacements 48 # number of replacements +system.cpu.dcache.sampled_refs 1827 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 1399.491436 # Cycle average of tags in use -system.cpu.dcache.total_refs 50864591 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 1387.955871 # Cycle average of tags in use +system.cpu.dcache.total_refs 50888924 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 16 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 36483964 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 165697 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 17673947 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 443458046 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 81104837 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 104098479 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 26775543 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 708476 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 846883 # Number of cycles decode is unblocking +system.cpu.decode.DECODE:BlockedCycles 36464777 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BranchMispred 170249 # Number of times decode detected a branch misprediction +system.cpu.decode.DECODE:BranchResolved 17878904 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 446600367 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 82272510 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 104826667 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 27129630 # Number of cycles decode is squashing +system.cpu.decode.DECODE:SquashedInsts 707147 # Number of squashed instructions handled by decode +system.cpu.decode.DECODE:UnblockCycles 824217 # Number of cycles decode is unblocking system.cpu.dtb.accesses 0 # DTB accesses system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions @@ -158,243 +158,243 @@ system.cpu.dtb.read_misses 0 # DT system.cpu.dtb.write_accesses 0 # DTB write accesses system.cpu.dtb.write_hits 0 # DTB write hits system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.fetch.Branches 110166863 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 38007450 # Number of cache lines fetched -system.cpu.fetch.Cycles 110625948 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 2015006 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 433901698 # Number of instructions fetch has processed -system.cpu.fetch.MiscStallCycles 54587 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.SquashCycles 9922678 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.441766 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 38007450 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 87337992 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 1.739933 # Number of inst fetches per cycle -system.cpu.fetch.rateDist::samples 249309706 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.873850 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.579021 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.Branches 110931092 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 38679890 # Number of cache lines fetched +system.cpu.fetch.Cycles 111498626 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 2123796 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 437074245 # Number of instructions fetch has processed +system.cpu.fetch.MiscStallCycles 43 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.SquashCycles 10106938 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.440926 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 38679890 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 87919702 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 1.737273 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 251517801 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.873210 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.581419 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 138852417 55.69% 55.69% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 4190440 1.68% 57.38% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 32866604 13.18% 70.56% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 15794774 6.34% 76.89% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 9866514 3.96% 80.85% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 16440428 6.59% 87.45% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 8394995 3.37% 90.81% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 5405379 2.17% 92.98% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 17498155 7.02% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 140210227 55.75% 55.75% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 4303837 1.71% 57.46% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 33014843 13.13% 70.58% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 15960765 6.35% 76.93% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 9874938 3.93% 80.85% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 16484434 6.55% 87.41% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 8406542 3.34% 90.75% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 5529159 2.20% 92.95% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 17733056 7.05% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 249309706 # Number of instructions fetched each cycle (Total) -system.cpu.fp_regfile_reads 2867836 # number of floating regfile reads -system.cpu.fp_regfile_writes 2467423 # number of floating regfile writes -system.cpu.icache.ReadReq_accesses 38007450 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 23681.144866 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 20351.582549 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 38003467 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 94322000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.000105 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 3983 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 476 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 71373000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000092 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 3507 # number of ReadReq MSHR misses +system.cpu.fetch.rateDist::total 251517801 # Number of instructions fetched each cycle (Total) +system.cpu.fp_regfile_reads 2866910 # number of floating regfile reads +system.cpu.fp_regfile_writes 2464301 # number of floating regfile writes +system.cpu.icache.ReadReq_accesses 38679890 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 23669.425633 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 20344.827586 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 38675903 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 94370000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.000103 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 3987 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 478 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 71390000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.000091 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 3509 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 10836.460508 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 11021.915930 # Average number of references to valid blocks. system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 38007450 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 23681.144866 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 20351.582549 # average overall mshr miss latency -system.cpu.icache.demand_hits 38003467 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 94322000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.000105 # miss rate for demand accesses -system.cpu.icache.demand_misses 3983 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 476 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 71373000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.000092 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 3507 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_accesses 38679890 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 23669.425633 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 20344.827586 # average overall mshr miss latency +system.cpu.icache.demand_hits 38675903 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 94370000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.000103 # miss rate for demand accesses +system.cpu.icache.demand_misses 3987 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 478 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 71390000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.000091 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 3509 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.620951 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 1271.708604 # Average occupied blocks per context -system.cpu.icache.overall_accesses 38007450 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 23681.144866 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 20351.582549 # average overall mshr miss latency +system.cpu.icache.occ_%::0 0.620491 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 1270.764699 # Average occupied blocks per context +system.cpu.icache.overall_accesses 38679890 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 23669.425633 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 20344.827586 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 38003467 # number of overall hits -system.cpu.icache.overall_miss_latency 94322000 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.000105 # miss rate for overall accesses -system.cpu.icache.overall_misses 3983 # number of overall misses -system.cpu.icache.overall_mshr_hits 476 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 71373000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.000092 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 3507 # number of overall MSHR misses +system.cpu.icache.overall_hits 38675903 # number of overall hits +system.cpu.icache.overall_miss_latency 94370000 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.000103 # miss rate for overall accesses +system.cpu.icache.overall_misses 3987 # number of overall misses +system.cpu.icache.overall_mshr_hits 478 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 71390000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.000091 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 3509 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.replacements 1849 # number of replacements -system.cpu.icache.sampled_refs 3507 # Sample count of references to valid blocks. +system.cpu.icache.replacements 1854 # number of replacements +system.cpu.icache.sampled_refs 3509 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1271.708604 # Cycle average of tags in use -system.cpu.icache.total_refs 38003467 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 1270.764699 # Cycle average of tags in use +system.cpu.icache.total_refs 38675903 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 68618 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 53002298 # Number of branches executed -system.cpu.iew.EXEC:nop 82764 # number of nop insts executed -system.cpu.iew.EXEC:rate 0.971537 # Inst execution rate -system.cpu.iew.EXEC:refs 53752491 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 13612548 # Number of stores executed +system.cpu.idleCycles 68606 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 53273558 # Number of branches executed +system.cpu.iew.EXEC:nop 53064 # number of nop insts executed +system.cpu.iew.EXEC:rate 0.964190 # Inst execution rate +system.cpu.iew.EXEC:refs 53783248 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 13613267 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 284939700 # num instructions consuming a value -system.cpu.iew.WB:count 238367932 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.498660 # average fanout of values written-back +system.cpu.iew.WB:consumers 284801843 # num instructions consuming a value +system.cpu.iew.WB:count 238885590 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.499623 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 142088077 # num instructions producing a value -system.cpu.iew.WB:rate 0.955849 # insts written-back per cycle -system.cpu.iew.WB:sent 239814409 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 10973411 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 19948 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 49638370 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 2232445 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 4819384 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 18009283 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 366444127 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 40139943 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 7486863 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 242280268 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 4512 # Number of times the IQ has become full, causing a stall +system.cpu.iew.WB:producers 142293577 # num instructions producing a value +system.cpu.iew.WB:rate 0.949517 # insts written-back per cycle +system.cpu.iew.WB:sent 240138833 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 11160275 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 19997 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 50338304 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 2241625 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 4879199 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 18109550 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 368485815 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 40169981 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 7843894 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 242577015 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 4549 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 2549 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 26775543 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 7301 # Number of cycles IEW is unblocking +system.cpu.iew.iewLSQFullEvents 2590 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 27129630 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 7356 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 948005 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 19233 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.forwLoads 954573 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 20572 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 222493 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.memOrderViolation 222499 # Number of memory ordering violations system.cpu.iew.lsq.thread.0.rescheduledLoads 3 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 19786357 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 5362122 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 222493 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 2339474 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 8633937 # Number of branches that were predicted taken incorrectly -system.cpu.int_regfile_reads 541531980 # number of integer regfile reads -system.cpu.int_regfile_writes 230759535 # number of integer regfile writes -system.cpu.ipc 0.756558 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.756558 # IPC: Total IPC of All Threads +system.cpu.iew.lsq.thread.0.squashedLoads 20486294 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 5462392 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 222499 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 2295597 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 8864678 # Number of branches that were predicted taken incorrectly +system.cpu.int_regfile_reads 542109498 # number of integer regfile reads +system.cpu.int_regfile_writes 231159220 # number of integer regfile writes +system.cpu.ipc 0.749918 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.749918 # IPC: Total IPC of All Threads system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntAlu 191948188 76.85% 76.85% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntMult 913529 0.37% 77.22% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 77.22% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 77.22% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 77.22% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 77.22% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 77.22% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 77.22% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 77.22% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAdd 7217 0.00% 77.22% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 77.22% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 77.22% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 77.22% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 77.22% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 77.22% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 77.22% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 77.22% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 77.22% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 77.22% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 77.22% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 32763 0.01% 77.23% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 77.23% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 160980 0.06% 77.30% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 256110 0.10% 77.40% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 76473 0.03% 77.43% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 455650 0.18% 77.61% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 202844 0.08% 77.69% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 71631 0.03% 77.72% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 326 0.00% 77.72% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemRead 41826421 16.75% 94.47% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemWrite 13815002 5.53% 100.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntAlu 192549438 76.89% 76.89% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntMult 913605 0.36% 77.26% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 77.26% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 77.26% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 77.26% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 77.26% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 77.26% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 77.26% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 77.26% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdAdd 7231 0.00% 77.26% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 77.26% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 77.26% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 77.26% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 77.26% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 77.26% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 77.26% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 77.26% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 77.26% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 77.26% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 77.26% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 32771 0.01% 77.27% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 77.27% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 160968 0.06% 77.34% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 255770 0.10% 77.44% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 76475 0.03% 77.47% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 457524 0.18% 77.65% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 202683 0.08% 77.73% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 71630 0.03% 77.76% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 325 0.00% 77.76% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemRead 41871023 16.72% 94.48% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemWrite 13821469 5.52% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::total 249767134 # Type of FU issued -system.cpu.iq.ISSUE:fu_busy_cnt 1600059 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.006406 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:FU_type_0::total 250420912 # Type of FU issued +system.cpu.iq.ISSUE:fu_busy_cnt 1580075 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.006310 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntAlu 17737 1.11% 1.11% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntMult 5657 0.35% 1.46% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 1.46% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 1.46% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 1.46% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 1.46% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 1.46% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 1.46% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 1.46% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 1.46% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 1.46% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 1.46% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 1.46% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 1.46% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 1.46% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 1.46% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 1.46% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 1.46% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 1.46% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 1.46% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 1.46% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 1.46% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 1.46% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 1.46% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 1.46% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 1.46% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 1.46% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 1.46% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 1.46% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemRead 1269103 79.32% 80.78% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemWrite 307562 19.22% 100.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntAlu 55 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntMult 5520 0.35% 0.35% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 0.35% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 0.35% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 0.35% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 0.35% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 0.35% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 0.35% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 0.35% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 0.35% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 0.35% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 0.35% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 0.35% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 0.35% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 0.35% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 0.35% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 0.35% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 0.35% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 0.35% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 0.35% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 0.35% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 0.35% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 0.35% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 0.35% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 0.35% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 0.35% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 0.35% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 0.35% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 0.35% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemRead 1266721 80.17% 80.52% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemWrite 307779 19.48% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:issued_per_cycle::samples 249309706 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::mean 1.001835 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.200885 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::samples 251517801 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::mean 0.995639 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.196239 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::0 113103229 45.37% 45.37% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::1 65846302 26.41% 71.78% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::2 43653759 17.51% 89.29% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::3 15345322 6.16% 95.44% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::4 7500866 3.01% 98.45% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::5 2857086 1.15% 99.60% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::6 799949 0.32% 99.92% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::7 136784 0.05% 99.97% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::8 66409 0.03% 100.00% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::0 114687732 45.60% 45.60% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::1 66176551 26.31% 71.91% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::2 44052792 17.51% 89.42% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::3 15274317 6.07% 95.50% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::4 7530457 2.99% 98.49% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::5 2838961 1.13% 99.62% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::6 766561 0.30% 99.92% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::7 123613 0.05% 99.97% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::8 66817 0.03% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::total 249309706 # Number of insts issued each cycle -system.cpu.iq.ISSUE:rate 1.001559 # Inst issue rate -system.cpu.iq.fp_alu_accesses 1880181 # Number of floating point alu accesses -system.cpu.iq.fp_inst_queue_reads 3740694 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_wakeup_accesses 1822482 # Number of floating instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_writes 2256352 # Number of floating instruction queue writes -system.cpu.iq.int_alu_accesses 249487012 # Number of integer alu accesses -system.cpu.iq.int_inst_queue_reads 746951727 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_wakeup_accesses 236545450 # Number of integer instruction queue wakeup accesses -system.cpu.iq.int_inst_queue_writes 539735109 # Number of integer instruction queue writes -system.cpu.iq.iqInstsAdded 364104789 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 249767134 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 2256574 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 175408140 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 248391 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 620652 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 277084807 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.ISSUE:issued_per_cycle::total 251517801 # Number of insts issued each cycle +system.cpu.iq.ISSUE:rate 0.995367 # Inst issue rate +system.cpu.iq.fp_alu_accesses 1881090 # Number of floating point alu accesses +system.cpu.iq.fp_inst_queue_reads 3742288 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_wakeup_accesses 1821838 # Number of floating instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_writes 2251906 # Number of floating instruction queue writes +system.cpu.iq.int_alu_accesses 250119897 # Number of integer alu accesses +system.cpu.iq.int_inst_queue_reads 750424252 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_wakeup_accesses 237063752 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_writes 543997175 # Number of integer instruction queue writes +system.cpu.iq.iqInstsAdded 366166997 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 250420912 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 2265754 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 177594377 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 226843 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 629835 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 280770553 # Number of squashed operands that are examined and possibly removed from graph system.cpu.itb.accesses 0 # DTB accesses system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions @@ -417,105 +417,105 @@ system.cpu.itb.write_accesses 0 # DT system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses system.cpu.l2cache.ReadExReq_accesses 1092 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 34297.509225 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31037.822878 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 34291.512915 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31033.671587 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_hits 8 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_miss_latency 37178500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 37172000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_rate 0.992674 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_misses 1084 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 33645000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 33640500 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.992674 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_misses 1084 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 4252 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 34293.776575 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31074.261275 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 1665 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 88718000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.608420 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 2587 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_hits 15 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_miss_latency 79923000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.604892 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 2572 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_accesses 4244 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 34289.280186 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31071.066978 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 1660 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 88603500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.608860 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 2584 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_hits 16 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_miss_latency 79790500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.605090 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 2568 # number of ReadReq MSHR misses system.cpu.l2cache.Writeback_accesses 16 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_hits 16 # number of Writeback hits system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.645349 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 0.644410 # Average number of references to valid blocks. system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 5344 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 34294.878780 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31063.457330 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 1673 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 125896500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.686939 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 3671 # number of demand (read+write) misses -system.cpu.l2cache.demand_mshr_hits 15 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 113568000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.684132 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 3656 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_accesses 5336 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 34289.940022 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31059.967141 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 1668 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 125775500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.687406 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 3668 # number of demand (read+write) misses +system.cpu.l2cache.demand_mshr_hits 16 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_miss_latency 113431000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.684408 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 3652 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.056059 # Average percentage of cache occupancy +system.cpu.l2cache.occ_%::0 0.055915 # Average percentage of cache occupancy system.cpu.l2cache.occ_%::1 0.000092 # Average percentage of cache occupancy -system.cpu.l2cache.occ_blocks::0 1836.948830 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 3.029636 # Average occupied blocks per context -system.cpu.l2cache.overall_accesses 5344 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 34294.878780 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31063.457330 # average overall mshr miss latency +system.cpu.l2cache.occ_blocks::0 1832.230344 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 3.029186 # Average occupied blocks per context +system.cpu.l2cache.overall_accesses 5336 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 34289.940022 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31059.967141 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 1673 # number of overall hits -system.cpu.l2cache.overall_miss_latency 125896500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.686939 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 3671 # number of overall misses -system.cpu.l2cache.overall_mshr_hits 15 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 113568000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.684132 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 3656 # number of overall MSHR misses +system.cpu.l2cache.overall_hits 1668 # number of overall hits +system.cpu.l2cache.overall_miss_latency 125775500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.687406 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 3668 # number of overall misses +system.cpu.l2cache.overall_mshr_hits 16 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_miss_latency 113431000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.684408 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 3652 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 2580 # Sample count of references to valid blocks. +system.cpu.l2cache.sampled_refs 2576 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 1839.978467 # Cycle average of tags in use -system.cpu.l2cache.total_refs 1665 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 1835.259530 # Cycle average of tags in use +system.cpu.l2cache.total_refs 1660 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.memDep0.conflictingLoads 5431209 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 4203967 # Number of conflicting stores. -system.cpu.memDep0.insertedLoads 49638370 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 18009283 # Number of stores inserted to the mem dependence unit. -system.cpu.misc_regfile_reads 520185841 # number of misc regfile reads -system.cpu.misc_regfile_writes 4959640 # number of misc regfile writes -system.cpu.numCycles 249378324 # number of cpu cycles simulated +system.cpu.memDep0.conflictingLoads 5314098 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 4016301 # Number of conflicting stores. +system.cpu.memDep0.insertedLoads 50338304 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 18109550 # Number of stores inserted to the mem dependence unit. +system.cpu.misc_regfile_reads 524567380 # number of misc regfile reads +system.cpu.misc_regfile_writes 825086 # number of misc regfile writes +system.cpu.numCycles 251586407 # number of cpu cycles simulated system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.rename.RENAME:BlockCycles 894474 # Number of cycles rename is blocking -system.cpu.rename.RENAME:CommittedMaps 182569794 # Number of HB maps that are committed -system.cpu.rename.RENAME:IQFullEvents 613304 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 89635884 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 2121775 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:RenameLookups 950994709 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 412692464 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 417292399 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 96328320 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 26775543 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 5285061 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 234722601 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:fp_rename_lookups 13811231 # Number of floating rename lookups -system.cpu.rename.RENAME:int_rename_lookups 937183478 # Number of integer rename lookups -system.cpu.rename.RENAME:serializeStallCycles 30390424 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 2644938 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 23801477 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 2441234 # count of temporary serializing insts renamed -system.cpu.rob.rob_reads 587177316 # The number of ROB reads -system.cpu.rob.rob_writes 759649734 # The number of ROB writes -system.cpu.timesIdled 1415 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.rename.RENAME:BlockCycles 895052 # Number of cycles rename is blocking +system.cpu.rename.RENAME:CommittedMaps 180981200 # Number of HB maps that are committed +system.cpu.rename.RENAME:IQFullEvents 614225 # Number of times rename has blocked due to IQ full +system.cpu.rename.RENAME:IdleCycles 90974405 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 2116730 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:RenameLookups 956098353 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 414819410 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 416850208 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 96863032 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 27129630 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 5258013 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 235869004 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:fp_rename_lookups 13790121 # Number of floating rename lookups +system.cpu.rename.RENAME:int_rename_lookups 942308232 # Number of integer rename lookups +system.cpu.rename.RENAME:serializeStallCycles 30397669 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 2658319 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 23659926 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 2454002 # count of temporary serializing insts renamed +system.cpu.rob.rob_reads 591075726 # The number of ROB reads +system.cpu.rob.rob_writes 764090765 # The number of ROB writes +system.cpu.timesIdled 1409 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 400 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/70.twolf/ref/arm/linux/simple-atomic/config.ini b/tests/long/70.twolf/ref/arm/linux/simple-atomic/config.ini index b4f12af94..d713880d3 100644 --- a/tests/long/70.twolf/ref/arm/linux/simple-atomic/config.ini +++ b/tests/long/70.twolf/ref/arm/linux/simple-atomic/config.ini @@ -61,7 +61,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=twolf smred -cwd=build/ARM_SE/tests/fast/long/70.twolf/arm/linux/simple-atomic +cwd=build/ARM_SE/tests/opt/long/70.twolf/arm/linux/simple-atomic egid=100 env= errout=cerr diff --git a/tests/long/70.twolf/ref/arm/linux/simple-atomic/simout b/tests/long/70.twolf/ref/arm/linux/simple-atomic/simout index 46b5d4995..8b4af0675 100755 --- a/tests/long/70.twolf/ref/arm/linux/simple-atomic/simout +++ b/tests/long/70.twolf/ref/arm/linux/simple-atomic/simout @@ -5,11 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Mar 11 2011 20:10:09 -M5 revision 4decc284606a 8095 default qtip tip ext/update_add_stats.patch -M5 started Mar 11 2011 21:03:59 +M5 compiled Mar 30 2011 17:47:57 +M5 started Mar 30 2011 19:22:24 M5 executing on u200439-lin.austin.arm.com -command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/70.twolf/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/fast/long/70.twolf/arm/linux/simple-atomic +command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/70.twolf/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/opt/long/70.twolf/arm/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/70.twolf/ref/arm/linux/simple-atomic/smred.out b/tests/long/70.twolf/ref/arm/linux/simple-atomic/smred.out new file mode 100644 index 000000000..00387ae5c --- /dev/null +++ b/tests/long/70.twolf/ref/arm/linux/simple-atomic/smred.out @@ -0,0 +1,276 @@ + +TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988 +Standard Cell Placement and Global Routing Program +Authors: Carl Sechen, Bill Swartz + Yale University + + +NOTE: Restart file .rs2 not used + +TimberWolf will perform a global route step +rowSep: 1.000000 +feedThruWidth: 4 + +****************** +BLOCK DATA +block:1 desire:85 +block:2 desire:85 +Total Desired Length: 170 +total cell length: 168 +total block length: 168 +block x-span:84 block y-span:78 +implicit feed thru range: -84 +Using default value of bin.penalty.control:1.000000 +numBins automatically set to:5 +binWidth = average_cell_width + 0 sigma= 17 +average_cell_width is:16 +standard deviation of cell length is:23.6305 +TimberWolfSC starting from the beginning + + + +THIS IS THE ROUTE COST OF THE ORIGINAL PLACEMENT: 645 +The number of nets with 1 pin is 4 +The number of nets with 2 pin is 9 +The number of nets with 3 pin is 0 +The number of nets with 4 pin is 2 +The number of nets with 5 pin is 0 +The number of nets with 6 pin is 0 +The number of nets with 7 pin is 0 +The number of nets with 8 pin is 0 +The number of nets with 9 pin is 0 +The number of nets with 10 pin or more is 0 + +New Cost Function: Initial Horizontal Cost:242 +New Cost Function: FEEDS:0 MISSING_ROWS:-46 + +bdxlen:86 bdylen:78 +l:0 t:78 r:86 b:0 + + + +THIS IS THE ROUTE COST OF THE CURRENT PLACEMENT: 645 + + + +THIS IS THE PENALTY OF THE CURRENT PLACEMENT: 44 + +The rand generator seed was at utemp() : 1 + + + tempfile[0][0] = 0.982500 tempfile[0][1] = 90.000000 + tempfile[1][0] = 0.915000 tempfile[1][1] = 20.000000 + tempfile[2][0] = 0.700000 tempfile[2][1] = 10.000000 + tempfile[3][0] = 0.100000 tempfile[3][1] = 0.000000 + + I T fds Wire Penalty P_lim Epct binC rowC acc s/p early FDs MRs + 1 500 0 929 592 160 30.0 1.0 3.0 84.2 34.7 0.0 0 40 + 2 491 0 876 106 726 0.0 0.8 2.5 80.0 18.5 0.0 0 46 + 3 482 0 822 273 372 0.0 0.5 1.5 80.8 21.2 0.0 0 46 + 4 474 0 826 53 247 0.0 0.5 0.9 65.0 21.9 0.0 0 48 + 5 465 8 987 73 190 0.0 0.5 0.5 50.0 38.3 0.0 0 46 + 6 457 8 851 67 226 0.0 0.5 0.5 53.8 42.9 0.0 0 52 + 7 449 8 1067 108 190 0.0 0.5 0.5 46.2 53.8 0.0 0 50 + 8 441 8 918 106 171 0.0 0.5 0.5 47.1 40.4 0.0 0 48 + 9 434 8 812 101 197 0.0 0.5 0.5 53.6 21.0 0.0 0 48 + 10 426 8 1038 121 181 0.0 0.5 0.5 43.6 27.1 0.0 0 48 + 11 419 8 898 93 187 0.0 0.5 0.5 45.3 47.8 0.0 0 50 + 12 411 4 857 94 240 0.0 0.5 0.5 62.7 51.6 0.0 0 44 + 13 404 8 1043 88 185 0.0 0.5 0.5 54.0 52.8 0.0 0 50 + 14 397 8 767 94 154 0.0 0.5 0.5 33.8 35.0 0.0 0 50 + 15 390 8 862 89 183 0.0 0.5 0.5 55.6 29.0 0.0 0 46 + 16 383 4 798 79 173 0.0 0.5 0.5 57.5 35.3 0.0 0 52 + 17 376 8 827 100 152 0.0 0.5 0.5 35.3 81.8 0.0 0 50 + 18 370 8 878 101 208 0.0 0.5 0.5 44.7 46.2 0.0 0 48 + 19 363 4 921 67 167 0.0 0.5 0.5 57.1 34.7 0.0 0 48 + 20 357 8 933 93 154 0.0 0.5 0.5 46.5 43.6 0.0 0 52 + 21 351 8 930 89 147 0.0 0.5 0.5 39.4 36.5 0.0 0 52 + 22 345 8 951 79 142 0.0 0.5 0.5 32.8 51.3 0.0 0 50 + 23 339 8 1046 87 207 0.0 0.5 0.5 52.8 61.0 0.0 0 48 + 24 333 4 989 96 185 0.0 0.5 0.5 45.3 43.3 0.0 0 42 + 25 327 4 577 86 157 0.0 0.5 0.5 31.1 55.3 0.0 0 52 + 26 321 8 776 97 174 0.0 0.5 0.5 47.9 62.5 0.0 0 52 + 27 315 8 850 81 188 0.0 0.5 0.5 45.0 55.2 0.0 0 50 + 28 310 8 898 97 148 0.0 0.5 0.5 43.0 45.8 0.0 0 48 + 29 304 8 889 65 173 0.0 0.5 0.5 32.5 41.3 0.0 0 50 + 30 299 8 858 81 153 0.0 0.5 0.5 44.3 29.2 0.0 0 46 + 31 294 8 871 82 187 0.0 0.5 0.5 45.7 47.7 0.0 0 48 + 32 289 8 782 109 173 0.0 0.5 0.5 35.2 57.4 0.0 0 48 + 33 284 8 743 98 189 0.0 0.6 0.5 41.8 64.3 0.0 0 52 + 34 279 8 943 90 147 0.0 0.5 0.5 38.6 32.8 0.0 0 48 + 35 274 8 907 57 166 0.0 0.5 0.5 33.6 51.0 0.0 0 48 + 36 269 8 900 70 148 0.0 0.5 0.5 45.0 41.4 0.0 0 50 + 37 264 4 875 106 133 0.0 0.5 0.5 31.7 55.3 0.0 0 52 + 38 260 8 1023 145 149 0.0 0.6 0.5 28.7 65.0 0.0 0 52 + 39 255 8 801 151 173 0.0 0.9 0.5 41.7 41.2 0.0 0 48 + 40 251 8 741 104 159 0.0 0.8 0.5 36.2 47.5 0.0 0 48 + 41 246 8 828 108 149 0.0 0.5 0.5 34.6 50.9 0.0 0 50 + 42 242 8 947 128 132 0.0 0.7 0.5 34.2 39.0 0.0 0 50 + 43 238 8 917 101 142 0.0 0.8 0.5 34.4 50.9 0.0 0 48 + 44 234 8 761 86 129 0.0 0.5 0.5 42.0 36.4 0.0 0 52 + 45 229 8 979 106 137 0.0 0.5 0.5 29.2 55.3 0.0 0 50 + 46 225 8 806 74 130 0.0 0.7 0.5 33.1 65.4 0.0 0 52 + 47 221 8 971 125 114 0.0 0.5 0.5 31.9 45.6 0.0 0 52 + 48 218 8 869 125 104 0.0 0.9 0.5 30.0 56.0 0.0 0 48 + 49 214 8 999 153 140 0.0 0.8 0.5 30.4 46.4 0.0 0 52 + 50 210 8 798 192 139 0.0 1.0 0.5 28.9 50.0 0.0 0 52 + 51 206 8 860 125 157 0.0 1.2 0.5 31.5 26.9 0.0 0 52 + 52 203 8 893 186 127 5.9 0.9 0.5 26.4 42.3 0.0 0 46 + 53 199 8 863 126 141 0.0 1.2 0.5 32.5 44.4 0.0 0 44 + 54 196 8 788 97 133 0.0 0.9 0.5 37.5 40.0 0.0 0 50 + 55 192 8 926 119 116 0.0 0.6 0.5 26.1 55.3 0.0 0 52 + 56 189 8 789 162 107 0.0 0.8 0.5 25.2 40.4 0.0 0 48 + 57 186 8 878 107 128 0.0 1.1 0.5 23.1 34.0 0.0 0 52 + 58 182 8 775 105 122 0.0 0.8 0.5 25.5 57.4 0.0 0 50 + 59 179 8 747 94 129 0.0 0.7 0.5 34.3 37.3 0.0 0 50 + 60 176 8 845 96 138 0.0 0.6 0.5 28.3 41.7 0.0 0 52 + 61 173 8 961 121 110 0.0 0.6 0.5 29.0 52.6 0.0 0 48 + 62 170 4 911 110 109 0.0 0.9 0.5 33.5 33.3 0.0 0 48 + 63 167 8 656 109 109 0.0 0.8 0.5 21.9 44.7 0.0 0 52 + 64 164 8 934 117 105 0.0 0.8 0.5 15.5 50.0 0.0 0 52 + 65 161 8 972 125 95 0.0 0.8 0.5 24.4 50.0 0.0 0 50 + 66 158 8 894 125 101 0.0 0.9 0.5 27.2 35.9 0.0 0 52 + 67 155 8 798 146 129 0.0 1.0 0.5 22.8 58.7 0.0 0 52 + 68 153 8 901 183 92 0.0 1.1 0.5 23.6 34.5 0.0 0 52 + 69 150 8 977 197 103 0.0 1.4 0.5 23.6 36.8 0.0 0 52 + 70 147 8 905 262 93 0.0 1.5 0.5 20.3 63.4 0.0 0 52 + 71 145 8 995 148 122 0.0 1.9 0.5 20.9 35.3 0.0 0 52 + 72 142 8 934 230 99 0.0 1.6 0.5 20.0 65.9 0.0 0 52 + 73 140 8 862 173 100 0.0 1.8 0.5 26.8 46.8 0.0 0 52 + 74 137 8 924 139 90 0.0 1.7 0.5 16.8 42.5 0.0 0 52 + 75 135 8 888 168 113 0.0 1.6 0.5 22.9 40.4 0.0 0 52 + 76 133 8 712 212 84 0.0 1.6 0.5 13.4 46.9 0.0 0 52 + 77 130 8 868 210 91 0.0 1.7 0.5 17.7 51.2 0.0 0 52 + 78 128 8 952 307 92 0.0 1.9 0.5 19.7 44.9 0.0 0 50 + 79 126 8 801 157 107 0.0 2.2 0.5 15.8 39.0 0.0 0 52 + 80 123 8 849 147 93 0.0 2.1 0.5 15.6 51.4 0.0 0 52 + 81 121 8 799 154 86 0.0 1.9 0.5 12.2 50.0 0.0 0 52 + 82 119 8 941 213 82 0.0 1.8 0.5 19.5 41.2 0.0 0 50 + 83 117 8 751 268 94 0.0 2.0 0.5 20.8 42.6 0.0 0 50 + 84 115 8 828 198 102 0.0 2.2 0.5 15.5 59.5 0.0 0 52 + 85 113 8 898 266 123 0.0 2.2 0.5 13.2 85.2 0.0 0 52 + 86 111 8 943 190 93 0.0 2.4 0.5 19.5 45.1 0.0 0 52 + 87 109 8 864 183 65 0.0 2.4 0.5 14.9 31.8 0.0 0 52 + 88 107 8 793 203 93 0.0 2.4 0.5 11.8 35.3 0.0 0 52 + 89 105 8 752 162 74 1.2 2.4 0.5 13.1 21.4 0.0 0 52 + 90 103 8 801 149 77 0.0 2.3 0.5 9.7 58.3 0.0 0 52 + 91 102 8 901 230 99 0.0 2.2 0.5 16.0 25.5 0.0 0 52 + 92 100 8 826 201 87 0.0 2.4 0.5 12.8 45.7 0.0 0 52 + 93 98 8 810 196 83 0.0 2.5 0.5 14.0 24.4 0.0 0 52 + 94 96 8 857 209 68 1.0 2.5 0.5 11.5 27.0 5.1 0 52 + 95 95 8 771 174 91 0.0 2.6 0.5 10.5 26.5 0.0 0 52 + 96 93 8 955 210 59 0.0 2.6 0.5 10.0 36.7 0.7 0 52 + 97 91 8 833 206 53 0.0 2.7 0.5 10.2 19.4 1.4 0 52 + 98 90 8 888 229 86 0.0 2.8 0.5 8.1 36.0 0.0 0 52 + 99 88 8 794 186 91 1.0 2.9 0.5 8.3 25.0 0.5 0 52 +100 81 8 756 170 72 1.0 2.9 0.5 6.0 23.8 7.0 0 52 +101 74 8 791 176 67 0.0 2.9 0.5 4.4 58.3 4.0 0 52 +102 67 8 813 213 43 0.0 3.0 0.5 7.0 150.0 4.2 0 52 +103 62 8 779 245 39 0.0 3.1 0.5 3.2 16.7 13.0 0 52 +104 56 8 767 303 63 0.0 3.2 0.5 4.1 20.0 0.7 0 52 +105 52 8 757 270 57 0.0 3.5 0.5 6.4 3.7 0.5 0 52 +106 47 8 763 283 41 0.0 3.7 0.5 4.5 0.0 0.0 0 52 +107 43 8 768 283 36 0.0 3.7 0.5 2.9 18.2 3.6 0 52 +108 39 8 804 283 25 0.0 3.7 0.5 3.1 0.0 6.2 0 52 +109 36 8 781 283 24 0.0 3.7 0.5 3.6 6.7 6.7 0 52 +110 33 8 738 298 42 0.0 3.7 0.5 3.3 15.4 3.5 0 52 +111 30 8 761 298 36 0.0 3.7 0.5 2.2 0.0 4.3 0 52 +112 27 8 769 298 37 0.0 3.7 0.5 0.9 0.0 2.2 0 52 +113 25 8 745 298 31 0.0 3.7 0.5 1.5 0.0 6.6 0 52 +114 23 8 753 298 16 0.0 3.7 0.5 1.3 0.0 2.8 0 52 +115 21 8 745 298 11 0.0 3.7 0.5 1.5 0.0 14.0 0 52 +116 19 8 747 298 21 0.0 3.7 0.5 2.1 0.0 5.8 0 52 +117 13 8 737 298 12 0.0 3.7 0.5 1.0 0.0 10.0 0 52 +118 9 8 736 298 4 0.0 3.7 0.5 1.5 0.0 18.5 0 52 +119 0 8 739 298 0 0.0 3.7 0.5 1.8 0.0 18.0 0 52 +120 0 8 732 298 0 0.0 3.7 0.5 1.2 0.0 21.8 0 52 +121 0 8 732 19 -1 0.0 0.0 0.5 0.0 100.0 54.8 + +Initial Wiring Cost: 645 Final Wiring Cost: 732 +############## Percent Wire Cost Reduction: -13 + + +Initial Wire Length: 645 Final Wire Length: 732 +************** Percent Wire Length Reduction: -13 + + +Initial Horiz. Wire: 216 Final Horiz. Wire: 147 +$$$$$$$$$$$ Percent H-Wire Length Reduction: 32 + + +Initial Vert. Wire: 429 Final Vert. Wire: 585 +@@@@@@@@@@@ Percent V-Wire Length Reduction: -36 + +Before Feeds are Added: +BLOCK TOTAL CELL LENGTHS OVER/UNDER TARGET + 1 82 -20 + 2 86 -16 + +LONGEST Block is:2 Its length is:86 +BLOCK TOTAL CELL LENGTHS OVER/UNDER TARGET + 1 86 -16 + 2 86 -16 + +LONGEST Block is:1 Its length is:86 +Added: 1 feed-through cells + +Removed the cell overlaps --- Will do neighbor interchanges only now + +TOTAL INTERCONNECT LENGTH: 994 +OVERLAP PENALTY: 0 + +initialRowControl: 1.650 +finalRowControl: 0.300 +iter T Wire accept + 122 0.001 976 16% + 123 0.001 971 0% + 124 0.001 971 0% +Total Feed-Alignment Movement (Pass 1): 0 +Total Feed-Alignment Movement (Pass 2): 0 +Total Feed-Alignment Movement (Pass 3): 0 +Total Feed-Alignment Movement (Pass 4): 0 +Total Feed-Alignment Movement (Pass 5): 0 +Total Feed-Alignment Movement (Pass 6): 0 +Total Feed-Alignment Movement (Pass 7): 0 +Total Feed-Alignment Movement (Pass 8): 0 + +The rand generator seed was at globroute() : 987654321 + + +Total Number of Net Segments: 9 +Number of Switchable Net Segments: 0 + +Number of channels: 3 + + + +THIS IS THE ORIGINAL NUMBER OF TRACKS: 5 + + +no. of accepted flips: 0 +no. of attempted flips: 0 +THIS IS THE NUMBER OF TRACKS: 5 + + + +FINAL NUMBER OF ROUTING TRACKS: 5 + +MAX OF CHANNEL: 1 is: 0 +MAX OF CHANNEL: 2 is: 4 +MAX OF CHANNEL: 3 is: 1 +FINAL TOTAL INTERCONNECT LENGTH: 978 +FINAL OVERLAP PENALTY: 0 FINAL VALUE OF TOTAL COST IS: 978 +MAX NUMBER OF ATTEMPTED FLIPS PER T: 55 + + +cost_scale_factor:3.90616 + +Number of Feed Thrus: 0 +Number of Implicit Feed Thrus: 0 + +Statistics: +Number of Standard Cells: 10 +Number of Pads: 0 +Number of Nets: 15 +Number of Pins: 46 +Usage statistics not available diff --git a/tests/long/70.twolf/ref/arm/linux/simple-atomic/stats.txt b/tests/long/70.twolf/ref/arm/linux/simple-atomic/stats.txt index a560430fc..bbc7121bd 100644 --- a/tests/long/70.twolf/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/70.twolf/ref/arm/linux/simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1749088 # Simulator instruction rate (inst/s) -host_mem_usage 249684 # Number of bytes of host memory used -host_seconds 107.87 # Real time elapsed on the host -host_tick_rate 955856938 # Simulator tick rate (ticks/s) +host_inst_rate 1042149 # Simulator instruction rate (inst/s) +host_mem_usage 250372 # Number of bytes of host memory used +host_seconds 181.04 # Real time elapsed on the host +host_tick_rate 569523249 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 188670900 # Number of instructions simulated sim_seconds 0.103107 # Number of seconds simulated @@ -56,18 +56,18 @@ system.cpu.numCycles 206213543 # nu system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.num_busy_cycles 206213543 # Number of busy cycles -system.cpu.num_conditional_control_insts 31909249 # number of instructions that are conditional controls +system.cpu.num_conditional_control_insts 31949383 # number of instructions that are conditional controls system.cpu.num_fp_alu_accesses 1752310 # Number of float alu accesses system.cpu.num_fp_insts 1752310 # number of float instructions system.cpu.num_fp_register_reads 2822225 # number of times the floating registers were read system.cpu.num_fp_register_writes 2378039 # number of times the floating registers were written -system.cpu.num_func_calls 3663001 # number of times a function call or return occured +system.cpu.num_func_calls 3504894 # number of times a function call or return occured system.cpu.num_idle_cycles 0 # Number of idle cycles system.cpu.num_insts 188670900 # Number of instructions executed system.cpu.num_int_alu_accesses 150261055 # Number of integer alu accesses system.cpu.num_int_insts 150261055 # number of integer instructions system.cpu.num_int_register_reads 444541710 # number of times the integer registers were read -system.cpu.num_int_register_writes 181190852 # number of times the integer registers were written +system.cpu.num_int_register_writes 177007633 # number of times the integer registers were written system.cpu.num_load_insts 29849485 # Number of load instructions system.cpu.num_mem_refs 42494120 # number of memory refs system.cpu.num_store_insts 12644635 # Number of store instructions diff --git a/tests/long/70.twolf/ref/arm/linux/simple-timing/config.ini b/tests/long/70.twolf/ref/arm/linux/simple-timing/config.ini index 21861df0c..0ecbfede5 100644 --- a/tests/long/70.twolf/ref/arm/linux/simple-timing/config.ini +++ b/tests/long/70.twolf/ref/arm/linux/simple-timing/config.ini @@ -164,7 +164,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=twolf smred -cwd=build/ARM_SE/tests/fast/long/70.twolf/arm/linux/simple-timing +cwd=build/ARM_SE/tests/opt/long/70.twolf/arm/linux/simple-timing egid=100 env= errout=cerr diff --git a/tests/long/70.twolf/ref/arm/linux/simple-timing/simerr b/tests/long/70.twolf/ref/arm/linux/simple-timing/simerr index 83ecbdfc0..eabe42249 100755 --- a/tests/long/70.twolf/ref/arm/linux/simple-timing/simerr +++ b/tests/long/70.twolf/ref/arm/linux/simple-timing/simerr @@ -1,13 +1,3 @@ warn: Sockets disabled, not accepting gdb connections For more information see: http://www.m5sim.org/warn/d946bea6 -warn: Complete acc isn't called on normal stores in O3. -For more information see: http://www.m5sim.org/warn/138d8573 -warn: Complete acc isn't called on normal stores in O3. -For more information see: http://www.m5sim.org/warn/138d8573 -warn: Complete acc isn't called on normal stores in O3. -For more information see: http://www.m5sim.org/warn/138d8573 -warn: Complete acc isn't called on normal stores in O3. -For more information see: http://www.m5sim.org/warn/138d8573 -warn: Complete acc isn't called on normal stores in O3. -For more information see: http://www.m5sim.org/warn/138d8573 hack: be nice to actually delete the event here diff --git a/tests/long/70.twolf/ref/arm/linux/simple-timing/simout b/tests/long/70.twolf/ref/arm/linux/simple-timing/simout index 40c466e50..9ae12354c 100755 --- a/tests/long/70.twolf/ref/arm/linux/simple-timing/simout +++ b/tests/long/70.twolf/ref/arm/linux/simple-timing/simout @@ -5,11 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Mar 11 2011 20:10:09 -M5 revision 4decc284606a 8095 default qtip tip ext/update_add_stats.patch -M5 started Mar 11 2011 21:02:08 +M5 compiled Mar 30 2011 17:47:57 +M5 started Mar 30 2011 19:25:36 M5 executing on u200439-lin.austin.arm.com -command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/70.twolf/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/fast/long/70.twolf/arm/linux/simple-timing +command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/70.twolf/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/opt/long/70.twolf/arm/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/70.twolf/ref/arm/linux/simple-timing/smred.out b/tests/long/70.twolf/ref/arm/linux/simple-timing/smred.out new file mode 100644 index 000000000..00387ae5c --- /dev/null +++ b/tests/long/70.twolf/ref/arm/linux/simple-timing/smred.out @@ -0,0 +1,276 @@ + +TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988 +Standard Cell Placement and Global Routing Program +Authors: Carl Sechen, Bill Swartz + Yale University + + +NOTE: Restart file .rs2 not used + +TimberWolf will perform a global route step +rowSep: 1.000000 +feedThruWidth: 4 + +****************** +BLOCK DATA +block:1 desire:85 +block:2 desire:85 +Total Desired Length: 170 +total cell length: 168 +total block length: 168 +block x-span:84 block y-span:78 +implicit feed thru range: -84 +Using default value of bin.penalty.control:1.000000 +numBins automatically set to:5 +binWidth = average_cell_width + 0 sigma= 17 +average_cell_width is:16 +standard deviation of cell length is:23.6305 +TimberWolfSC starting from the beginning + + + +THIS IS THE ROUTE COST OF THE ORIGINAL PLACEMENT: 645 +The number of nets with 1 pin is 4 +The number of nets with 2 pin is 9 +The number of nets with 3 pin is 0 +The number of nets with 4 pin is 2 +The number of nets with 5 pin is 0 +The number of nets with 6 pin is 0 +The number of nets with 7 pin is 0 +The number of nets with 8 pin is 0 +The number of nets with 9 pin is 0 +The number of nets with 10 pin or more is 0 + +New Cost Function: Initial Horizontal Cost:242 +New Cost Function: FEEDS:0 MISSING_ROWS:-46 + +bdxlen:86 bdylen:78 +l:0 t:78 r:86 b:0 + + + +THIS IS THE ROUTE COST OF THE CURRENT PLACEMENT: 645 + + + +THIS IS THE PENALTY OF THE CURRENT PLACEMENT: 44 + +The rand generator seed was at utemp() : 1 + + + tempfile[0][0] = 0.982500 tempfile[0][1] = 90.000000 + tempfile[1][0] = 0.915000 tempfile[1][1] = 20.000000 + tempfile[2][0] = 0.700000 tempfile[2][1] = 10.000000 + tempfile[3][0] = 0.100000 tempfile[3][1] = 0.000000 + + I T fds Wire Penalty P_lim Epct binC rowC acc s/p early FDs MRs + 1 500 0 929 592 160 30.0 1.0 3.0 84.2 34.7 0.0 0 40 + 2 491 0 876 106 726 0.0 0.8 2.5 80.0 18.5 0.0 0 46 + 3 482 0 822 273 372 0.0 0.5 1.5 80.8 21.2 0.0 0 46 + 4 474 0 826 53 247 0.0 0.5 0.9 65.0 21.9 0.0 0 48 + 5 465 8 987 73 190 0.0 0.5 0.5 50.0 38.3 0.0 0 46 + 6 457 8 851 67 226 0.0 0.5 0.5 53.8 42.9 0.0 0 52 + 7 449 8 1067 108 190 0.0 0.5 0.5 46.2 53.8 0.0 0 50 + 8 441 8 918 106 171 0.0 0.5 0.5 47.1 40.4 0.0 0 48 + 9 434 8 812 101 197 0.0 0.5 0.5 53.6 21.0 0.0 0 48 + 10 426 8 1038 121 181 0.0 0.5 0.5 43.6 27.1 0.0 0 48 + 11 419 8 898 93 187 0.0 0.5 0.5 45.3 47.8 0.0 0 50 + 12 411 4 857 94 240 0.0 0.5 0.5 62.7 51.6 0.0 0 44 + 13 404 8 1043 88 185 0.0 0.5 0.5 54.0 52.8 0.0 0 50 + 14 397 8 767 94 154 0.0 0.5 0.5 33.8 35.0 0.0 0 50 + 15 390 8 862 89 183 0.0 0.5 0.5 55.6 29.0 0.0 0 46 + 16 383 4 798 79 173 0.0 0.5 0.5 57.5 35.3 0.0 0 52 + 17 376 8 827 100 152 0.0 0.5 0.5 35.3 81.8 0.0 0 50 + 18 370 8 878 101 208 0.0 0.5 0.5 44.7 46.2 0.0 0 48 + 19 363 4 921 67 167 0.0 0.5 0.5 57.1 34.7 0.0 0 48 + 20 357 8 933 93 154 0.0 0.5 0.5 46.5 43.6 0.0 0 52 + 21 351 8 930 89 147 0.0 0.5 0.5 39.4 36.5 0.0 0 52 + 22 345 8 951 79 142 0.0 0.5 0.5 32.8 51.3 0.0 0 50 + 23 339 8 1046 87 207 0.0 0.5 0.5 52.8 61.0 0.0 0 48 + 24 333 4 989 96 185 0.0 0.5 0.5 45.3 43.3 0.0 0 42 + 25 327 4 577 86 157 0.0 0.5 0.5 31.1 55.3 0.0 0 52 + 26 321 8 776 97 174 0.0 0.5 0.5 47.9 62.5 0.0 0 52 + 27 315 8 850 81 188 0.0 0.5 0.5 45.0 55.2 0.0 0 50 + 28 310 8 898 97 148 0.0 0.5 0.5 43.0 45.8 0.0 0 48 + 29 304 8 889 65 173 0.0 0.5 0.5 32.5 41.3 0.0 0 50 + 30 299 8 858 81 153 0.0 0.5 0.5 44.3 29.2 0.0 0 46 + 31 294 8 871 82 187 0.0 0.5 0.5 45.7 47.7 0.0 0 48 + 32 289 8 782 109 173 0.0 0.5 0.5 35.2 57.4 0.0 0 48 + 33 284 8 743 98 189 0.0 0.6 0.5 41.8 64.3 0.0 0 52 + 34 279 8 943 90 147 0.0 0.5 0.5 38.6 32.8 0.0 0 48 + 35 274 8 907 57 166 0.0 0.5 0.5 33.6 51.0 0.0 0 48 + 36 269 8 900 70 148 0.0 0.5 0.5 45.0 41.4 0.0 0 50 + 37 264 4 875 106 133 0.0 0.5 0.5 31.7 55.3 0.0 0 52 + 38 260 8 1023 145 149 0.0 0.6 0.5 28.7 65.0 0.0 0 52 + 39 255 8 801 151 173 0.0 0.9 0.5 41.7 41.2 0.0 0 48 + 40 251 8 741 104 159 0.0 0.8 0.5 36.2 47.5 0.0 0 48 + 41 246 8 828 108 149 0.0 0.5 0.5 34.6 50.9 0.0 0 50 + 42 242 8 947 128 132 0.0 0.7 0.5 34.2 39.0 0.0 0 50 + 43 238 8 917 101 142 0.0 0.8 0.5 34.4 50.9 0.0 0 48 + 44 234 8 761 86 129 0.0 0.5 0.5 42.0 36.4 0.0 0 52 + 45 229 8 979 106 137 0.0 0.5 0.5 29.2 55.3 0.0 0 50 + 46 225 8 806 74 130 0.0 0.7 0.5 33.1 65.4 0.0 0 52 + 47 221 8 971 125 114 0.0 0.5 0.5 31.9 45.6 0.0 0 52 + 48 218 8 869 125 104 0.0 0.9 0.5 30.0 56.0 0.0 0 48 + 49 214 8 999 153 140 0.0 0.8 0.5 30.4 46.4 0.0 0 52 + 50 210 8 798 192 139 0.0 1.0 0.5 28.9 50.0 0.0 0 52 + 51 206 8 860 125 157 0.0 1.2 0.5 31.5 26.9 0.0 0 52 + 52 203 8 893 186 127 5.9 0.9 0.5 26.4 42.3 0.0 0 46 + 53 199 8 863 126 141 0.0 1.2 0.5 32.5 44.4 0.0 0 44 + 54 196 8 788 97 133 0.0 0.9 0.5 37.5 40.0 0.0 0 50 + 55 192 8 926 119 116 0.0 0.6 0.5 26.1 55.3 0.0 0 52 + 56 189 8 789 162 107 0.0 0.8 0.5 25.2 40.4 0.0 0 48 + 57 186 8 878 107 128 0.0 1.1 0.5 23.1 34.0 0.0 0 52 + 58 182 8 775 105 122 0.0 0.8 0.5 25.5 57.4 0.0 0 50 + 59 179 8 747 94 129 0.0 0.7 0.5 34.3 37.3 0.0 0 50 + 60 176 8 845 96 138 0.0 0.6 0.5 28.3 41.7 0.0 0 52 + 61 173 8 961 121 110 0.0 0.6 0.5 29.0 52.6 0.0 0 48 + 62 170 4 911 110 109 0.0 0.9 0.5 33.5 33.3 0.0 0 48 + 63 167 8 656 109 109 0.0 0.8 0.5 21.9 44.7 0.0 0 52 + 64 164 8 934 117 105 0.0 0.8 0.5 15.5 50.0 0.0 0 52 + 65 161 8 972 125 95 0.0 0.8 0.5 24.4 50.0 0.0 0 50 + 66 158 8 894 125 101 0.0 0.9 0.5 27.2 35.9 0.0 0 52 + 67 155 8 798 146 129 0.0 1.0 0.5 22.8 58.7 0.0 0 52 + 68 153 8 901 183 92 0.0 1.1 0.5 23.6 34.5 0.0 0 52 + 69 150 8 977 197 103 0.0 1.4 0.5 23.6 36.8 0.0 0 52 + 70 147 8 905 262 93 0.0 1.5 0.5 20.3 63.4 0.0 0 52 + 71 145 8 995 148 122 0.0 1.9 0.5 20.9 35.3 0.0 0 52 + 72 142 8 934 230 99 0.0 1.6 0.5 20.0 65.9 0.0 0 52 + 73 140 8 862 173 100 0.0 1.8 0.5 26.8 46.8 0.0 0 52 + 74 137 8 924 139 90 0.0 1.7 0.5 16.8 42.5 0.0 0 52 + 75 135 8 888 168 113 0.0 1.6 0.5 22.9 40.4 0.0 0 52 + 76 133 8 712 212 84 0.0 1.6 0.5 13.4 46.9 0.0 0 52 + 77 130 8 868 210 91 0.0 1.7 0.5 17.7 51.2 0.0 0 52 + 78 128 8 952 307 92 0.0 1.9 0.5 19.7 44.9 0.0 0 50 + 79 126 8 801 157 107 0.0 2.2 0.5 15.8 39.0 0.0 0 52 + 80 123 8 849 147 93 0.0 2.1 0.5 15.6 51.4 0.0 0 52 + 81 121 8 799 154 86 0.0 1.9 0.5 12.2 50.0 0.0 0 52 + 82 119 8 941 213 82 0.0 1.8 0.5 19.5 41.2 0.0 0 50 + 83 117 8 751 268 94 0.0 2.0 0.5 20.8 42.6 0.0 0 50 + 84 115 8 828 198 102 0.0 2.2 0.5 15.5 59.5 0.0 0 52 + 85 113 8 898 266 123 0.0 2.2 0.5 13.2 85.2 0.0 0 52 + 86 111 8 943 190 93 0.0 2.4 0.5 19.5 45.1 0.0 0 52 + 87 109 8 864 183 65 0.0 2.4 0.5 14.9 31.8 0.0 0 52 + 88 107 8 793 203 93 0.0 2.4 0.5 11.8 35.3 0.0 0 52 + 89 105 8 752 162 74 1.2 2.4 0.5 13.1 21.4 0.0 0 52 + 90 103 8 801 149 77 0.0 2.3 0.5 9.7 58.3 0.0 0 52 + 91 102 8 901 230 99 0.0 2.2 0.5 16.0 25.5 0.0 0 52 + 92 100 8 826 201 87 0.0 2.4 0.5 12.8 45.7 0.0 0 52 + 93 98 8 810 196 83 0.0 2.5 0.5 14.0 24.4 0.0 0 52 + 94 96 8 857 209 68 1.0 2.5 0.5 11.5 27.0 5.1 0 52 + 95 95 8 771 174 91 0.0 2.6 0.5 10.5 26.5 0.0 0 52 + 96 93 8 955 210 59 0.0 2.6 0.5 10.0 36.7 0.7 0 52 + 97 91 8 833 206 53 0.0 2.7 0.5 10.2 19.4 1.4 0 52 + 98 90 8 888 229 86 0.0 2.8 0.5 8.1 36.0 0.0 0 52 + 99 88 8 794 186 91 1.0 2.9 0.5 8.3 25.0 0.5 0 52 +100 81 8 756 170 72 1.0 2.9 0.5 6.0 23.8 7.0 0 52 +101 74 8 791 176 67 0.0 2.9 0.5 4.4 58.3 4.0 0 52 +102 67 8 813 213 43 0.0 3.0 0.5 7.0 150.0 4.2 0 52 +103 62 8 779 245 39 0.0 3.1 0.5 3.2 16.7 13.0 0 52 +104 56 8 767 303 63 0.0 3.2 0.5 4.1 20.0 0.7 0 52 +105 52 8 757 270 57 0.0 3.5 0.5 6.4 3.7 0.5 0 52 +106 47 8 763 283 41 0.0 3.7 0.5 4.5 0.0 0.0 0 52 +107 43 8 768 283 36 0.0 3.7 0.5 2.9 18.2 3.6 0 52 +108 39 8 804 283 25 0.0 3.7 0.5 3.1 0.0 6.2 0 52 +109 36 8 781 283 24 0.0 3.7 0.5 3.6 6.7 6.7 0 52 +110 33 8 738 298 42 0.0 3.7 0.5 3.3 15.4 3.5 0 52 +111 30 8 761 298 36 0.0 3.7 0.5 2.2 0.0 4.3 0 52 +112 27 8 769 298 37 0.0 3.7 0.5 0.9 0.0 2.2 0 52 +113 25 8 745 298 31 0.0 3.7 0.5 1.5 0.0 6.6 0 52 +114 23 8 753 298 16 0.0 3.7 0.5 1.3 0.0 2.8 0 52 +115 21 8 745 298 11 0.0 3.7 0.5 1.5 0.0 14.0 0 52 +116 19 8 747 298 21 0.0 3.7 0.5 2.1 0.0 5.8 0 52 +117 13 8 737 298 12 0.0 3.7 0.5 1.0 0.0 10.0 0 52 +118 9 8 736 298 4 0.0 3.7 0.5 1.5 0.0 18.5 0 52 +119 0 8 739 298 0 0.0 3.7 0.5 1.8 0.0 18.0 0 52 +120 0 8 732 298 0 0.0 3.7 0.5 1.2 0.0 21.8 0 52 +121 0 8 732 19 -1 0.0 0.0 0.5 0.0 100.0 54.8 + +Initial Wiring Cost: 645 Final Wiring Cost: 732 +############## Percent Wire Cost Reduction: -13 + + +Initial Wire Length: 645 Final Wire Length: 732 +************** Percent Wire Length Reduction: -13 + + +Initial Horiz. Wire: 216 Final Horiz. Wire: 147 +$$$$$$$$$$$ Percent H-Wire Length Reduction: 32 + + +Initial Vert. Wire: 429 Final Vert. Wire: 585 +@@@@@@@@@@@ Percent V-Wire Length Reduction: -36 + +Before Feeds are Added: +BLOCK TOTAL CELL LENGTHS OVER/UNDER TARGET + 1 82 -20 + 2 86 -16 + +LONGEST Block is:2 Its length is:86 +BLOCK TOTAL CELL LENGTHS OVER/UNDER TARGET + 1 86 -16 + 2 86 -16 + +LONGEST Block is:1 Its length is:86 +Added: 1 feed-through cells + +Removed the cell overlaps --- Will do neighbor interchanges only now + +TOTAL INTERCONNECT LENGTH: 994 +OVERLAP PENALTY: 0 + +initialRowControl: 1.650 +finalRowControl: 0.300 +iter T Wire accept + 122 0.001 976 16% + 123 0.001 971 0% + 124 0.001 971 0% +Total Feed-Alignment Movement (Pass 1): 0 +Total Feed-Alignment Movement (Pass 2): 0 +Total Feed-Alignment Movement (Pass 3): 0 +Total Feed-Alignment Movement (Pass 4): 0 +Total Feed-Alignment Movement (Pass 5): 0 +Total Feed-Alignment Movement (Pass 6): 0 +Total Feed-Alignment Movement (Pass 7): 0 +Total Feed-Alignment Movement (Pass 8): 0 + +The rand generator seed was at globroute() : 987654321 + + +Total Number of Net Segments: 9 +Number of Switchable Net Segments: 0 + +Number of channels: 3 + + + +THIS IS THE ORIGINAL NUMBER OF TRACKS: 5 + + +no. of accepted flips: 0 +no. of attempted flips: 0 +THIS IS THE NUMBER OF TRACKS: 5 + + + +FINAL NUMBER OF ROUTING TRACKS: 5 + +MAX OF CHANNEL: 1 is: 0 +MAX OF CHANNEL: 2 is: 4 +MAX OF CHANNEL: 3 is: 1 +FINAL TOTAL INTERCONNECT LENGTH: 978 +FINAL OVERLAP PENALTY: 0 FINAL VALUE OF TOTAL COST IS: 978 +MAX NUMBER OF ATTEMPTED FLIPS PER T: 55 + + +cost_scale_factor:3.90616 + +Number of Feed Thrus: 0 +Number of Implicit Feed Thrus: 0 + +Statistics: +Number of Standard Cells: 10 +Number of Pads: 0 +Number of Nets: 15 +Number of Pins: 46 +Usage statistics not available diff --git a/tests/long/70.twolf/ref/arm/linux/simple-timing/stats.txt b/tests/long/70.twolf/ref/arm/linux/simple-timing/stats.txt index 630ae5fa6..1ea8a3c3d 100644 --- a/tests/long/70.twolf/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/70.twolf/ref/arm/linux/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 793653 # Simulator instruction rate (inst/s) -host_mem_usage 257372 # Number of bytes of host memory used -host_seconds 237.11 # Real time elapsed on the host -host_tick_rate 978757790 # Simulator tick rate (ticks/s) +host_inst_rate 569972 # Simulator instruction rate (inst/s) +host_mem_usage 258100 # Number of bytes of host memory used +host_seconds 330.17 # Real time elapsed on the host +host_tick_rate 702907358 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 188185929 # Number of instructions simulated sim_seconds 0.232077 # Number of seconds simulated @@ -249,18 +249,18 @@ system.cpu.numCycles 464154308 # nu system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.num_busy_cycles 464154308 # Number of busy cycles -system.cpu.num_conditional_control_insts 31909249 # number of instructions that are conditional controls +system.cpu.num_conditional_control_insts 31949383 # number of instructions that are conditional controls system.cpu.num_fp_alu_accesses 1752310 # Number of float alu accesses system.cpu.num_fp_insts 1752310 # number of float instructions system.cpu.num_fp_register_reads 2822225 # number of times the floating registers were read system.cpu.num_fp_register_writes 2378039 # number of times the floating registers were written -system.cpu.num_func_calls 3663001 # number of times a function call or return occured +system.cpu.num_func_calls 3504894 # number of times a function call or return occured system.cpu.num_idle_cycles 0 # Number of idle cycles system.cpu.num_insts 188185929 # Number of instructions executed system.cpu.num_int_alu_accesses 150261055 # Number of integer alu accesses system.cpu.num_int_insts 150261055 # number of integer instructions system.cpu.num_int_register_reads 474507625 # number of times the integer registers were read -system.cpu.num_int_register_writes 181422710 # number of times the integer registers were written +system.cpu.num_int_register_writes 177007633 # number of times the integer registers were written system.cpu.num_load_insts 29849485 # Number of load instructions system.cpu.num_mem_refs 42494120 # number of memory refs system.cpu.num_store_insts 12644635 # Number of store instructions |