diff options
Diffstat (limited to 'tests/long')
230 files changed, 2770 insertions, 816 deletions
diff --git a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini index ed1344dd3..41c6a83e0 100644 --- a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini @@ -1,13 +1,22 @@ [root] type=Root children=system -dummy=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem mem_mode=atomic physmem=system.physmem +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 [system.cpu] type=DerivO3CPU diff --git a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout index a359bdb55..5ab603e64 100755 --- a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jan 17 2011 16:24:53 -M5 revision f72d94f8c275 7839 default qtip tip outgoing.patch qbase -M5 started Jan 17 2011 16:40:29 -M5 executing on zizzer +M5 compiled Feb 7 2011 01:47:18 +M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip +M5 started Feb 7 2011 01:47:50 +M5 executing on burrito command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt index 240486239..9ddf470e4 100644 --- a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 207877 # Simulator instruction rate (inst/s) -host_mem_usage 206352 # Number of bytes of host memory used -host_seconds 2720.61 # Real time elapsed on the host -host_tick_rate 59832123 # Simulator tick rate (ticks/s) +host_inst_rate 121046 # Simulator instruction rate (inst/s) +host_mem_usage 226784 # Number of bytes of host memory used +host_seconds 4672.20 # Real time elapsed on the host +host_tick_rate 34840083 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 565552443 # Number of instructions simulated sim_seconds 0.162780 # Number of seconds simulated @@ -37,6 +37,9 @@ system.cpu.commit.COM:committed_per_cycle::min_value 0 system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::total 315794082 # Number of insts commited each cycle system.cpu.commit.COM:count 601856963 # Number of instructions committed +system.cpu.commit.COM:fp_insts 1520 # Number of committed floating point instructions. +system.cpu.commit.COM:function_calls 1197610 # Number of function calls committed. +system.cpu.commit.COM:int_insts 563954763 # Number of committed integer instructions. system.cpu.commit.COM:loads 114514042 # Number of loads committed system.cpu.commit.COM:membars 0 # Number of memory barriers committed system.cpu.commit.COM:refs 153965363 # Number of memory references committed @@ -171,6 +174,8 @@ system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Nu system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::total 325492829 # Number of instructions fetched each cycle (Total) +system.cpu.fp_regfile_reads 265 # number of floating regfile reads +system.cpu.fp_regfile_writes 58 # number of floating regfile writes system.cpu.icache.ReadReq_accesses 65560315 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_avg_miss_latency 36252.118644 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 35514.835165 # average ReadReq mshr miss latency @@ -270,6 +275,8 @@ system.cpu.iew.lsq.thread.0.squashedStores 3177577 # system.cpu.iew.memOrderViolationEvents 70243 # Number of memory order violations system.cpu.iew.predictedNotTakenIncorrect 943658 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedTakenIncorrect 3659139 # Number of branches that were predicted taken incorrectly +system.cpu.int_regfile_reads 844691087 # number of integer regfile reads +system.cpu.int_regfile_writes 489153092 # number of integer regfile writes system.cpu.ipc 1.737170 # IPC: Instructions Per Cycle system.cpu.ipc_total 1.737170 # IPC: Total IPC of All Threads system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued @@ -361,6 +368,14 @@ system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::total 325492829 # Number of insts issued each cycle system.cpu.iq.ISSUE:rate 1.859166 # Inst issue rate +system.cpu.iq.fp_alu_accesses 1679 # Number of floating point alu accesses +system.cpu.iq.fp_inst_queue_reads 3330 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_wakeup_accesses 1605 # Number of floating instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_writes 1800 # Number of floating instruction queue writes +system.cpu.iq.int_alu_accesses 612363224 # Number of integer alu accesses +system.cpu.iq.int_inst_queue_reads 1543136462 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_wakeup_accesses 595804344 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_writes 671661588 # Number of integer instruction queue writes system.cpu.iq.iqInstsAdded 619293624 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqInstsIssued 605269413 # Number of instructions issued system.cpu.iq.iqNonSpecInstsAdded 25 # Number of non-speculative instructions added to the IQ @@ -457,7 +472,11 @@ system.cpu.memDep0.conflictingLoads 17165638 # Nu system.cpu.memDep0.conflictingStores 12779208 # Number of conflicting stores. system.cpu.memDep0.insertedLoads 126095826 # Number of loads inserted to the mem dependence unit. system.cpu.memDep0.insertedStores 42628898 # Number of stores inserted to the mem dependence unit. +system.cpu.misc_regfile_reads 1 # number of misc regfile reads +system.cpu.misc_regfile_writes 1 # number of misc regfile writes system.cpu.numCycles 325559560 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.rename.RENAME:BlockCycles 12578826 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 463854889 # Number of HB maps that are committed system.cpu.rename.RENAME:IQFullEvents 31670463 # Number of times rename has blocked due to IQ full @@ -471,10 +490,14 @@ system.cpu.rename.RENAME:RunCycles 115552585 # Nu system.cpu.rename.RENAME:SquashCycles 9698747 # Number of cycles rename is squashing system.cpu.rename.RENAME:UnblockCycles 37704265 # Number of cycles rename is unblocking system.cpu.rename.RENAME:UndoneMaps 54254608 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:fp_rename_lookups 1958 # Number of floating rename lookups +system.cpu.rename.RENAME:int_rename_lookups 894826947 # Number of integer rename lookups system.cpu.rename.RENAME:serializeStallCycles 531 # count of cycles rename stalled for serializing inst system.cpu.rename.RENAME:serializingInsts 30 # count of serializing insts renamed system.cpu.rename.RENAME:skidInsts 73685603 # count of insts added to the skid buffer system.cpu.rename.RENAME:tempSerializingInsts 29 # count of temporary serializing insts renamed +system.cpu.rob.rob_reads 958179178 # The number of ROB reads +system.cpu.rob.rob_writes 1334457472 # The number of ROB writes system.cpu.timesIdled 2072 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 17 # Number of system calls diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/config.ini index d0f6032a2..355960d42 100644 --- a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/config.ini +++ b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/config.ini @@ -1,13 +1,22 @@ [root] type=Root children=system -dummy=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem mem_mode=atomic physmem=system.physmem +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 [system.cpu] type=AtomicSimpleCPU @@ -57,7 +66,7 @@ egid=100 env= errout=cerr euid=100 -executable=/chips/pd/randd/dist/cpu2000/binaries/alpha/tru64/gzip +executable=/dist/m5/cpu2000/binaries/alpha/tru64/gzip gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/simerr b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/simerr index 67f69f09d..79a2396a6 100755 --- a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/simerr +++ b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/simerr @@ -1,5 +1,11 @@ warn: Sockets disabled, not accepting gdb connections For more information see: http://www.m5sim.org/warn/d946bea6 +warn: Prefetch instrutions is Alpha do not do anything +For more information see: http://www.m5sim.org/warn/3e0eccba +warn: Prefetch instrutions is Alpha do not do anything +For more information see: http://www.m5sim.org/warn/3e0eccba +warn: Prefetch instrutions is Alpha do not do anything +For more information see: http://www.m5sim.org/warn/3e0eccba warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...) For more information see: http://www.m5sim.org/warn/5c5b547f hack: be nice to actually delete the event here diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/simout b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/simout index 635701ab6..b96d561c3 100755 --- a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/simout +++ b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/simout @@ -1,5 +1,3 @@ -Redirecting stdout to build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-atomic/simout -Redirecting stderr to build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-atomic/simerr M5 Simulator System Copyright (c) 2001-2008 @@ -7,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Nov 2 2010 21:30:55 -M5 revision 0af3760102ec+ 7713+ default qtip ext/alpha_prefetch.patch tip -M5 started Nov 2 2010 21:31:02 -M5 executing on aus-bc2-b15 +M5 compiled Feb 7 2011 01:47:18 +M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip +M5 started Feb 7 2011 01:47:37 +M5 executing on burrito command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stats.txt index 739ca9c21..4dfa82a45 100644 --- a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stats.txt +++ b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 6224890 # Simulator instruction rate (inst/s) -host_mem_usage 232016 # Number of bytes of host memory used -host_seconds 96.69 # Real time elapsed on the host -host_tick_rate 3112463113 # Simulator tick rate (ticks/s) +host_inst_rate 1697811 # Simulator instruction rate (inst/s) +host_mem_usage 218112 # Number of bytes of host memory used +host_seconds 354.49 # Real time elapsed on the host +host_tick_rate 848911876 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 601856964 # Number of instructions simulated sim_seconds 0.300931 # Number of seconds simulated @@ -43,8 +43,24 @@ system.cpu.itb.write_hits 0 # DT system.cpu.itb.write_misses 0 # DTB write misses system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.numCycles 601861917 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.num_busy_cycles 601861917 # Number of busy cycles +system.cpu.num_conditional_control_insts 58554292 # number of instructions that are conditional controls +system.cpu.num_fp_alu_accesses 1520 # Number of float alu accesses +system.cpu.num_fp_insts 1520 # number of float instructions +system.cpu.num_fp_register_reads 169 # number of times the floating registers were read +system.cpu.num_fp_register_writes 42 # number of times the floating registers were written +system.cpu.num_func_calls 2395217 # number of times a function call or return occured +system.cpu.num_idle_cycles 0 # Number of idle cycles system.cpu.num_insts 601856964 # Number of instructions executed -system.cpu.num_refs 153970296 # Number of memory references +system.cpu.num_int_alu_accesses 563959696 # Number of integer alu accesses +system.cpu.num_int_insts 563959696 # number of integer instructions +system.cpu.num_int_register_reads 801088993 # number of times the integer registers were read +system.cpu.num_int_register_writes 463854847 # number of times the integer registers were written +system.cpu.num_load_insts 114516673 # Number of load instructions +system.cpu.num_mem_refs 153970296 # number of memory refs +system.cpu.num_store_insts 39453623 # Number of store instructions system.cpu.workload.PROG:num_syscalls 17 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini index 6ed9b214f..5dbdc6426 100644 --- a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini @@ -1,13 +1,22 @@ [root] type=Root children=system -dummy=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem mem_mode=atomic physmem=system.physmem +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 [system.cpu] type=TimingSimpleCPU @@ -157,7 +166,7 @@ egid=100 env= errout=cerr euid=100 -executable=/chips/pd/randd/dist/cpu2000/binaries/alpha/tru64/gzip +executable=/dist/m5/cpu2000/binaries/alpha/tru64/gzip gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/simerr b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/simerr index 67f69f09d..79a2396a6 100755 --- a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/simerr +++ b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/simerr @@ -1,5 +1,11 @@ warn: Sockets disabled, not accepting gdb connections For more information see: http://www.m5sim.org/warn/d946bea6 +warn: Prefetch instrutions is Alpha do not do anything +For more information see: http://www.m5sim.org/warn/3e0eccba +warn: Prefetch instrutions is Alpha do not do anything +For more information see: http://www.m5sim.org/warn/3e0eccba +warn: Prefetch instrutions is Alpha do not do anything +For more information see: http://www.m5sim.org/warn/3e0eccba warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...) For more information see: http://www.m5sim.org/warn/5c5b547f hack: be nice to actually delete the event here diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/simout b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/simout index 15443bcd3..5133de4f2 100755 --- a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/simout +++ b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/simout @@ -1,5 +1,3 @@ -Redirecting stdout to build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-timing/simout -Redirecting stderr to build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-timing/simerr M5 Simulator System Copyright (c) 2001-2008 @@ -7,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Nov 2 2010 21:30:55 -M5 revision 0af3760102ec+ 7713+ default qtip ext/alpha_prefetch.patch tip -M5 started Nov 2 2010 21:44:32 -M5 executing on aus-bc2-b15 +M5 compiled Feb 7 2011 01:47:18 +M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip +M5 started Feb 7 2011 01:47:36 +M5 executing on burrito command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/stats.txt index d095a4f5f..0f44a109b 100644 --- a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 2723974 # Simulator instruction rate (inst/s) -host_mem_usage 239668 # Number of bytes of host memory used -host_seconds 220.95 # Real time elapsed on the host -host_tick_rate 3465167347 # Simulator tick rate (ticks/s) +host_inst_rate 591495 # Simulator instruction rate (inst/s) +host_mem_usage 225828 # Number of bytes of host memory used +host_seconds 1017.52 # Real time elapsed on the host +host_tick_rate 752441266 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 601856964 # Number of instructions simulated sim_seconds 0.765623 # Number of seconds simulated @@ -232,8 +232,24 @@ system.cpu.l2cache.warmup_cycle 0 # Cy system.cpu.l2cache.writebacks 59341 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.numCycles 1531246064 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.num_busy_cycles 1531246064 # Number of busy cycles +system.cpu.num_conditional_control_insts 58554292 # number of instructions that are conditional controls +system.cpu.num_fp_alu_accesses 1520 # Number of float alu accesses +system.cpu.num_fp_insts 1520 # number of float instructions +system.cpu.num_fp_register_reads 169 # number of times the floating registers were read +system.cpu.num_fp_register_writes 42 # number of times the floating registers were written +system.cpu.num_func_calls 2395217 # number of times a function call or return occured +system.cpu.num_idle_cycles 0 # Number of idle cycles system.cpu.num_insts 601856964 # Number of instructions executed -system.cpu.num_refs 153970296 # Number of memory references +system.cpu.num_int_alu_accesses 563959696 # Number of integer alu accesses +system.cpu.num_int_insts 563959696 # number of integer instructions +system.cpu.num_int_register_reads 801088993 # number of times the integer registers were read +system.cpu.num_int_register_writes 463854847 # number of times the integer registers were written +system.cpu.num_load_insts 114516673 # Number of load instructions +system.cpu.num_mem_refs 153970296 # number of memory refs +system.cpu.num_store_insts 39453623 # Number of store instructions system.cpu.workload.PROG:num_syscalls 17 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/00.gzip/ref/arm/linux/o3-timing/config.ini b/tests/long/00.gzip/ref/arm/linux/o3-timing/config.ini index 1ca0fc2d1..b2393d69d 100644 --- a/tests/long/00.gzip/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/00.gzip/ref/arm/linux/o3-timing/config.ini @@ -1,13 +1,22 @@ [root] type=Root children=system -dummy=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem mem_mode=atomic physmem=system.physmem +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 [system.cpu] type=DerivO3CPU @@ -484,7 +493,7 @@ egid=100 env= errout=cerr euid=100 -executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/gzip +executable=/dist/m5/cpu2000/binaries/arm/linux/gzip gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/00.gzip/ref/arm/linux/o3-timing/simout b/tests/long/00.gzip/ref/arm/linux/o3-timing/simout index 913163576..c00731590 100755 --- a/tests/long/00.gzip/ref/arm/linux/o3-timing/simout +++ b/tests/long/00.gzip/ref/arm/linux/o3-timing/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jan 11 2011 18:16:01 -M5 revision b39a8457b332 7816 default ext/o3_regressions.patch qtip tip -M5 started Jan 12 2011 02:01:01 -M5 executing on u200439-lin.austin.arm.com +M5 compiled Feb 7 2011 01:56:16 +M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip +M5 started Feb 7 2011 01:59:50 +M5 executing on burrito command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/00.gzip/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/fast/long/00.gzip/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/00.gzip/ref/arm/linux/o3-timing/stats.txt b/tests/long/00.gzip/ref/arm/linux/o3-timing/stats.txt index c8f41239c..3c92d3925 100644 --- a/tests/long/00.gzip/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/00.gzip/ref/arm/linux/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 117336 # Simulator instruction rate (inst/s) -host_mem_usage 251760 # Number of bytes of host memory used -host_seconds 5118.46 # Real time elapsed on the host -host_tick_rate 42393313 # Simulator tick rate (ticks/s) +host_inst_rate 115233 # Simulator instruction rate (inst/s) +host_mem_usage 238284 # Number of bytes of host memory used +host_seconds 5211.87 # Real time elapsed on the host +host_tick_rate 41633525 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 600581394 # Number of instructions simulated sim_seconds 0.216988 # Number of seconds simulated @@ -37,6 +37,9 @@ system.cpu.commit.COM:committed_per_cycle::min_value 0 system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::total 415629341 # Number of insts commited each cycle system.cpu.commit.COM:count 600581394 # Number of instructions committed +system.cpu.commit.COM:fp_insts 16 # Number of committed floating point instructions. +system.cpu.commit.COM:function_calls 0 # Number of function calls committed. +system.cpu.commit.COM:int_insts 531746837 # Number of committed integer instructions. system.cpu.commit.COM:loads 148953025 # Number of loads committed system.cpu.commit.COM:membars 0 # Number of memory barriers committed system.cpu.commit.COM:refs 219174038 # Number of memory references committed @@ -171,6 +174,7 @@ system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Nu system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::total 433097730 # Number of instructions fetched each cycle (Total) +system.cpu.fp_regfile_reads 16 # number of floating regfile reads system.cpu.icache.ReadReq_accesses 75163464 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_avg_miss_latency 35391.803279 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 34026.104418 # average ReadReq mshr miss latency @@ -270,6 +274,8 @@ system.cpu.iew.lsq.thread.0.squashedStores 18357789 # system.cpu.iew.memOrderViolationEvents 927620 # Number of memory order violations system.cpu.iew.predictedNotTakenIncorrect 1456086 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedTakenIncorrect 3807013 # Number of branches that were predicted taken incorrectly +system.cpu.int_regfile_reads 1741733302 # number of integer regfile reads +system.cpu.int_regfile_writes 500762065 # number of integer regfile writes system.cpu.ipc 1.383903 # IPC: Instructions Per Cycle system.cpu.ipc_total 1.383903 # IPC: Total IPC of All Threads system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued @@ -361,6 +367,14 @@ system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::total 433097730 # Number of insts issued each cycle system.cpu.iq.ISSUE:rate 1.505667 # Inst issue rate +system.cpu.iq.fp_alu_accesses 20 # Number of floating point alu accesses +system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_writes 16 # Number of floating instruction queue writes +system.cpu.iq.int_alu_accesses 661113885 # Number of integer alu accesses +system.cpu.iq.int_inst_queue_reads 1748261718 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_wakeup_accesses 638555076 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_writes 843800706 # Number of integer instruction queue writes system.cpu.iq.iqInstsAdded 721925689 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqInstsIssued 653424127 # Number of instructions issued system.cpu.iq.iqNonSpecInstsAdded 3886 # Number of non-speculative instructions added to the IQ @@ -470,7 +484,11 @@ system.cpu.memDep0.conflictingLoads 56143840 # Nu system.cpu.memDep0.conflictingStores 33466008 # Number of conflicting stores. system.cpu.memDep0.insertedLoads 184696678 # Number of loads inserted to the mem dependence unit. system.cpu.memDep0.insertedStores 88578802 # Number of stores inserted to the mem dependence unit. +system.cpu.misc_regfile_reads 960863166 # number of misc regfile reads +system.cpu.misc_regfile_writes 9367 # number of misc regfile writes system.cpu.numCycles 433976628 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.rename.RENAME:BlockCycles 12394432 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 469246940 # Number of HB maps that are committed system.cpu.rename.RENAME:IQFullEvents 63310884 # Number of times rename has blocked due to IQ full @@ -484,10 +502,14 @@ system.cpu.rename.RENAME:RunCycles 140765492 # Nu system.cpu.rename.RENAME:SquashCycles 17468389 # Number of cycles rename is squashing system.cpu.rename.RENAME:UnblockCycles 71980169 # Number of cycles rename is unblocking system.cpu.rename.RENAME:UndoneMaps 110388314 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:fp_rename_lookups 96 # Number of floating rename lookups +system.cpu.rename.RENAME:int_rename_lookups 2146132242 # Number of integer rename lookups system.cpu.rename.RENAME:serializeStallCycles 56297 # count of cycles rename stalled for serializing inst system.cpu.rename.RENAME:serializingInsts 3959 # count of serializing insts renamed system.cpu.rename.RENAME:skidInsts 128598467 # count of insts added to the skid buffer system.cpu.rename.RENAME:tempSerializingInsts 3953 # count of temporary serializing insts renamed +system.cpu.rob.rob_reads 1130322956 # The number of ROB reads +system.cpu.rob.rob_writes 1461347493 # The number of ROB writes system.cpu.timesIdled 36486 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 48 # Number of system calls diff --git a/tests/long/00.gzip/ref/arm/linux/simple-atomic/config.ini b/tests/long/00.gzip/ref/arm/linux/simple-atomic/config.ini index 04cb6159a..17d38a039 100644 --- a/tests/long/00.gzip/ref/arm/linux/simple-atomic/config.ini +++ b/tests/long/00.gzip/ref/arm/linux/simple-atomic/config.ini @@ -1,13 +1,22 @@ [root] type=Root children=system -dummy=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem mem_mode=atomic physmem=system.physmem +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 [system.cpu] type=AtomicSimpleCPU @@ -52,12 +61,12 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=gzip input.log 1 -cwd=build/ARM_SE/tests/opt/long/00.gzip/arm/linux/simple-atomic +cwd=build/ARM_SE/tests/fast/long/00.gzip/arm/linux/simple-atomic egid=100 env= errout=cerr euid=100 -executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/gzip +executable=/dist/m5/cpu2000/binaries/arm/linux/gzip gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/00.gzip/ref/arm/linux/simple-atomic/simout b/tests/long/00.gzip/ref/arm/linux/simple-atomic/simout index dea298989..f425b3c91 100755 --- a/tests/long/00.gzip/ref/arm/linux/simple-atomic/simout +++ b/tests/long/00.gzip/ref/arm/linux/simple-atomic/simout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Oct 11 2010 18:37:23 -M5 revision c4e3d74d9a68 7726 default ext/mp_boot.patch qtip tip -M5 started Oct 11 2010 19:16:15 -M5 executing on aus-bc3-b4 -command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/00.gzip/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/opt/long/00.gzip/arm/linux/simple-atomic +M5 compiled Feb 7 2011 01:56:16 +M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip +M5 started Feb 7 2011 02:00:03 +M5 executing on burrito +command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/00.gzip/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/fast/long/00.gzip/arm/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... spec_init diff --git a/tests/long/00.gzip/ref/arm/linux/simple-atomic/stats.txt b/tests/long/00.gzip/ref/arm/linux/simple-atomic/stats.txt index 6361eb760..fb68d0899 100644 --- a/tests/long/00.gzip/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/00.gzip/ref/arm/linux/simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 2821771 # Simulator instruction rate (inst/s) -host_mem_usage 253968 # Number of bytes of host memory used -host_seconds 212.84 # Real time elapsed on the host -host_tick_rate 1410937507 # Simulator tick rate (ticks/s) +host_inst_rate 1026292 # Simulator instruction rate (inst/s) +host_mem_usage 229344 # Number of bytes of host memory used +host_seconds 585.20 # Real time elapsed on the host +host_tick_rate 513165203 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 600581394 # Number of instructions simulated sim_seconds 0.300302 # Number of seconds simulated @@ -53,8 +53,24 @@ system.cpu.itb.write_hits 0 # DT system.cpu.itb.write_misses 0 # DTB write misses system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.numCycles 600604284 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.num_busy_cycles 600604284 # Number of busy cycles +system.cpu.num_conditional_control_insts 0 # number of instructions that are conditional controls +system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses +system.cpu.num_fp_insts 16 # number of float instructions +system.cpu.num_fp_register_reads 16 # number of times the floating registers were read +system.cpu.num_fp_register_writes 0 # number of times the floating registers were written +system.cpu.num_func_calls 0 # number of times a function call or return occured +system.cpu.num_idle_cycles 0 # Number of idle cycles system.cpu.num_insts 600581394 # Number of instructions executed -system.cpu.num_refs 219174038 # Number of memory references +system.cpu.num_int_alu_accesses 531746837 # Number of integer alu accesses +system.cpu.num_int_insts 531746837 # number of integer instructions +system.cpu.num_int_register_reads 1690709529 # number of times the integer registers were read +system.cpu.num_int_register_writes 456307392 # number of times the integer registers were written +system.cpu.num_load_insts 148953025 # Number of load instructions +system.cpu.num_mem_refs 219174038 # number of memory refs +system.cpu.num_store_insts 70221013 # Number of store instructions system.cpu.workload.PROG:num_syscalls 48 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/00.gzip/ref/arm/linux/simple-timing/config.ini b/tests/long/00.gzip/ref/arm/linux/simple-timing/config.ini index 36e9f985b..de769cd56 100644 --- a/tests/long/00.gzip/ref/arm/linux/simple-timing/config.ini +++ b/tests/long/00.gzip/ref/arm/linux/simple-timing/config.ini @@ -1,13 +1,22 @@ [root] type=Root children=system -dummy=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem mem_mode=atomic physmem=system.physmem +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 [system.cpu] type=TimingSimpleCPU @@ -152,12 +161,12 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=gzip input.log 1 -cwd=build/ARM_SE/tests/opt/long/00.gzip/arm/linux/simple-timing +cwd=build/ARM_SE/tests/fast/long/00.gzip/arm/linux/simple-timing egid=100 env= errout=cerr euid=100 -executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/gzip +executable=/dist/m5/cpu2000/binaries/arm/linux/gzip gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/00.gzip/ref/arm/linux/simple-timing/simerr b/tests/long/00.gzip/ref/arm/linux/simple-timing/simerr index eabe42249..c1c8fcec5 100755 --- a/tests/long/00.gzip/ref/arm/linux/simple-timing/simerr +++ b/tests/long/00.gzip/ref/arm/linux/simple-timing/simerr @@ -1,3 +1,7 @@ warn: Sockets disabled, not accepting gdb connections For more information see: http://www.m5sim.org/warn/d946bea6 +warn: Complete acc isn't called on normal stores in O3. +For more information see: http://www.m5sim.org/warn/138d8573 +warn: Complete acc isn't called on normal stores in O3. +For more information see: http://www.m5sim.org/warn/138d8573 hack: be nice to actually delete the event here diff --git a/tests/long/00.gzip/ref/arm/linux/simple-timing/simout b/tests/long/00.gzip/ref/arm/linux/simple-timing/simout index 38b916fc4..70559ac7d 100755 --- a/tests/long/00.gzip/ref/arm/linux/simple-timing/simout +++ b/tests/long/00.gzip/ref/arm/linux/simple-timing/simout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Oct 11 2010 18:37:23 -M5 revision c4e3d74d9a68 7726 default ext/mp_boot.patch qtip tip -M5 started Oct 11 2010 18:44:50 -M5 executing on aus-bc3-b4 -command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/00.gzip/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/opt/long/00.gzip/arm/linux/simple-timing +M5 compiled Feb 7 2011 01:56:16 +M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip +M5 started Feb 7 2011 01:56:25 +M5 executing on burrito +command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/00.gzip/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/fast/long/00.gzip/arm/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... spec_init diff --git a/tests/long/00.gzip/ref/arm/linux/simple-timing/stats.txt b/tests/long/00.gzip/ref/arm/linux/simple-timing/stats.txt index 8e10bdbf4..2b5fb88ae 100644 --- a/tests/long/00.gzip/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/00.gzip/ref/arm/linux/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 652561 # Simulator instruction rate (inst/s) -host_mem_usage 261720 # Number of bytes of host memory used -host_seconds 917.34 # Real time elapsed on the host -host_tick_rate 868554806 # Simulator tick rate (ticks/s) +host_inst_rate 452045 # Simulator instruction rate (inst/s) +host_mem_usage 237056 # Number of bytes of host memory used +host_seconds 1324.25 # Real time elapsed on the host +host_tick_rate 601669731 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 598619824 # Number of instructions simulated sim_seconds 0.796760 # Number of seconds simulated @@ -242,8 +242,24 @@ system.cpu.l2cache.warmup_cycle 0 # Cy system.cpu.l2cache.writebacks 57886 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.numCycles 1593519872 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.num_busy_cycles 1593519872 # Number of busy cycles +system.cpu.num_conditional_control_insts 0 # number of instructions that are conditional controls +system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses +system.cpu.num_fp_insts 16 # number of float instructions +system.cpu.num_fp_register_reads 16 # number of times the floating registers were read +system.cpu.num_fp_register_writes 0 # number of times the floating registers were written +system.cpu.num_func_calls 0 # number of times a function call or return occured +system.cpu.num_idle_cycles 0 # Number of idle cycles system.cpu.num_insts 598619824 # Number of instructions executed -system.cpu.num_refs 219174038 # Number of memory references +system.cpu.num_int_alu_accesses 531746837 # Number of integer alu accesses +system.cpu.num_int_insts 531746837 # number of integer instructions +system.cpu.num_int_register_reads 1837343724 # number of times the integer registers were read +system.cpu.num_int_register_writes 456308029 # number of times the integer registers were written +system.cpu.num_load_insts 148953025 # Number of load instructions +system.cpu.num_mem_refs 219174038 # number of memory refs +system.cpu.num_store_insts 70221013 # Number of store instructions system.cpu.workload.PROG:num_syscalls 48 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini b/tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini index 02ce84b2d..239140dc5 100644 --- a/tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini +++ b/tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini @@ -1,13 +1,22 @@ [root] type=Root children=system -dummy=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem mem_mode=atomic physmem=system.physmem +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 [system.cpu] type=DerivO3CPU diff --git a/tests/long/00.gzip/ref/sparc/linux/o3-timing/simout b/tests/long/00.gzip/ref/sparc/linux/o3-timing/simout index df93e233e..44a2a20b1 100755 --- a/tests/long/00.gzip/ref/sparc/linux/o3-timing/simout +++ b/tests/long/00.gzip/ref/sparc/linux/o3-timing/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jan 17 2011 21:17:52 -M5 revision f72d94f8c275 7839 default qtip tip outgoing.patch qbase -M5 started Jan 17 2011 21:17:55 -M5 executing on zizzer +M5 compiled Feb 7 2011 02:13:30 +M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip +M5 started Feb 7 2011 02:13:36 +M5 executing on burrito command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/o3-timing -re tests/run.py build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt b/tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt index c2bc04472..2fc2b1f97 100644 --- a/tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt +++ b/tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 144426 # Simulator instruction rate (inst/s) -host_mem_usage 207996 # Number of bytes of host memory used -host_seconds 9732.45 # Real time elapsed on the host -host_tick_rate 61799305 # Simulator tick rate (ticks/s) +host_inst_rate 165526 # Simulator instruction rate (inst/s) +host_mem_usage 228372 # Number of bytes of host memory used +host_seconds 8491.76 # Real time elapsed on the host +host_tick_rate 70828550 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1405604152 # Number of instructions simulated sim_seconds 0.601459 # Number of seconds simulated @@ -37,6 +37,9 @@ system.cpu.commit.COM:committed_per_cycle::min_value 0 system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::total 1172142071 # Number of insts commited each cycle system.cpu.commit.COM:count 1489523295 # Number of instructions committed +system.cpu.commit.COM:fp_insts 8452036 # Number of committed floating point instructions. +system.cpu.commit.COM:function_calls 0 # Number of function calls committed. +system.cpu.commit.COM:int_insts 1319476388 # Number of committed integer instructions. system.cpu.commit.COM:loads 402512844 # Number of loads committed system.cpu.commit.COM:membars 51356 # Number of memory barriers committed system.cpu.commit.COM:refs 569360986 # Number of memory references committed @@ -160,6 +163,8 @@ system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Nu system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::total 1202551977 # Number of instructions fetched each cycle (Total) +system.cpu.fp_regfile_reads 16952700 # number of floating regfile reads +system.cpu.fp_regfile_writes 10422320 # number of floating regfile writes system.cpu.icache.ReadReq_accesses 173097327 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_avg_miss_latency 35070.194986 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 35059.073359 # average ReadReq mshr miss latency @@ -259,6 +264,8 @@ system.cpu.iew.lsq.thread.0.squashedStores 21427986 # system.cpu.iew.memOrderViolationEvents 832421 # Number of memory order violations system.cpu.iew.predictedNotTakenIncorrect 648481 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedTakenIncorrect 4876062 # Number of branches that were predicted taken incorrectly +system.cpu.int_regfile_reads 1994642284 # number of integer regfile reads +system.cpu.int_regfile_writes 1296237136 # number of integer regfile writes system.cpu.ipc 1.168496 # IPC: Instructions Per Cycle system.cpu.ipc_total 1.168496 # IPC: Total IPC of All Threads system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued @@ -350,6 +357,14 @@ system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::total 1202551977 # Number of insts issued each cycle system.cpu.iq.ISSUE:rate 1.231945 # Inst issue rate +system.cpu.iq.fp_alu_accesses 9139758 # Number of floating point alu accesses +system.cpu.iq.fp_inst_queue_reads 17716192 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_wakeup_accesses 8503894 # Number of floating instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_writes 9202883 # Number of floating instruction queue writes +system.cpu.iq.int_alu_accesses 1476034706 # Number of integer alu accesses +system.cpu.iq.int_inst_queue_reads 4152007639 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_wakeup_accesses 1463994823 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_writes 1798910142 # Number of integer instruction queue writes system.cpu.iq.iqInstsAdded 1603626285 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqInstsIssued 1481928851 # Number of instructions issued system.cpu.iq.iqNonSpecInstsAdded 3075919 # Number of non-speculative instructions added to the IQ @@ -430,7 +445,11 @@ system.cpu.memDep0.conflictingLoads 406523724 # Nu system.cpu.memDep0.conflictingStores 165663867 # Number of conflicting stores. system.cpu.memDep0.insertedLoads 468104279 # Number of loads inserted to the mem dependence unit. system.cpu.memDep0.insertedStores 188276128 # Number of stores inserted to the mem dependence unit. +system.cpu.misc_regfile_reads 596285867 # number of misc regfile reads +system.cpu.misc_regfile_writes 2258933 # number of misc regfile writes system.cpu.numCycles 1202917849 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.rename.RENAME:BlockCycles 123850519 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 1244770452 # Number of HB maps that are committed system.cpu.rename.RENAME:FullRegisterEvents 28358883 # Number of times there has been no free registers @@ -445,10 +464,14 @@ system.cpu.rename.RENAME:RunCycles 329588798 # Nu system.cpu.rename.RENAME:SquashCycles 30410517 # Number of cycles rename is squashing system.cpu.rename.RENAME:UnblockCycles 217220436 # Number of cycles rename is unblocking system.cpu.rename.RENAME:UndoneMaps 200424116 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:fp_rename_lookups 33734828 # Number of floating rename lookups +system.cpu.rename.RENAME:int_rename_lookups 2890766205 # Number of integer rename lookups system.cpu.rename.RENAME:serializeStallCycles 57780774 # count of cycles rename stalled for serializing inst system.cpu.rename.RENAME:serializingInsts 3037077 # count of serializing insts renamed system.cpu.rename.RENAME:skidInsts 385267398 # count of insts added to the skid buffer system.cpu.rename.RENAME:tempSerializingInsts 3036332 # count of temporary serializing insts renamed +system.cpu.rob.rob_reads 2859629611 # The number of ROB reads +system.cpu.rob.rob_writes 3448202738 # The number of ROB writes system.cpu.timesIdled 11390 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 49 # Number of system calls diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-atomic/config.ini b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/config.ini index 25252561e..0b3b6266f 100644 --- a/tests/long/00.gzip/ref/sparc/linux/simple-atomic/config.ini +++ b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/config.ini @@ -1,13 +1,22 @@ [root] type=Root children=system -dummy=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem mem_mode=atomic physmem=system.physmem +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 [system.cpu] type=AtomicSimpleCPU @@ -57,7 +66,7 @@ egid=100 env= errout=cerr euid=100 -executable=/proj/aatl_perfmod_arch/m5_binaries/cpu2000/binaries/sparc/linux/gzip +executable=/dist/m5/cpu2000/binaries/sparc/linux/gzip gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-atomic/simout b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/simout index c99734c27..4748a164d 100755 --- a/tests/long/00.gzip/ref/sparc/linux/simple-atomic/simout +++ b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 25 2010 03:11:27 -M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip -M5 started Feb 25 2010 03:19:07 -M5 executing on SC2B0619 +M5 compiled Feb 7 2011 02:13:30 +M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip +M5 started Feb 7 2011 02:14:57 +M5 executing on burrito command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-atomic -re tests/run.py build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-atomic/stats.txt b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/stats.txt index d04149323..16c920737 100644 --- a/tests/long/00.gzip/ref/sparc/linux/simple-atomic/stats.txt +++ b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1748575 # Simulator instruction rate (inst/s) -host_mem_usage 185740 # Number of bytes of host memory used -host_seconds 851.85 # Real time elapsed on the host -host_tick_rate 874289976 # Simulator tick rate (ticks/s) +host_inst_rate 1524596 # Simulator instruction rate (inst/s) +host_mem_usage 219684 # Number of bytes of host memory used +host_seconds 977.00 # Real time elapsed on the host +host_tick_rate 762300416 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1489523295 # Number of instructions simulated sim_seconds 0.744764 # Number of seconds simulated @@ -11,8 +11,24 @@ sim_ticks 744764119000 # Nu system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.numCycles 1489528239 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.num_busy_cycles 1489528239 # Number of busy cycles +system.cpu.num_conditional_control_insts 0 # number of instructions that are conditional controls +system.cpu.num_fp_alu_accesses 8454127 # Number of float alu accesses +system.cpu.num_fp_insts 8454127 # number of float instructions +system.cpu.num_fp_register_reads 16769332 # number of times the floating registers were read +system.cpu.num_fp_register_writes 10359244 # number of times the floating registers were written +system.cpu.num_func_calls 0 # number of times a function call or return occured +system.cpu.num_idle_cycles 0 # Number of idle cycles system.cpu.num_insts 1489523295 # Number of instructions executed -system.cpu.num_refs 569365767 # Number of memory references +system.cpu.num_int_alu_accesses 1319481298 # Number of integer alu accesses +system.cpu.num_int_insts 1319481298 # number of integer instructions +system.cpu.num_int_register_reads 2499743582 # number of times the integer registers were read +system.cpu.num_int_register_writes 1234411208 # number of times the integer registers were written +system.cpu.num_load_insts 402515346 # Number of load instructions +system.cpu.num_mem_refs 569365767 # number of memory refs +system.cpu.num_store_insts 166850421 # Number of store instructions system.cpu.workload.PROG:num_syscalls 49 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-timing/config.ini b/tests/long/00.gzip/ref/sparc/linux/simple-timing/config.ini index 9772b8626..9789f7d05 100644 --- a/tests/long/00.gzip/ref/sparc/linux/simple-timing/config.ini +++ b/tests/long/00.gzip/ref/sparc/linux/simple-timing/config.ini @@ -1,13 +1,22 @@ [root] type=Root children=system -dummy=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem mem_mode=atomic physmem=system.physmem +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 [system.cpu] type=TimingSimpleCPU @@ -152,12 +161,12 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=gzip input.log 1 -cwd=build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/simple-timing +cwd=build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-timing egid=100 env= errout=cerr euid=100 -executable=/home/stever/m5/dist/cpu2000/binaries/sparc/linux/gzip +executable=/dist/m5/cpu2000/binaries/sparc/linux/gzip gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-timing/simout b/tests/long/00.gzip/ref/sparc/linux/simple-timing/simout index 78e3d8264..f2b4b3e16 100755 --- a/tests/long/00.gzip/ref/sparc/linux/simple-timing/simout +++ b/tests/long/00.gzip/ref/sparc/linux/simple-timing/simout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Sep 20 2010 15:04:49 -M5 revision 0c4a7d867247 7686 default qtip print-identical tip -M5 started Sep 20 2010 16:28:00 -M5 executing on phenom -command line: build/SPARC_SE/m5.opt -d build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/simple-timing +M5 compiled Feb 7 2011 02:13:30 +M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip +M5 started Feb 7 2011 02:13:36 +M5 executing on burrito +command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... spec_init diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-timing/stats.txt b/tests/long/00.gzip/ref/sparc/linux/simple-timing/stats.txt index 04e7c144d..8bc8178fc 100644 --- a/tests/long/00.gzip/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/long/00.gzip/ref/sparc/linux/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1333935 # Simulator instruction rate (inst/s) -host_mem_usage 197236 # Number of bytes of host memory used -host_seconds 1116.64 # Real time elapsed on the host -host_tick_rate 1848636408 # Simulator tick rate (ticks/s) +host_inst_rate 594721 # Simulator instruction rate (inst/s) +host_mem_usage 227400 # Number of bytes of host memory used +host_seconds 2504.58 # Real time elapsed on the host +host_tick_rate 824195004 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1489523295 # Number of instructions simulated sim_seconds 2.064259 # Number of seconds simulated @@ -210,8 +210,24 @@ system.cpu.l2cache.warmup_cycle 0 # Cy system.cpu.l2cache.writebacks 59035 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.numCycles 4128517334 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.num_busy_cycles 4128517334 # Number of busy cycles +system.cpu.num_conditional_control_insts 0 # number of instructions that are conditional controls +system.cpu.num_fp_alu_accesses 8454127 # Number of float alu accesses +system.cpu.num_fp_insts 8454127 # number of float instructions +system.cpu.num_fp_register_reads 16769332 # number of times the floating registers were read +system.cpu.num_fp_register_writes 10359244 # number of times the floating registers were written +system.cpu.num_func_calls 0 # number of times a function call or return occured +system.cpu.num_idle_cycles 0 # Number of idle cycles system.cpu.num_insts 1489523295 # Number of instructions executed -system.cpu.num_refs 569365767 # Number of memory references +system.cpu.num_int_alu_accesses 1319481298 # Number of integer alu accesses +system.cpu.num_int_insts 1319481298 # number of integer instructions +system.cpu.num_int_register_reads 2499743582 # number of times the integer registers were read +system.cpu.num_int_register_writes 1234411207 # number of times the integer registers were written +system.cpu.num_load_insts 402515346 # Number of load instructions +system.cpu.num_mem_refs 569365767 # number of memory refs +system.cpu.num_store_insts 166850421 # Number of store instructions system.cpu.workload.PROG:num_syscalls 49 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/00.gzip/ref/x86/linux/o3-timing/config.ini b/tests/long/00.gzip/ref/x86/linux/o3-timing/config.ini index f7f0c46d4..503c61f1c 100644 --- a/tests/long/00.gzip/ref/x86/linux/o3-timing/config.ini +++ b/tests/long/00.gzip/ref/x86/linux/o3-timing/config.ini @@ -10,6 +10,13 @@ type=System children=cpu membus physmem mem_mode=atomic physmem=system.physmem +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 [system.cpu] type=DerivO3CPU @@ -481,7 +488,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=gzip input.log 1 -cwd=build/X86_SE/tests/opt/long/00.gzip/x86/linux/o3-timing +cwd=build/X86_SE/tests/fast/long/00.gzip/x86/linux/o3-timing egid=100 env= errout=cerr diff --git a/tests/long/00.gzip/ref/x86/linux/o3-timing/simout b/tests/long/00.gzip/ref/x86/linux/o3-timing/simout index f9fa6a62e..3dbb4b0b4 100755 --- a/tests/long/00.gzip/ref/x86/linux/o3-timing/simout +++ b/tests/long/00.gzip/ref/x86/linux/o3-timing/simout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jan 31 2011 16:34:44 -M5 revision 1b98eea40540 7883 default qtip tip x86o3regressions.patch -M5 started Jan 31 2011 16:34:46 +M5 compiled Feb 7 2011 02:32:07 +M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip +M5 started Feb 7 2011 02:32:13 M5 executing on burrito -command line: build/X86_SE/m5.opt -d build/X86_SE/tests/opt/long/00.gzip/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/opt/long/00.gzip/x86/linux/o3-timing +command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/00.gzip/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/fast/long/00.gzip/x86/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... spec_init diff --git a/tests/long/00.gzip/ref/x86/linux/o3-timing/stats.txt b/tests/long/00.gzip/ref/x86/linux/o3-timing/stats.txt index 6441cfabc..05b37528b 100644 --- a/tests/long/00.gzip/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/00.gzip/ref/x86/linux/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 136188 # Simulator instruction rate (inst/s) -host_mem_usage 231788 # Number of bytes of host memory used -host_seconds 11906.26 # Real time elapsed on the host -host_tick_rate 64872637 # Simulator tick rate (ticks/s) +host_inst_rate 168346 # Simulator instruction rate (inst/s) +host_mem_usage 232444 # Number of bytes of host memory used +host_seconds 9631.89 # Real time elapsed on the host +host_tick_rate 80190939 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1621493982 # Number of instructions simulated sim_seconds 0.772390 # Number of seconds simulated @@ -37,6 +37,9 @@ system.cpu.commit.COM:committed_per_cycle::min_value 0 system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::total 1511501895 # Number of insts commited each cycle system.cpu.commit.COM:count 1621493982 # Number of instructions committed +system.cpu.commit.COM:fp_insts 0 # Number of committed floating point instructions. +system.cpu.commit.COM:function_calls 0 # Number of function calls committed. +system.cpu.commit.COM:int_insts 1621354492 # Number of committed integer instructions. system.cpu.commit.COM:loads 419042125 # Number of loads committed system.cpu.commit.COM:membars 0 # Number of memory barriers committed system.cpu.commit.COM:refs 607228182 # Number of memory references committed @@ -150,6 +153,7 @@ system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Nu system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::total 1544565042 # Number of instructions fetched each cycle (Total) +system.cpu.fp_regfile_reads 2 # number of floating regfile reads system.cpu.icache.ReadReq_accesses 119630706 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_avg_miss_latency 37171.926007 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 35433.712121 # average ReadReq mshr miss latency @@ -249,6 +253,8 @@ system.cpu.iew.lsq.thread.0.squashedStores 22026294 # system.cpu.iew.memOrderViolationEvents 3968261 # Number of memory order violations system.cpu.iew.predictedNotTakenIncorrect 2078 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedTakenIncorrect 6120468 # Number of branches that were predicted taken incorrectly +system.cpu.int_regfile_reads 4148897019 # number of integer regfile reads +system.cpu.int_regfile_writes 1677631671 # number of integer regfile writes system.cpu.ipc 1.049659 # IPC: Instructions Per Cycle system.cpu.ipc_total 1.049659 # IPC: Total IPC of All Threads system.cpu.iq.ISSUE:FU_type_0::No_OpClass 24157467 1.43% 1.43% # Type of FU issued @@ -340,6 +346,14 @@ system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::total 1544565042 # Number of insts issued each cycle system.cpu.iq.ISSUE:rate 1.096282 # Inst issue rate +system.cpu.iq.fp_alu_accesses 4 # Number of floating point alu accesses +system.cpu.iq.fp_inst_queue_reads 8 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_wakeup_accesses 2 # Number of floating instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_writes 8 # Number of floating instruction queue writes +system.cpu.iq.int_alu_accesses 1669611057 # Number of integer alu accesses +system.cpu.iq.int_inst_queue_reads 4931850619 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_wakeup_accesses 1680860109 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_writes 2080058032 # Number of integer instruction queue writes system.cpu.iq.iqInstsAdded 1849358797 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqInstsIssued 1693515784 # Number of instructions issued system.cpu.iq.iqNonSpecInstsAdded 66 # Number of non-speculative instructions added to the IQ @@ -420,7 +434,10 @@ system.cpu.memDep0.conflictingLoads 289036318 # Nu system.cpu.memDep0.conflictingStores 113016383 # Number of conflicting stores. system.cpu.memDep0.insertedLoads 492554241 # Number of loads inserted to the mem dependence unit. system.cpu.memDep0.insertedStores 210212351 # Number of stores inserted to the mem dependence unit. +system.cpu.misc_regfile_reads 864820574 # number of misc regfile reads system.cpu.numCycles 1544781000 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.rename.RENAME:BlockCycles 55578139 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 1617994650 # Number of HB maps that are committed system.cpu.rename.RENAME:IQFullEvents 65710608 # Number of times rename has blocked due to IQ full @@ -434,10 +451,14 @@ system.cpu.rename.RENAME:RunCycles 968560202 # Nu system.cpu.rename.RENAME:SquashCycles 33063147 # Number of cycles rename is squashing system.cpu.rename.RENAME:UnblockCycles 126195704 # Number of cycles rename is unblocking system.cpu.rename.RENAME:UndoneMaps 253681708 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:fp_rename_lookups 32 # Number of floating rename lookups +system.cpu.rename.RENAME:int_rename_lookups 5668050349 # Number of integer rename lookups system.cpu.rename.RENAME:serializeStallCycles 2169 # count of cycles rename stalled for serializing inst system.cpu.rename.RENAME:serializingInsts 67 # count of serializing insts renamed system.cpu.rename.RENAME:skidInsts 186996608 # count of insts added to the skid buffer system.cpu.rename.RENAME:tempSerializingInsts 71 # count of temporary serializing insts renamed +system.cpu.rob.rob_reads 3357159543 # The number of ROB reads +system.cpu.rob.rob_writes 3732197477 # The number of ROB writes system.cpu.timesIdled 45108 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 48 # Number of system calls diff --git a/tests/long/00.gzip/ref/x86/linux/simple-atomic/config.ini b/tests/long/00.gzip/ref/x86/linux/simple-atomic/config.ini index 5a8f812f4..6c9d60230 100644 --- a/tests/long/00.gzip/ref/x86/linux/simple-atomic/config.ini +++ b/tests/long/00.gzip/ref/x86/linux/simple-atomic/config.ini @@ -10,6 +10,13 @@ type=System children=cpu membus physmem mem_mode=atomic physmem=system.physmem +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 [system.cpu] type=AtomicSimpleCPU @@ -54,7 +61,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=gzip input.log 1 -cwd=build/X86_SE/tests/opt/long/00.gzip/x86/linux/simple-atomic +cwd=build/X86_SE/tests/fast/long/00.gzip/x86/linux/simple-atomic egid=100 env= errout=cerr diff --git a/tests/long/00.gzip/ref/x86/linux/simple-atomic/simout b/tests/long/00.gzip/ref/x86/linux/simple-atomic/simout index 2cf82dff0..1dd3bb0d2 100755 --- a/tests/long/00.gzip/ref/x86/linux/simple-atomic/simout +++ b/tests/long/00.gzip/ref/x86/linux/simple-atomic/simout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jan 31 2011 14:03:49 -M5 revision aa283c8952a9 7880 default qtip stupdstats.patch tip -M5 started Jan 31 2011 14:03:51 +M5 compiled Feb 7 2011 02:32:07 +M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip +M5 started Feb 7 2011 02:38:48 M5 executing on burrito -command line: build/X86_SE/m5.opt -d build/X86_SE/tests/opt/long/00.gzip/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/opt/long/00.gzip/x86/linux/simple-atomic +command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/00.gzip/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/fast/long/00.gzip/x86/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... spec_init diff --git a/tests/long/00.gzip/ref/x86/linux/simple-atomic/stats.txt b/tests/long/00.gzip/ref/x86/linux/simple-atomic/stats.txt index c7162281a..ce8635d17 100644 --- a/tests/long/00.gzip/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/long/00.gzip/ref/x86/linux/simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1409865 # Simulator instruction rate (inst/s) -host_mem_usage 219780 # Number of bytes of host memory used -host_seconds 1150.11 # Real time elapsed on the host -host_tick_rate 838177430 # Simulator tick rate (ticks/s) +host_inst_rate 1066510 # Simulator instruction rate (inst/s) +host_mem_usage 223440 # Number of bytes of host memory used +host_seconds 1520.37 # Real time elapsed on the host +host_tick_rate 634049597 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1621493983 # Number of instructions simulated sim_seconds 0.963993 # Number of seconds simulated @@ -11,8 +11,24 @@ sim_ticks 963992704000 # Nu system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.numCycles 1927985409 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.num_busy_cycles 1927985409 # Number of busy cycles +system.cpu.num_conditional_control_insts 99478861 # number of instructions that are conditional controls +system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses +system.cpu.num_fp_insts 0 # number of float instructions +system.cpu.num_fp_register_reads 0 # number of times the floating registers were read +system.cpu.num_fp_register_writes 0 # number of times the floating registers were written +system.cpu.num_func_calls 0 # number of times a function call or return occured +system.cpu.num_idle_cycles 0 # Number of idle cycles system.cpu.num_insts 1621493983 # Number of instructions executed -system.cpu.num_refs 607228182 # Number of memory references +system.cpu.num_int_alu_accesses 1621354493 # Number of integer alu accesses +system.cpu.num_int_insts 1621354493 # number of integer instructions +system.cpu.num_int_register_reads 4883555465 # number of times the integer registers were read +system.cpu.num_int_register_writes 1617994650 # number of times the integer registers were written +system.cpu.num_load_insts 419042125 # Number of load instructions +system.cpu.num_mem_refs 607228182 # number of memory refs +system.cpu.num_store_insts 188186057 # Number of store instructions system.cpu.workload.PROG:num_syscalls 48 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/00.gzip/ref/x86/linux/simple-timing/config.ini b/tests/long/00.gzip/ref/x86/linux/simple-timing/config.ini index 56899b979..967d3d328 100644 --- a/tests/long/00.gzip/ref/x86/linux/simple-timing/config.ini +++ b/tests/long/00.gzip/ref/x86/linux/simple-timing/config.ini @@ -10,6 +10,13 @@ type=System children=cpu membus physmem mem_mode=atomic physmem=system.physmem +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 [system.cpu] type=TimingSimpleCPU @@ -154,7 +161,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=gzip input.log 1 -cwd=build/X86_SE/tests/opt/long/00.gzip/x86/linux/simple-timing +cwd=build/X86_SE/tests/fast/long/00.gzip/x86/linux/simple-timing egid=100 env= errout=cerr diff --git a/tests/long/00.gzip/ref/x86/linux/simple-timing/simout b/tests/long/00.gzip/ref/x86/linux/simple-timing/simout index c71548d66..889c6868b 100755 --- a/tests/long/00.gzip/ref/x86/linux/simple-timing/simout +++ b/tests/long/00.gzip/ref/x86/linux/simple-timing/simout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jan 31 2011 14:03:49 -M5 revision aa283c8952a9 7880 default qtip stupdstats.patch tip -M5 started Jan 31 2011 14:03:51 +M5 compiled Feb 7 2011 02:32:07 +M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip +M5 started Feb 7 2011 02:32:35 M5 executing on burrito -command line: build/X86_SE/m5.opt -d build/X86_SE/tests/opt/long/00.gzip/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/opt/long/00.gzip/x86/linux/simple-timing +command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/00.gzip/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/fast/long/00.gzip/x86/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... spec_init diff --git a/tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt b/tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt index 8adfcec1a..46400c920 100644 --- a/tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1099985 # Simulator instruction rate (inst/s) -host_mem_usage 227480 # Number of bytes of host memory used -host_seconds 1474.11 # Real time elapsed on the host -host_tick_rate 1223290364 # Simulator tick rate (ticks/s) +host_inst_rate 685934 # Simulator instruction rate (inst/s) +host_mem_usage 231240 # Number of bytes of host memory used +host_seconds 2363.92 # Real time elapsed on the host +host_tick_rate 762824620 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1621493983 # Number of instructions simulated sim_seconds 1.803259 # Number of seconds simulated @@ -200,8 +200,24 @@ system.cpu.l2cache.warmup_cycle 0 # Cy system.cpu.l2cache.writebacks 58007 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.numCycles 3606517174 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.num_busy_cycles 3606517174 # Number of busy cycles +system.cpu.num_conditional_control_insts 99478861 # number of instructions that are conditional controls +system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses +system.cpu.num_fp_insts 0 # number of float instructions +system.cpu.num_fp_register_reads 0 # number of times the floating registers were read +system.cpu.num_fp_register_writes 0 # number of times the floating registers were written +system.cpu.num_func_calls 0 # number of times a function call or return occured +system.cpu.num_idle_cycles 0 # Number of idle cycles system.cpu.num_insts 1621493983 # Number of instructions executed -system.cpu.num_refs 607228182 # Number of memory references +system.cpu.num_int_alu_accesses 1621354493 # Number of integer alu accesses +system.cpu.num_int_insts 1621354493 # number of integer instructions +system.cpu.num_int_register_reads 4883555465 # number of times the integer registers were read +system.cpu.num_int_register_writes 1617994650 # number of times the integer registers were written +system.cpu.num_load_insts 419042125 # Number of load instructions +system.cpu.num_mem_refs 607228182 # number of memory refs +system.cpu.num_store_insts 188186057 # Number of store instructions system.cpu.workload.PROG:num_syscalls 48 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini index 70f885c82..b96a83286 100644 --- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini @@ -1,7 +1,9 @@ [root] type=Root children=system -dummy=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 [system] type=LinuxAlphaSystem @@ -19,6 +21,13 @@ readfile=tests/halt.sh symbolfile= system_rev=1024 system_type=34 +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 [system.bridge] type=Bridge diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout index 169564b5c..dcb4e3644 100755 --- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jan 17 2011 17:11:38 -M5 revision f72d94f8c275 7839 default qtip tip outgoing.patch qbase -M5 started Jan 17 2011 17:12:29 -M5 executing on zizzer +M5 compiled Feb 7 2011 01:46:17 +M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip +M5 started Feb 7 2011 01:46:32 +M5 executing on burrito command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3-dual -re tests/run.py build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3-dual Global frequency set at 1000000000000 ticks per second info: kernel located at: /dist/m5/system/binaries/vmlinux diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt index cba8f3d91..3a665541f 100644 --- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 123407 # Simulator instruction rate (inst/s) -host_mem_usage 293584 # Number of bytes of host memory used -host_seconds 461.81 # Real time elapsed on the host -host_tick_rate 4116011383 # Simulator tick rate (ticks/s) +host_inst_rate 67358 # Simulator instruction rate (inst/s) +host_mem_usage 313516 # Number of bytes of host memory used +host_seconds 846.09 # Real time elapsed on the host +host_tick_rate 2246601111 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 56990797 # Number of instructions simulated sim_seconds 1.900831 # Number of seconds simulated @@ -37,6 +37,9 @@ system.cpu0.commit.COM:committed_per_cycle::min_value 0 system.cpu0.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle system.cpu0.commit.COM:committed_per_cycle::total 78252168 # Number of insts commited each cycle system.cpu0.commit.COM:count 49773781 # Number of instructions committed +system.cpu0.commit.COM:fp_insts 245595 # Number of committed floating point instructions. +system.cpu0.commit.COM:function_calls 636046 # Number of function calls committed. +system.cpu0.commit.COM:int_insts 46098576 # Number of committed integer instructions. system.cpu0.commit.COM:loads 7894849 # Number of loads committed system.cpu0.commit.COM:membars 191655 # Number of memory barriers committed system.cpu0.commit.COM:refs 13318728 # Number of memory references committed @@ -248,6 +251,8 @@ system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Nu system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::total 79523293 # Number of instructions fetched each cycle (Total) +system.cpu0.fp_regfile_reads 120916 # number of floating regfile reads +system.cpu0.fp_regfile_writes 122710 # number of floating regfile writes system.cpu0.icache.ReadReq_accesses::0 7790772 # number of ReadReq accesses(hits+misses) system.cpu0.icache.ReadReq_accesses::total 7790772 # number of ReadReq accesses(hits+misses) system.cpu0.icache.ReadReq_avg_miss_latency::0 15066.907100 # average ReadReq miss latency @@ -378,6 +383,8 @@ system.cpu0.iew.lsq.thread.0.squashedStores 419501 # system.cpu0.iew.memOrderViolationEvents 38522 # Number of memory order violations system.cpu0.iew.predictedNotTakenIncorrect 332064 # Number of branches that were predicted not taken incorrectly system.cpu0.iew.predictedTakenIncorrect 379789 # Number of branches that were predicted taken incorrectly +system.cpu0.int_regfile_reads 66329266 # number of integer regfile reads +system.cpu0.int_regfile_writes 36276231 # number of integer regfile writes system.cpu0.ipc 0.416037 # IPC: Instructions Per Cycle system.cpu0.ipc_total 0.416037 # IPC: Total IPC of All Threads system.cpu0.iq.ISSUE:FU_type_0::No_OpClass 3762 0.01% 0.01% # Type of FU issued @@ -469,6 +476,14 @@ system.cpu0.iq.ISSUE:issued_per_cycle::min_value 0 system.cpu0.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle system.cpu0.iq.ISSUE:issued_per_cycle::total 79523293 # Number of insts issued each cycle system.cpu0.iq.ISSUE:rate 0.450743 # Inst issue rate +system.cpu0.iq.fp_alu_accesses 260476 # Number of floating point alu accesses +system.cpu0.iq.fp_inst_queue_reads 508189 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_wakeup_accesses 246844 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_writes 251997 # Number of floating instruction queue writes +system.cpu0.iq.int_alu_accesses 50944800 # Number of integer alu accesses +system.cpu0.iq.int_inst_queue_reads 181074941 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_wakeup_accesses 49741828 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.int_inst_queue_writes 60494151 # Number of integer instruction queue writes system.cpu0.iq.iqInstsAdded 52250537 # Number of instructions added to the IQ (excludes non-spec) system.cpu0.iq.iqInstsIssued 50826749 # Number of instructions issued system.cpu0.iq.iqNonSpecInstsAdded 1722211 # Number of non-speculative instructions added to the IQ @@ -584,7 +599,11 @@ system.cpu0.memDep0.conflictingLoads 2324520 # Nu system.cpu0.memDep0.conflictingStores 1920330 # Number of conflicting stores. system.cpu0.memDep0.insertedLoads 9134564 # Number of loads inserted to the mem dependence unit. system.cpu0.memDep0.insertedStores 5843380 # Number of stores inserted to the mem dependence unit. +system.cpu0.misc_regfile_reads 1626369 # number of misc regfile reads +system.cpu0.misc_regfile_writes 787165 # number of misc regfile writes system.cpu0.numCycles 112762027 # number of cpu cycles simulated +system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.rename.RENAME:BlockCycles 12784616 # Number of cycles rename is blocking system.cpu0.rename.RENAME:CommittedMaps 33979042 # Number of HB maps that are committed system.cpu0.rename.RENAME:IQFullEvents 1006695 # Number of times rename has blocked due to IQ full @@ -598,10 +617,14 @@ system.cpu0.rename.RENAME:RunCycles 11035754 # Nu system.cpu0.rename.RENAME:SquashCycles 1271125 # Number of cycles rename is squashing system.cpu0.rename.RENAME:UnblockCycles 3987965 # Number of cycles rename is unblocking system.cpu0.rename.RENAME:UndoneMaps 6000063 # Number of HB maps that are undone due to squashing +system.cpu0.rename.RENAME:fp_rename_lookups 359001 # Number of floating rename lookups +system.cpu0.rename.RENAME:int_rename_lookups 72178524 # Number of integer rename lookups system.cpu0.rename.RENAME:serializeStallCycles 16862175 # count of cycles rename stalled for serializing inst system.cpu0.rename.RENAME:serializingInsts 1393641 # count of serializing insts renamed system.cpu0.rename.RENAME:skidInsts 10087757 # count of insts added to the skid buffer system.cpu0.rename.RENAME:tempSerializingInsts 207582 # count of temporary serializing insts renamed +system.cpu0.rob.rob_reads 134196739 # The number of ROB reads +system.cpu0.rob.rob_writes 115376344 # The number of ROB writes system.cpu0.timesIdled 1187239 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu1.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu1.BPredUnit.BTBHits 1159872 # Number of BTB hits @@ -632,6 +655,9 @@ system.cpu1.commit.COM:committed_per_cycle::min_value 0 system.cpu1.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle system.cpu1.commit.COM:committed_per_cycle::total 17838555 # Number of insts commited each cycle system.cpu1.commit.COM:count 10605058 # Number of instructions committed +system.cpu1.commit.COM:fp_insts 116296 # Number of committed floating point instructions. +system.cpu1.commit.COM:function_calls 166623 # Number of function calls committed. +system.cpu1.commit.COM:int_insts 9814589 # Number of committed integer instructions. system.cpu1.commit.COM:loads 1991974 # Number of loads committed system.cpu1.commit.COM:membars 52733 # Number of memory barriers committed system.cpu1.commit.COM:refs 3376359 # Number of memory references committed @@ -841,6 +867,8 @@ system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Nu system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::total 18144360 # Number of instructions fetched each cycle (Total) +system.cpu1.fp_regfile_reads 63103 # number of floating regfile reads +system.cpu1.fp_regfile_writes 63156 # number of floating regfile writes system.cpu1.icache.ReadReq_accesses::0 1676515 # number of ReadReq accesses(hits+misses) system.cpu1.icache.ReadReq_accesses::total 1676515 # number of ReadReq accesses(hits+misses) system.cpu1.icache.ReadReq_avg_miss_latency::0 14673.731413 # average ReadReq miss latency @@ -971,6 +999,8 @@ system.cpu1.iew.lsq.thread.0.squashedStores 128329 # system.cpu1.iew.memOrderViolationEvents 10653 # Number of memory order violations system.cpu1.iew.predictedNotTakenIncorrect 104816 # Number of branches that were predicted not taken incorrectly system.cpu1.iew.predictedTakenIncorrect 73994 # Number of branches that were predicted taken incorrectly +system.cpu1.int_regfile_reads 13933756 # number of integer regfile reads +system.cpu1.int_regfile_writes 7611585 # number of integer regfile writes system.cpu1.ipc 0.513113 # IPC: Instructions Per Cycle system.cpu1.ipc_total 0.513113 # IPC: Total IPC of All Threads system.cpu1.iq.ISSUE:FU_type_0::No_OpClass 3524 0.03% 0.03% # Type of FU issued @@ -1062,6 +1092,14 @@ system.cpu1.iq.ISSUE:issued_per_cycle::min_value 0 system.cpu1.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle system.cpu1.iq.ISSUE:issued_per_cycle::total 18144360 # Number of insts issued each cycle system.cpu1.iq.ISSUE:rate 0.557524 # Inst issue rate +system.cpu1.iq.fp_alu_accesses 125165 # Number of floating point alu accesses +system.cpu1.iq.fp_inst_queue_reads 243017 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_wakeup_accesses 117535 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_writes 119622 # Number of floating instruction queue writes +system.cpu1.iq.int_alu_accesses 10976050 # Number of integer alu accesses +system.cpu1.iq.int_inst_queue_reads 39966063 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_wakeup_accesses 10617468 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.int_inst_queue_writes 13352810 # Number of integer instruction queue writes system.cpu1.iq.iqInstsAdded 11252421 # Number of instructions added to the IQ (excludes non-spec) system.cpu1.iq.iqInstsIssued 10949829 # Number of instructions issued system.cpu1.iq.iqNonSpecInstsAdded 555783 # Number of non-speculative instructions added to the IQ @@ -1166,7 +1204,11 @@ system.cpu1.memDep0.conflictingLoads 496033 # Nu system.cpu1.memDep0.conflictingStores 413880 # Number of conflicting stores. system.cpu1.memDep0.insertedLoads 2309588 # Number of loads inserted to the mem dependence unit. system.cpu1.memDep0.insertedStores 1512714 # Number of stores inserted to the mem dependence unit. +system.cpu1.misc_regfile_reads 594436 # number of misc regfile reads +system.cpu1.misc_regfile_writes 255211 # number of misc regfile writes system.cpu1.numCycles 19640104 # number of cpu cycles simulated +system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.rename.RENAME:BlockCycles 522822 # Number of cycles rename is blocking system.cpu1.rename.RENAME:CommittedMaps 7159583 # Number of HB maps that are committed system.cpu1.rename.RENAME:IQFullEvents 32718 # Number of times rename has blocked due to IQ full @@ -1180,10 +1222,14 @@ system.cpu1.rename.RENAME:RunCycles 2359874 # Nu system.cpu1.rename.RENAME:SquashCycles 305805 # Number of cycles rename is squashing system.cpu1.rename.RENAME:UnblockCycles 801183 # Number of cycles rename is unblocking system.cpu1.rename.RENAME:UndoneMaps 1329621 # Number of HB maps that are undone due to squashing +system.cpu1.rename.RENAME:fp_rename_lookups 171444 # Number of floating rename lookups +system.cpu1.rename.RENAME:int_rename_lookups 15302029 # Number of integer rename lookups system.cpu1.rename.RENAME:serializeStallCycles 5653749 # count of cycles rename stalled for serializing inst system.cpu1.rename.RENAME:serializingInsts 515468 # count of serializing insts renamed system.cpu1.rename.RENAME:skidInsts 2303190 # count of insts added to the skid buffer system.cpu1.rename.RENAME:tempSerializingInsts 52722 # count of temporary serializing insts renamed +system.cpu1.rob.rob_reads 29861070 # The number of ROB reads +system.cpu1.rob.rob_writes 24957765 # The number of ROB writes system.cpu1.timesIdled 194766 # Number of times that the entire CPU went into an idle state and unscheduled itself system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini index 0ecea254a..838d9a364 100644 --- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini @@ -1,7 +1,9 @@ [root] type=Root children=system -dummy=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 [system] type=LinuxAlphaSystem @@ -19,6 +21,13 @@ readfile=tests/halt.sh symbolfile= system_rev=1024 system_type=34 +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 [system.bridge] type=Bridge diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout index cd15fbaad..bdb8a98f8 100755 --- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jan 17 2011 17:11:38 -M5 revision f72d94f8c275 7839 default qtip tip outgoing.patch qbase -M5 started Jan 17 2011 17:11:41 -M5 executing on zizzer +M5 compiled Feb 7 2011 01:46:17 +M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip +M5 started Feb 7 2011 01:46:32 +M5 executing on burrito command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3 -re tests/run.py build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3 Global frequency set at 1000000000000 ticks per second info: kernel located at: /dist/m5/system/binaries/vmlinux diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt index 549afdb19..e3a6bbb06 100644 --- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 145689 # Simulator instruction rate (inst/s) -host_mem_usage 291364 # Number of bytes of host memory used -host_seconds 364.14 # Real time elapsed on the host -host_tick_rate 5126322811 # Simulator tick rate (ticks/s) +host_inst_rate 66360 # Simulator instruction rate (inst/s) +host_mem_usage 311288 # Number of bytes of host memory used +host_seconds 799.45 # Real time elapsed on the host +host_tick_rate 2334981918 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 53051251 # Number of instructions simulated sim_seconds 1.866703 # Number of seconds simulated @@ -37,6 +37,9 @@ system.cpu.commit.COM:committed_per_cycle::min_value 0 system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::total 89231545 # Number of insts commited each cycle system.cpu.commit.COM:count 56244349 # Number of instructions committed +system.cpu.commit.COM:fp_insts 324384 # Number of committed floating point instructions. +system.cpu.commit.COM:function_calls 744090 # Number of function calls committed. +system.cpu.commit.COM:int_insts 52084301 # Number of committed integer instructions. system.cpu.commit.COM:loads 9107235 # Number of loads committed system.cpu.commit.COM:membars 227951 # Number of memory barriers committed system.cpu.commit.COM:refs 15496318 # Number of memory references committed @@ -246,6 +249,8 @@ system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Nu system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::total 90747041 # Number of instructions fetched each cycle (Total) +system.cpu.fp_regfile_reads 164450 # number of floating regfile reads +system.cpu.fp_regfile_writes 166718 # number of floating regfile writes system.cpu.icache.ReadReq_accesses::0 8856318 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 8856318 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_avg_miss_latency::0 14954.328072 # average ReadReq miss latency @@ -376,6 +381,8 @@ system.cpu.iew.lsq.thread.0.squashedStores 554299 # system.cpu.iew.memOrderViolationEvents 42661 # Number of memory order violations system.cpu.iew.predictedNotTakenIncorrect 406369 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedTakenIncorrect 431404 # Number of branches that were predicted taken incorrectly +system.cpu.int_regfile_reads 74886349 # number of integer regfile reads +system.cpu.int_regfile_writes 40928930 # number of integer regfile writes system.cpu.ipc 0.424064 # IPC: Instructions Per Cycle system.cpu.ipc_total 0.424064 # IPC: Total IPC of All Threads system.cpu.iq.ISSUE:FU_type_0::No_OpClass 7281 0.01% 0.01% # Type of FU issued @@ -467,6 +474,14 @@ system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::total 90747041 # Number of insts issued each cycle system.cpu.iq.ISSUE:rate 0.460931 # Inst issue rate +system.cpu.iq.fp_alu_accesses 341243 # Number of floating point alu accesses +system.cpu.iq.fp_inst_queue_reads 667907 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_wakeup_accesses 325691 # Number of floating instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_writes 334133 # Number of floating instruction queue writes +system.cpu.iq.int_alu_accesses 57747809 # Number of integer alu accesses +system.cpu.iq.int_inst_queue_reads 205867710 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_wakeup_accesses 56371536 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_writes 69251365 # Number of integer instruction queue writes system.cpu.iq.iqInstsAdded 59448706 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqInstsIssued 57663428 # Number of instructions issued system.cpu.iq.iqNonSpecInstsAdded 2039751 # Number of non-speculative instructions added to the IQ @@ -578,7 +593,11 @@ system.cpu.memDep0.conflictingLoads 3018201 # Nu system.cpu.memDep0.conflictingStores 2591237 # Number of conflicting stores. system.cpu.memDep0.insertedLoads 10628246 # Number of loads inserted to the mem dependence unit. system.cpu.memDep0.insertedStores 6943382 # Number of stores inserted to the mem dependence unit. +system.cpu.misc_regfile_reads 1993439 # number of misc regfile reads +system.cpu.misc_regfile_writes 949389 # number of misc regfile writes system.cpu.numCycles 125102122 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.rename.RENAME:BlockCycles 13297534 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 38227478 # Number of HB maps that are committed system.cpu.rename.RENAME:IQFullEvents 1065628 # Number of times rename has blocked due to IQ full @@ -592,10 +611,14 @@ system.cpu.rename.RENAME:RunCycles 12514369 # Nu system.cpu.rename.RENAME:SquashCycles 1515496 # Number of cycles rename is squashing system.cpu.rename.RENAME:UnblockCycles 4654173 # Number of cycles rename is unblocking system.cpu.rename.RENAME:UndoneMaps 7066231 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:fp_rename_lookups 474968 # Number of floating rename lookups +system.cpu.rename.RENAME:int_rename_lookups 81738953 # Number of integer rename lookups system.cpu.rename.RENAME:serializeStallCycles 19705456 # count of cycles rename stalled for serializing inst system.cpu.rename.RENAME:serializingInsts 1694142 # count of serializing insts renamed system.cpu.rename.RENAME:skidInsts 11744700 # count of insts added to the skid buffer system.cpu.rename.RENAME:tempSerializingInsts 247271 # count of temporary serializing insts renamed +system.cpu.rob.rob_reads 152916375 # The number of ROB reads +system.cpu.rob.rob_writes 131403689 # The number of ROB writes system.cpu.timesIdled 1310957 # Number of times that the entire CPU went into an idle state and unscheduled itself system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). diff --git a/tests/long/10.mcf/ref/arm/linux/o3-timing/config.ini b/tests/long/10.mcf/ref/arm/linux/o3-timing/config.ini index 67f0de766..9285fee06 100644 --- a/tests/long/10.mcf/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/10.mcf/ref/arm/linux/o3-timing/config.ini @@ -1,13 +1,22 @@ [root] type=Root children=system -dummy=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem mem_mode=atomic physmem=system.physmem +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 [system.cpu] type=DerivO3CPU @@ -484,9 +493,9 @@ egid=100 env= errout=cerr euid=100 -executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/mcf +executable=/dist/m5/cpu2000/binaries/arm/linux/mcf gid=100 -input=/chips/pd/randd/dist/cpu2000/data/mcf/smred/input/mcf.in +input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in max_stack_size=67108864 output=cout pid=100 diff --git a/tests/long/10.mcf/ref/arm/linux/o3-timing/simout b/tests/long/10.mcf/ref/arm/linux/o3-timing/simout index 43dc1d1fc..591032c8f 100755 --- a/tests/long/10.mcf/ref/arm/linux/o3-timing/simout +++ b/tests/long/10.mcf/ref/arm/linux/o3-timing/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jan 11 2011 18:16:01 -M5 revision b39a8457b332 7816 default ext/o3_regressions.patch qtip tip -M5 started Jan 12 2011 03:03:04 -M5 executing on u200439-lin.austin.arm.com +M5 compiled Feb 7 2011 01:56:16 +M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip +M5 started Feb 7 2011 01:58:27 +M5 executing on burrito command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/10.mcf/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/fast/long/10.mcf/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/10.mcf/ref/arm/linux/o3-timing/stats.txt b/tests/long/10.mcf/ref/arm/linux/o3-timing/stats.txt index 674012633..390072636 100644 --- a/tests/long/10.mcf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/10.mcf/ref/arm/linux/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 109166 # Simulator instruction rate (inst/s) -host_mem_usage 384348 # Number of bytes of host memory used -host_seconds 835.45 # Real time elapsed on the host -host_tick_rate 67095197 # Simulator tick rate (ticks/s) +host_inst_rate 65288 # Simulator instruction rate (inst/s) +host_mem_usage 370872 # Number of bytes of host memory used +host_seconds 1396.92 # Real time elapsed on the host +host_tick_rate 40127232 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 91202735 # Number of instructions simulated sim_seconds 0.056055 # Number of seconds simulated @@ -37,6 +37,9 @@ system.cpu.commit.COM:committed_per_cycle::min_value 0 system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::total 109380669 # Number of insts commited each cycle system.cpu.commit.COM:count 91202735 # Number of instructions committed +system.cpu.commit.COM:fp_insts 48 # Number of committed floating point instructions. +system.cpu.commit.COM:function_calls 0 # Number of function calls committed. +system.cpu.commit.COM:int_insts 72483223 # Number of committed integer instructions. system.cpu.commit.COM:loads 22585492 # Number of loads committed system.cpu.commit.COM:membars 0 # Number of memory barriers committed system.cpu.commit.COM:refs 27330336 # Number of memory references committed @@ -171,6 +174,8 @@ system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Nu system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::total 112077802 # Number of instructions fetched each cycle (Total) +system.cpu.fp_regfile_reads 75 # number of floating regfile reads +system.cpu.fp_regfile_writes 47 # number of floating regfile writes system.cpu.icache.ReadReq_accesses 12683523 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_avg_miss_latency 36326.451613 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 34504.457652 # average ReadReq mshr miss latency @@ -270,6 +275,8 @@ system.cpu.iew.lsq.thread.0.squashedStores 788441 # system.cpu.iew.memOrderViolationEvents 1330 # Number of memory order violations system.cpu.iew.predictedNotTakenIncorrect 76117 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedTakenIncorrect 1979748 # Number of branches that were predicted taken incorrectly +system.cpu.int_regfile_reads 246289928 # number of integer regfile reads +system.cpu.int_regfile_writes 76222702 # number of integer regfile writes system.cpu.ipc 0.813516 # IPC: Instructions Per Cycle system.cpu.ipc_total 0.813516 # IPC: Total IPC of All Threads system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued @@ -361,6 +368,14 @@ system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::total 112077802 # Number of insts issued each cycle system.cpu.iq.ISSUE:rate 0.888775 # Inst issue rate +system.cpu.iq.fp_alu_accesses 74 # Number of floating point alu accesses +system.cpu.iq.fp_inst_queue_reads 144 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_wakeup_accesses 66 # Number of floating instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_writes 98 # Number of floating instruction queue writes +system.cpu.iq.int_alu_accesses 100131195 # Number of integer alu accesses +system.cpu.iq.int_inst_queue_reads 311849254 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_wakeup_accesses 96607706 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_writes 112840034 # Number of integer instruction queue writes system.cpu.iq.iqInstsAdded 102487226 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqInstsIssued 99639939 # Number of instructions issued system.cpu.iq.iqNonSpecInstsAdded 553822 # Number of non-speculative instructions added to the IQ @@ -463,7 +478,11 @@ system.cpu.memDep0.conflictingLoads 436025 # Nu system.cpu.memDep0.conflictingStores 249497 # Number of conflicting stores. system.cpu.memDep0.insertedLoads 24681131 # Number of loads inserted to the mem dependence unit. system.cpu.memDep0.insertedStores 5533285 # Number of stores inserted to the mem dependence unit. +system.cpu.misc_regfile_reads 157552604 # number of misc regfile reads +system.cpu.misc_regfile_writes 1603309 # number of misc regfile writes system.cpu.numCycles 112109302 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.rename.RENAME:BlockCycles 294826 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 72061910 # Number of HB maps that are committed system.cpu.rename.RENAME:IQFullEvents 4906 # Number of times rename has blocked due to IQ full @@ -476,10 +495,14 @@ system.cpu.rename.RENAME:RunCycles 72730212 # Nu system.cpu.rename.RENAME:SquashCycles 2697133 # Number of cycles rename is squashing system.cpu.rename.RENAME:UnblockCycles 723330 # Number of cycles rename is unblocking system.cpu.rename.RENAME:UndoneMaps 11862848 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:fp_rename_lookups 474 # Number of floating rename lookups +system.cpu.rename.RENAME:int_rename_lookups 277458644 # Number of integer rename lookups system.cpu.rename.RENAME:serializeStallCycles 5701177 # count of cycles rename stalled for serializing inst system.cpu.rename.RENAME:serializingInsts 592742 # count of serializing insts renamed system.cpu.rename.RENAME:skidInsts 1065555 # count of insts added to the skid buffer system.cpu.rename.RENAME:tempSerializingInsts 576556 # count of temporary serializing insts renamed +system.cpu.rob.rob_reads 212048427 # The number of ROB reads +system.cpu.rob.rob_writes 208775903 # The number of ROB writes system.cpu.timesIdled 1292 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 442 # Number of system calls diff --git a/tests/long/10.mcf/ref/arm/linux/simple-atomic/config.ini b/tests/long/10.mcf/ref/arm/linux/simple-atomic/config.ini index bfff6943f..a584d29ed 100644 --- a/tests/long/10.mcf/ref/arm/linux/simple-atomic/config.ini +++ b/tests/long/10.mcf/ref/arm/linux/simple-atomic/config.ini @@ -1,13 +1,22 @@ [root] type=Root children=system -dummy=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem mem_mode=atomic physmem=system.physmem +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 [system.cpu] type=AtomicSimpleCPU @@ -52,14 +61,14 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=mcf mcf.in -cwd=build/ARM_SE/tests/opt/long/10.mcf/arm/linux/simple-atomic +cwd=build/ARM_SE/tests/fast/long/10.mcf/arm/linux/simple-atomic egid=100 env= errout=cerr euid=100 -executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/mcf +executable=/dist/m5/cpu2000/binaries/arm/linux/mcf gid=100 -input=/chips/pd/randd/dist/cpu2000/data/mcf/smred/input/mcf.in +input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in max_stack_size=67108864 output=cout pid=100 diff --git a/tests/long/10.mcf/ref/arm/linux/simple-atomic/simout b/tests/long/10.mcf/ref/arm/linux/simple-atomic/simout index d622d0388..34dd3ff53 100755 --- a/tests/long/10.mcf/ref/arm/linux/simple-atomic/simout +++ b/tests/long/10.mcf/ref/arm/linux/simple-atomic/simout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Oct 11 2010 18:37:23 -M5 revision c4e3d74d9a68 7726 default ext/mp_boot.patch qtip tip -M5 started Oct 11 2010 18:40:32 -M5 executing on aus-bc3-b4 -command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/10.mcf/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/opt/long/10.mcf/arm/linux/simple-atomic +M5 compiled Feb 7 2011 01:56:16 +M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip +M5 started Feb 7 2011 01:56:24 +M5 executing on burrito +command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/10.mcf/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/fast/long/10.mcf/arm/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/10.mcf/ref/arm/linux/simple-atomic/stats.txt b/tests/long/10.mcf/ref/arm/linux/simple-atomic/stats.txt index 9bb34897d..0d4b35c47 100644 --- a/tests/long/10.mcf/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/10.mcf/ref/arm/linux/simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 2560594 # Simulator instruction rate (inst/s) -host_mem_usage 386656 # Number of bytes of host memory used -host_seconds 35.62 # Real time elapsed on the host -host_tick_rate 1522136495 # Simulator tick rate (ticks/s) +host_inst_rate 937948 # Simulator instruction rate (inst/s) +host_mem_usage 362060 # Number of bytes of host memory used +host_seconds 97.24 # Real time elapsed on the host +host_tick_rate 557562760 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 91202735 # Number of instructions simulated sim_seconds 0.054216 # Number of seconds simulated @@ -53,8 +53,24 @@ system.cpu.itb.write_hits 0 # DT system.cpu.itb.write_misses 0 # DTB write misses system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.numCycles 108431099 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.num_busy_cycles 108431099 # Number of busy cycles +system.cpu.num_conditional_control_insts 0 # number of instructions that are conditional controls +system.cpu.num_fp_alu_accesses 48 # Number of float alu accesses +system.cpu.num_fp_insts 48 # number of float instructions +system.cpu.num_fp_register_reads 54 # number of times the floating registers were read +system.cpu.num_fp_register_writes 30 # number of times the floating registers were written +system.cpu.num_func_calls 0 # number of times a function call or return occured +system.cpu.num_idle_cycles 0 # Number of idle cycles system.cpu.num_insts 91202735 # Number of instructions executed -system.cpu.num_refs 27330336 # Number of memory references +system.cpu.num_int_alu_accesses 72483223 # Number of integer alu accesses +system.cpu.num_int_insts 72483223 # number of integer instructions +system.cpu.num_int_register_reads 234567931 # number of times the integer registers were read +system.cpu.num_int_register_writes 72546720 # number of times the integer registers were written +system.cpu.num_load_insts 22585492 # Number of load instructions +system.cpu.num_mem_refs 27330336 # number of memory refs +system.cpu.num_store_insts 4744844 # Number of store instructions system.cpu.workload.PROG:num_syscalls 442 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/10.mcf/ref/arm/linux/simple-timing/config.ini b/tests/long/10.mcf/ref/arm/linux/simple-timing/config.ini index d78abde62..d7d6a4868 100644 --- a/tests/long/10.mcf/ref/arm/linux/simple-timing/config.ini +++ b/tests/long/10.mcf/ref/arm/linux/simple-timing/config.ini @@ -1,13 +1,22 @@ [root] type=Root children=system -dummy=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem mem_mode=atomic physmem=system.physmem +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 [system.cpu] type=TimingSimpleCPU @@ -152,14 +161,14 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=mcf mcf.in -cwd=build/ARM_SE/tests/opt/long/10.mcf/arm/linux/simple-timing +cwd=build/ARM_SE/tests/fast/long/10.mcf/arm/linux/simple-timing egid=100 env= errout=cerr euid=100 -executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/mcf +executable=/dist/m5/cpu2000/binaries/arm/linux/mcf gid=100 -input=/chips/pd/randd/dist/cpu2000/data/mcf/smred/input/mcf.in +input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in max_stack_size=67108864 output=cout pid=100 diff --git a/tests/long/10.mcf/ref/arm/linux/simple-timing/simerr b/tests/long/10.mcf/ref/arm/linux/simple-timing/simerr index eabe42249..c1c8fcec5 100755 --- a/tests/long/10.mcf/ref/arm/linux/simple-timing/simerr +++ b/tests/long/10.mcf/ref/arm/linux/simple-timing/simerr @@ -1,3 +1,7 @@ warn: Sockets disabled, not accepting gdb connections For more information see: http://www.m5sim.org/warn/d946bea6 +warn: Complete acc isn't called on normal stores in O3. +For more information see: http://www.m5sim.org/warn/138d8573 +warn: Complete acc isn't called on normal stores in O3. +For more information see: http://www.m5sim.org/warn/138d8573 hack: be nice to actually delete the event here diff --git a/tests/long/10.mcf/ref/arm/linux/simple-timing/simout b/tests/long/10.mcf/ref/arm/linux/simple-timing/simout index c45082899..b290f1d74 100755 --- a/tests/long/10.mcf/ref/arm/linux/simple-timing/simout +++ b/tests/long/10.mcf/ref/arm/linux/simple-timing/simout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Oct 11 2010 18:37:23 -M5 revision c4e3d74d9a68 7726 default ext/mp_boot.patch qtip tip -M5 started Oct 11 2010 18:41:18 -M5 executing on aus-bc3-b4 -command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/10.mcf/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/opt/long/10.mcf/arm/linux/simple-timing +M5 compiled Feb 7 2011 01:56:16 +M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip +M5 started Feb 7 2011 01:56:25 +M5 executing on burrito +command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/10.mcf/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/fast/long/10.mcf/arm/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/10.mcf/ref/arm/linux/simple-timing/stats.txt b/tests/long/10.mcf/ref/arm/linux/simple-timing/stats.txt index bb2ffd900..5c965f81e 100644 --- a/tests/long/10.mcf/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/10.mcf/ref/arm/linux/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 587679 # Simulator instruction rate (inst/s) -host_mem_usage 394372 # Number of bytes of host memory used -host_seconds 155.15 # Real time elapsed on the host -host_tick_rate 954493550 # Simulator tick rate (ticks/s) +host_inst_rate 419592 # Simulator instruction rate (inst/s) +host_mem_usage 369772 # Number of bytes of host memory used +host_seconds 217.30 # Real time elapsed on the host +host_tick_rate 681491064 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 91176087 # Number of instructions simulated sim_seconds 0.148086 # Number of seconds simulated @@ -242,8 +242,24 @@ system.cpu.l2cache.warmup_cycle 0 # Cy system.cpu.l2cache.writebacks 32 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.numCycles 296172438 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.num_busy_cycles 296172438 # Number of busy cycles +system.cpu.num_conditional_control_insts 0 # number of instructions that are conditional controls +system.cpu.num_fp_alu_accesses 48 # Number of float alu accesses +system.cpu.num_fp_insts 48 # number of float instructions +system.cpu.num_fp_register_reads 54 # number of times the floating registers were read +system.cpu.num_fp_register_writes 30 # number of times the floating registers were written +system.cpu.num_func_calls 0 # number of times a function call or return occured +system.cpu.num_idle_cycles 0 # Number of idle cycles system.cpu.num_insts 91176087 # Number of instructions executed -system.cpu.num_refs 27330336 # Number of memory references +system.cpu.num_int_alu_accesses 72483223 # Number of integer alu accesses +system.cpu.num_int_insts 72483223 # number of integer instructions +system.cpu.num_int_register_reads 257112085 # number of times the integer registers were read +system.cpu.num_int_register_writes 72558730 # number of times the integer registers were written +system.cpu.num_load_insts 22585492 # Number of load instructions +system.cpu.num_mem_refs 27330336 # number of memory refs +system.cpu.num_store_insts 4744844 # Number of store instructions system.cpu.workload.PROG:num_syscalls 442 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-atomic/config.ini b/tests/long/10.mcf/ref/sparc/linux/simple-atomic/config.ini index 06fed5d59..164664341 100644 --- a/tests/long/10.mcf/ref/sparc/linux/simple-atomic/config.ini +++ b/tests/long/10.mcf/ref/sparc/linux/simple-atomic/config.ini @@ -1,13 +1,22 @@ [root] type=Root children=system -dummy=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem mem_mode=atomic physmem=system.physmem +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 [system.cpu] type=AtomicSimpleCPU @@ -57,9 +66,9 @@ egid=100 env= errout=cerr euid=100 -executable=/proj/aatl_perfmod_arch/m5_binaries/cpu2000/binaries/sparc/linux/mcf +executable=/dist/m5/cpu2000/binaries/sparc/linux/mcf gid=100 -input=/proj/aatl_perfmod_arch/m5_binaries/cpu2000/data/mcf/smred/input/mcf.in +input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in max_stack_size=67108864 output=cout pid=100 diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-atomic/simout b/tests/long/10.mcf/ref/sparc/linux/simple-atomic/simout index 6c4e0d9c5..a011c886e 100755 --- a/tests/long/10.mcf/ref/sparc/linux/simple-atomic/simout +++ b/tests/long/10.mcf/ref/sparc/linux/simple-atomic/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 25 2010 03:11:27 -M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip -M5 started Feb 25 2010 03:27:41 -M5 executing on SC2B0619 +M5 compiled Feb 7 2011 02:13:30 +M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip +M5 started Feb 7 2011 02:14:01 +M5 executing on burrito command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/10.mcf/sparc/linux/simple-atomic -re tests/run.py build/SPARC_SE/tests/fast/long/10.mcf/sparc/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-atomic/stats.txt b/tests/long/10.mcf/ref/sparc/linux/simple-atomic/stats.txt index 2eefb0962..282686242 100644 --- a/tests/long/10.mcf/ref/sparc/linux/simple-atomic/stats.txt +++ b/tests/long/10.mcf/ref/sparc/linux/simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1458389 # Simulator instruction rate (inst/s) -host_mem_usage 317928 # Number of bytes of host memory used -host_seconds 167.20 # Real time elapsed on the host -host_tick_rate 730976871 # Simulator tick rate (ticks/s) +host_inst_rate 1159873 # Simulator instruction rate (inst/s) +host_mem_usage 351876 # Number of bytes of host memory used +host_seconds 210.23 # Real time elapsed on the host +host_tick_rate 581353978 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 243835278 # Number of instructions simulated sim_seconds 0.122216 # Number of seconds simulated @@ -11,8 +11,24 @@ sim_ticks 122215830000 # Nu system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.numCycles 244431661 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.num_busy_cycles 244431661 # Number of busy cycles +system.cpu.num_conditional_control_insts 0 # number of instructions that are conditional controls +system.cpu.num_fp_alu_accesses 11630 # Number of float alu accesses +system.cpu.num_fp_insts 11630 # number of float instructions +system.cpu.num_fp_register_reads 23256 # number of times the floating registers were read +system.cpu.num_fp_register_writes 90 # number of times the floating registers were written +system.cpu.num_func_calls 0 # number of times a function call or return occured +system.cpu.num_idle_cycles 0 # Number of idle cycles system.cpu.num_insts 243835278 # Number of instructions executed -system.cpu.num_refs 105711442 # Number of memory references +system.cpu.num_int_alu_accesses 194726506 # Number of integer alu accesses +system.cpu.num_int_insts 194726506 # number of integer instructions +system.cpu.num_int_register_reads 456819010 # number of times the integer registers were read +system.cpu.num_int_register_writes 215451609 # number of times the integer registers were written +system.cpu.num_load_insts 82803522 # Number of load instructions +system.cpu.num_mem_refs 105711442 # number of memory refs +system.cpu.num_store_insts 22907920 # Number of store instructions system.cpu.workload.PROG:num_syscalls 443 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-timing/config.ini b/tests/long/10.mcf/ref/sparc/linux/simple-timing/config.ini index e885b2b99..dd7acffe5 100644 --- a/tests/long/10.mcf/ref/sparc/linux/simple-timing/config.ini +++ b/tests/long/10.mcf/ref/sparc/linux/simple-timing/config.ini @@ -1,13 +1,22 @@ [root] type=Root children=system -dummy=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem mem_mode=atomic physmem=system.physmem +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 [system.cpu] type=TimingSimpleCPU @@ -152,14 +161,14 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=mcf mcf.in -cwd=build/SPARC_SE/tests/opt/long/10.mcf/sparc/linux/simple-timing +cwd=build/SPARC_SE/tests/fast/long/10.mcf/sparc/linux/simple-timing egid=100 env= errout=cerr euid=100 -executable=/home/stever/m5/dist/cpu2000/binaries/sparc/linux/mcf +executable=/dist/m5/cpu2000/binaries/sparc/linux/mcf gid=100 -input=/home/stever/m5/dist/cpu2000/data/mcf/smred/input/mcf.in +input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in max_stack_size=67108864 output=cout pid=100 diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-timing/simout b/tests/long/10.mcf/ref/sparc/linux/simple-timing/simout index b2d326b66..280cd1a31 100755 --- a/tests/long/10.mcf/ref/sparc/linux/simple-timing/simout +++ b/tests/long/10.mcf/ref/sparc/linux/simple-timing/simout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Sep 20 2010 15:04:49 -M5 revision 0c4a7d867247 7686 default qtip print-identical tip -M5 started Sep 20 2010 16:31:43 -M5 executing on phenom -command line: build/SPARC_SE/m5.opt -d build/SPARC_SE/tests/opt/long/10.mcf/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/opt/long/10.mcf/sparc/linux/simple-timing +M5 compiled Feb 7 2011 02:13:30 +M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip +M5 started Feb 7 2011 02:13:48 +M5 executing on burrito +command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/10.mcf/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/fast/long/10.mcf/sparc/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-timing/stats.txt b/tests/long/10.mcf/ref/sparc/linux/simple-timing/stats.txt index f56720371..1b0d7fe21 100644 --- a/tests/long/10.mcf/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/long/10.mcf/ref/sparc/linux/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1229097 # Simulator instruction rate (inst/s) -host_mem_usage 329428 # Number of bytes of host memory used -host_seconds 198.39 # Real time elapsed on the host -host_tick_rate 1826897848 # Simulator tick rate (ticks/s) +host_inst_rate 483058 # Simulator instruction rate (inst/s) +host_mem_usage 359588 # Number of bytes of host memory used +host_seconds 504.77 # Real time elapsed on the host +host_tick_rate 718005180 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 243835278 # Number of instructions simulated sim_seconds 0.362431 # Number of seconds simulated @@ -210,8 +210,24 @@ system.cpu.l2cache.warmup_cycle 0 # Cy system.cpu.l2cache.writebacks 40 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.numCycles 724861774 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.num_busy_cycles 724861774 # Number of busy cycles +system.cpu.num_conditional_control_insts 0 # number of instructions that are conditional controls +system.cpu.num_fp_alu_accesses 11630 # Number of float alu accesses +system.cpu.num_fp_insts 11630 # number of float instructions +system.cpu.num_fp_register_reads 23256 # number of times the floating registers were read +system.cpu.num_fp_register_writes 90 # number of times the floating registers were written +system.cpu.num_func_calls 0 # number of times a function call or return occured +system.cpu.num_idle_cycles 0 # Number of idle cycles system.cpu.num_insts 243835278 # Number of instructions executed -system.cpu.num_refs 105711442 # Number of memory references +system.cpu.num_int_alu_accesses 194726506 # Number of integer alu accesses +system.cpu.num_int_insts 194726506 # number of integer instructions +system.cpu.num_int_register_reads 456819010 # number of times the integer registers were read +system.cpu.num_int_register_writes 215451608 # number of times the integer registers were written +system.cpu.num_load_insts 82803522 # Number of load instructions +system.cpu.num_mem_refs 105711442 # number of memory refs +system.cpu.num_store_insts 22907920 # Number of store instructions system.cpu.workload.PROG:num_syscalls 443 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/10.mcf/ref/x86/linux/o3-timing/config.ini b/tests/long/10.mcf/ref/x86/linux/o3-timing/config.ini index 60f53a64a..8e006cde5 100644 --- a/tests/long/10.mcf/ref/x86/linux/o3-timing/config.ini +++ b/tests/long/10.mcf/ref/x86/linux/o3-timing/config.ini @@ -10,6 +10,13 @@ type=System children=cpu membus physmem mem_mode=atomic physmem=system.physmem +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 [system.cpu] type=DerivO3CPU @@ -481,7 +488,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=mcf mcf.in -cwd=build/X86_SE/tests/opt/long/10.mcf/x86/linux/o3-timing +cwd=build/X86_SE/tests/fast/long/10.mcf/x86/linux/o3-timing egid=100 env= errout=cerr diff --git a/tests/long/10.mcf/ref/x86/linux/o3-timing/simout b/tests/long/10.mcf/ref/x86/linux/o3-timing/simout index fde487a8e..bf0cc96de 100755 --- a/tests/long/10.mcf/ref/x86/linux/o3-timing/simout +++ b/tests/long/10.mcf/ref/x86/linux/o3-timing/simout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jan 31 2011 16:34:44 -M5 revision 1b98eea40540 7883 default qtip tip x86o3regressions.patch -M5 started Jan 31 2011 16:34:46 +M5 compiled Feb 7 2011 02:32:07 +M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip +M5 started Feb 7 2011 02:32:24 M5 executing on burrito -command line: build/X86_SE/m5.opt -d build/X86_SE/tests/opt/long/10.mcf/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/opt/long/10.mcf/x86/linux/o3-timing +command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/10.mcf/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/fast/long/10.mcf/x86/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/10.mcf/ref/x86/linux/o3-timing/stats.txt b/tests/long/10.mcf/ref/x86/linux/o3-timing/stats.txt index 8ba88fe5a..3db6ff161 100644 --- a/tests/long/10.mcf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/10.mcf/ref/x86/linux/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 76828 # Simulator instruction rate (inst/s) -host_mem_usage 366252 # Number of bytes of host memory used -host_seconds 3621.00 # Real time elapsed on the host -host_tick_rate 47136339 # Simulator tick rate (ticks/s) +host_inst_rate 83481 # Simulator instruction rate (inst/s) +host_mem_usage 366872 # Number of bytes of host memory used +host_seconds 3332.41 # Real time elapsed on the host +host_tick_rate 51218385 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 278192519 # Number of instructions simulated sim_seconds 0.170681 # Number of seconds simulated @@ -37,6 +37,9 @@ system.cpu.commit.COM:committed_per_cycle::min_value 0 system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::total 321793097 # Number of insts commited each cycle system.cpu.commit.COM:count 278192519 # Number of instructions committed +system.cpu.commit.COM:fp_insts 40 # Number of committed floating point instructions. +system.cpu.commit.COM:function_calls 0 # Number of function calls committed. +system.cpu.commit.COM:int_insts 278186227 # Number of committed integer instructions. system.cpu.commit.COM:loads 90779388 # Number of loads committed system.cpu.commit.COM:membars 0 # Number of memory barriers committed system.cpu.commit.COM:refs 122219139 # Number of memory references committed @@ -150,6 +153,8 @@ system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Nu system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::total 341246945 # Number of instructions fetched each cycle (Total) +system.cpu.fp_regfile_reads 44 # number of floating regfile reads +system.cpu.fp_regfile_writes 31 # number of floating regfile writes system.cpu.icache.ReadReq_accesses 39245397 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_avg_miss_latency 37208.490566 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 35316.192560 # average ReadReq mshr miss latency @@ -249,6 +254,8 @@ system.cpu.iew.lsq.thread.0.squashedStores 9599437 # system.cpu.iew.memOrderViolationEvents 5520980 # Number of memory order violations system.cpu.iew.predictedNotTakenIncorrect 16897 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedTakenIncorrect 5373424 # Number of branches that were predicted taken incorrectly +system.cpu.int_regfile_reads 754340794 # number of integer regfile reads +system.cpu.int_regfile_writes 286169707 # number of integer regfile writes system.cpu.ipc 0.814950 # IPC: Instructions Per Cycle system.cpu.ipc_total 0.814950 # IPC: Total IPC of All Threads system.cpu.iq.ISSUE:FU_type_0::No_OpClass 16700 0.01% 0.01% # Type of FU issued @@ -340,6 +347,14 @@ system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::total 341246945 # Number of insts issued each cycle system.cpu.iq.ISSUE:rate 0.976510 # Inst issue rate +system.cpu.iq.fp_alu_accesses 55 # Number of floating point alu accesses +system.cpu.iq.fp_inst_queue_reads 110 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_wakeup_accesses 49 # Number of floating instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_writes 110 # Number of floating instruction queue writes +system.cpu.iq.int_alu_accesses 333424039 # Number of integer alu accesses +system.cpu.iq.int_inst_queue_reads 1008030271 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_wakeup_accesses 317781500 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_writes 504991584 # Number of integer instruction queue writes system.cpu.iq.iqInstsAdded 389592403 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqInstsIssued 333342642 # Number of instructions issued system.cpu.iq.iqNonSpecInstsAdded 455 # Number of non-speculative instructions added to the IQ @@ -419,7 +434,10 @@ system.cpu.memDep0.conflictingLoads 22358679 # Nu system.cpu.memDep0.conflictingStores 3757180 # Number of conflicting stores. system.cpu.memDep0.insertedLoads 131280417 # Number of loads inserted to the mem dependence unit. system.cpu.memDep0.insertedStores 41039188 # Number of stores inserted to the mem dependence unit. +system.cpu.misc_regfile_reads 204301939 # number of misc regfile reads system.cpu.numCycles 341361263 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.rename.RENAME:BlockCycles 486743 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 248344192 # Number of HB maps that are committed system.cpu.rename.RENAME:IQFullEvents 12249 # Number of times rename has blocked due to IQ full @@ -432,10 +450,14 @@ system.cpu.rename.RENAME:RunCycles 222275258 # Nu system.cpu.rename.RENAME:SquashCycles 19453848 # Number of cycles rename is squashing system.cpu.rename.RENAME:UnblockCycles 514692 # Number of cycles rename is unblocking system.cpu.rename.RENAME:UndoneMaps 129004058 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:fp_rename_lookups 291 # Number of floating rename lookups +system.cpu.rename.RENAME:int_rename_lookups 1292599352 # Number of integer rename lookups system.cpu.rename.RENAME:serializeStallCycles 5287 # count of cycles rename stalled for serializing inst system.cpu.rename.RENAME:serializingInsts 454 # count of serializing insts renamed system.cpu.rename.RENAME:skidInsts 779091 # count of insts added to the skid buffer system.cpu.rename.RENAME:tempSerializingInsts 452 # count of temporary serializing insts renamed +system.cpu.rob.rob_reads 708961934 # The number of ROB reads +system.cpu.rob.rob_writes 799263493 # The number of ROB writes system.cpu.timesIdled 5627 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 444 # Number of system calls diff --git a/tests/long/10.mcf/ref/x86/linux/simple-atomic/config.ini b/tests/long/10.mcf/ref/x86/linux/simple-atomic/config.ini index f7e610d03..f21f47f4d 100644 --- a/tests/long/10.mcf/ref/x86/linux/simple-atomic/config.ini +++ b/tests/long/10.mcf/ref/x86/linux/simple-atomic/config.ini @@ -10,6 +10,13 @@ type=System children=cpu membus physmem mem_mode=atomic physmem=system.physmem +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 [system.cpu] type=AtomicSimpleCPU @@ -54,7 +61,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=mcf mcf.in -cwd=build/X86_SE/tests/opt/long/10.mcf/x86/linux/simple-atomic +cwd=build/X86_SE/tests/fast/long/10.mcf/x86/linux/simple-atomic egid=100 env= errout=cerr diff --git a/tests/long/10.mcf/ref/x86/linux/simple-atomic/simout b/tests/long/10.mcf/ref/x86/linux/simple-atomic/simout index dfdd5bece..e76d60819 100755 --- a/tests/long/10.mcf/ref/x86/linux/simple-atomic/simout +++ b/tests/long/10.mcf/ref/x86/linux/simple-atomic/simout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jan 31 2011 14:03:49 -M5 revision aa283c8952a9 7880 default qtip stupdstats.patch tip -M5 started Jan 31 2011 14:03:51 +M5 compiled Feb 7 2011 02:32:07 +M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip +M5 started Feb 7 2011 02:32:12 M5 executing on burrito -command line: build/X86_SE/m5.opt -d build/X86_SE/tests/opt/long/10.mcf/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/opt/long/10.mcf/x86/linux/simple-atomic +command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/10.mcf/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/fast/long/10.mcf/x86/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/10.mcf/ref/x86/linux/simple-atomic/stats.txt b/tests/long/10.mcf/ref/x86/linux/simple-atomic/stats.txt index 82026f43b..bcab65c40 100644 --- a/tests/long/10.mcf/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/long/10.mcf/ref/x86/linux/simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 938582 # Simulator instruction rate (inst/s) -host_mem_usage 354336 # Number of bytes of host memory used -host_seconds 296.40 # Real time elapsed on the host -host_tick_rate 570013222 # Simulator tick rate (ticks/s) +host_inst_rate 722489 # Simulator instruction rate (inst/s) +host_mem_usage 358012 # Number of bytes of host memory used +host_seconds 385.05 # Real time elapsed on the host +host_tick_rate 438776725 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 278192520 # Number of instructions simulated sim_seconds 0.168950 # Number of seconds simulated @@ -11,8 +11,24 @@ sim_ticks 168950072000 # Nu system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.numCycles 337900145 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.num_busy_cycles 337900145 # Number of busy cycles +system.cpu.num_conditional_control_insts 18628012 # number of instructions that are conditional controls +system.cpu.num_fp_alu_accesses 40 # Number of float alu accesses +system.cpu.num_fp_insts 40 # number of float instructions +system.cpu.num_fp_register_reads 40 # number of times the floating registers were read +system.cpu.num_fp_register_writes 26 # number of times the floating registers were written +system.cpu.num_func_calls 0 # number of times a function call or return occured +system.cpu.num_idle_cycles 0 # Number of idle cycles system.cpu.num_insts 278192520 # Number of instructions executed -system.cpu.num_refs 122219139 # Number of memory references +system.cpu.num_int_alu_accesses 278186228 # Number of integer alu accesses +system.cpu.num_int_insts 278186228 # number of integer instructions +system.cpu.num_int_register_reads 855210512 # number of times the integer registers were read +system.cpu.num_int_register_writes 248344166 # number of times the integer registers were written +system.cpu.num_load_insts 90779388 # Number of load instructions +system.cpu.num_mem_refs 122219139 # number of memory refs +system.cpu.num_store_insts 31439751 # Number of store instructions system.cpu.workload.PROG:num_syscalls 444 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/10.mcf/ref/x86/linux/simple-timing/config.ini b/tests/long/10.mcf/ref/x86/linux/simple-timing/config.ini index 217d838ce..12f3ad44d 100644 --- a/tests/long/10.mcf/ref/x86/linux/simple-timing/config.ini +++ b/tests/long/10.mcf/ref/x86/linux/simple-timing/config.ini @@ -10,6 +10,13 @@ type=System children=cpu membus physmem mem_mode=atomic physmem=system.physmem +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 [system.cpu] type=TimingSimpleCPU @@ -154,7 +161,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=mcf mcf.in -cwd=build/X86_SE/tests/opt/long/10.mcf/x86/linux/simple-timing +cwd=build/X86_SE/tests/fast/long/10.mcf/x86/linux/simple-timing egid=100 env= errout=cerr diff --git a/tests/long/10.mcf/ref/x86/linux/simple-timing/simout b/tests/long/10.mcf/ref/x86/linux/simple-timing/simout index 68ecd8732..0b92276cc 100755 --- a/tests/long/10.mcf/ref/x86/linux/simple-timing/simout +++ b/tests/long/10.mcf/ref/x86/linux/simple-timing/simout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jan 31 2011 14:03:49 -M5 revision aa283c8952a9 7880 default qtip stupdstats.patch tip -M5 started Jan 31 2011 14:03:51 +M5 compiled Feb 7 2011 02:32:07 +M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip +M5 started Feb 7 2011 02:32:12 M5 executing on burrito -command line: build/X86_SE/m5.opt -d build/X86_SE/tests/opt/long/10.mcf/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/opt/long/10.mcf/x86/linux/simple-timing +command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/10.mcf/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/fast/long/10.mcf/x86/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/10.mcf/ref/x86/linux/simple-timing/stats.txt b/tests/long/10.mcf/ref/x86/linux/simple-timing/stats.txt index 7c84c26e1..cf6f03e98 100644 --- a/tests/long/10.mcf/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/10.mcf/ref/x86/linux/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 734335 # Simulator instruction rate (inst/s) -host_mem_usage 362052 # Number of bytes of host memory used -host_seconds 378.84 # Real time elapsed on the host -host_tick_rate 976703915 # Simulator tick rate (ticks/s) +host_inst_rate 424375 # Simulator instruction rate (inst/s) +host_mem_usage 365728 # Number of bytes of host memory used +host_seconds 655.54 # Real time elapsed on the host +host_tick_rate 564440982 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 278192520 # Number of instructions simulated sim_seconds 0.370011 # Number of seconds simulated @@ -200,8 +200,24 @@ system.cpu.l2cache.warmup_cycle 0 # Cy system.cpu.l2cache.writebacks 29460 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.numCycles 740021680 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.num_busy_cycles 740021680 # Number of busy cycles +system.cpu.num_conditional_control_insts 18628012 # number of instructions that are conditional controls +system.cpu.num_fp_alu_accesses 40 # Number of float alu accesses +system.cpu.num_fp_insts 40 # number of float instructions +system.cpu.num_fp_register_reads 40 # number of times the floating registers were read +system.cpu.num_fp_register_writes 26 # number of times the floating registers were written +system.cpu.num_func_calls 0 # number of times a function call or return occured +system.cpu.num_idle_cycles 0 # Number of idle cycles system.cpu.num_insts 278192520 # Number of instructions executed -system.cpu.num_refs 122219139 # Number of memory references +system.cpu.num_int_alu_accesses 278186228 # Number of integer alu accesses +system.cpu.num_int_insts 278186228 # number of integer instructions +system.cpu.num_int_register_reads 855210512 # number of times the integer registers were read +system.cpu.num_int_register_writes 248344166 # number of times the integer registers were written +system.cpu.num_load_insts 90779388 # Number of load instructions +system.cpu.num_mem_refs 122219139 # number of memory refs +system.cpu.num_store_insts 31439751 # Number of store instructions system.cpu.workload.PROG:num_syscalls 444 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/20.parser/ref/arm/linux/o3-timing/config.ini b/tests/long/20.parser/ref/arm/linux/o3-timing/config.ini index 5f7dcc6cf..92faf41fb 100644 --- a/tests/long/20.parser/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/20.parser/ref/arm/linux/o3-timing/config.ini @@ -1,13 +1,22 @@ [root] type=Root children=system -dummy=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem mem_mode=atomic physmem=system.physmem +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 [system.cpu] type=DerivO3CPU @@ -484,9 +493,9 @@ egid=100 env= errout=cerr euid=100 -executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/parser +executable=/dist/m5/cpu2000/binaries/arm/linux/parser gid=100 -input=/chips/pd/randd/dist/cpu2000/data/parser/mdred/input/parser.in +input=/dist/m5/cpu2000/data/parser/mdred/input/parser.in max_stack_size=67108864 output=cout pid=100 diff --git a/tests/long/20.parser/ref/arm/linux/o3-timing/simout b/tests/long/20.parser/ref/arm/linux/o3-timing/simout index 7fcfd6a75..b1ee33712 100755 --- a/tests/long/20.parser/ref/arm/linux/o3-timing/simout +++ b/tests/long/20.parser/ref/arm/linux/o3-timing/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jan 11 2011 18:16:01 -M5 revision b39a8457b332 7816 default ext/o3_regressions.patch qtip tip -M5 started Jan 12 2011 03:20:30 -M5 executing on u200439-lin.austin.arm.com +M5 compiled Feb 7 2011 01:56:16 +M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip +M5 started Feb 7 2011 01:56:25 +M5 executing on burrito command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/20.parser/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/fast/long/20.parser/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/20.parser/ref/arm/linux/o3-timing/stats.txt b/tests/long/20.parser/ref/arm/linux/o3-timing/stats.txt index b9adedb70..5862f2750 100644 --- a/tests/long/20.parser/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/20.parser/ref/arm/linux/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 95936 # Simulator instruction rate (inst/s) -host_mem_usage 255716 # Number of bytes of host memory used -host_seconds 5851.87 # Real time elapsed on the host -host_tick_rate 62464794 # Simulator tick rate (ticks/s) +host_inst_rate 89247 # Simulator instruction rate (inst/s) +host_mem_usage 242220 # Number of bytes of host memory used +host_seconds 6290.45 # Real time elapsed on the host +host_tick_rate 58109668 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 561403855 # Number of instructions simulated sim_seconds 0.365536 # Number of seconds simulated @@ -37,6 +37,9 @@ system.cpu.commit.COM:committed_per_cycle::min_value 0 system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::total 660408748 # Number of insts commited each cycle system.cpu.commit.COM:count 561403855 # Number of instructions committed +system.cpu.commit.COM:fp_insts 16 # Number of committed floating point instructions. +system.cpu.commit.COM:function_calls 0 # Number of function calls committed. +system.cpu.commit.COM:int_insts 464140463 # Number of committed integer instructions. system.cpu.commit.COM:loads 128127024 # Number of loads committed system.cpu.commit.COM:membars 0 # Number of memory barriers committed system.cpu.commit.COM:refs 184987501 # Number of memory references committed @@ -171,6 +174,7 @@ system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Nu system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::total 726668486 # Number of instructions fetched each cycle (Total) +system.cpu.fp_regfile_reads 16 # number of floating regfile reads system.cpu.icache.ReadReq_accesses 122785155 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_avg_miss_latency 13335.070892 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 9658.160050 # average ReadReq mshr miss latency @@ -270,6 +274,8 @@ system.cpu.iew.lsq.thread.0.squashedStores 83223254 # system.cpu.iew.memOrderViolationEvents 352056 # Number of memory order violations system.cpu.iew.predictedNotTakenIncorrect 15636111 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedTakenIncorrect 14467473 # Number of branches that were predicted taken incorrectly +system.cpu.int_regfile_reads 1624866525 # number of integer regfile reads +system.cpu.int_regfile_writes 504061562 # number of integer regfile writes system.cpu.ipc 0.767919 # IPC: Instructions Per Cycle system.cpu.ipc_total 0.767919 # IPC: Total IPC of All Threads system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued @@ -361,6 +367,14 @@ system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::total 726668486 # Number of insts issued each cycle system.cpu.iq.ISSUE:rate 1.039903 # Inst issue rate +system.cpu.iq.fp_alu_accesses 140 # Number of floating point alu accesses +system.cpu.iq.fp_inst_queue_reads 276 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_writes 652 # Number of floating instruction queue writes +system.cpu.iq.int_alu_accesses 771704903 # Number of integer alu accesses +system.cpu.iq.int_inst_queue_reads 2266614625 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_wakeup_accesses 674936607 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_writes 1350317509 # Number of integer instruction queue writes system.cpu.iq.iqInstsAdded 960829595 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqInstsIssued 760243815 # Number of instructions issued system.cpu.iq.iqNonSpecInstsAdded 162257 # Number of non-speculative instructions added to the IQ @@ -465,7 +479,11 @@ system.cpu.memDep0.conflictingLoads 60170710 # Nu system.cpu.memDep0.conflictingStores 74734099 # Number of conflicting stores. system.cpu.memDep0.insertedLoads 200154824 # Number of loads inserted to the mem dependence unit. system.cpu.memDep0.insertedStores 140083731 # Number of stores inserted to the mem dependence unit. +system.cpu.misc_regfile_reads 1169165868 # number of misc regfile reads +system.cpu.misc_regfile_writes 344748 # number of misc regfile writes system.cpu.numCycles 731071595 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.rename.RENAME:BlockCycles 7125233 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 435368498 # Number of HB maps that are committed system.cpu.rename.RENAME:IQFullEvents 5221350 # Number of times rename has blocked due to IQ full @@ -479,10 +497,14 @@ system.cpu.rename.RENAME:RunCycles 326862324 # Nu system.cpu.rename.RENAME:SquashCycles 66259738 # Number of cycles rename is squashing system.cpu.rename.RENAME:UnblockCycles 15428382 # Number of cycles rename is unblocking system.cpu.rename.RENAME:UndoneMaps 278321764 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:fp_rename_lookups 2110 # Number of floating rename lookups +system.cpu.rename.RENAME:int_rename_lookups 2644674034 # Number of integer rename lookups system.cpu.rename.RENAME:serializeStallCycles 1706138 # count of cycles rename stalled for serializing inst system.cpu.rename.RENAME:serializingInsts 233255 # count of serializing insts renamed system.cpu.rename.RENAME:skidInsts 48704887 # count of insts added to the skid buffer system.cpu.rename.RENAME:tempSerializingInsts 185624 # count of temporary serializing insts renamed +system.cpu.rob.rob_reads 1617861624 # The number of ROB reads +system.cpu.rob.rob_writes 1988299741 # The number of ROB writes system.cpu.timesIdled 93433 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 548 # Number of system calls diff --git a/tests/long/20.parser/ref/arm/linux/simple-atomic/config.ini b/tests/long/20.parser/ref/arm/linux/simple-atomic/config.ini index 8f051c01c..8b55eca4f 100644 --- a/tests/long/20.parser/ref/arm/linux/simple-atomic/config.ini +++ b/tests/long/20.parser/ref/arm/linux/simple-atomic/config.ini @@ -1,13 +1,22 @@ [root] type=Root children=system -dummy=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem mem_mode=atomic physmem=system.physmem +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 [system.cpu] type=AtomicSimpleCPU @@ -52,14 +61,14 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=parser 2.1.dict -batch -cwd=build/ARM_SE/tests/opt/long/20.parser/arm/linux/simple-atomic +cwd=build/ARM_SE/tests/fast/long/20.parser/arm/linux/simple-atomic egid=100 env= errout=cerr euid=100 -executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/parser +executable=/dist/m5/cpu2000/binaries/arm/linux/parser gid=100 -input=/chips/pd/randd/dist/cpu2000/data/parser/mdred/input/parser.in +input=/dist/m5/cpu2000/data/parser/mdred/input/parser.in max_stack_size=67108864 output=cout pid=100 diff --git a/tests/long/20.parser/ref/arm/linux/simple-atomic/simout b/tests/long/20.parser/ref/arm/linux/simple-atomic/simout index e187e6939..c27562976 100755 --- a/tests/long/20.parser/ref/arm/linux/simple-atomic/simout +++ b/tests/long/20.parser/ref/arm/linux/simple-atomic/simout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Oct 11 2010 18:37:23 -M5 revision c4e3d74d9a68 7726 default ext/mp_boot.patch qtip tip -M5 started Oct 11 2010 18:37:50 -M5 executing on aus-bc3-b4 -command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/20.parser/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/opt/long/20.parser/arm/linux/simple-atomic +M5 compiled Feb 7 2011 01:56:16 +M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip +M5 started Feb 7 2011 01:56:25 +M5 executing on burrito +command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/20.parser/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/fast/long/20.parser/arm/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/20.parser/ref/arm/linux/simple-atomic/stats.txt b/tests/long/20.parser/ref/arm/linux/simple-atomic/stats.txt index 3d8390b34..0871fb1fa 100644 --- a/tests/long/20.parser/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/20.parser/ref/arm/linux/simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 2845430 # Simulator instruction rate (inst/s) -host_mem_usage 257528 # Number of bytes of host memory used -host_seconds 197.30 # Real time elapsed on the host -host_tick_rate 1448130657 # Simulator tick rate (ticks/s) +host_inst_rate 1052675 # Simulator instruction rate (inst/s) +host_mem_usage 232888 # Number of bytes of host memory used +host_seconds 533.31 # Real time elapsed on the host +host_tick_rate 535740490 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 561403855 # Number of instructions simulated sim_seconds 0.285717 # Number of seconds simulated @@ -53,8 +53,24 @@ system.cpu.itb.write_hits 0 # DT system.cpu.itb.write_misses 0 # DTB write misses system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.numCycles 571433624 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.num_busy_cycles 571433624 # Number of busy cycles +system.cpu.num_conditional_control_insts 0 # number of instructions that are conditional controls +system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses +system.cpu.num_fp_insts 16 # number of float instructions +system.cpu.num_fp_register_reads 16 # number of times the floating registers were read +system.cpu.num_fp_register_writes 0 # number of times the floating registers were written +system.cpu.num_func_calls 0 # number of times a function call or return occured +system.cpu.num_idle_cycles 0 # Number of idle cycles system.cpu.num_insts 561403855 # Number of instructions executed -system.cpu.num_refs 184987503 # Number of memory references +system.cpu.num_int_alu_accesses 464140465 # Number of integer alu accesses +system.cpu.num_int_insts 464140465 # number of integer instructions +system.cpu.num_int_register_reads 1370673061 # number of times the integer registers were read +system.cpu.num_int_register_writes 415936275 # number of times the integer registers were written +system.cpu.num_load_insts 128127024 # Number of load instructions +system.cpu.num_mem_refs 184987503 # number of memory refs +system.cpu.num_store_insts 56860479 # Number of store instructions system.cpu.workload.PROG:num_syscalls 548 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/20.parser/ref/arm/linux/simple-timing/config.ini b/tests/long/20.parser/ref/arm/linux/simple-timing/config.ini index 2acf6aa8b..9596a7281 100644 --- a/tests/long/20.parser/ref/arm/linux/simple-timing/config.ini +++ b/tests/long/20.parser/ref/arm/linux/simple-timing/config.ini @@ -1,13 +1,22 @@ [root] type=Root children=system -dummy=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem mem_mode=atomic physmem=system.physmem +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 [system.cpu] type=TimingSimpleCPU @@ -152,14 +161,14 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=parser 2.1.dict -batch -cwd=build/ARM_SE/tests/opt/long/20.parser/arm/linux/simple-timing +cwd=build/ARM_SE/tests/fast/long/20.parser/arm/linux/simple-timing egid=100 env= errout=cerr euid=100 -executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/parser +executable=/dist/m5/cpu2000/binaries/arm/linux/parser gid=100 -input=/chips/pd/randd/dist/cpu2000/data/parser/mdred/input/parser.in +input=/dist/m5/cpu2000/data/parser/mdred/input/parser.in max_stack_size=67108864 output=cout pid=100 diff --git a/tests/long/20.parser/ref/arm/linux/simple-timing/simerr b/tests/long/20.parser/ref/arm/linux/simple-timing/simerr index eabe42249..cdafa164c 100755 --- a/tests/long/20.parser/ref/arm/linux/simple-timing/simerr +++ b/tests/long/20.parser/ref/arm/linux/simple-timing/simerr @@ -1,3 +1,5 @@ warn: Sockets disabled, not accepting gdb connections For more information see: http://www.m5sim.org/warn/d946bea6 +warn: Complete acc isn't called on normal stores in O3. +For more information see: http://www.m5sim.org/warn/138d8573 hack: be nice to actually delete the event here diff --git a/tests/long/20.parser/ref/arm/linux/simple-timing/simout b/tests/long/20.parser/ref/arm/linux/simple-timing/simout index 76b9031da..db8a10df5 100755 --- a/tests/long/20.parser/ref/arm/linux/simple-timing/simout +++ b/tests/long/20.parser/ref/arm/linux/simple-timing/simout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Oct 11 2010 18:37:23 -M5 revision c4e3d74d9a68 7726 default ext/mp_boot.patch qtip tip -M5 started Oct 11 2010 19:30:07 -M5 executing on aus-bc3-b4 -command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/20.parser/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/opt/long/20.parser/arm/linux/simple-timing +M5 compiled Feb 7 2011 01:56:16 +M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip +M5 started Feb 7 2011 02:00:20 +M5 executing on burrito +command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/20.parser/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/fast/long/20.parser/arm/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/20.parser/ref/arm/linux/simple-timing/stats.txt b/tests/long/20.parser/ref/arm/linux/simple-timing/stats.txt index d49ea7a07..5187afa41 100644 --- a/tests/long/20.parser/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/20.parser/ref/arm/linux/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 698342 # Simulator instruction rate (inst/s) -host_mem_usage 265248 # Number of bytes of host memory used -host_seconds 801.14 # Real time elapsed on the host -host_tick_rate 898558125 # Simulator tick rate (ticks/s) +host_inst_rate 427899 # Simulator instruction rate (inst/s) +host_mem_usage 240600 # Number of bytes of host memory used +host_seconds 1307.48 # Real time elapsed on the host +host_tick_rate 550579326 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 559470527 # Number of instructions simulated sim_seconds 0.719872 # Number of seconds simulated @@ -242,8 +242,24 @@ system.cpu.l2cache.warmup_cycle 510281834000 # Cy system.cpu.l2cache.writebacks 172310 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.numCycles 1439744848 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.num_busy_cycles 1439744848 # Number of busy cycles +system.cpu.num_conditional_control_insts 0 # number of instructions that are conditional controls +system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses +system.cpu.num_fp_insts 16 # number of float instructions +system.cpu.num_fp_register_reads 16 # number of times the floating registers were read +system.cpu.num_fp_register_writes 0 # number of times the floating registers were written +system.cpu.num_func_calls 0 # number of times a function call or return occured +system.cpu.num_idle_cycles 0 # Number of idle cycles system.cpu.num_insts 559470527 # Number of instructions executed -system.cpu.num_refs 184987503 # Number of memory references +system.cpu.num_int_alu_accesses 464140465 # Number of integer alu accesses +system.cpu.num_int_insts 464140465 # number of integer instructions +system.cpu.num_int_register_reads 1497198689 # number of times the integer registers were read +system.cpu.num_int_register_writes 415939738 # number of times the integer registers were written +system.cpu.num_load_insts 128127024 # Number of load instructions +system.cpu.num_mem_refs 184987503 # number of memory refs +system.cpu.num_store_insts 56860479 # Number of store instructions system.cpu.workload.PROG:num_syscalls 548 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/20.parser/ref/x86/linux/o3-timing/config.ini b/tests/long/20.parser/ref/x86/linux/o3-timing/config.ini index aa5254a3b..8363ae747 100644 --- a/tests/long/20.parser/ref/x86/linux/o3-timing/config.ini +++ b/tests/long/20.parser/ref/x86/linux/o3-timing/config.ini @@ -10,6 +10,13 @@ type=System children=cpu membus physmem mem_mode=atomic physmem=system.physmem +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 [system.cpu] type=DerivO3CPU @@ -481,7 +488,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=parser 2.1.dict -batch -cwd=build/X86_SE/tests/opt/long/20.parser/x86/linux/o3-timing +cwd=build/X86_SE/tests/fast/long/20.parser/x86/linux/o3-timing egid=100 env= errout=cerr diff --git a/tests/long/20.parser/ref/x86/linux/o3-timing/simout b/tests/long/20.parser/ref/x86/linux/o3-timing/simout index 6e2ddc167..4d3b5f29b 100755 --- a/tests/long/20.parser/ref/x86/linux/o3-timing/simout +++ b/tests/long/20.parser/ref/x86/linux/o3-timing/simout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jan 31 2011 16:34:44 -M5 revision 1b98eea40540 7883 default qtip tip x86o3regressions.patch -M5 started Jan 31 2011 16:34:46 +M5 compiled Feb 7 2011 02:32:07 +M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip +M5 started Feb 7 2011 02:32:13 M5 executing on burrito -command line: build/X86_SE/m5.opt -d build/X86_SE/tests/opt/long/20.parser/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/opt/long/20.parser/x86/linux/o3-timing +command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/20.parser/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/fast/long/20.parser/x86/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/20.parser/ref/x86/linux/o3-timing/stats.txt b/tests/long/20.parser/ref/x86/linux/o3-timing/stats.txt index c8db50488..c39e8dfae 100644 --- a/tests/long/20.parser/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/20.parser/ref/x86/linux/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 123365 # Simulator instruction rate (inst/s) -host_mem_usage 239740 # Number of bytes of host memory used -host_seconds 12393.99 # Real time elapsed on the host -host_tick_rate 65919204 # Simulator tick rate (ticks/s) +host_inst_rate 160923 # Simulator instruction rate (inst/s) +host_mem_usage 240360 # Number of bytes of host memory used +host_seconds 9501.35 # Real time elapsed on the host +host_tick_rate 85987979 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1528988756 # Number of instructions simulated sim_seconds 0.817002 # Number of seconds simulated @@ -37,6 +37,9 @@ system.cpu.commit.COM:committed_per_cycle::min_value 0 system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::total 1552269342 # Number of insts commited each cycle system.cpu.commit.COM:count 1528988756 # Number of instructions committed +system.cpu.commit.COM:fp_insts 0 # Number of committed floating point instructions. +system.cpu.commit.COM:function_calls 0 # Number of function calls committed. +system.cpu.commit.COM:int_insts 1528317614 # Number of committed integer instructions. system.cpu.commit.COM:loads 384102160 # Number of loads committed system.cpu.commit.COM:membars 0 # Number of memory barriers committed system.cpu.commit.COM:refs 533262345 # Number of memory references committed @@ -150,6 +153,7 @@ system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Nu system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::total 1623905370 # Number of instructions fetched each cycle (Total) +system.cpu.fp_regfile_reads 10 # number of floating regfile reads system.cpu.icache.ReadReq_accesses 165973622 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_avg_miss_latency 22741.617211 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 19372.661290 # average ReadReq mshr miss latency @@ -249,6 +253,8 @@ system.cpu.iew.lsq.thread.0.squashedStores 44929168 # system.cpu.iew.memOrderViolationEvents 11954619 # Number of memory order violations system.cpu.iew.predictedNotTakenIncorrect 280770 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedTakenIncorrect 18292736 # Number of branches that were predicted taken incorrectly +system.cpu.int_regfile_reads 3876226209 # number of integer regfile reads +system.cpu.int_regfile_writes 1582892637 # number of integer regfile writes system.cpu.ipc 0.935731 # IPC: Instructions Per Cycle system.cpu.ipc_total 0.935731 # IPC: Total IPC of All Threads system.cpu.iq.ISSUE:FU_type_0::No_OpClass 1927969 0.11% 0.11% # Type of FU issued @@ -340,6 +346,14 @@ system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::total 1623905370 # Number of insts issued each cycle system.cpu.iq.ISSUE:rate 1.060682 # Inst issue rate +system.cpu.iq.fp_alu_accesses 24 # Number of floating point alu accesses +system.cpu.iq.fp_inst_queue_reads 48 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_wakeup_accesses 10 # Number of floating instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_writes 68 # Number of floating instruction queue writes +system.cpu.iq.int_alu_accesses 1732259326 # Number of integer alu accesses +system.cpu.iq.int_inst_queue_reads 5091250901 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_wakeup_accesses 1694146357 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_writes 2453039449 # Number of integer instruction queue writes system.cpu.iq.iqInstsAdded 1988096819 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqInstsIssued 1733158148 # Number of instructions issued system.cpu.iq.iqNonSpecInstsAdded 579 # Number of non-speculative instructions added to the IQ @@ -430,7 +444,10 @@ system.cpu.memDep0.conflictingLoads 151128770 # Nu system.cpu.memDep0.conflictingStores 47539398 # Number of conflicting stores. system.cpu.memDep0.insertedLoads 508224738 # Number of loads inserted to the mem dependence unit. system.cpu.memDep0.insertedStores 194089353 # Number of stores inserted to the mem dependence unit. +system.cpu.misc_regfile_reads 947795380 # number of misc regfile reads system.cpu.numCycles 1634004079 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.rename.RENAME:BlockCycles 11181498 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 1427299027 # Number of HB maps that are committed system.cpu.rename.RENAME:IQFullEvents 8162354 # Number of times rename has blocked due to IQ full @@ -444,10 +461,14 @@ system.cpu.rename.RENAME:RunCycles 1095363349 # Nu system.cpu.rename.RENAME:SquashCycles 71636028 # Number of cycles rename is squashing system.cpu.rename.RENAME:UnblockCycles 14962968 # Number of cycles rename is unblocking system.cpu.rename.RENAME:UndoneMaps 538631225 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:fp_rename_lookups 168 # Number of floating rename lookups +system.cpu.rename.RENAME:int_rename_lookups 6064799758 # Number of integer rename lookups system.cpu.rename.RENAME:serializeStallCycles 6110 # count of cycles rename stalled for serializing inst system.cpu.rename.RENAME:serializingInsts 566 # count of serializing insts renamed system.cpu.rename.RENAME:skidInsts 21122292 # count of insts added to the skid buffer system.cpu.rename.RENAME:tempSerializingInsts 563 # count of temporary serializing insts renamed +system.cpu.rob.rob_reads 3532180532 # The number of ROB reads +system.cpu.rob.rob_writes 4048956705 # The number of ROB writes system.cpu.timesIdled 351337 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 551 # Number of system calls diff --git a/tests/long/20.parser/ref/x86/linux/simple-atomic/config.ini b/tests/long/20.parser/ref/x86/linux/simple-atomic/config.ini index 2edd32f29..fdc891c59 100644 --- a/tests/long/20.parser/ref/x86/linux/simple-atomic/config.ini +++ b/tests/long/20.parser/ref/x86/linux/simple-atomic/config.ini @@ -10,6 +10,13 @@ type=System children=cpu membus physmem mem_mode=atomic physmem=system.physmem +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 [system.cpu] type=AtomicSimpleCPU @@ -54,7 +61,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=parser 2.1.dict -batch -cwd=build/X86_SE/tests/opt/long/20.parser/x86/linux/simple-atomic +cwd=build/X86_SE/tests/fast/long/20.parser/x86/linux/simple-atomic egid=100 env= errout=cerr diff --git a/tests/long/20.parser/ref/x86/linux/simple-atomic/simout b/tests/long/20.parser/ref/x86/linux/simple-atomic/simout index 1a82abfd9..70ab31a10 100755 --- a/tests/long/20.parser/ref/x86/linux/simple-atomic/simout +++ b/tests/long/20.parser/ref/x86/linux/simple-atomic/simout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jan 31 2011 14:03:49 -M5 revision aa283c8952a9 7880 default qtip stupdstats.patch tip -M5 started Jan 31 2011 14:03:51 +M5 compiled Feb 7 2011 02:32:07 +M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip +M5 started Feb 7 2011 02:32:12 M5 executing on burrito -command line: build/X86_SE/m5.opt -d build/X86_SE/tests/opt/long/20.parser/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/opt/long/20.parser/x86/linux/simple-atomic +command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/20.parser/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/fast/long/20.parser/x86/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/20.parser/ref/x86/linux/simple-atomic/stats.txt b/tests/long/20.parser/ref/x86/linux/simple-atomic/stats.txt index 016faf2ec..836ed1519 100644 --- a/tests/long/20.parser/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/long/20.parser/ref/x86/linux/simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1495739 # Simulator instruction rate (inst/s) -host_mem_usage 223620 # Number of bytes of host memory used -host_seconds 1022.23 # Real time elapsed on the host -host_tick_rate 865978759 # Simulator tick rate (ticks/s) +host_inst_rate 904614 # Simulator instruction rate (inst/s) +host_mem_usage 227300 # Number of bytes of host memory used +host_seconds 1690.21 # Real time elapsed on the host +host_tick_rate 523739013 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1528988757 # Number of instructions simulated sim_seconds 0.885229 # Number of seconds simulated @@ -11,8 +11,24 @@ sim_ticks 885229360000 # Nu system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.numCycles 1770458721 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.num_busy_cycles 1770458721 # Number of busy cycles +system.cpu.num_conditional_control_insts 92658800 # number of instructions that are conditional controls +system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses +system.cpu.num_fp_insts 0 # number of float instructions +system.cpu.num_fp_register_reads 0 # number of times the floating registers were read +system.cpu.num_fp_register_writes 0 # number of times the floating registers were written +system.cpu.num_func_calls 0 # number of times a function call or return occured +system.cpu.num_idle_cycles 0 # Number of idle cycles system.cpu.num_insts 1528988757 # Number of instructions executed -system.cpu.num_refs 533262345 # Number of memory references +system.cpu.num_int_alu_accesses 1528317615 # Number of integer alu accesses +system.cpu.num_int_insts 1528317615 # number of integer instructions +system.cpu.num_int_register_reads 4418676175 # number of times the integer registers were read +system.cpu.num_int_register_writes 1427299027 # number of times the integer registers were written +system.cpu.num_load_insts 384102160 # Number of load instructions +system.cpu.num_mem_refs 533262345 # number of memory refs +system.cpu.num_store_insts 149160185 # Number of store instructions system.cpu.workload.PROG:num_syscalls 551 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/20.parser/ref/x86/linux/simple-timing/config.ini b/tests/long/20.parser/ref/x86/linux/simple-timing/config.ini index fc75460ef..4c1fe374d 100644 --- a/tests/long/20.parser/ref/x86/linux/simple-timing/config.ini +++ b/tests/long/20.parser/ref/x86/linux/simple-timing/config.ini @@ -10,6 +10,13 @@ type=System children=cpu membus physmem mem_mode=atomic physmem=system.physmem +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 [system.cpu] type=TimingSimpleCPU @@ -154,7 +161,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=parser 2.1.dict -batch -cwd=build/X86_SE/tests/opt/long/20.parser/x86/linux/simple-timing +cwd=build/X86_SE/tests/fast/long/20.parser/x86/linux/simple-timing egid=100 env= errout=cerr diff --git a/tests/long/20.parser/ref/x86/linux/simple-timing/simout b/tests/long/20.parser/ref/x86/linux/simple-timing/simout index 2f7e6c58c..9e491e500 100755 --- a/tests/long/20.parser/ref/x86/linux/simple-timing/simout +++ b/tests/long/20.parser/ref/x86/linux/simple-timing/simout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jan 31 2011 14:03:49 -M5 revision aa283c8952a9 7880 default qtip stupdstats.patch tip -M5 started Jan 31 2011 14:03:51 +M5 compiled Feb 7 2011 02:32:07 +M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip +M5 started Feb 7 2011 02:36:47 M5 executing on burrito -command line: build/X86_SE/m5.opt -d build/X86_SE/tests/opt/long/20.parser/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/opt/long/20.parser/x86/linux/simple-timing +command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/20.parser/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/fast/long/20.parser/x86/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/20.parser/ref/x86/linux/simple-timing/stats.txt b/tests/long/20.parser/ref/x86/linux/simple-timing/stats.txt index 630224d3a..2cd323573 100644 --- a/tests/long/20.parser/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/20.parser/ref/x86/linux/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1108188 # Simulator instruction rate (inst/s) -host_mem_usage 231336 # Number of bytes of host memory used -host_seconds 1379.72 # Real time elapsed on the host -host_tick_rate 1202222105 # Simulator tick rate (ticks/s) +host_inst_rate 738382 # Simulator instruction rate (inst/s) +host_mem_usage 235020 # Number of bytes of host memory used +host_seconds 2070.73 # Real time elapsed on the host +host_tick_rate 801036637 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1528988757 # Number of instructions simulated sim_seconds 1.658730 # Number of seconds simulated @@ -200,8 +200,24 @@ system.cpu.l2cache.warmup_cycle 896565143000 # Cy system.cpu.l2cache.writebacks 411709 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.numCycles 3317459208 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.num_busy_cycles 3317459208 # Number of busy cycles +system.cpu.num_conditional_control_insts 92658800 # number of instructions that are conditional controls +system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses +system.cpu.num_fp_insts 0 # number of float instructions +system.cpu.num_fp_register_reads 0 # number of times the floating registers were read +system.cpu.num_fp_register_writes 0 # number of times the floating registers were written +system.cpu.num_func_calls 0 # number of times a function call or return occured +system.cpu.num_idle_cycles 0 # Number of idle cycles system.cpu.num_insts 1528988757 # Number of instructions executed -system.cpu.num_refs 533262345 # Number of memory references +system.cpu.num_int_alu_accesses 1528317615 # Number of integer alu accesses +system.cpu.num_int_insts 1528317615 # number of integer instructions +system.cpu.num_int_register_reads 4418676175 # number of times the integer registers were read +system.cpu.num_int_register_writes 1427299027 # number of times the integer registers were written +system.cpu.num_load_insts 384102160 # Number of load instructions +system.cpu.num_mem_refs 533262345 # number of memory refs +system.cpu.num_store_insts 149160185 # Number of store instructions system.cpu.workload.PROG:num_syscalls 551 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/30.eon/ref/alpha/tru64/o3-timing/config.ini b/tests/long/30.eon/ref/alpha/tru64/o3-timing/config.ini index 73c8936cc..e6dd679c1 100644 --- a/tests/long/30.eon/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/30.eon/ref/alpha/tru64/o3-timing/config.ini @@ -1,13 +1,22 @@ [root] type=Root children=system -dummy=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem mem_mode=atomic physmem=system.physmem +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 [system.cpu] type=DerivO3CPU diff --git a/tests/long/30.eon/ref/alpha/tru64/o3-timing/simout b/tests/long/30.eon/ref/alpha/tru64/o3-timing/simout index 1688d3208..9a3fdb284 100755 --- a/tests/long/30.eon/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/30.eon/ref/alpha/tru64/o3-timing/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jan 17 2011 16:24:53 -M5 revision f72d94f8c275 7839 default qtip tip outgoing.patch qbase -M5 started Jan 17 2011 16:25:09 -M5 executing on zizzer +M5 compiled Feb 7 2011 01:47:18 +M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip +M5 started Feb 7 2011 01:47:47 +M5 executing on burrito command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/30.eon/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/30.eon/ref/alpha/tru64/o3-timing/stats.txt index eb0b216c3..05fbc791d 100644 --- a/tests/long/30.eon/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/30.eon/ref/alpha/tru64/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 178067 # Simulator instruction rate (inst/s) -host_mem_usage 212832 # Number of bytes of host memory used -host_seconds 2109.17 # Real time elapsed on the host -host_tick_rate 64635199 # Simulator tick rate (ticks/s) +host_inst_rate 86954 # Simulator instruction rate (inst/s) +host_mem_usage 233264 # Number of bytes of host memory used +host_seconds 4319.23 # Real time elapsed on the host +host_tick_rate 31562755 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 375574819 # Number of instructions simulated sim_seconds 0.136327 # Number of seconds simulated @@ -37,6 +37,9 @@ system.cpu.commit.COM:committed_per_cycle::min_value 0 system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::total 256761438 # Number of insts commited each cycle system.cpu.commit.COM:count 398664594 # Number of instructions committed +system.cpu.commit.COM:fp_insts 155295106 # Number of committed floating point instructions. +system.cpu.commit.COM:function_calls 8007752 # Number of function calls committed. +system.cpu.commit.COM:int_insts 316365851 # Number of committed integer instructions. system.cpu.commit.COM:loads 94754489 # Number of loads committed system.cpu.commit.COM:membars 0 # Number of memory barriers committed system.cpu.commit.COM:refs 168275218 # Number of memory references committed @@ -171,6 +174,8 @@ system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Nu system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::total 272512875 # Number of instructions fetched each cycle (Total) +system.cpu.fp_regfile_reads 161565122 # number of floating regfile reads +system.cpu.fp_regfile_writes 106206809 # number of floating regfile writes system.cpu.icache.ReadReq_accesses 64427463 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_avg_miss_latency 32238.031366 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 30836.486832 # average ReadReq mshr miss latency @@ -270,6 +275,8 @@ system.cpu.iew.lsq.thread.0.squashedStores 19394112 # system.cpu.iew.memOrderViolationEvents 663165 # Number of memory order violations system.cpu.iew.predictedNotTakenIncorrect 1101512 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedTakenIncorrect 5016228 # Number of branches that were predicted taken incorrectly +system.cpu.int_regfile_reads 421360455 # number of integer regfile reads +system.cpu.int_regfile_writes 182139619 # number of integer regfile writes system.cpu.ipc 1.377479 # IPC: Instructions Per Cycle system.cpu.ipc_total 1.377479 # IPC: Total IPC of All Threads system.cpu.iq.ISSUE:FU_type_0::No_OpClass 33581 0.01% 0.01% # Type of FU issued @@ -361,6 +368,14 @@ system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::total 272512875 # Number of insts issued each cycle system.cpu.iq.ISSUE:rate 1.578500 # Inst issue rate +system.cpu.iq.fp_alu_accesses 175992487 # Number of floating point alu accesses +system.cpu.iq.fp_inst_queue_reads 346671239 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_wakeup_accesses 165916628 # Number of floating instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_writes 231922736 # Number of floating instruction queue writes +system.cpu.iq.int_alu_accesses 262987844 # Number of integer alu accesses +system.cpu.iq.int_inst_queue_reads 796105773 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_wakeup_accesses 251613948 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_writes 330463092 # Number of integer instruction queue writes system.cpu.iq.iqInstsAdded 469247183 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqInstsIssued 430384006 # Number of instructions issued system.cpu.iq.iqNonSpecInstsAdded 241 # Number of non-speculative instructions added to the IQ @@ -457,7 +472,11 @@ system.cpu.memDep0.conflictingLoads 71937561 # Nu system.cpu.memDep0.conflictingStores 54246192 # Number of conflicting stores. system.cpu.memDep0.insertedLoads 117580442 # Number of loads inserted to the mem dependence unit. system.cpu.memDep0.insertedStores 92914841 # Number of stores inserted to the mem dependence unit. +system.cpu.misc_regfile_reads 350572 # number of misc regfile reads +system.cpu.misc_regfile_writes 1 # number of misc regfile writes system.cpu.numCycles 272653822 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.rename.RENAME:BlockCycles 10643219 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 259532341 # Number of HB maps that are committed system.cpu.rename.RENAME:IQFullEvents 2331141 # Number of times rename has blocked due to IQ full @@ -471,10 +490,14 @@ system.cpu.rename.RENAME:RunCycles 96677987 # Nu system.cpu.rename.RENAME:SquashCycles 15751437 # Number of cycles rename is squashing system.cpu.rename.RENAME:UnblockCycles 10596756 # Number of cycles rename is unblocking system.cpu.rename.RENAME:UndoneMaps 78407825 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:fp_rename_lookups 326649614 # Number of floating rename lookups +system.cpu.rename.RENAME:int_rename_lookups 361910200 # Number of integer rename lookups system.cpu.rename.RENAME:serializeStallCycles 367264 # count of cycles rename stalled for serializing inst system.cpu.rename.RENAME:serializingInsts 37559 # count of serializing insts renamed system.cpu.rename.RENAME:skidInsts 23060243 # count of insts added to the skid buffer system.cpu.rename.RENAME:tempSerializingInsts 258 # count of temporary serializing insts renamed +system.cpu.rob.rob_reads 740781417 # The number of ROB reads +system.cpu.rob.rob_writes 1009223784 # The number of ROB writes system.cpu.timesIdled 3093 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 215 # Number of system calls diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/30.eon/ref/alpha/tru64/simple-atomic/config.ini index a541de94f..5f40a4aa8 100644 --- a/tests/long/30.eon/ref/alpha/tru64/simple-atomic/config.ini +++ b/tests/long/30.eon/ref/alpha/tru64/simple-atomic/config.ini @@ -1,13 +1,22 @@ [root] type=Root children=system -dummy=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem mem_mode=atomic physmem=system.physmem +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 [system.cpu] type=AtomicSimpleCPU @@ -57,7 +66,7 @@ egid=100 env= errout=cerr euid=100 -executable=/chips/pd/randd/dist/cpu2000/binaries/alpha/tru64/eon +executable=/dist/m5/cpu2000/binaries/alpha/tru64/eon gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-atomic/simerr b/tests/long/30.eon/ref/alpha/tru64/simple-atomic/simerr index f259e0f2b..ea7dd73a3 100755 --- a/tests/long/30.eon/ref/alpha/tru64/simple-atomic/simerr +++ b/tests/long/30.eon/ref/alpha/tru64/simple-atomic/simerr @@ -1,5 +1,11 @@ warn: Sockets disabled, not accepting gdb connections For more information see: http://www.m5sim.org/warn/d946bea6 +warn: Prefetch instrutions is Alpha do not do anything +For more information see: http://www.m5sim.org/warn/3e0eccba +warn: Prefetch instrutions is Alpha do not do anything +For more information see: http://www.m5sim.org/warn/3e0eccba +warn: Prefetch instrutions is Alpha do not do anything +For more information see: http://www.m5sim.org/warn/3e0eccba getting pixel output filename pixels_out.cook opening control file chair.control.cook opening camera file chair.camera diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-atomic/simout b/tests/long/30.eon/ref/alpha/tru64/simple-atomic/simout index 602c1e755..96b5bf3c9 100755 --- a/tests/long/30.eon/ref/alpha/tru64/simple-atomic/simout +++ b/tests/long/30.eon/ref/alpha/tru64/simple-atomic/simout @@ -1,5 +1,3 @@ -Redirecting stdout to build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/simple-atomic/simout -Redirecting stderr to build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/simple-atomic/simerr M5 Simulator System Copyright (c) 2001-2008 @@ -7,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Nov 2 2010 21:30:55 -M5 revision 0af3760102ec+ 7713+ default qtip ext/alpha_prefetch.patch tip -M5 started Nov 2 2010 21:31:02 -M5 executing on aus-bc2-b15 +M5 compiled Feb 7 2011 01:47:18 +M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip +M5 started Feb 7 2011 01:47:38 +M5 executing on burrito command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/30.eon/ref/alpha/tru64/simple-atomic/stats.txt index aa6437370..6fcc67a34 100644 --- a/tests/long/30.eon/ref/alpha/tru64/simple-atomic/stats.txt +++ b/tests/long/30.eon/ref/alpha/tru64/simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 4732897 # Simulator instruction rate (inst/s) -host_mem_usage 238480 # Number of bytes of host memory used -host_seconds 84.23 # Real time elapsed on the host -host_tick_rate 2366444186 # Simulator tick rate (ticks/s) +host_inst_rate 1382202 # Simulator instruction rate (inst/s) +host_mem_usage 224632 # Number of bytes of host memory used +host_seconds 288.43 # Real time elapsed on the host +host_tick_rate 691100750 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 398664595 # Number of instructions simulated sim_seconds 0.199332 # Number of seconds simulated @@ -43,8 +43,24 @@ system.cpu.itb.write_hits 0 # DT system.cpu.itb.write_misses 0 # DTB write misses system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.numCycles 398664824 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.num_busy_cycles 398664824 # Number of busy cycles +system.cpu.num_conditional_control_insts 25997787 # number of instructions that are conditional controls +system.cpu.num_fp_alu_accesses 155295119 # Number of float alu accesses +system.cpu.num_fp_insts 155295119 # number of float instructions +system.cpu.num_fp_register_reads 151776196 # number of times the floating registers were read +system.cpu.num_fp_register_writes 100196481 # number of times the floating registers were written +system.cpu.num_func_calls 16015498 # number of times a function call or return occured +system.cpu.num_idle_cycles 0 # Number of idle cycles system.cpu.num_insts 398664595 # Number of instructions executed -system.cpu.num_refs 168275274 # Number of memory references +system.cpu.num_int_alu_accesses 316365907 # Number of integer alu accesses +system.cpu.num_int_insts 316365907 # number of integer instructions +system.cpu.num_int_register_reads 372938760 # number of times the integer registers were read +system.cpu.num_int_register_writes 159335860 # number of times the integer registers were written +system.cpu.num_load_insts 94754510 # Number of load instructions +system.cpu.num_mem_refs 168275274 # number of memory refs +system.cpu.num_store_insts 73520764 # Number of store instructions system.cpu.workload.PROG:num_syscalls 215 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-timing/config.ini b/tests/long/30.eon/ref/alpha/tru64/simple-timing/config.ini index dee4088d8..91f994c0c 100644 --- a/tests/long/30.eon/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/long/30.eon/ref/alpha/tru64/simple-timing/config.ini @@ -1,13 +1,22 @@ [root] type=Root children=system -dummy=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem mem_mode=atomic physmem=system.physmem +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 [system.cpu] type=TimingSimpleCPU @@ -157,7 +166,7 @@ egid=100 env= errout=cerr euid=100 -executable=/chips/pd/randd/dist/cpu2000/binaries/alpha/tru64/eon +executable=/dist/m5/cpu2000/binaries/alpha/tru64/eon gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-timing/simerr b/tests/long/30.eon/ref/alpha/tru64/simple-timing/simerr index f259e0f2b..ea7dd73a3 100755 --- a/tests/long/30.eon/ref/alpha/tru64/simple-timing/simerr +++ b/tests/long/30.eon/ref/alpha/tru64/simple-timing/simerr @@ -1,5 +1,11 @@ warn: Sockets disabled, not accepting gdb connections For more information see: http://www.m5sim.org/warn/d946bea6 +warn: Prefetch instrutions is Alpha do not do anything +For more information see: http://www.m5sim.org/warn/3e0eccba +warn: Prefetch instrutions is Alpha do not do anything +For more information see: http://www.m5sim.org/warn/3e0eccba +warn: Prefetch instrutions is Alpha do not do anything +For more information see: http://www.m5sim.org/warn/3e0eccba getting pixel output filename pixels_out.cook opening control file chair.control.cook opening camera file chair.camera diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-timing/simout b/tests/long/30.eon/ref/alpha/tru64/simple-timing/simout index 3f5e4009e..4f3149cad 100755 --- a/tests/long/30.eon/ref/alpha/tru64/simple-timing/simout +++ b/tests/long/30.eon/ref/alpha/tru64/simple-timing/simout @@ -1,5 +1,3 @@ -Redirecting stdout to build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/simple-timing/simout -Redirecting stderr to build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/simple-timing/simerr M5 Simulator System Copyright (c) 2001-2008 @@ -7,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Nov 2 2010 21:30:55 -M5 revision 0af3760102ec+ 7713+ default qtip ext/alpha_prefetch.patch tip -M5 started Nov 2 2010 21:41:16 -M5 executing on aus-bc2-b15 +M5 compiled Feb 7 2011 01:47:18 +M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip +M5 started Feb 7 2011 01:47:38 +M5 executing on burrito command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/30.eon/ref/alpha/tru64/simple-timing/stats.txt index 70d7495a6..31ad19d58 100644 --- a/tests/long/30.eon/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/30.eon/ref/alpha/tru64/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 2252516 # Simulator instruction rate (inst/s) -host_mem_usage 246196 # Number of bytes of host memory used -host_seconds 176.99 # Real time elapsed on the host -host_tick_rate 3205571054 # Simulator tick rate (ticks/s) +host_inst_rate 531142 # Simulator instruction rate (inst/s) +host_mem_usage 232344 # Number of bytes of host memory used +host_seconds 750.58 # Real time elapsed on the host +host_tick_rate 755872580 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 398664609 # Number of instructions simulated sim_seconds 0.567343 # Number of seconds simulated @@ -232,8 +232,24 @@ system.cpu.l2cache.warmup_cycle 0 # Cy system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.numCycles 1134686340 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.num_busy_cycles 1134686340 # Number of busy cycles +system.cpu.num_conditional_control_insts 25997790 # number of instructions that are conditional controls +system.cpu.num_fp_alu_accesses 155295119 # Number of float alu accesses +system.cpu.num_fp_insts 155295119 # number of float instructions +system.cpu.num_fp_register_reads 151776196 # number of times the floating registers were read +system.cpu.num_fp_register_writes 100196481 # number of times the floating registers were written +system.cpu.num_func_calls 16015498 # number of times a function call or return occured +system.cpu.num_idle_cycles 0 # Number of idle cycles system.cpu.num_insts 398664609 # Number of instructions executed -system.cpu.num_refs 168275276 # Number of memory references +system.cpu.num_int_alu_accesses 316365921 # Number of integer alu accesses +system.cpu.num_int_insts 316365921 # number of integer instructions +system.cpu.num_int_register_reads 372938779 # number of times the integer registers were read +system.cpu.num_int_register_writes 159335870 # number of times the integer registers were written +system.cpu.num_load_insts 94754511 # Number of load instructions +system.cpu.num_mem_refs 168275276 # number of memory refs +system.cpu.num_store_insts 73520765 # Number of store instructions system.cpu.workload.PROG:num_syscalls 215 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/30.eon/ref/arm/linux/o3-timing/config.ini b/tests/long/30.eon/ref/arm/linux/o3-timing/config.ini index 05c074be9..5e5332f9b 100644 --- a/tests/long/30.eon/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/30.eon/ref/arm/linux/o3-timing/config.ini @@ -1,13 +1,22 @@ [root] type=Root children=system -dummy=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem mem_mode=atomic physmem=system.physmem +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 [system.cpu] type=DerivO3CPU @@ -484,7 +493,7 @@ egid=100 env= errout=cerr euid=100 -executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/eon +executable=/dist/m5/cpu2000/binaries/arm/linux/eon gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/30.eon/ref/arm/linux/o3-timing/simout b/tests/long/30.eon/ref/arm/linux/o3-timing/simout index 026fec0e6..da6bef881 100755 --- a/tests/long/30.eon/ref/arm/linux/o3-timing/simout +++ b/tests/long/30.eon/ref/arm/linux/o3-timing/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jan 11 2011 18:16:01 -M5 revision b39a8457b332 7816 default ext/o3_regressions.patch qtip tip -M5 started Jan 12 2011 03:29:33 -M5 executing on u200439-lin.austin.arm.com +M5 compiled Feb 7 2011 01:56:16 +M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip +M5 started Feb 7 2011 01:56:35 +M5 executing on burrito command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/30.eon/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/fast/long/30.eon/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/30.eon/ref/arm/linux/o3-timing/stats.txt b/tests/long/30.eon/ref/arm/linux/o3-timing/stats.txt index 432c33c36..6d2d3d9a2 100644 --- a/tests/long/30.eon/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/30.eon/ref/arm/linux/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 100561 # Simulator instruction rate (inst/s) -host_mem_usage 266348 # Number of bytes of host memory used -host_seconds 3428.53 # Real time elapsed on the host -host_tick_rate 62832373 # Simulator tick rate (ticks/s) +host_inst_rate 72451 # Simulator instruction rate (inst/s) +host_mem_usage 252856 # Number of bytes of host memory used +host_seconds 4758.76 # Real time elapsed on the host +host_tick_rate 45268689 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 344777955 # Number of instructions simulated sim_seconds 0.215423 # Number of seconds simulated @@ -37,6 +37,9 @@ system.cpu.commit.COM:committed_per_cycle::min_value 0 system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::total 417225954 # Number of insts commited each cycle system.cpu.commit.COM:count 344777955 # Number of instructions committed +system.cpu.commit.COM:fp_insts 114216705 # Number of committed floating point instructions. +system.cpu.commit.COM:function_calls 0 # Number of function calls committed. +system.cpu.commit.COM:int_insts 283262899 # Number of committed integer instructions. system.cpu.commit.COM:loads 94652977 # Number of loads committed system.cpu.commit.COM:membars 0 # Number of memory barriers committed system.cpu.commit.COM:refs 177028572 # Number of memory references committed @@ -171,6 +174,8 @@ system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Nu system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::total 430736614 # Number of instructions fetched each cycle (Total) +system.cpu.fp_regfile_reads 185889152 # number of floating regfile reads +system.cpu.fp_regfile_writes 130863264 # number of floating regfile writes system.cpu.icache.ReadReq_accesses 45676058 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_avg_miss_latency 11498.094859 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 7998.634691 # average ReadReq mshr miss latency @@ -270,6 +275,8 @@ system.cpu.iew.lsq.thread.0.squashedStores 11245258 # system.cpu.iew.memOrderViolationEvents 6487 # Number of memory order violations system.cpu.iew.predictedNotTakenIncorrect 2859204 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedTakenIncorrect 7562654 # Number of branches that were predicted taken incorrectly +system.cpu.int_regfile_reads 857434842 # number of integer regfile reads +system.cpu.int_regfile_writes 187420899 # number of integer regfile writes system.cpu.ipc 0.800235 # IPC: Instructions Per Cycle system.cpu.ipc_total 0.800235 # IPC: Total IPC of All Threads system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued @@ -361,6 +368,14 @@ system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::total 430736614 # Number of insts issued each cycle system.cpu.iq.ISSUE:rate 0.876078 # Inst issue rate +system.cpu.iq.fp_alu_accesses 122762429 # Number of floating point alu accesses +system.cpu.iq.fp_inst_queue_reads 242026964 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_wakeup_accesses 116081453 # Number of floating instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_writes 130324765 # Number of floating instruction queue writes +system.cpu.iq.int_alu_accesses 261691284 # Number of integer alu accesses +system.cpu.iq.int_inst_queue_reads 951420966 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_wakeup_accesses 249709151 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_writes 308466887 # Number of integer instruction queue writes system.cpu.iq.iqInstsAdded 389801085 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqInstsIssued 377454477 # Number of instructions issued system.cpu.iq.iqNonSpecInstsAdded 3540937 # Number of non-speculative instructions added to the IQ @@ -463,7 +478,11 @@ system.cpu.memDep0.conflictingLoads 34606299 # Nu system.cpu.memDep0.conflictingStores 43565672 # Number of conflicting stores. system.cpu.memDep0.insertedLoads 108215524 # Number of loads inserted to the mem dependence unit. system.cpu.memDep0.insertedStores 93620853 # Number of stores inserted to the mem dependence unit. +system.cpu.misc_regfile_reads 1021297951 # number of misc regfile reads +system.cpu.misc_regfile_writes 43097547 # number of misc regfile writes system.cpu.numCycles 430845860 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.rename.RENAME:BlockCycles 2009946 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 340171955 # Number of HB maps that are committed system.cpu.rename.RENAME:IQFullEvents 2410 # Number of times rename has blocked due to IQ full @@ -476,10 +495,14 @@ system.cpu.rename.RENAME:RunCycles 159405057 # Nu system.cpu.rename.RENAME:SquashCycles 13510660 # Number of cycles rename is squashing system.cpu.rename.RENAME:UnblockCycles 15892138 # Number of cycles rename is unblocking system.cpu.rename.RENAME:UndoneMaps 73676716 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:fp_rename_lookups 836456573 # Number of floating rename lookups +system.cpu.rename.RENAME:int_rename_lookups 842367236 # Number of integer rename lookups system.cpu.rename.RENAME:serializeStallCycles 117198109 # count of cycles rename stalled for serializing inst system.cpu.rename.RENAME:serializingInsts 12788197 # count of serializing insts renamed system.cpu.rename.RENAME:skidInsts 37692287 # count of insts added to the skid buffer system.cpu.rename.RENAME:tempSerializingInsts 3543781 # count of temporary serializing insts renamed +system.cpu.rob.rob_reads 805385527 # The number of ROB reads +system.cpu.rob.rob_writes 800205983 # The number of ROB writes system.cpu.timesIdled 2211 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 191 # Number of system calls diff --git a/tests/long/30.eon/ref/arm/linux/simple-atomic/config.ini b/tests/long/30.eon/ref/arm/linux/simple-atomic/config.ini index ac380ff0f..a5b41f00b 100644 --- a/tests/long/30.eon/ref/arm/linux/simple-atomic/config.ini +++ b/tests/long/30.eon/ref/arm/linux/simple-atomic/config.ini @@ -1,13 +1,22 @@ [root] type=Root children=system -dummy=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem mem_mode=atomic physmem=system.physmem +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 [system.cpu] type=AtomicSimpleCPU @@ -52,12 +61,12 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook -cwd=build/ARM_SE/tests/opt/long/30.eon/arm/linux/simple-atomic +cwd=build/ARM_SE/tests/fast/long/30.eon/arm/linux/simple-atomic egid=100 env= errout=cerr euid=100 -executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/eon +executable=/dist/m5/cpu2000/binaries/arm/linux/eon gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/30.eon/ref/arm/linux/simple-atomic/simout b/tests/long/30.eon/ref/arm/linux/simple-atomic/simout index f5391da34..934921226 100755 --- a/tests/long/30.eon/ref/arm/linux/simple-atomic/simout +++ b/tests/long/30.eon/ref/arm/linux/simple-atomic/simout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Oct 11 2010 18:37:23 -M5 revision c4e3d74d9a68 7726 default ext/mp_boot.patch qtip tip -M5 started Oct 11 2010 19:19:59 -M5 executing on aus-bc3-b4 -command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/30.eon/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/opt/long/30.eon/arm/linux/simple-atomic +M5 compiled Feb 7 2011 01:56:16 +M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip +M5 started Feb 7 2011 01:56:25 +M5 executing on burrito +command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/30.eon/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/fast/long/30.eon/arm/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/long/30.eon/ref/arm/linux/simple-atomic/stats.txt b/tests/long/30.eon/ref/arm/linux/simple-atomic/stats.txt index 4b61fce38..f26b1f1eb 100644 --- a/tests/long/30.eon/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/30.eon/ref/arm/linux/simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 2280191 # Simulator instruction rate (inst/s) -host_mem_usage 262416 # Number of bytes of host memory used -host_seconds 151.21 # Real time elapsed on the host -host_tick_rate 1390158822 # Simulator tick rate (ticks/s) +host_inst_rate 829275 # Simulator instruction rate (inst/s) +host_mem_usage 237784 # Number of bytes of host memory used +host_seconds 415.76 # Real time elapsed on the host +host_tick_rate 505582613 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 344777955 # Number of instructions simulated sim_seconds 0.210200 # Number of seconds simulated @@ -53,8 +53,24 @@ system.cpu.itb.write_hits 0 # DT system.cpu.itb.write_misses 0 # DTB write misses system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.numCycles 420400644 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.num_busy_cycles 420400644 # Number of busy cycles +system.cpu.num_conditional_control_insts 0 # number of instructions that are conditional controls +system.cpu.num_fp_alu_accesses 114216705 # Number of float alu accesses +system.cpu.num_fp_insts 114216705 # number of float instructions +system.cpu.num_fp_register_reads 180262959 # number of times the floating registers were read +system.cpu.num_fp_register_writes 126152315 # number of times the floating registers were written +system.cpu.num_func_calls 0 # number of times a function call or return occured +system.cpu.num_idle_cycles 0 # Number of idle cycles system.cpu.num_insts 344777955 # Number of instructions executed -system.cpu.num_refs 177028576 # Number of memory references +system.cpu.num_int_alu_accesses 283262903 # Number of integer alu accesses +system.cpu.num_int_insts 283262903 # number of integer instructions +system.cpu.num_int_register_reads 1207980255 # number of times the integer registers were read +system.cpu.num_int_register_writes 211974282 # number of times the integer registers were written +system.cpu.num_load_insts 94652977 # Number of load instructions +system.cpu.num_mem_refs 177028576 # number of memory refs +system.cpu.num_store_insts 82375599 # Number of store instructions system.cpu.workload.PROG:num_syscalls 191 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/30.eon/ref/arm/linux/simple-timing/config.ini b/tests/long/30.eon/ref/arm/linux/simple-timing/config.ini index 3b627362e..9c15d1771 100644 --- a/tests/long/30.eon/ref/arm/linux/simple-timing/config.ini +++ b/tests/long/30.eon/ref/arm/linux/simple-timing/config.ini @@ -1,13 +1,22 @@ [root] type=Root children=system -dummy=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem mem_mode=atomic physmem=system.physmem +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 [system.cpu] type=TimingSimpleCPU @@ -152,12 +161,12 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook -cwd=build/ARM_SE/tests/opt/long/30.eon/arm/linux/simple-timing +cwd=build/ARM_SE/tests/fast/long/30.eon/arm/linux/simple-timing egid=100 env= errout=cerr euid=100 -executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/eon +executable=/dist/m5/cpu2000/binaries/arm/linux/eon gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/30.eon/ref/arm/linux/simple-timing/simerr b/tests/long/30.eon/ref/arm/linux/simple-timing/simerr index 0de362399..fc990d9e5 100755 --- a/tests/long/30.eon/ref/arm/linux/simple-timing/simerr +++ b/tests/long/30.eon/ref/arm/linux/simple-timing/simerr @@ -1,12 +1,20 @@ warn: Sockets disabled, not accepting gdb connections For more information see: http://www.m5sim.org/warn/d946bea6 +warn: Complete acc isn't called on normal stores in O3. +For more information see: http://www.m5sim.org/warn/138d8573 +warn: Complete acc isn't called on normal stores in O3. +For more information see: http://www.m5sim.org/warn/138d8573 getting pixel output filename pixels_out.cook opening control file chair.control.cook opening camera file chair.camera opening surfaces file chair.surfaces reading data processing 8parts -Grid measure is 6 by 3.0001 by 6 +Grid measure is warn: Complete acc isn't called on normal stores in O3. +For more information see: http://www.m5sim.org/warn/138d8573 +warn: Complete acc isn't called on normal stores in O3. +For more information see: http://www.m5sim.org/warn/138d8573 +6 by 3.0001 by 6 cell dimension is 0.863065 Creating grid for list of length 21 Grid size = 7 by 4 by 7 diff --git a/tests/long/30.eon/ref/arm/linux/simple-timing/simout b/tests/long/30.eon/ref/arm/linux/simple-timing/simout index 26d019ac6..1f52687a3 100755 --- a/tests/long/30.eon/ref/arm/linux/simple-timing/simout +++ b/tests/long/30.eon/ref/arm/linux/simple-timing/simout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Oct 11 2010 18:37:23 -M5 revision c4e3d74d9a68 7726 default ext/mp_boot.patch qtip tip -M5 started Oct 11 2010 19:23:59 -M5 executing on aus-bc3-b4 -command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/30.eon/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/opt/long/30.eon/arm/linux/simple-timing +M5 compiled Feb 7 2011 01:56:16 +M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip +M5 started Feb 7 2011 02:00:13 +M5 executing on burrito +command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/30.eon/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/fast/long/30.eon/arm/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/long/30.eon/ref/arm/linux/simple-timing/stats.txt b/tests/long/30.eon/ref/arm/linux/simple-timing/stats.txt index 9ac8b63de..b6636f892 100644 --- a/tests/long/30.eon/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/30.eon/ref/arm/linux/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 520438 # Simulator instruction rate (inst/s) -host_mem_usage 270128 # Number of bytes of host memory used -host_seconds 661.75 # Real time elapsed on the host -host_tick_rate 794599336 # Simulator tick rate (ticks/s) +host_inst_rate 394687 # Simulator instruction rate (inst/s) +host_mem_usage 245492 # Number of bytes of host memory used +host_seconds 872.59 # Real time elapsed on the host +host_tick_rate 602604420 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 344399678 # Number of instructions simulated sim_seconds 0.525826 # Number of seconds simulated @@ -242,8 +242,24 @@ system.cpu.l2cache.warmup_cycle 0 # Cy system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.numCycles 1051651768 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.num_busy_cycles 1051651768 # Number of busy cycles +system.cpu.num_conditional_control_insts 0 # number of instructions that are conditional controls +system.cpu.num_fp_alu_accesses 114216705 # Number of float alu accesses +system.cpu.num_fp_insts 114216705 # number of float instructions +system.cpu.num_fp_register_reads 180262959 # number of times the floating registers were read +system.cpu.num_fp_register_writes 126152315 # number of times the floating registers were written +system.cpu.num_func_calls 0 # number of times a function call or return occured +system.cpu.num_idle_cycles 0 # Number of idle cycles system.cpu.num_insts 344399678 # Number of instructions executed -system.cpu.num_refs 177028576 # Number of memory references +system.cpu.num_int_alu_accesses 283262902 # Number of integer alu accesses +system.cpu.num_int_insts 283262902 # number of integer instructions +system.cpu.num_int_register_reads 1344047799 # number of times the integer registers were read +system.cpu.num_int_register_writes 212263713 # number of times the integer registers were written +system.cpu.num_load_insts 94652977 # Number of load instructions +system.cpu.num_mem_refs 177028576 # number of memory refs +system.cpu.num_store_insts 82375599 # Number of store instructions system.cpu.workload.PROG:num_syscalls 191 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini b/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini index cbf5155cb..be2448eae 100644 --- a/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini @@ -1,13 +1,22 @@ [root] type=Root children=system -dummy=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem mem_mode=atomic physmem=system.physmem +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 [system.cpu] type=DerivO3CPU diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/simout b/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/simout index 7d9e000fc..79d6b4e40 100755 --- a/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jan 17 2011 16:24:53 -M5 revision f72d94f8c275 7839 default qtip tip outgoing.patch qbase -M5 started Jan 17 2011 16:24:57 -M5 executing on zizzer +M5 compiled Feb 7 2011 01:47:18 +M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip +M5 started Feb 7 2011 01:47:38 +M5 executing on burrito command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt index 63c7a2e36..375e28f85 100644 --- a/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 156459 # Simulator instruction rate (inst/s) -host_mem_usage 213156 # Number of bytes of host memory used -host_seconds 11651.86 # Real time elapsed on the host -host_tick_rate 60063670 # Simulator tick rate (ticks/s) +host_inst_rate 179836 # Simulator instruction rate (inst/s) +host_mem_usage 233568 # Number of bytes of host memory used +host_seconds 10137.27 # Real time elapsed on the host +host_tick_rate 69037678 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1823043370 # Number of instructions simulated sim_seconds 0.699854 # Number of seconds simulated @@ -37,6 +37,9 @@ system.cpu.commit.COM:committed_per_cycle::min_value 0 system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::total 1301001982 # Number of insts commited each cycle system.cpu.commit.COM:count 2008987604 # Number of instructions committed +system.cpu.commit.COM:fp_insts 71824891 # Number of committed floating point instructions. +system.cpu.commit.COM:function_calls 39955347 # Number of function calls committed. +system.cpu.commit.COM:int_insts 1778941351 # Number of committed integer instructions. system.cpu.commit.COM:loads 511070026 # Number of loads committed system.cpu.commit.COM:membars 0 # Number of memory barriers committed system.cpu.commit.COM:refs 721864922 # Number of memory references committed @@ -171,6 +174,8 @@ system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Nu system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::total 1399572740 # Number of instructions fetched each cycle (Total) +system.cpu.fp_regfile_reads 79145201 # number of floating regfile reads +system.cpu.fp_regfile_writes 52656290 # number of floating regfile writes system.cpu.icache.ReadReq_accesses 346350693 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_avg_miss_latency 15859.786377 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 11646.165644 # average ReadReq mshr miss latency @@ -270,6 +275,8 @@ system.cpu.iew.lsq.thread.0.squashedStores 92047647 # system.cpu.iew.memOrderViolationEvents 3569 # Number of memory order violations system.cpu.iew.predictedNotTakenIncorrect 787992 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedTakenIncorrect 30086110 # Number of branches that were predicted taken incorrectly +system.cpu.int_regfile_reads 2538504149 # number of integer regfile reads +system.cpu.int_regfile_writes 1455287800 # number of integer regfile writes system.cpu.ipc 1.302446 # IPC: Instructions Per Cycle system.cpu.ipc_total 1.302446 # IPC: Total IPC of All Threads system.cpu.iq.ISSUE:FU_type_0::No_OpClass 2752 0.00% 0.00% # Type of FU issued @@ -361,6 +368,14 @@ system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::total 1399572740 # Number of insts issued each cycle system.cpu.iq.ISSUE:rate 1.488357 # Inst issue rate +system.cpu.iq.fp_alu_accesses 76224315 # Number of floating point alu accesses +system.cpu.iq.fp_inst_queue_reads 150190709 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_wakeup_accesses 73940522 # Number of floating instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_writes 77634670 # Number of floating instruction queue writes +system.cpu.iq.int_alu_accesses 2044010329 # Number of integer alu accesses +system.cpu.iq.int_inst_queue_reads 5465284170 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_wakeup_accesses 1924287563 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_writes 2854317928 # Number of integer instruction queue writes system.cpu.iq.iqInstsAdded 2377509698 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqInstsIssued 2083264453 # Number of instructions issued system.cpu.iq.iqNonSpecInstsAdded 67 # Number of non-speculative instructions added to the IQ @@ -457,7 +472,11 @@ system.cpu.memDep0.conflictingLoads 118268475 # Nu system.cpu.memDep0.conflictingStores 21018090 # Number of conflicting stores. system.cpu.memDep0.insertedLoads 651766159 # Number of loads inserted to the mem dependence unit. system.cpu.memDep0.insertedStores 302842543 # Number of stores inserted to the mem dependence unit. +system.cpu.misc_regfile_reads 1 # number of misc regfile reads +system.cpu.misc_regfile_writes 1 # number of misc regfile writes system.cpu.numCycles 1399707092 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.rename.RENAME:BlockCycles 19659094 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 1384969070 # Number of HB maps that are committed system.cpu.rename.RENAME:IQFullEvents 672257 # Number of times rename has blocked due to IQ full @@ -471,10 +490,14 @@ system.cpu.rename.RENAME:RunCycles 542782008 # Nu system.cpu.rename.RENAME:SquashCycles 98570758 # Number of cycles rename is squashing system.cpu.rename.RENAME:UnblockCycles 13186877 # Number of cycles rename is unblocking system.cpu.rename.RENAME:UndoneMaps 495793350 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:fp_rename_lookups 113413742 # Number of floating rename lookups +system.cpu.rename.RENAME:int_rename_lookups 3181273204 # Number of integer rename lookups system.cpu.rename.RENAME:serializeStallCycles 21539 # count of cycles rename stalled for serializing inst system.cpu.rename.RENAME:serializingInsts 2826 # count of serializing insts renamed system.cpu.rename.RENAME:skidInsts 26818332 # count of insts added to the skid buffer system.cpu.rename.RENAME:tempSerializingInsts 73 # count of temporary serializing insts renamed +system.cpu.rob.rob_reads 3921848396 # The number of ROB reads +system.cpu.rob.rob_writes 5489856325 # The number of ROB writes system.cpu.timesIdled 3665 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 39 # Number of system calls diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/config.ini index 233f88432..f80631f28 100644 --- a/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/config.ini +++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/config.ini @@ -1,13 +1,22 @@ [root] type=Root children=system -dummy=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem mem_mode=atomic physmem=system.physmem +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 [system.cpu] type=AtomicSimpleCPU @@ -57,7 +66,7 @@ egid=100 env= errout=cerr euid=100 -executable=/chips/pd/randd/dist/cpu2000/binaries/alpha/tru64/perlbmk +executable=/dist/m5/cpu2000/binaries/alpha/tru64/perlbmk gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/simerr b/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/simerr index 1fdd222af..abaf1cb79 100755 --- a/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/simerr +++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/simerr @@ -1,5 +1,11 @@ warn: Sockets disabled, not accepting gdb connections For more information see: http://www.m5sim.org/warn/d946bea6 +warn: Prefetch instrutions is Alpha do not do anything +For more information see: http://www.m5sim.org/warn/3e0eccba +warn: Prefetch instrutions is Alpha do not do anything +For more information see: http://www.m5sim.org/warn/3e0eccba +warn: Prefetch instrutions is Alpha do not do anything +For more information see: http://www.m5sim.org/warn/3e0eccba warn: ignoring syscall sigprocmask(0, 1, ...) For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...) diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/simout b/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/simout index 7fa3cc9e1..b7ecd550d 100755 --- a/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/simout +++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/simout @@ -1,5 +1,3 @@ -Redirecting stdout to build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/simple-atomic/simout -Redirecting stderr to build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/simple-atomic/simerr M5 Simulator System Copyright (c) 2001-2008 @@ -7,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Nov 2 2010 21:30:55 -M5 revision 0af3760102ec+ 7713+ default qtip ext/alpha_prefetch.patch tip -M5 started Nov 2 2010 21:59:54 -M5 executing on aus-bc2-b15 +M5 compiled Feb 7 2011 01:47:18 +M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip +M5 started Feb 7 2011 01:47:37 +M5 executing on burrito command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt index c5afc67b3..855c5964e 100644 --- a/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt +++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 5515431 # Simulator instruction rate (inst/s) -host_mem_usage 238276 # Number of bytes of host memory used -host_seconds 364.25 # Real time elapsed on the host -host_tick_rate 2758309260 # Simulator tick rate (ticks/s) +host_inst_rate 1477901 # Simulator instruction rate (inst/s) +host_mem_usage 224424 # Number of bytes of host memory used +host_seconds 1359.35 # Real time elapsed on the host +host_tick_rate 739109964 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 2008987605 # Number of instructions simulated sim_seconds 1.004711 # Number of seconds simulated @@ -43,8 +43,24 @@ system.cpu.itb.write_hits 0 # DT system.cpu.itb.write_misses 0 # DTB write misses system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.numCycles 2009421175 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.num_busy_cycles 2009421175 # Number of busy cycles +system.cpu.num_conditional_control_insts 172959296 # number of instructions that are conditional controls +system.cpu.num_fp_alu_accesses 71831671 # Number of float alu accesses +system.cpu.num_fp_insts 71831671 # number of float instructions +system.cpu.num_fp_register_reads 77066699 # number of times the floating registers were read +system.cpu.num_fp_register_writes 52280770 # number of times the floating registers were written +system.cpu.num_func_calls 79910682 # number of times a function call or return occured +system.cpu.num_idle_cycles 0 # Number of idle cycles system.cpu.num_insts 2008987605 # Number of instructions executed -system.cpu.num_refs 722298387 # Number of memory references +system.cpu.num_int_alu_accesses 1779374816 # Number of integer alu accesses +system.cpu.num_int_insts 1779374816 # number of integer instructions +system.cpu.num_int_register_reads 2314712013 # number of times the integer registers were read +system.cpu.num_int_register_writes 1332688300 # number of times the integer registers were written +system.cpu.num_load_insts 511488910 # Number of load instructions +system.cpu.num_mem_refs 722298387 # number of memory refs +system.cpu.num_store_insts 210809477 # Number of store instructions system.cpu.workload.PROG:num_syscalls 39 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini index f0aef1670..9be1cb679 100644 --- a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini @@ -1,13 +1,22 @@ [root] type=Root children=system -dummy=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem mem_mode=atomic physmem=system.physmem +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 [system.cpu] type=TimingSimpleCPU @@ -157,7 +166,7 @@ egid=100 env= errout=cerr euid=100 -executable=/chips/pd/randd/dist/cpu2000/binaries/alpha/tru64/perlbmk +executable=/dist/m5/cpu2000/binaries/alpha/tru64/perlbmk gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/simerr b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/simerr index 1fdd222af..abaf1cb79 100755 --- a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/simerr +++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/simerr @@ -1,5 +1,11 @@ warn: Sockets disabled, not accepting gdb connections For more information see: http://www.m5sim.org/warn/d946bea6 +warn: Prefetch instrutions is Alpha do not do anything +For more information see: http://www.m5sim.org/warn/3e0eccba +warn: Prefetch instrutions is Alpha do not do anything +For more information see: http://www.m5sim.org/warn/3e0eccba +warn: Prefetch instrutions is Alpha do not do anything +For more information see: http://www.m5sim.org/warn/3e0eccba warn: ignoring syscall sigprocmask(0, 1, ...) For more information see: http://www.m5sim.org/warn/5c5b547f warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...) diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/simout b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/simout index fcac3af61..03731b56d 100755 --- a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/simout +++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/simout @@ -1,5 +1,3 @@ -Redirecting stdout to build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/simple-timing/simout -Redirecting stderr to build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/simple-timing/simerr M5 Simulator System Copyright (c) 2001-2008 @@ -7,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Nov 2 2010 21:30:55 -M5 revision 0af3760102ec+ 7713+ default qtip ext/alpha_prefetch.patch tip -M5 started Nov 2 2010 22:06:01 -M5 executing on aus-bc2-b15 +M5 compiled Feb 7 2011 01:47:18 +M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip +M5 started Feb 7 2011 01:47:38 +M5 executing on burrito command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt index 0d35bbf18..c88cbd8f6 100644 --- a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 2134538 # Simulator instruction rate (inst/s) -host_mem_usage 246068 # Number of bytes of host memory used -host_seconds 941.18 # Real time elapsed on the host -host_tick_rate 2989292617 # Simulator tick rate (ticks/s) +host_inst_rate 584935 # Simulator instruction rate (inst/s) +host_mem_usage 232204 # Number of bytes of host memory used +host_seconds 3434.55 # Real time elapsed on the host +host_tick_rate 819166202 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 2008987605 # Number of instructions simulated sim_seconds 2.813468 # Number of seconds simulated @@ -232,8 +232,24 @@ system.cpu.l2cache.warmup_cycle 0 # Cy system.cpu.l2cache.writebacks 66898 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.numCycles 5626935684 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.num_busy_cycles 5626935684 # Number of busy cycles +system.cpu.num_conditional_control_insts 172959296 # number of instructions that are conditional controls +system.cpu.num_fp_alu_accesses 71831671 # Number of float alu accesses +system.cpu.num_fp_insts 71831671 # number of float instructions +system.cpu.num_fp_register_reads 77066699 # number of times the floating registers were read +system.cpu.num_fp_register_writes 52280770 # number of times the floating registers were written +system.cpu.num_func_calls 79910682 # number of times a function call or return occured +system.cpu.num_idle_cycles 0 # Number of idle cycles system.cpu.num_insts 2008987605 # Number of instructions executed -system.cpu.num_refs 722298387 # Number of memory references +system.cpu.num_int_alu_accesses 1779374816 # Number of integer alu accesses +system.cpu.num_int_insts 1779374816 # number of integer instructions +system.cpu.num_int_register_reads 2314712013 # number of times the integer registers were read +system.cpu.num_int_register_writes 1332688300 # number of times the integer registers were written +system.cpu.num_load_insts 511488910 # Number of load instructions +system.cpu.num_mem_refs 722298387 # number of memory refs +system.cpu.num_store_insts 210809477 # Number of store instructions system.cpu.workload.PROG:num_syscalls 39 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/40.perlbmk/ref/arm/linux/o3-timing/config.ini b/tests/long/40.perlbmk/ref/arm/linux/o3-timing/config.ini index 0ccefb2ad..3820d828c 100644 --- a/tests/long/40.perlbmk/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/40.perlbmk/ref/arm/linux/o3-timing/config.ini @@ -1,13 +1,22 @@ [root] type=Root children=system -dummy=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem mem_mode=atomic physmem=system.physmem +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 [system.cpu] type=DerivO3CPU @@ -484,7 +493,7 @@ egid=100 env= errout=cerr euid=100 -executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/perlbmk +executable=/dist/m5/cpu2000/binaries/arm/linux/perlbmk gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/40.perlbmk/ref/arm/linux/o3-timing/simout b/tests/long/40.perlbmk/ref/arm/linux/o3-timing/simout index 32de132ae..ddea5239d 100755 --- a/tests/long/40.perlbmk/ref/arm/linux/o3-timing/simout +++ b/tests/long/40.perlbmk/ref/arm/linux/o3-timing/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jan 11 2011 18:16:01 -M5 revision b39a8457b332 7816 default ext/o3_regressions.patch qtip tip -M5 started Jan 12 2011 03:34:31 -M5 executing on u200439-lin.austin.arm.com +M5 compiled Feb 7 2011 01:56:16 +M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip +M5 started Feb 7 2011 02:00:50 +M5 executing on burrito command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/40.perlbmk/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/fast/long/40.perlbmk/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/40.perlbmk/ref/arm/linux/o3-timing/stats.txt b/tests/long/40.perlbmk/ref/arm/linux/o3-timing/stats.txt index 46557403f..a1dda945d 100644 --- a/tests/long/40.perlbmk/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/40.perlbmk/ref/arm/linux/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 126560 # Simulator instruction rate (inst/s) -host_mem_usage 258084 # Number of bytes of host memory used -host_seconds 14568.38 # Real time elapsed on the host -host_tick_rate 75985562 # Simulator tick rate (ticks/s) +host_inst_rate 139604 # Simulator instruction rate (inst/s) +host_mem_usage 244852 # Number of bytes of host memory used +host_seconds 13207.13 # Real time elapsed on the host +host_tick_rate 83817309 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1843766922 # Number of instructions simulated sim_seconds 1.106986 # Number of seconds simulated @@ -37,6 +37,9 @@ system.cpu.commit.COM:committed_per_cycle::min_value 0 system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::total 2026425019 # Number of insts commited each cycle system.cpu.commit.COM:count 1843766922 # Number of instructions committed +system.cpu.commit.COM:fp_insts 52289415 # Number of committed floating point instructions. +system.cpu.commit.COM:function_calls 0 # Number of function calls committed. +system.cpu.commit.COM:int_insts 1619025870 # Number of committed integer instructions. system.cpu.commit.COM:loads 631405848 # Number of loads committed system.cpu.commit.COM:membars 0 # Number of memory barriers committed system.cpu.commit.COM:refs 908401145 # Number of memory references committed @@ -171,6 +174,8 @@ system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Nu system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::total 2213708436 # Number of instructions fetched each cycle (Total) +system.cpu.fp_regfile_reads 66048246 # number of floating regfile reads +system.cpu.fp_regfile_writes 52282096 # number of floating regfile writes system.cpu.icache.ReadReq_accesses 400588369 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_avg_miss_latency 8967.410787 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 5871.276669 # average ReadReq mshr miss latency @@ -270,6 +275,8 @@ system.cpu.iew.lsq.thread.0.squashedStores 210074657 # system.cpu.iew.memOrderViolationEvents 2755264 # Number of memory order violations system.cpu.iew.predictedNotTakenIncorrect 45730558 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedTakenIncorrect 48147488 # Number of branches that were predicted taken incorrectly +system.cpu.int_regfile_reads 5403725947 # number of integer regfile reads +system.cpu.int_regfile_writes 1668305359 # number of integer regfile writes system.cpu.ipc 0.832787 # IPC: Instructions Per Cycle system.cpu.ipc_total 0.832787 # IPC: Total IPC of All Threads system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued @@ -361,6 +368,14 @@ system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::total 2213708436 # Number of insts issued each cycle system.cpu.iq.ISSUE:rate 1.104443 # Inst issue rate +system.cpu.iq.fp_alu_accesses 64689412 # Number of floating point alu accesses +system.cpu.iq.fp_inst_queue_reads 126628637 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_wakeup_accesses 56420382 # Number of floating instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_writes 101846831 # Number of floating instruction queue writes +system.cpu.iq.int_alu_accesses 2441240602 # Number of integer alu accesses +system.cpu.iq.int_inst_queue_reads 7046560079 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_wakeup_accesses 2188392805 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_writes 4055397012 # Number of integer instruction queue writes system.cpu.iq.iqInstsAdded 3002770977 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqInstsIssued 2445205760 # Number of instructions issued system.cpu.iq.iqNonSpecInstsAdded 9835077 # Number of non-speculative instructions added to the IQ @@ -470,7 +485,11 @@ system.cpu.memDep0.conflictingLoads 48375882 # Nu system.cpu.memDep0.conflictingStores 167873780 # Number of conflicting stores. system.cpu.memDep0.insertedLoads 976823890 # Number of loads inserted to the mem dependence unit. system.cpu.memDep0.insertedStores 487069954 # Number of stores inserted to the mem dependence unit. +system.cpu.misc_regfile_reads 4207984120 # number of misc regfile reads +system.cpu.misc_regfile_writes 14227476 # number of misc regfile writes system.cpu.numCycles 2213972582 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.rename.RENAME:BlockCycles 17658494 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 1482327508 # Number of HB maps that are committed system.cpu.rename.RENAME:IQFullEvents 4825678 # Number of times rename has blocked due to IQ full @@ -484,10 +503,14 @@ system.cpu.rename.RENAME:RunCycles 880460602 # Nu system.cpu.rename.RENAME:SquashCycles 187283417 # Number of cycles rename is squashing system.cpu.rename.RENAME:UnblockCycles 23975327 # Number of cycles rename is unblocking system.cpu.rename.RENAME:UndoneMaps 1203658997 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:fp_rename_lookups 485863672 # Number of floating rename lookups +system.cpu.rename.RENAME:int_rename_lookups 8770011391 # Number of integer rename lookups system.cpu.rename.RENAME:serializeStallCycles 185210215 # count of cycles rename stalled for serializing inst system.cpu.rename.RENAME:serializingInsts 19466962 # count of serializing insts renamed system.cpu.rename.RENAME:skidInsts 226114375 # count of insts added to the skid buffer system.cpu.rename.RENAME:tempSerializingInsts 13965391 # count of temporary serializing insts renamed +system.cpu.rob.rob_reads 4997592572 # The number of ROB reads +system.cpu.rob.rob_writes 6212467818 # The number of ROB writes system.cpu.timesIdled 87015 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 1411 # Number of system calls diff --git a/tests/long/40.perlbmk/ref/arm/linux/simple-atomic/config.ini b/tests/long/40.perlbmk/ref/arm/linux/simple-atomic/config.ini index ecd3fff8c..97cb6c6e4 100644 --- a/tests/long/40.perlbmk/ref/arm/linux/simple-atomic/config.ini +++ b/tests/long/40.perlbmk/ref/arm/linux/simple-atomic/config.ini @@ -1,13 +1,22 @@ [root] type=Root children=system -dummy=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem mem_mode=atomic physmem=system.physmem +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 [system.cpu] type=AtomicSimpleCPU @@ -52,12 +61,12 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=perlbmk -I. -I lib lgred.makerand.pl -cwd=build/ARM_SE/tests/opt/long/40.perlbmk/arm/linux/simple-atomic +cwd=build/ARM_SE/tests/fast/long/40.perlbmk/arm/linux/simple-atomic egid=100 env= errout=cerr euid=100 -executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/perlbmk +executable=/dist/m5/cpu2000/binaries/arm/linux/perlbmk gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/40.perlbmk/ref/arm/linux/simple-atomic/simout b/tests/long/40.perlbmk/ref/arm/linux/simple-atomic/simout index 6f1aaca4d..e6fdba858 100755 --- a/tests/long/40.perlbmk/ref/arm/linux/simple-atomic/simout +++ b/tests/long/40.perlbmk/ref/arm/linux/simple-atomic/simout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Oct 11 2010 18:37:23 -M5 revision c4e3d74d9a68 7726 default ext/mp_boot.patch qtip tip -M5 started Oct 11 2010 19:04:52 -M5 executing on aus-bc3-b4 -command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/40.perlbmk/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/opt/long/40.perlbmk/arm/linux/simple-atomic +M5 compiled Feb 7 2011 01:56:16 +M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip +M5 started Feb 7 2011 01:56:24 +M5 executing on burrito +command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/40.perlbmk/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/fast/long/40.perlbmk/arm/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/long/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt b/tests/long/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt index 62cb1fa61..807917422 100644 --- a/tests/long/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 2747008 # Simulator instruction rate (inst/s) -host_mem_usage 259372 # Number of bytes of host memory used -host_seconds 671.19 # Real time elapsed on the host -host_tick_rate 1377891283 # Simulator tick rate (ticks/s) +host_inst_rate 966272 # Simulator instruction rate (inst/s) +host_mem_usage 234680 # Number of bytes of host memory used +host_seconds 1908.12 # Real time elapsed on the host +host_tick_rate 484679459 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1843766922 # Number of instructions simulated sim_seconds 0.924828 # Number of seconds simulated @@ -53,8 +53,24 @@ system.cpu.itb.write_hits 0 # DT system.cpu.itb.write_misses 0 # DTB write misses system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.numCycles 1849656818 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.num_busy_cycles 1849656818 # Number of busy cycles +system.cpu.num_conditional_control_insts 0 # number of instructions that are conditional controls +system.cpu.num_fp_alu_accesses 52289415 # Number of float alu accesses +system.cpu.num_fp_insts 52289415 # number of float instructions +system.cpu.num_fp_register_reads 60540850 # number of times the floating registers were read +system.cpu.num_fp_register_writes 46777010 # number of times the floating registers were written +system.cpu.num_func_calls 0 # number of times a function call or return occured +system.cpu.num_idle_cycles 0 # Number of idle cycles system.cpu.num_insts 1843766922 # Number of instructions executed -system.cpu.num_refs 908401146 # Number of memory references +system.cpu.num_int_alu_accesses 1619025871 # Number of integer alu accesses +system.cpu.num_int_insts 1619025871 # number of integer instructions +system.cpu.num_int_register_reads 4830749754 # number of times the integer registers were read +system.cpu.num_int_register_writes 1365217022 # number of times the integer registers were written +system.cpu.num_load_insts 631405848 # Number of load instructions +system.cpu.num_mem_refs 908401146 # number of memory refs +system.cpu.num_store_insts 276995298 # Number of store instructions system.cpu.workload.PROG:num_syscalls 1411 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/40.perlbmk/ref/arm/linux/simple-timing/config.ini b/tests/long/40.perlbmk/ref/arm/linux/simple-timing/config.ini index 32ec6dcf7..dfd8de545 100644 --- a/tests/long/40.perlbmk/ref/arm/linux/simple-timing/config.ini +++ b/tests/long/40.perlbmk/ref/arm/linux/simple-timing/config.ini @@ -1,13 +1,22 @@ [root] type=Root children=system -dummy=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem mem_mode=atomic physmem=system.physmem +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 [system.cpu] type=TimingSimpleCPU @@ -152,12 +161,12 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=perlbmk -I. -I lib lgred.makerand.pl -cwd=build/ARM_SE/tests/opt/long/40.perlbmk/arm/linux/simple-timing +cwd=build/ARM_SE/tests/fast/long/40.perlbmk/arm/linux/simple-timing egid=100 env= errout=cerr euid=100 -executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/perlbmk +executable=/dist/m5/cpu2000/binaries/arm/linux/perlbmk gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/40.perlbmk/ref/arm/linux/simple-timing/simerr b/tests/long/40.perlbmk/ref/arm/linux/simple-timing/simerr index 805a6606f..d834843e9 100755 --- a/tests/long/40.perlbmk/ref/arm/linux/simple-timing/simerr +++ b/tests/long/40.perlbmk/ref/arm/linux/simple-timing/simerr @@ -1,5 +1,11 @@ warn: Sockets disabled, not accepting gdb connections For more information see: http://www.m5sim.org/warn/d946bea6 +warn: Complete acc isn't called on normal stores in O3. +For more information see: http://www.m5sim.org/warn/138d8573 +warn: Complete acc isn't called on normal stores in O3. +For more information see: http://www.m5sim.org/warn/138d8573 +warn: Complete acc isn't called on normal stores in O3. +For more information see: http://www.m5sim.org/warn/138d8573 warn: fcntl64(3, 2) passed through to host For more information see: http://www.m5sim.org/warn/a55e2c46 hack: be nice to actually delete the event here diff --git a/tests/long/40.perlbmk/ref/arm/linux/simple-timing/simout b/tests/long/40.perlbmk/ref/arm/linux/simple-timing/simout index 850a4596a..b556adbf3 100755 --- a/tests/long/40.perlbmk/ref/arm/linux/simple-timing/simout +++ b/tests/long/40.perlbmk/ref/arm/linux/simple-timing/simout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Oct 11 2010 18:37:23 -M5 revision c4e3d74d9a68 7726 default ext/mp_boot.patch qtip tip -M5 started Oct 11 2010 18:41:18 -M5 executing on aus-bc3-b4 -command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/40.perlbmk/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/opt/long/40.perlbmk/arm/linux/simple-timing +M5 compiled Feb 7 2011 01:56:16 +M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip +M5 started Feb 7 2011 01:56:25 +M5 executing on burrito +command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/40.perlbmk/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/fast/long/40.perlbmk/arm/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/long/40.perlbmk/ref/arm/linux/simple-timing/stats.txt b/tests/long/40.perlbmk/ref/arm/linux/simple-timing/stats.txt index 2158e673a..1e3225702 100644 --- a/tests/long/40.perlbmk/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/40.perlbmk/ref/arm/linux/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 628678 # Simulator instruction rate (inst/s) -host_mem_usage 267092 # Number of bytes of host memory used -host_seconds 2915.13 # Real time elapsed on the host -host_tick_rate 812964589 # Simulator tick rate (ticks/s) +host_inst_rate 494422 # Simulator instruction rate (inst/s) +host_mem_usage 242392 # Number of bytes of host memory used +host_seconds 3706.70 # Real time elapsed on the host +host_tick_rate 639353926 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1832675505 # Number of instructions simulated sim_seconds 2.369896 # Number of seconds simulated @@ -242,8 +242,24 @@ system.cpu.l2cache.warmup_cycle 0 # Cy system.cpu.l2cache.writebacks 66099 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.numCycles 4739792356 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.num_busy_cycles 4739792356 # Number of busy cycles +system.cpu.num_conditional_control_insts 0 # number of instructions that are conditional controls +system.cpu.num_fp_alu_accesses 52289415 # Number of float alu accesses +system.cpu.num_fp_insts 52289415 # number of float instructions +system.cpu.num_fp_register_reads 60540850 # number of times the floating registers were read +system.cpu.num_fp_register_writes 46777010 # number of times the floating registers were written +system.cpu.num_func_calls 0 # number of times a function call or return occured +system.cpu.num_idle_cycles 0 # Number of idle cycles system.cpu.num_insts 1832675505 # Number of instructions executed -system.cpu.num_refs 908401146 # Number of memory references +system.cpu.num_int_alu_accesses 1619025871 # Number of integer alu accesses +system.cpu.num_int_insts 1619025871 # number of integer instructions +system.cpu.num_int_register_reads 5455211671 # number of times the integer registers were read +system.cpu.num_int_register_writes 1365288731 # number of times the integer registers were written +system.cpu.num_load_insts 631405848 # Number of load instructions +system.cpu.num_mem_refs 908401146 # number of memory refs +system.cpu.num_store_insts 276995298 # Number of store instructions system.cpu.workload.PROG:num_syscalls 1411 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/config.ini b/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/config.ini index 83b3078ca..46d47f481 100644 --- a/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/config.ini +++ b/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/config.ini @@ -1,13 +1,22 @@ [root] type=Root children=system -dummy=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem mem_mode=atomic physmem=system.physmem +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 [system.cpu] type=InOrderCPU diff --git a/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/simout b/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/simout index 38b60786d..1ec8b66f1 100755 --- a/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/simout +++ b/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jan 24 2011 21:05:28 -M5 revision Unknown -M5 started Jan 24 2011 21:53:14 -M5 executing on m55-002.pool +M5 compiled Feb 7 2011 01:47:18 +M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip +M5 started Feb 7 2011 01:47:38 +M5 executing on burrito command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/inorder-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt index 827d1ba1c..d26ecb349 100644 --- a/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 68116 # Simulator instruction rate (inst/s) -host_mem_usage 1627972 # Number of bytes of host memory used -host_seconds 1296.92 # Real time elapsed on the host -host_tick_rate 33685044 # Simulator tick rate (ticks/s) +host_inst_rate 27953 # Simulator instruction rate (inst/s) +host_mem_usage 1692040 # Number of bytes of host memory used +host_seconds 3160.33 # Real time elapsed on the host +host_tick_rate 13823537 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 88340674 # Number of instructions simulated sim_seconds 0.043687 # Number of seconds simulated @@ -272,6 +272,8 @@ system.cpu.l2cache.total_refs 134496 # To system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 120516 # number of writebacks system.cpu.numCycles 87373938 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.runCycles 61786224 # Number of cycles cpu stages are processed. system.cpu.smtCommittedInsts 0 # Number of SMT Instructions Simulated (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode diff --git a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini index a73ef9125..669e84c5b 100644 --- a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini @@ -1,13 +1,22 @@ [root] type=Root children=system -dummy=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem mem_mode=atomic physmem=system.physmem +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 [system.cpu] type=DerivO3CPU diff --git a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/simout b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/simout index 2cca5705e..ea4e5025f 100755 --- a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jan 17 2011 16:24:53 -M5 revision f72d94f8c275 7839 default qtip tip outgoing.patch qbase -M5 started Jan 17 2011 16:25:07 -M5 executing on zizzer +M5 compiled Feb 7 2011 01:47:18 +M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip +M5 started Feb 7 2011 01:47:37 +M5 executing on burrito command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stats.txt index 4f92cd575..553c740bc 100644 --- a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 227615 # Simulator instruction rate (inst/s) -host_mem_usage 215572 # Number of bytes of host memory used -host_seconds 349.68 # Real time elapsed on the host -host_tick_rate 77104293 # Simulator tick rate (ticks/s) +host_inst_rate 86589 # Simulator instruction rate (inst/s) +host_mem_usage 236008 # Number of bytes of host memory used +host_seconds 919.19 # Real time elapsed on the host +host_tick_rate 29331748 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 79591756 # Number of instructions simulated sim_seconds 0.026962 # Number of seconds simulated @@ -37,6 +37,9 @@ system.cpu.commit.COM:committed_per_cycle::min_value 0 system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::total 51426557 # Number of insts commited each cycle system.cpu.commit.COM:count 88340672 # Number of instructions committed +system.cpu.commit.COM:fp_insts 267754 # Number of committed floating point instructions. +system.cpu.commit.COM:function_calls 1661057 # Number of function calls committed. +system.cpu.commit.COM:int_insts 77942044 # Number of committed integer instructions. system.cpu.commit.COM:loads 20276638 # Number of loads committed system.cpu.commit.COM:membars 0 # Number of memory barriers committed system.cpu.commit.COM:refs 34890015 # Number of memory references committed @@ -171,6 +174,8 @@ system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Nu system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::total 52727427 # Number of instructions fetched each cycle (Total) +system.cpu.fp_regfile_reads 245061 # number of floating regfile reads +system.cpu.fp_regfile_writes 242344 # number of floating regfile writes system.cpu.icache.ReadReq_accesses 13394904 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_avg_miss_latency 9553.478677 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 6055.148214 # average ReadReq mshr miss latency @@ -270,6 +275,8 @@ system.cpu.iew.lsq.thread.0.squashedStores 1499472 # system.cpu.iew.memOrderViolationEvents 20765 # Number of memory order violations system.cpu.iew.predictedNotTakenIncorrect 133024 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedTakenIncorrect 270323 # Number of branches that were predicted taken incorrectly +system.cpu.int_regfile_reads 112261025 # number of integer regfile reads +system.cpu.int_regfile_writes 55957664 # number of integer regfile writes system.cpu.ipc 1.476021 # IPC: Instructions Per Cycle system.cpu.ipc_total 1.476021 # IPC: Total IPC of All Threads system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued @@ -361,6 +368,14 @@ system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::total 52727427 # Number of insts issued each cycle system.cpu.iq.ISSUE:rate 1.584713 # Inst issue rate +system.cpu.iq.fp_alu_accesses 300330 # Number of floating point alu accesses +system.cpu.iq.fp_inst_queue_reads 600062 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_wakeup_accesses 291336 # Number of floating instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_writes 449677 # Number of floating instruction queue writes +system.cpu.iq.int_alu_accesses 86057957 # Number of integer alu accesses +system.cpu.iq.int_inst_queue_reads 223986187 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_wakeup_accesses 84142849 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_writes 99078725 # Number of integer instruction queue writes system.cpu.iq.iqInstsAdded 89657627 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqInstsIssued 85452764 # Number of instructions issued system.cpu.iq.iqNonSpecInstsAdded 5005 # Number of non-speculative instructions added to the IQ @@ -457,7 +472,11 @@ system.cpu.memDep0.conflictingLoads 12487229 # Nu system.cpu.memDep0.conflictingStores 11176863 # Number of conflicting stores. system.cpu.memDep0.insertedLoads 22901502 # Number of loads inserted to the mem dependence unit. system.cpu.memDep0.insertedStores 16112849 # Number of stores inserted to the mem dependence unit. +system.cpu.misc_regfile_reads 38001 # number of misc regfile reads +system.cpu.misc_regfile_writes 1 # number of misc regfile writes system.cpu.numCycles 53923173 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.rename.RENAME:BlockCycles 1782763 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 52546881 # Number of HB maps that are committed system.cpu.rename.RENAME:IQFullEvents 52474 # Number of times rename has blocked due to IQ full @@ -471,10 +490,14 @@ system.cpu.rename.RENAME:RunCycles 19225803 # Nu system.cpu.rename.RENAME:SquashCycles 1300870 # Number of cycles rename is squashing system.cpu.rename.RENAME:UnblockCycles 1439133 # Number of cycles rename is unblocking system.cpu.rename.RENAME:UndoneMaps 8237313 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:fp_rename_lookups 444545 # Number of floating rename lookups +system.cpu.rename.RENAME:int_rename_lookups 121310909 # Number of integer rename lookups system.cpu.rename.RENAME:serializeStallCycles 77780 # count of cycles rename stalled for serializing inst system.cpu.rename.RENAME:serializingInsts 5276 # count of serializing insts renamed system.cpu.rename.RENAME:skidInsts 3015491 # count of insts added to the skid buffer system.cpu.rename.RENAME:tempSerializingInsts 5274 # count of temporary serializing insts renamed +system.cpu.rob.rob_reads 143406999 # The number of ROB reads +system.cpu.rob.rob_writes 194680217 # The number of ROB writes system.cpu.timesIdled 39379 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 4583 # Number of system calls diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/config.ini index e19472c60..d98970549 100644 --- a/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/config.ini +++ b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/config.ini @@ -1,13 +1,22 @@ [root] type=Root children=system -dummy=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem mem_mode=atomic physmem=system.physmem +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 [system.cpu] type=AtomicSimpleCPU @@ -57,7 +66,7 @@ egid=100 env= errout=cerr euid=100 -executable=/chips/pd/randd/dist/cpu2000/binaries/alpha/tru64/vortex +executable=/dist/m5/cpu2000/binaries/alpha/tru64/vortex gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/simerr b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/simerr index 67f69f09d..79a2396a6 100755 --- a/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/simerr +++ b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/simerr @@ -1,5 +1,11 @@ warn: Sockets disabled, not accepting gdb connections For more information see: http://www.m5sim.org/warn/d946bea6 +warn: Prefetch instrutions is Alpha do not do anything +For more information see: http://www.m5sim.org/warn/3e0eccba +warn: Prefetch instrutions is Alpha do not do anything +For more information see: http://www.m5sim.org/warn/3e0eccba +warn: Prefetch instrutions is Alpha do not do anything +For more information see: http://www.m5sim.org/warn/3e0eccba warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...) For more information see: http://www.m5sim.org/warn/5c5b547f hack: be nice to actually delete the event here diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/simout b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/simout index 9be789dc3..47e63ab68 100755 --- a/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/simout +++ b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/simout @@ -1,5 +1,3 @@ -Redirecting stdout to build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/simple-atomic/simout -Redirecting stderr to build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/simple-atomic/simerr M5 Simulator System Copyright (c) 2001-2008 @@ -7,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Nov 2 2010 21:30:55 -M5 revision 0af3760102ec+ 7713+ default qtip ext/alpha_prefetch.patch tip -M5 started Nov 2 2010 21:44:15 -M5 executing on aus-bc2-b15 +M5 compiled Feb 7 2011 01:47:18 +M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip +M5 started Feb 7 2011 01:47:38 +M5 executing on burrito command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt index 65fd7857e..1ad0b8bf6 100644 --- a/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt +++ b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 5477905 # Simulator instruction rate (inst/s) -host_mem_usage 240580 # Number of bytes of host memory used -host_seconds 16.13 # Real time elapsed on the host -host_tick_rate 2742055845 # Simulator tick rate (ticks/s) +host_inst_rate 1614429 # Simulator instruction rate (inst/s) +host_mem_usage 226740 # Number of bytes of host memory used +host_seconds 54.72 # Real time elapsed on the host +host_tick_rate 808136192 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 88340673 # Number of instructions simulated sim_seconds 0.044221 # Number of seconds simulated @@ -43,8 +43,24 @@ system.cpu.itb.write_hits 0 # DT system.cpu.itb.write_misses 0 # DTB write misses system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.numCycles 88442007 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.num_busy_cycles 88442007 # Number of busy cycles +system.cpu.num_conditional_control_insts 8920848 # number of instructions that are conditional controls +system.cpu.num_fp_alu_accesses 267757 # Number of float alu accesses +system.cpu.num_fp_insts 267757 # number of float instructions +system.cpu.num_fp_register_reads 229023 # number of times the floating registers were read +system.cpu.num_fp_register_writes 227630 # number of times the floating registers were written +system.cpu.num_func_calls 3321606 # number of times a function call or return occured +system.cpu.num_idle_cycles 0 # Number of idle cycles system.cpu.num_insts 88340673 # Number of instructions executed -system.cpu.num_refs 34987415 # Number of memory references +system.cpu.num_int_alu_accesses 78039444 # Number of integer alu accesses +system.cpu.num_int_insts 78039444 # number of integer instructions +system.cpu.num_int_register_reads 105931758 # number of times the integer registers were read +system.cpu.num_int_register_writes 52319251 # number of times the integer registers were written +system.cpu.num_load_insts 20366786 # Number of load instructions +system.cpu.num_mem_refs 34987415 # number of memory refs +system.cpu.num_store_insts 14620629 # Number of store instructions system.cpu.workload.PROG:num_syscalls 4583 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.ini b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.ini index 0830e222d..6f171a7fa 100644 --- a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.ini @@ -1,13 +1,22 @@ [root] type=Root children=system -dummy=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem mem_mode=atomic physmem=system.physmem +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 [system.cpu] type=TimingSimpleCPU @@ -157,7 +166,7 @@ egid=100 env= errout=cerr euid=100 -executable=/chips/pd/randd/dist/cpu2000/binaries/alpha/tru64/vortex +executable=/dist/m5/cpu2000/binaries/alpha/tru64/vortex gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/simerr b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/simerr index 67f69f09d..79a2396a6 100755 --- a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/simerr +++ b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/simerr @@ -1,5 +1,11 @@ warn: Sockets disabled, not accepting gdb connections For more information see: http://www.m5sim.org/warn/d946bea6 +warn: Prefetch instrutions is Alpha do not do anything +For more information see: http://www.m5sim.org/warn/3e0eccba +warn: Prefetch instrutions is Alpha do not do anything +For more information see: http://www.m5sim.org/warn/3e0eccba +warn: Prefetch instrutions is Alpha do not do anything +For more information see: http://www.m5sim.org/warn/3e0eccba warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...) For more information see: http://www.m5sim.org/warn/5c5b547f hack: be nice to actually delete the event here diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/simout b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/simout index 121823232..4f3f97870 100755 --- a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/simout +++ b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/simout @@ -1,5 +1,3 @@ -Redirecting stdout to build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/simple-timing/simout -Redirecting stderr to build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/simple-timing/simerr M5 Simulator System Copyright (c) 2001-2008 @@ -7,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Nov 2 2010 21:30:55 -M5 revision 0af3760102ec+ 7713+ default qtip ext/alpha_prefetch.patch tip -M5 started Nov 2 2010 21:40:34 -M5 executing on aus-bc2-b15 +M5 compiled Feb 7 2011 01:47:18 +M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip +M5 started Feb 7 2011 01:47:37 +M5 executing on burrito command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/stats.txt index 291724593..4a3fdb24c 100644 --- a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 2249900 # Simulator instruction rate (inst/s) -host_mem_usage 248308 # Number of bytes of host memory used -host_seconds 39.26 # Real time elapsed on the host -host_tick_rate 3419804648 # Simulator tick rate (ticks/s) +host_inst_rate 599191 # Simulator instruction rate (inst/s) +host_mem_usage 234452 # Number of bytes of host memory used +host_seconds 147.43 # Real time elapsed on the host +host_tick_rate 910763031 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 88340673 # Number of instructions simulated sim_seconds 0.134277 # Number of seconds simulated @@ -232,8 +232,24 @@ system.cpu.l2cache.warmup_cycle 0 # Cy system.cpu.l2cache.writebacks 120506 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.numCycles 268553976 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.num_busy_cycles 268553976 # Number of busy cycles +system.cpu.num_conditional_control_insts 8920848 # number of instructions that are conditional controls +system.cpu.num_fp_alu_accesses 267757 # Number of float alu accesses +system.cpu.num_fp_insts 267757 # number of float instructions +system.cpu.num_fp_register_reads 229023 # number of times the floating registers were read +system.cpu.num_fp_register_writes 227630 # number of times the floating registers were written +system.cpu.num_func_calls 3321606 # number of times a function call or return occured +system.cpu.num_idle_cycles 0 # Number of idle cycles system.cpu.num_insts 88340673 # Number of instructions executed -system.cpu.num_refs 34987415 # Number of memory references +system.cpu.num_int_alu_accesses 78039444 # Number of integer alu accesses +system.cpu.num_int_insts 78039444 # number of integer instructions +system.cpu.num_int_register_reads 105931758 # number of times the integer registers were read +system.cpu.num_int_register_writes 52319251 # number of times the integer registers were written +system.cpu.num_load_insts 20366786 # Number of load instructions +system.cpu.num_mem_refs 34987415 # number of memory refs +system.cpu.num_store_insts 14620629 # Number of store instructions system.cpu.workload.PROG:num_syscalls 4583 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/50.vortex/ref/arm/linux/o3-timing/config.ini b/tests/long/50.vortex/ref/arm/linux/o3-timing/config.ini index d32286142..2381c9471 100644 --- a/tests/long/50.vortex/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/50.vortex/ref/arm/linux/o3-timing/config.ini @@ -1,13 +1,22 @@ [root] type=Root children=system -dummy=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem mem_mode=atomic physmem=system.physmem +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 [system.cpu] type=DerivO3CPU @@ -484,7 +493,7 @@ egid=100 env= errout=cerr euid=100 -executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/vortex +executable=/dist/m5/cpu2000/binaries/arm/linux/vortex gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/50.vortex/ref/arm/linux/o3-timing/simout b/tests/long/50.vortex/ref/arm/linux/o3-timing/simout index 4650e6a0c..93fbb5edc 100755 --- a/tests/long/50.vortex/ref/arm/linux/o3-timing/simout +++ b/tests/long/50.vortex/ref/arm/linux/o3-timing/simout @@ -1,5 +1,3 @@ -Redirecting stdout to build/ARM_SE/tests/fast/long/50.vortex/arm/linux/o3-timing/simout -Redirecting stderr to build/ARM_SE/tests/fast/long/50.vortex/arm/linux/o3-timing/simerr M5 Simulator System Copyright (c) 2001-2008 @@ -7,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jan 18 2011 03:54:36 -M5 revision 218f733923f8 7861 default qtip int/arm_gdb.patch tip -M5 started Jan 18 2011 04:19:02 -M5 executing on aus-bc2-b9 +M5 compiled Feb 7 2011 01:56:16 +M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip +M5 started Feb 7 2011 01:56:24 +M5 executing on burrito command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/50.vortex/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/fast/long/50.vortex/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/50.vortex/ref/arm/linux/o3-timing/stats.txt b/tests/long/50.vortex/ref/arm/linux/o3-timing/stats.txt index c8769189d..ca56969f4 100644 --- a/tests/long/50.vortex/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/50.vortex/ref/arm/linux/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 156565 # Simulator instruction rate (inst/s) -host_mem_usage 260328 # Number of bytes of host memory used -host_seconds 631.29 # Real time elapsed on the host -host_tick_rate 93871242 # Simulator tick rate (ticks/s) +host_inst_rate 60156 # Simulator instruction rate (inst/s) +host_mem_usage 246816 # Number of bytes of host memory used +host_seconds 1643.03 # Real time elapsed on the host +host_tick_rate 36067570 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 98838077 # Number of instructions simulated sim_seconds 0.059260 # Number of seconds simulated @@ -37,6 +37,9 @@ system.cpu.commit.COM:committed_per_cycle::min_value 0 system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::total 114018884 # Number of insts commited each cycle system.cpu.commit.COM:count 98838077 # Number of instructions committed +system.cpu.commit.COM:fp_insts 56 # Number of committed floating point instructions. +system.cpu.commit.COM:function_calls 0 # Number of function calls committed. +system.cpu.commit.COM:int_insts 89710266 # Number of committed integer instructions. system.cpu.commit.COM:loads 27315295 # Number of loads committed system.cpu.commit.COM:membars 0 # Number of memory barriers committed system.cpu.commit.COM:refs 47871033 # Number of memory references committed @@ -171,6 +174,8 @@ system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Nu system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::total 117533456 # Number of instructions fetched each cycle (Total) +system.cpu.fp_regfile_reads 58 # number of floating regfile reads +system.cpu.fp_regfile_writes 40 # number of floating regfile writes system.cpu.icache.ReadReq_accesses 12122688 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_avg_miss_latency 12759.423411 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 9476.994450 # average ReadReq mshr miss latency @@ -270,6 +275,8 @@ system.cpu.iew.lsq.thread.0.squashedStores 2833293 # system.cpu.iew.memOrderViolationEvents 39532 # Number of memory order violations system.cpu.iew.predictedNotTakenIncorrect 1768227 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedTakenIncorrect 860228 # Number of branches that were predicted taken incorrectly +system.cpu.int_regfile_reads 255816186 # number of integer regfile reads +system.cpu.int_regfile_writes 78479487 # number of integer regfile writes system.cpu.ipc 0.833936 # IPC: Instructions Per Cycle system.cpu.ipc_total 0.833936 # IPC: Total IPC of All Threads system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued @@ -361,6 +368,14 @@ system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::total 117533456 # Number of insts issued each cycle system.cpu.iq.ISSUE:rate 0.920997 # Inst issue rate +system.cpu.iq.fp_alu_accesses 187 # Number of floating point alu accesses +system.cpu.iq.fp_inst_queue_reads 370 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_wakeup_accesses 59 # Number of floating instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_writes 568 # Number of floating instruction queue writes +system.cpu.iq.int_alu_accesses 110479458 # Number of integer alu accesses +system.cpu.iq.int_inst_queue_reads 337237563 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_wakeup_accesses 104978377 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_writes 134232957 # Number of integer instruction queue writes system.cpu.iq.iqInstsAdded 116084938 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqInstsIssued 109156507 # Number of instructions issued system.cpu.iq.iqNonSpecInstsAdded 1016199 # Number of non-speculative instructions added to the IQ @@ -473,7 +488,11 @@ system.cpu.memDep0.conflictingLoads 7990320 # Nu system.cpu.memDep0.conflictingStores 10924699 # Number of conflicting stores. system.cpu.memDep0.insertedLoads 32508348 # Number of loads inserted to the mem dependence unit. system.cpu.memDep0.insertedStores 23389031 # Number of stores inserted to the mem dependence unit. +system.cpu.misc_regfile_reads 153116651 # number of misc regfile reads +system.cpu.misc_regfile_writes 1948149 # number of misc regfile writes system.cpu.numCycles 118519960 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.rename.RENAME:BlockCycles 1866194 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 74745628 # Number of HB maps that are committed system.cpu.rename.RENAME:IQFullEvents 1883 # Number of times rename has blocked due to IQ full @@ -487,10 +506,14 @@ system.cpu.rename.RENAME:RunCycles 68672790 # Nu system.cpu.rename.RENAME:SquashCycles 3514572 # Number of cycles rename is squashing system.cpu.rename.RENAME:UnblockCycles 1591233 # Number of cycles rename is unblocking system.cpu.rename.RENAME:UndoneMaps 18613027 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:fp_rename_lookups 83717 # Number of floating rename lookups +system.cpu.rename.RENAME:int_rename_lookups 333328918 # Number of integer rename lookups system.cpu.rename.RENAME:serializeStallCycles 11499162 # count of cycles rename stalled for serializing inst system.cpu.rename.RENAME:serializingInsts 818368 # count of serializing insts renamed system.cpu.rename.RENAME:skidInsts 3724500 # count of insts added to the skid buffer system.cpu.rename.RENAME:tempSerializingInsts 819368 # count of temporary serializing insts renamed +system.cpu.rob.rob_reads 229794357 # The number of ROB reads +system.cpu.rob.rob_writes 237655572 # The number of ROB writes system.cpu.timesIdled 60726 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 1946 # Number of system calls diff --git a/tests/long/50.vortex/ref/arm/linux/simple-atomic/config.ini b/tests/long/50.vortex/ref/arm/linux/simple-atomic/config.ini index 451406111..d284ed163 100644 --- a/tests/long/50.vortex/ref/arm/linux/simple-atomic/config.ini +++ b/tests/long/50.vortex/ref/arm/linux/simple-atomic/config.ini @@ -1,13 +1,22 @@ [root] type=Root children=system -dummy=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem mem_mode=atomic physmem=system.physmem +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 [system.cpu] type=AtomicSimpleCPU @@ -52,12 +61,12 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=vortex lendian.raw -cwd=build/ARM_SE/tests/opt/long/50.vortex/arm/linux/simple-atomic +cwd=build/ARM_SE/tests/fast/long/50.vortex/arm/linux/simple-atomic egid=100 env= errout=cerr euid=100 -executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/vortex +executable=/dist/m5/cpu2000/binaries/arm/linux/vortex gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/50.vortex/ref/arm/linux/simple-atomic/simout b/tests/long/50.vortex/ref/arm/linux/simple-atomic/simout index 843c8c748..4cf2e23b7 100755 --- a/tests/long/50.vortex/ref/arm/linux/simple-atomic/simout +++ b/tests/long/50.vortex/ref/arm/linux/simple-atomic/simout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Oct 11 2010 18:37:23 -M5 revision c4e3d74d9a68 7726 default ext/mp_boot.patch qtip tip -M5 started Oct 11 2010 18:44:04 -M5 executing on aus-bc3-b4 -command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/50.vortex/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/opt/long/50.vortex/arm/linux/simple-atomic +M5 compiled Feb 7 2011 01:56:16 +M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip +M5 started Feb 7 2011 01:56:25 +M5 executing on burrito +command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/50.vortex/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/fast/long/50.vortex/arm/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/long/50.vortex/ref/arm/linux/simple-atomic/stats.txt b/tests/long/50.vortex/ref/arm/linux/simple-atomic/stats.txt index d9333fa95..a170aadf3 100644 --- a/tests/long/50.vortex/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/50.vortex/ref/arm/linux/simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 2790357 # Simulator instruction rate (inst/s) -host_mem_usage 261760 # Number of bytes of host memory used -host_seconds 35.42 # Real time elapsed on the host -host_tick_rate 1497251955 # Simulator tick rate (ticks/s) +host_inst_rate 986864 # Simulator instruction rate (inst/s) +host_mem_usage 237100 # Number of bytes of host memory used +host_seconds 100.15 # Real time elapsed on the host +host_tick_rate 529534290 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 98838077 # Number of instructions simulated sim_seconds 0.053035 # Number of seconds simulated @@ -53,8 +53,24 @@ system.cpu.itb.write_hits 0 # DT system.cpu.itb.write_misses 0 # DTB write misses system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.numCycles 106069965 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.num_busy_cycles 106069965 # Number of busy cycles +system.cpu.num_conditional_control_insts 0 # number of instructions that are conditional controls +system.cpu.num_fp_alu_accesses 56 # Number of float alu accesses +system.cpu.num_fp_insts 56 # number of float instructions +system.cpu.num_fp_register_reads 36 # number of times the floating registers were read +system.cpu.num_fp_register_writes 20 # number of times the floating registers were written +system.cpu.num_func_calls 0 # number of times a function call or return occured +system.cpu.num_idle_cycles 0 # Number of idle cycles system.cpu.num_insts 98838077 # Number of instructions executed -system.cpu.num_refs 47871034 # Number of memory references +system.cpu.num_int_alu_accesses 89710267 # Number of integer alu accesses +system.cpu.num_int_insts 89710267 # number of integer instructions +system.cpu.num_int_register_reads 258410605 # number of times the integer registers were read +system.cpu.num_int_register_writes 73280343 # number of times the integer registers were written +system.cpu.num_load_insts 27315295 # Number of load instructions +system.cpu.num_mem_refs 47871034 # number of memory refs +system.cpu.num_store_insts 20555739 # Number of store instructions system.cpu.workload.PROG:num_syscalls 1946 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/50.vortex/ref/arm/linux/simple-timing/config.ini b/tests/long/50.vortex/ref/arm/linux/simple-timing/config.ini index 1d235cb1e..0e5c2c18c 100644 --- a/tests/long/50.vortex/ref/arm/linux/simple-timing/config.ini +++ b/tests/long/50.vortex/ref/arm/linux/simple-timing/config.ini @@ -1,13 +1,22 @@ [root] type=Root children=system -dummy=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem mem_mode=atomic physmem=system.physmem +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 [system.cpu] type=TimingSimpleCPU @@ -152,12 +161,12 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=vortex lendian.raw -cwd=build/ARM_SE/tests/opt/long/50.vortex/arm/linux/simple-timing +cwd=build/ARM_SE/tests/fast/long/50.vortex/arm/linux/simple-timing egid=100 env= errout=cerr euid=100 -executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/vortex +executable=/dist/m5/cpu2000/binaries/arm/linux/vortex gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/50.vortex/ref/arm/linux/simple-timing/simerr b/tests/long/50.vortex/ref/arm/linux/simple-timing/simerr index eabe42249..e391217dd 100755 --- a/tests/long/50.vortex/ref/arm/linux/simple-timing/simerr +++ b/tests/long/50.vortex/ref/arm/linux/simple-timing/simerr @@ -1,3 +1,11 @@ warn: Sockets disabled, not accepting gdb connections For more information see: http://www.m5sim.org/warn/d946bea6 +warn: Complete acc isn't called on normal stores in O3. +For more information see: http://www.m5sim.org/warn/138d8573 +warn: Complete acc isn't called on normal stores in O3. +For more information see: http://www.m5sim.org/warn/138d8573 +warn: Complete acc isn't called on normal stores in O3. +For more information see: http://www.m5sim.org/warn/138d8573 +warn: Complete acc isn't called on normal stores in O3. +For more information see: http://www.m5sim.org/warn/138d8573 hack: be nice to actually delete the event here diff --git a/tests/long/50.vortex/ref/arm/linux/simple-timing/simout b/tests/long/50.vortex/ref/arm/linux/simple-timing/simout index 8e789b6bf..54e01817e 100755 --- a/tests/long/50.vortex/ref/arm/linux/simple-timing/simout +++ b/tests/long/50.vortex/ref/arm/linux/simple-timing/simout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Oct 11 2010 18:37:23 -M5 revision c4e3d74d9a68 7726 default ext/mp_boot.patch qtip tip -M5 started Oct 11 2010 18:37:39 -M5 executing on aus-bc3-b4 -command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/50.vortex/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/opt/long/50.vortex/arm/linux/simple-timing +M5 compiled Feb 7 2011 01:56:16 +M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip +M5 started Feb 7 2011 01:56:25 +M5 executing on burrito +command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/50.vortex/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/fast/long/50.vortex/arm/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/long/50.vortex/ref/arm/linux/simple-timing/stats.txt b/tests/long/50.vortex/ref/arm/linux/simple-timing/stats.txt index 595ab3b43..b20318b2f 100644 --- a/tests/long/50.vortex/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/50.vortex/ref/arm/linux/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 607999 # Simulator instruction rate (inst/s) -host_mem_usage 269484 # Number of bytes of host memory used -host_seconds 161.18 # Real time elapsed on the host -host_tick_rate 825650483 # Simulator tick rate (ticks/s) +host_inst_rate 430473 # Simulator instruction rate (inst/s) +host_mem_usage 244816 # Number of bytes of host memory used +host_seconds 227.65 # Real time elapsed on the host +host_tick_rate 584574230 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 97997303 # Number of instructions simulated sim_seconds 0.133079 # Number of seconds simulated @@ -242,8 +242,24 @@ system.cpu.l2cache.warmup_cycle 0 # Cy system.cpu.l2cache.writebacks 88450 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.numCycles 266157390 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.num_busy_cycles 266157390 # Number of busy cycles +system.cpu.num_conditional_control_insts 0 # number of instructions that are conditional controls +system.cpu.num_fp_alu_accesses 56 # Number of float alu accesses +system.cpu.num_fp_insts 56 # number of float instructions +system.cpu.num_fp_register_reads 36 # number of times the floating registers were read +system.cpu.num_fp_register_writes 20 # number of times the floating registers were written +system.cpu.num_func_calls 0 # number of times a function call or return occured +system.cpu.num_idle_cycles 0 # Number of idle cycles system.cpu.num_insts 97997303 # Number of instructions executed -system.cpu.num_refs 47871034 # Number of memory references +system.cpu.num_int_alu_accesses 89710267 # Number of integer alu accesses +system.cpu.num_int_insts 89710267 # number of integer instructions +system.cpu.num_int_register_reads 285424208 # number of times the integer registers were read +system.cpu.num_int_register_writes 73333595 # number of times the integer registers were written +system.cpu.num_load_insts 27315295 # Number of load instructions +system.cpu.num_mem_refs 47871034 # number of memory refs +system.cpu.num_store_insts 20555739 # Number of store instructions system.cpu.workload.PROG:num_syscalls 1946 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/config.ini b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/config.ini index 51965dbb5..0962890e6 100644 --- a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/config.ini +++ b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/config.ini @@ -1,13 +1,22 @@ [root] type=Root children=system -dummy=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem mem_mode=atomic physmem=system.physmem +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 [system.cpu] type=AtomicSimpleCPU @@ -57,7 +66,7 @@ egid=100 env= errout=cerr euid=100 -executable=/proj/aatl_perfmod_arch/m5_binaries/cpu2000/binaries/sparc/linux/vortex +executable=/dist/m5/cpu2000/binaries/sparc/linux/vortex gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/simout b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/simout index 27a5cc38b..7f5789393 100755 --- a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/simout +++ b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 25 2010 03:11:27 -M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip -M5 started Feb 25 2010 03:33:19 -M5 executing on SC2B0619 +M5 compiled Feb 7 2011 02:13:30 +M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip +M5 started Feb 7 2011 02:14:11 +M5 executing on burrito command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/50.vortex/sparc/linux/simple-atomic -re tests/run.py build/SPARC_SE/tests/fast/long/50.vortex/sparc/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/stats.txt b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/stats.txt index b6b56aac5..d6bfda298 100644 --- a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/stats.txt +++ b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1397341 # Simulator instruction rate (inst/s) -host_mem_usage 194632 # Number of bytes of host memory used -host_seconds 97.43 # Real time elapsed on the host -host_tick_rate 699480350 # Simulator tick rate (ticks/s) +host_inst_rate 1204089 # Simulator instruction rate (inst/s) +host_mem_usage 228576 # Number of bytes of host memory used +host_seconds 113.06 # Real time elapsed on the host +host_tick_rate 602742669 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 136139203 # Number of instructions simulated sim_seconds 0.068149 # Number of seconds simulated @@ -11,8 +11,24 @@ sim_ticks 68148678500 # Nu system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.numCycles 136297358 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.num_busy_cycles 136297358 # Number of busy cycles +system.cpu.num_conditional_control_insts 0 # number of instructions that are conditional controls +system.cpu.num_fp_alu_accesses 2326977 # Number of float alu accesses +system.cpu.num_fp_insts 2326977 # number of float instructions +system.cpu.num_fp_register_reads 4725607 # number of times the floating registers were read +system.cpu.num_fp_register_writes 1150968 # number of times the floating registers were written +system.cpu.num_func_calls 0 # number of times a function call or return occured +system.cpu.num_idle_cycles 0 # Number of idle cycles system.cpu.num_insts 136139203 # Number of instructions executed -system.cpu.num_refs 58160249 # Number of memory references +system.cpu.num_int_alu_accesses 115187758 # Number of integer alu accesses +system.cpu.num_int_insts 115187758 # number of integer instructions +system.cpu.num_int_register_reads 263032383 # number of times the integer registers were read +system.cpu.num_int_register_writes 113225733 # number of times the integer registers were written +system.cpu.num_load_insts 37275868 # Number of load instructions +system.cpu.num_mem_refs 58160249 # number of memory refs +system.cpu.num_store_insts 20884381 # Number of store instructions system.cpu.workload.PROG:num_syscalls 1946 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-timing/config.ini b/tests/long/50.vortex/ref/sparc/linux/simple-timing/config.ini index 08b8aa7ee..8ec9f75ef 100644 --- a/tests/long/50.vortex/ref/sparc/linux/simple-timing/config.ini +++ b/tests/long/50.vortex/ref/sparc/linux/simple-timing/config.ini @@ -1,13 +1,22 @@ [root] type=Root children=system -dummy=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem mem_mode=atomic physmem=system.physmem +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 [system.cpu] type=TimingSimpleCPU @@ -152,12 +161,12 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=vortex bendian.raw -cwd=build/SPARC_SE/tests/opt/long/50.vortex/sparc/linux/simple-timing +cwd=build/SPARC_SE/tests/fast/long/50.vortex/sparc/linux/simple-timing egid=100 env= errout=cerr euid=100 -executable=/home/stever/m5/dist/cpu2000/binaries/sparc/linux/vortex +executable=/dist/m5/cpu2000/binaries/sparc/linux/vortex gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-timing/simout b/tests/long/50.vortex/ref/sparc/linux/simple-timing/simout index e214aaa33..b27952d03 100755 --- a/tests/long/50.vortex/ref/sparc/linux/simple-timing/simout +++ b/tests/long/50.vortex/ref/sparc/linux/simple-timing/simout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Sep 20 2010 15:04:49 -M5 revision 0c4a7d867247 7686 default qtip print-identical tip -M5 started Sep 20 2010 16:35:02 -M5 executing on phenom -command line: build/SPARC_SE/m5.opt -d build/SPARC_SE/tests/opt/long/50.vortex/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/opt/long/50.vortex/sparc/linux/simple-timing +M5 compiled Feb 7 2011 02:13:30 +M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip +M5 started Feb 7 2011 02:13:39 +M5 executing on burrito +command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/50.vortex/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/fast/long/50.vortex/sparc/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-timing/stats.txt b/tests/long/50.vortex/ref/sparc/linux/simple-timing/stats.txt index d33aa6f85..eb6eca0bd 100644 --- a/tests/long/50.vortex/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/long/50.vortex/ref/sparc/linux/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1222037 # Simulator instruction rate (inst/s) -host_mem_usage 206136 # Number of bytes of host memory used -host_seconds 111.40 # Real time elapsed on the host -host_tick_rate 1821674437 # Simulator tick rate (ticks/s) +host_inst_rate 463084 # Simulator instruction rate (inst/s) +host_mem_usage 236284 # Number of bytes of host memory used +host_seconds 293.98 # Real time elapsed on the host +host_tick_rate 690315679 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 136139203 # Number of instructions simulated sim_seconds 0.202942 # Number of seconds simulated @@ -210,8 +210,24 @@ system.cpu.l2cache.warmup_cycle 0 # Cy system.cpu.l2cache.writebacks 87265 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.numCycles 405883984 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.num_busy_cycles 405883984 # Number of busy cycles +system.cpu.num_conditional_control_insts 0 # number of instructions that are conditional controls +system.cpu.num_fp_alu_accesses 2326977 # Number of float alu accesses +system.cpu.num_fp_insts 2326977 # number of float instructions +system.cpu.num_fp_register_reads 4725607 # number of times the floating registers were read +system.cpu.num_fp_register_writes 1150968 # number of times the floating registers were written +system.cpu.num_func_calls 0 # number of times a function call or return occured +system.cpu.num_idle_cycles 0 # Number of idle cycles system.cpu.num_insts 136139203 # Number of instructions executed -system.cpu.num_refs 58160249 # Number of memory references +system.cpu.num_int_alu_accesses 115187758 # Number of integer alu accesses +system.cpu.num_int_insts 115187758 # number of integer instructions +system.cpu.num_int_register_reads 263032383 # number of times the integer registers were read +system.cpu.num_int_register_writes 113225732 # number of times the integer registers were written +system.cpu.num_load_insts 37275868 # Number of load instructions +system.cpu.num_mem_refs 58160249 # number of memory refs +system.cpu.num_store_insts 20884381 # Number of store instructions system.cpu.workload.PROG:num_syscalls 1946 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.ini b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.ini index 5e62dfe3a..28a997af9 100644 --- a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.ini @@ -1,13 +1,22 @@ [root] type=Root children=system -dummy=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem mem_mode=atomic physmem=system.physmem +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 [system.cpu] type=DerivO3CPU diff --git a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/simout b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/simout index b301ecfc9..d5dabed4c 100755 --- a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jan 17 2011 16:24:53 -M5 revision f72d94f8c275 7839 default qtip tip outgoing.patch qbase -M5 started Jan 17 2011 16:24:57 -M5 executing on zizzer +M5 compiled Feb 7 2011 01:47:18 +M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip +M5 started Feb 7 2011 01:47:37 +M5 executing on burrito command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt index aaad6352f..025b36e9a 100644 --- a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 148199 # Simulator instruction rate (inst/s) -host_mem_usage 206348 # Number of bytes of host memory used -host_seconds 11714.26 # Real time elapsed on the host -host_tick_rate 61804258 # Simulator tick rate (ticks/s) +host_inst_rate 163492 # Simulator instruction rate (inst/s) +host_mem_usage 226772 # Number of bytes of host memory used +host_seconds 10618.50 # Real time elapsed on the host +host_tick_rate 68182084 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1736043781 # Number of instructions simulated sim_seconds 0.723991 # Number of seconds simulated @@ -37,6 +37,9 @@ system.cpu.commit.COM:committed_per_cycle::min_value 0 system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::total 1347786892 # Number of insts commited each cycle system.cpu.commit.COM:count 1819780126 # Number of instructions committed +system.cpu.commit.COM:fp_insts 805525 # Number of committed floating point instructions. +system.cpu.commit.COM:function_calls 16767440 # Number of function calls committed. +system.cpu.commit.COM:int_insts 1718967519 # Number of committed integer instructions. system.cpu.commit.COM:loads 444595663 # Number of loads committed system.cpu.commit.COM:membars 0 # Number of memory barriers committed system.cpu.commit.COM:refs 605324165 # Number of memory references committed @@ -179,6 +182,8 @@ system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Nu system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::total 1436774330 # Number of instructions fetched each cycle (Total) +system.cpu.fp_regfile_reads 752 # number of floating regfile reads +system.cpu.fp_regfile_writes 445 # number of floating regfile writes system.cpu.icache.ReadReq_accesses 354412327 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_avg_miss_latency 35305.051302 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 35462.540717 # average ReadReq mshr miss latency @@ -278,6 +283,8 @@ system.cpu.iew.lsq.thread.0.squashedStores 71840083 # system.cpu.iew.memOrderViolationEvents 2851639 # Number of memory order violations system.cpu.iew.predictedNotTakenIncorrect 3390000 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedTakenIncorrect 18332236 # Number of branches that were predicted taken incorrectly +system.cpu.int_regfile_reads 3052206207 # number of integer regfile reads +system.cpu.int_regfile_writes 1779704780 # number of integer regfile writes system.cpu.ipc 1.198940 # IPC: Instructions Per Cycle system.cpu.ipc_total 1.198940 # IPC: Total IPC of All Threads system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued @@ -369,6 +376,14 @@ system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::total 1436774330 # Number of insts issued each cycle system.cpu.iq.ISSUE:rate 1.592073 # Inst issue rate +system.cpu.iq.fp_alu_accesses 831640 # Number of floating point alu accesses +system.cpu.iq.fp_inst_queue_reads 1663270 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_wakeup_accesses 822278 # Number of floating instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_writes 878238 # Number of floating instruction queue writes +system.cpu.iq.int_alu_accesses 2317801511 # Number of integer alu accesses +system.cpu.iq.int_inst_queue_reads 6060328576 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_wakeup_accesses 2227662406 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_writes 3193875126 # Number of integer instruction queue writes system.cpu.iq.iqInstsAdded 2474285485 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqInstsIssued 2305294087 # Number of instructions issued system.cpu.iq.iqNonSpecInstsAdded 45 # Number of non-speculative instructions added to the IQ @@ -465,7 +480,11 @@ system.cpu.memDep0.conflictingLoads 123159990 # Nu system.cpu.memDep0.conflictingStores 64312407 # Number of conflicting stores. system.cpu.memDep0.insertedLoads 617102957 # Number of loads inserted to the mem dependence unit. system.cpu.memDep0.insertedStores 232568585 # Number of stores inserted to the mem dependence unit. +system.cpu.misc_regfile_reads 25 # number of misc regfile reads +system.cpu.misc_regfile_writes 1 # number of misc regfile writes system.cpu.numCycles 1447982395 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.rename.RENAME:BlockCycles 51393371 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 1376202963 # Number of HB maps that are committed system.cpu.rename.RENAME:IQFullEvents 5887635 # Number of times rename has blocked due to IQ full @@ -479,10 +498,14 @@ system.cpu.rename.RENAME:RunCycles 528076479 # Nu system.cpu.rename.RENAME:SquashCycles 88987438 # Number of cycles rename is squashing system.cpu.rename.RENAME:UnblockCycles 27475071 # Number of cycles rename is unblocking system.cpu.rename.RENAME:UndoneMaps 671478700 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:fp_rename_lookups 885045 # Number of floating rename lookups +system.cpu.rename.RENAME:int_rename_lookups 3534388873 # Number of integer rename lookups system.cpu.rename.RENAME:serializeStallCycles 849 # count of cycles rename stalled for serializing inst system.cpu.rename.RENAME:serializingInsts 49 # count of serializing insts renamed system.cpu.rename.RENAME:skidInsts 54007891 # count of insts added to the skid buffer system.cpu.rename.RENAME:tempSerializingInsts 47 # count of temporary serializing insts renamed +system.cpu.rob.rob_reads 3612840225 # The number of ROB reads +system.cpu.rob.rob_writes 4916793262 # The number of ROB writes system.cpu.timesIdled 425188 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 29 # Number of system calls diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/config.ini index 889a2c50f..e886c5917 100644 --- a/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/config.ini +++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/config.ini @@ -1,13 +1,22 @@ [root] type=Root children=system -dummy=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem mem_mode=atomic physmem=system.physmem +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 [system.cpu] type=AtomicSimpleCPU @@ -57,7 +66,7 @@ egid=100 env= errout=cerr euid=100 -executable=/chips/pd/randd/dist/cpu2000/binaries/alpha/tru64/bzip2 +executable=/dist/m5/cpu2000/binaries/alpha/tru64/bzip2 gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/simerr b/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/simerr index 67f69f09d..79a2396a6 100755 --- a/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/simerr +++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/simerr @@ -1,5 +1,11 @@ warn: Sockets disabled, not accepting gdb connections For more information see: http://www.m5sim.org/warn/d946bea6 +warn: Prefetch instrutions is Alpha do not do anything +For more information see: http://www.m5sim.org/warn/3e0eccba +warn: Prefetch instrutions is Alpha do not do anything +For more information see: http://www.m5sim.org/warn/3e0eccba +warn: Prefetch instrutions is Alpha do not do anything +For more information see: http://www.m5sim.org/warn/3e0eccba warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...) For more information see: http://www.m5sim.org/warn/5c5b547f hack: be nice to actually delete the event here diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/simout b/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/simout index 5c31e9414..56c0d3893 100755 --- a/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/simout +++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/simout @@ -1,5 +1,3 @@ -Redirecting stdout to build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/simple-atomic/simout -Redirecting stderr to build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/simple-atomic/simerr M5 Simulator System Copyright (c) 2001-2008 @@ -7,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Nov 2 2010 21:30:55 -M5 revision 0af3760102ec+ 7713+ default qtip ext/alpha_prefetch.patch tip -M5 started Nov 2 2010 21:35:16 -M5 executing on aus-bc2-b15 +M5 compiled Feb 7 2011 01:47:18 +M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip +M5 started Feb 7 2011 01:47:37 +M5 executing on burrito command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt index 0e81a5825..7812c0d15 100644 --- a/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt +++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 5747960 # Simulator instruction rate (inst/s) -host_mem_usage 231948 # Number of bytes of host memory used -host_seconds 316.60 # Real time elapsed on the host -host_tick_rate 2884399053 # Simulator tick rate (ticks/s) +host_inst_rate 1468260 # Simulator instruction rate (inst/s) +host_mem_usage 218108 # Number of bytes of host memory used +host_seconds 1239.41 # Real time elapsed on the host +host_tick_rate 736791940 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1819780127 # Number of instructions simulated sim_seconds 0.913189 # Number of seconds simulated @@ -43,8 +43,24 @@ system.cpu.itb.write_hits 0 # DT system.cpu.itb.write_misses 0 # DTB write misses system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.numCycles 1826378527 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.num_busy_cycles 1826378527 # Number of busy cycles +system.cpu.num_conditional_control_insts 164021647 # number of instructions that are conditional controls +system.cpu.num_fp_alu_accesses 805526 # Number of float alu accesses +system.cpu.num_fp_insts 805526 # number of float instructions +system.cpu.num_fp_register_reads 357 # number of times the floating registers were read +system.cpu.num_fp_register_writes 345 # number of times the floating registers were written +system.cpu.num_func_calls 33534877 # number of times a function call or return occured +system.cpu.num_idle_cycles 0 # Number of idle cycles system.cpu.num_insts 1819780127 # Number of instructions executed -system.cpu.num_refs 611922547 # Number of memory references +system.cpu.num_int_alu_accesses 1725565901 # Number of integer alu accesses +system.cpu.num_int_insts 1725565901 # number of integer instructions +system.cpu.num_int_register_reads 2347934659 # number of times the integer registers were read +system.cpu.num_int_register_writes 1376202618 # number of times the integer registers were written +system.cpu.num_load_insts 449492741 # Number of load instructions +system.cpu.num_mem_refs 611922547 # number of memory refs +system.cpu.num_store_insts 162429806 # Number of store instructions system.cpu.workload.PROG:num_syscalls 29 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.ini b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.ini index 6c6b88ddd..6d6374beb 100644 --- a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.ini @@ -1,13 +1,22 @@ [root] type=Root children=system -dummy=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem mem_mode=atomic physmem=system.physmem +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 [system.cpu] type=TimingSimpleCPU @@ -157,7 +166,7 @@ egid=100 env= errout=cerr euid=100 -executable=/chips/pd/randd/dist/cpu2000/binaries/alpha/tru64/bzip2 +executable=/dist/m5/cpu2000/binaries/alpha/tru64/bzip2 gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/simerr b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/simerr index 67f69f09d..79a2396a6 100755 --- a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/simerr +++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/simerr @@ -1,5 +1,11 @@ warn: Sockets disabled, not accepting gdb connections For more information see: http://www.m5sim.org/warn/d946bea6 +warn: Prefetch instrutions is Alpha do not do anything +For more information see: http://www.m5sim.org/warn/3e0eccba +warn: Prefetch instrutions is Alpha do not do anything +For more information see: http://www.m5sim.org/warn/3e0eccba +warn: Prefetch instrutions is Alpha do not do anything +For more information see: http://www.m5sim.org/warn/3e0eccba warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...) For more information see: http://www.m5sim.org/warn/5c5b547f hack: be nice to actually delete the event here diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/simout b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/simout index d211942d5..b361f245f 100755 --- a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/simout +++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/simout @@ -1,5 +1,3 @@ -Redirecting stdout to build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/simple-timing/simout -Redirecting stderr to build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/simple-timing/simerr M5 Simulator System Copyright (c) 2001-2008 @@ -7,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Nov 2 2010 21:30:55 -M5 revision 0af3760102ec+ 7713+ default qtip ext/alpha_prefetch.patch tip -M5 started Nov 2 2010 21:53:28 -M5 executing on aus-bc2-b15 +M5 compiled Feb 7 2011 01:47:18 +M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip +M5 started Feb 7 2011 01:47:37 +M5 executing on burrito command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt index 7c181b6aa..f893b334a 100644 --- a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 2423488 # Simulator instruction rate (inst/s) -host_mem_usage 239668 # Number of bytes of host memory used -host_seconds 750.89 # Real time elapsed on the host -host_tick_rate 3547033530 # Simulator tick rate (ticks/s) +host_inst_rate 590383 # Simulator instruction rate (inst/s) +host_mem_usage 225824 # Number of bytes of host memory used +host_seconds 3082.37 # Real time elapsed on the host +host_tick_rate 864089077 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1819780127 # Number of instructions simulated sim_seconds 2.663444 # Number of seconds simulated @@ -232,8 +232,24 @@ system.cpu.l2cache.warmup_cycle 582065656000 # Cy system.cpu.l2cache.writebacks 1170923 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.numCycles 5326887432 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.num_busy_cycles 5326887432 # Number of busy cycles +system.cpu.num_conditional_control_insts 164021647 # number of instructions that are conditional controls +system.cpu.num_fp_alu_accesses 805526 # Number of float alu accesses +system.cpu.num_fp_insts 805526 # number of float instructions +system.cpu.num_fp_register_reads 357 # number of times the floating registers were read +system.cpu.num_fp_register_writes 345 # number of times the floating registers were written +system.cpu.num_func_calls 33534877 # number of times a function call or return occured +system.cpu.num_idle_cycles 0 # Number of idle cycles system.cpu.num_insts 1819780127 # Number of instructions executed -system.cpu.num_refs 611922547 # Number of memory references +system.cpu.num_int_alu_accesses 1725565901 # Number of integer alu accesses +system.cpu.num_int_insts 1725565901 # number of integer instructions +system.cpu.num_int_register_reads 2347934659 # number of times the integer registers were read +system.cpu.num_int_register_writes 1376202618 # number of times the integer registers were written +system.cpu.num_load_insts 449492741 # Number of load instructions +system.cpu.num_mem_refs 611922547 # number of memory refs +system.cpu.num_store_insts 162429806 # Number of store instructions system.cpu.workload.PROG:num_syscalls 29 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/60.bzip2/ref/arm/linux/o3-timing/config.ini b/tests/long/60.bzip2/ref/arm/linux/o3-timing/config.ini index 3ef4a25fb..731b0df43 100644 --- a/tests/long/60.bzip2/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/60.bzip2/ref/arm/linux/o3-timing/config.ini @@ -1,13 +1,22 @@ [root] type=Root children=system -dummy=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem mem_mode=atomic physmem=system.physmem +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 [system.cpu] type=DerivO3CPU @@ -484,7 +493,7 @@ egid=100 env= errout=cerr euid=100 -executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/bzip2 +executable=/dist/m5/cpu2000/binaries/arm/linux/bzip2 gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/60.bzip2/ref/arm/linux/o3-timing/simout b/tests/long/60.bzip2/ref/arm/linux/o3-timing/simout index 2f2c51bdb..e9bf20924 100755 --- a/tests/long/60.bzip2/ref/arm/linux/o3-timing/simout +++ b/tests/long/60.bzip2/ref/arm/linux/o3-timing/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jan 11 2011 18:16:01 -M5 revision b39a8457b332 7816 default ext/o3_regressions.patch qtip tip -M5 started Jan 12 2011 03:57:47 -M5 executing on u200439-lin.austin.arm.com +M5 compiled Feb 7 2011 01:56:16 +M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip +M5 started Feb 7 2011 01:56:25 +M5 executing on burrito command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/60.bzip2/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/fast/long/60.bzip2/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/60.bzip2/ref/arm/linux/o3-timing/stats.txt b/tests/long/60.bzip2/ref/arm/linux/o3-timing/stats.txt index ab126a693..24c1e17c3 100644 --- a/tests/long/60.bzip2/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/60.bzip2/ref/arm/linux/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 165173 # Simulator instruction rate (inst/s) -host_mem_usage 251872 # Number of bytes of host memory used -host_seconds 10349.18 # Real time elapsed on the host -host_tick_rate 71148819 # Simulator tick rate (ticks/s) +host_inst_rate 152870 # Simulator instruction rate (inst/s) +host_mem_usage 238404 # Number of bytes of host memory used +host_seconds 11182.08 # Real time elapsed on the host +host_tick_rate 65849295 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1709408682 # Number of instructions simulated sim_seconds 0.736332 # Number of seconds simulated @@ -37,6 +37,9 @@ system.cpu.commit.COM:committed_per_cycle::min_value 0 system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::total 1325593863 # Number of insts commited each cycle system.cpu.commit.COM:count 1709408682 # Number of instructions committed +system.cpu.commit.COM:fp_insts 36 # Number of committed floating point instructions. +system.cpu.commit.COM:function_calls 0 # Number of function calls committed. +system.cpu.commit.COM:int_insts 1523276792 # Number of committed integer instructions. system.cpu.commit.COM:loads 485926830 # Number of loads committed system.cpu.commit.COM:membars 0 # Number of memory barriers committed system.cpu.commit.COM:refs 660773875 # Number of memory references committed @@ -171,6 +174,8 @@ system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Nu system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::total 1437192539 # Number of instructions fetched each cycle (Total) +system.cpu.fp_regfile_reads 66 # number of floating regfile reads +system.cpu.fp_regfile_writes 62 # number of floating regfile writes system.cpu.icache.ReadReq_accesses 305341372 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_avg_miss_latency 34138.917794 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 34194.369973 # average ReadReq mshr miss latency @@ -270,6 +275,8 @@ system.cpu.iew.lsq.thread.0.squashedStores 145359637 # system.cpu.iew.memOrderViolationEvents 2909115 # Number of memory order violations system.cpu.iew.predictedNotTakenIncorrect 16680292 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedTakenIncorrect 18278981 # Number of branches that were predicted taken incorrectly +system.cpu.int_regfile_reads 5217275964 # number of integer regfile reads +system.cpu.int_regfile_writes 1582136898 # number of integer regfile writes system.cpu.ipc 1.160759 # IPC: Instructions Per Cycle system.cpu.ipc_total 1.160759 # IPC: Total IPC of All Threads system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued @@ -361,6 +368,14 @@ system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::total 1437192539 # Number of insts issued each cycle system.cpu.iq.ISSUE:rate 1.426534 # Inst issue rate +system.cpu.iq.fp_alu_accesses 101 # Number of floating point alu accesses +system.cpu.iq.fp_inst_queue_reads 196 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_wakeup_accesses 78 # Number of floating instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_writes 252 # Number of floating instruction queue writes +system.cpu.iq.int_alu_accesses 2136057911 # Number of integer alu accesses +system.cpu.iq.int_inst_queue_reads 5702380947 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_wakeup_accesses 2009251443 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_writes 3154359191 # Number of integer instruction queue writes system.cpu.iq.iqInstsAdded 2433961117 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqInstsIssued 2100805548 # Number of instructions issued system.cpu.iq.iqNonSpecInstsAdded 422 # Number of non-speculative instructions added to the IQ @@ -463,7 +478,11 @@ system.cpu.memDep0.conflictingLoads 102861524 # Nu system.cpu.memDep0.conflictingStores 93795307 # Number of conflicting stores. system.cpu.memDep0.insertedLoads 660629203 # Number of loads inserted to the mem dependence unit. system.cpu.memDep0.insertedStores 320206682 # Number of stores inserted to the mem dependence unit. +system.cpu.misc_regfile_reads 3121183601 # number of misc regfile reads +system.cpu.misc_regfile_writes 895 # number of misc regfile writes system.cpu.numCycles 1472664444 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.rename.RENAME:BlockCycles 52825853 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 1347252520 # Number of HB maps that are committed system.cpu.rename.RENAME:IQFullEvents 13396688 # Number of times rename has blocked due to IQ full @@ -477,10 +496,14 @@ system.cpu.rename.RENAME:RunCycles 526018927 # Nu system.cpu.rename.RENAME:SquashCycles 111598676 # Number of cycles rename is squashing system.cpu.rename.RENAME:UnblockCycles 55598501 # Number of cycles rename is unblocking system.cpu.rename.RENAME:UndoneMaps 598647716 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:fp_rename_lookups 1008 # Number of floating rename lookups +system.cpu.rename.RENAME:int_rename_lookups 7136668460 # Number of integer rename lookups system.cpu.rename.RENAME:serializeStallCycles 9673 # count of cycles rename stalled for serializing inst system.cpu.rename.RENAME:serializingInsts 448 # count of serializing insts renamed system.cpu.rename.RENAME:skidInsts 110186399 # count of insts added to the skid buffer system.cpu.rename.RENAME:tempSerializingInsts 445 # count of temporary serializing insts renamed +system.cpu.rob.rob_reads 3717337450 # The number of ROB reads +system.cpu.rob.rob_writes 4979785274 # The number of ROB writes system.cpu.timesIdled 1109854 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 46 # Number of system calls diff --git a/tests/long/60.bzip2/ref/arm/linux/simple-atomic/config.ini b/tests/long/60.bzip2/ref/arm/linux/simple-atomic/config.ini index 14dc84cb3..8d90d74d0 100644 --- a/tests/long/60.bzip2/ref/arm/linux/simple-atomic/config.ini +++ b/tests/long/60.bzip2/ref/arm/linux/simple-atomic/config.ini @@ -1,13 +1,22 @@ [root] type=Root children=system -dummy=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem mem_mode=atomic physmem=system.physmem +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 [system.cpu] type=AtomicSimpleCPU @@ -52,12 +61,12 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=bzip2 input.source 1 -cwd=build/ARM_SE/tests/opt/long/60.bzip2/arm/linux/simple-atomic +cwd=build/ARM_SE/tests/fast/long/60.bzip2/arm/linux/simple-atomic egid=100 env= errout=cerr euid=100 -executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/bzip2 +executable=/dist/m5/cpu2000/binaries/arm/linux/bzip2 gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/60.bzip2/ref/arm/linux/simple-atomic/simout b/tests/long/60.bzip2/ref/arm/linux/simple-atomic/simout index 9eea795e5..1ce869a83 100755 --- a/tests/long/60.bzip2/ref/arm/linux/simple-atomic/simout +++ b/tests/long/60.bzip2/ref/arm/linux/simple-atomic/simout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Oct 11 2010 18:37:23 -M5 revision c4e3d74d9a68 7726 default ext/mp_boot.patch qtip tip -M5 started Oct 11 2010 18:37:39 -M5 executing on aus-bc3-b4 -command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/60.bzip2/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/opt/long/60.bzip2/arm/linux/simple-atomic +M5 compiled Feb 7 2011 01:56:16 +M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip +M5 started Feb 7 2011 01:58:23 +M5 executing on burrito +command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/60.bzip2/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/fast/long/60.bzip2/arm/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... spec_init diff --git a/tests/long/60.bzip2/ref/arm/linux/simple-atomic/stats.txt b/tests/long/60.bzip2/ref/arm/linux/simple-atomic/stats.txt index 11106ff07..8d3a8d25e 100644 --- a/tests/long/60.bzip2/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/60.bzip2/ref/arm/linux/simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 2718053 # Simulator instruction rate (inst/s) -host_mem_usage 254288 # Number of bytes of host memory used -host_seconds 628.91 # Real time elapsed on the host -host_tick_rate 1359028059 # Simulator tick rate (ticks/s) +host_inst_rate 1030645 # Simulator instruction rate (inst/s) +host_mem_usage 229520 # Number of bytes of host memory used +host_seconds 1658.58 # Real time elapsed on the host +host_tick_rate 515323054 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1709408682 # Number of instructions simulated sim_seconds 0.854706 # Number of seconds simulated @@ -53,8 +53,24 @@ system.cpu.itb.write_hits 0 # DT system.cpu.itb.write_misses 0 # DTB write misses system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.numCycles 1709411231 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.num_busy_cycles 1709411231 # Number of busy cycles +system.cpu.num_conditional_control_insts 0 # number of instructions that are conditional controls +system.cpu.num_fp_alu_accesses 36 # Number of float alu accesses +system.cpu.num_fp_insts 36 # number of float instructions +system.cpu.num_fp_register_reads 24 # number of times the floating registers were read +system.cpu.num_fp_register_writes 16 # number of times the floating registers were written +system.cpu.num_func_calls 0 # number of times a function call or return occured +system.cpu.num_idle_cycles 0 # Number of idle cycles system.cpu.num_insts 1709408682 # Number of instructions executed -system.cpu.num_refs 660773876 # Number of memory references +system.cpu.num_int_alu_accesses 1523276793 # Number of integer alu accesses +system.cpu.num_int_insts 1523276793 # number of integer instructions +system.cpu.num_int_register_reads 4636623941 # number of times the integer registers were read +system.cpu.num_int_register_writes 1316065665 # number of times the integer registers were written +system.cpu.num_load_insts 485926830 # Number of load instructions +system.cpu.num_mem_refs 660773876 # number of memory refs +system.cpu.num_store_insts 174847046 # Number of store instructions system.cpu.workload.PROG:num_syscalls 46 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/60.bzip2/ref/arm/linux/simple-timing/config.ini b/tests/long/60.bzip2/ref/arm/linux/simple-timing/config.ini index d8eed8875..3f9e59a85 100644 --- a/tests/long/60.bzip2/ref/arm/linux/simple-timing/config.ini +++ b/tests/long/60.bzip2/ref/arm/linux/simple-timing/config.ini @@ -1,13 +1,22 @@ [root] type=Root children=system -dummy=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem mem_mode=atomic physmem=system.physmem +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 [system.cpu] type=TimingSimpleCPU @@ -152,12 +161,12 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=bzip2 input.source 1 -cwd=build/ARM_SE/tests/opt/long/60.bzip2/arm/linux/simple-timing +cwd=build/ARM_SE/tests/fast/long/60.bzip2/arm/linux/simple-timing egid=100 env= errout=cerr euid=100 -executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/bzip2 +executable=/dist/m5/cpu2000/binaries/arm/linux/bzip2 gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/60.bzip2/ref/arm/linux/simple-timing/simerr b/tests/long/60.bzip2/ref/arm/linux/simple-timing/simerr index eabe42249..cdafa164c 100755 --- a/tests/long/60.bzip2/ref/arm/linux/simple-timing/simerr +++ b/tests/long/60.bzip2/ref/arm/linux/simple-timing/simerr @@ -1,3 +1,5 @@ warn: Sockets disabled, not accepting gdb connections For more information see: http://www.m5sim.org/warn/d946bea6 +warn: Complete acc isn't called on normal stores in O3. +For more information see: http://www.m5sim.org/warn/138d8573 hack: be nice to actually delete the event here diff --git a/tests/long/60.bzip2/ref/arm/linux/simple-timing/simout b/tests/long/60.bzip2/ref/arm/linux/simple-timing/simout index fd7ecdb8c..ba8cd6dca 100755 --- a/tests/long/60.bzip2/ref/arm/linux/simple-timing/simout +++ b/tests/long/60.bzip2/ref/arm/linux/simple-timing/simout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Oct 11 2010 18:37:23 -M5 revision c4e3d74d9a68 7726 default ext/mp_boot.patch qtip tip -M5 started Oct 11 2010 18:48:19 -M5 executing on aus-bc3-b4 -command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/60.bzip2/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/opt/long/60.bzip2/arm/linux/simple-timing +M5 compiled Feb 7 2011 01:56:16 +M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip +M5 started Feb 7 2011 01:56:25 +M5 executing on burrito +command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/60.bzip2/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/fast/long/60.bzip2/arm/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... spec_init diff --git a/tests/long/60.bzip2/ref/arm/linux/simple-timing/stats.txt b/tests/long/60.bzip2/ref/arm/linux/simple-timing/stats.txt index 4a18c77a9..923e9c734 100644 --- a/tests/long/60.bzip2/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/60.bzip2/ref/arm/linux/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 640383 # Simulator instruction rate (inst/s) -host_mem_usage 262008 # Number of bytes of host memory used -host_seconds 2660.29 # Real time elapsed on the host -host_tick_rate 913967481 # Simulator tick rate (ticks/s) +host_inst_rate 495941 # Simulator instruction rate (inst/s) +host_mem_usage 237232 # Number of bytes of host memory used +host_seconds 3435.10 # Real time elapsed on the host +host_tick_rate 707817123 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1703605163 # Number of instructions simulated sim_seconds 2.431420 # Number of seconds simulated @@ -242,8 +242,24 @@ system.cpu.l2cache.warmup_cycle 538044067000 # Cy system.cpu.l2cache.writebacks 1171981 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.numCycles 4862840230 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.num_busy_cycles 4862840230 # Number of busy cycles +system.cpu.num_conditional_control_insts 0 # number of instructions that are conditional controls +system.cpu.num_fp_alu_accesses 36 # Number of float alu accesses +system.cpu.num_fp_insts 36 # number of float instructions +system.cpu.num_fp_register_reads 24 # number of times the floating registers were read +system.cpu.num_fp_register_writes 16 # number of times the floating registers were written +system.cpu.num_func_calls 0 # number of times a function call or return occured +system.cpu.num_idle_cycles 0 # Number of idle cycles system.cpu.num_insts 1703605163 # Number of instructions executed -system.cpu.num_refs 660773876 # Number of memory references +system.cpu.num_int_alu_accesses 1523276793 # Number of integer alu accesses +system.cpu.num_int_insts 1523276793 # number of integer instructions +system.cpu.num_int_register_reads 5115465619 # number of times the integer registers were read +system.cpu.num_int_register_writes 1316065727 # number of times the integer registers were written +system.cpu.num_load_insts 485926830 # Number of load instructions +system.cpu.num_mem_refs 660773876 # number of memory refs +system.cpu.num_store_insts 174847046 # Number of store instructions system.cpu.workload.PROG:num_syscalls 46 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/60.bzip2/ref/x86/linux/simple-atomic/config.ini b/tests/long/60.bzip2/ref/x86/linux/simple-atomic/config.ini index 56d944c30..89aae9c00 100644 --- a/tests/long/60.bzip2/ref/x86/linux/simple-atomic/config.ini +++ b/tests/long/60.bzip2/ref/x86/linux/simple-atomic/config.ini @@ -10,6 +10,13 @@ type=System children=cpu membus physmem mem_mode=atomic physmem=system.physmem +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 [system.cpu] type=AtomicSimpleCPU @@ -54,7 +61,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=bzip2 input.source 1 -cwd=build/X86_SE/tests/opt/long/60.bzip2/x86/linux/simple-atomic +cwd=build/X86_SE/tests/fast/long/60.bzip2/x86/linux/simple-atomic egid=100 env= errout=cerr diff --git a/tests/long/60.bzip2/ref/x86/linux/simple-atomic/simout b/tests/long/60.bzip2/ref/x86/linux/simple-atomic/simout index 2a66d5524..228e6ab0c 100755 --- a/tests/long/60.bzip2/ref/x86/linux/simple-atomic/simout +++ b/tests/long/60.bzip2/ref/x86/linux/simple-atomic/simout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jan 31 2011 14:03:49 -M5 revision aa283c8952a9 7880 default qtip stupdstats.patch tip -M5 started Jan 31 2011 14:03:51 +M5 compiled Feb 7 2011 02:32:07 +M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip +M5 started Feb 7 2011 02:32:13 M5 executing on burrito -command line: build/X86_SE/m5.opt -d build/X86_SE/tests/opt/long/60.bzip2/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/opt/long/60.bzip2/x86/linux/simple-atomic +command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/60.bzip2/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/fast/long/60.bzip2/x86/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... spec_init diff --git a/tests/long/60.bzip2/ref/x86/linux/simple-atomic/stats.txt b/tests/long/60.bzip2/ref/x86/linux/simple-atomic/stats.txt index 90a5205b5..a0361e843 100644 --- a/tests/long/60.bzip2/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/long/60.bzip2/ref/x86/linux/simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1732973 # Simulator instruction rate (inst/s) -host_mem_usage 219700 # Number of bytes of host memory used -host_seconds 2704.52 # Real time elapsed on the host -host_tick_rate 1052314398 # Simulator tick rate (ticks/s) +host_inst_rate 1421831 # Simulator instruction rate (inst/s) +host_mem_usage 223380 # Number of bytes of host memory used +host_seconds 3296.36 # Real time elapsed on the host +host_tick_rate 863379215 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 4686862651 # Number of instructions simulated sim_seconds 2.846007 # Number of seconds simulated @@ -11,8 +11,24 @@ sim_ticks 2846007259500 # N system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.numCycles 5692014520 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.num_busy_cycles 5692014520 # Number of busy cycles +system.cpu.num_conditional_control_insts 182173305 # number of instructions that are conditional controls +system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses +system.cpu.num_fp_insts 0 # number of float instructions +system.cpu.num_fp_register_reads 0 # number of times the floating registers were read +system.cpu.num_fp_register_writes 0 # number of times the floating registers were written +system.cpu.num_func_calls 0 # number of times a function call or return occured +system.cpu.num_idle_cycles 0 # Number of idle cycles system.cpu.num_insts 4686862651 # Number of instructions executed -system.cpu.num_refs 1677713086 # Number of memory references +system.cpu.num_int_alu_accesses 4686862580 # Number of integer alu accesses +system.cpu.num_int_insts 4686862580 # number of integer instructions +system.cpu.num_int_register_reads 14008880122 # number of times the integer registers were read +system.cpu.num_int_register_writes 4679057393 # number of times the integer registers were written +system.cpu.num_load_insts 1239184749 # Number of load instructions +system.cpu.num_mem_refs 1677713086 # number of memory refs +system.cpu.num_store_insts 438528337 # Number of store instructions system.cpu.workload.PROG:num_syscalls 46 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/60.bzip2/ref/x86/linux/simple-timing/config.ini b/tests/long/60.bzip2/ref/x86/linux/simple-timing/config.ini index c92e9f8b5..a92ea4a1d 100644 --- a/tests/long/60.bzip2/ref/x86/linux/simple-timing/config.ini +++ b/tests/long/60.bzip2/ref/x86/linux/simple-timing/config.ini @@ -10,6 +10,13 @@ type=System children=cpu membus physmem mem_mode=atomic physmem=system.physmem +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 [system.cpu] type=TimingSimpleCPU @@ -154,7 +161,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=bzip2 input.source 1 -cwd=build/X86_SE/tests/opt/long/60.bzip2/x86/linux/simple-timing +cwd=build/X86_SE/tests/fast/long/60.bzip2/x86/linux/simple-timing egid=100 env= errout=cerr diff --git a/tests/long/60.bzip2/ref/x86/linux/simple-timing/simout b/tests/long/60.bzip2/ref/x86/linux/simple-timing/simout index ecac67c27..2ae184132 100755 --- a/tests/long/60.bzip2/ref/x86/linux/simple-timing/simout +++ b/tests/long/60.bzip2/ref/x86/linux/simple-timing/simout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jan 31 2011 14:03:49 -M5 revision aa283c8952a9 7880 default qtip stupdstats.patch tip -M5 started Jan 31 2011 14:03:51 +M5 compiled Feb 7 2011 02:32:07 +M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip +M5 started Feb 7 2011 02:32:12 M5 executing on burrito -command line: build/X86_SE/m5.opt -d build/X86_SE/tests/opt/long/60.bzip2/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/opt/long/60.bzip2/x86/linux/simple-timing +command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/60.bzip2/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/fast/long/60.bzip2/x86/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... spec_init diff --git a/tests/long/60.bzip2/ref/x86/linux/simple-timing/stats.txt b/tests/long/60.bzip2/ref/x86/linux/simple-timing/stats.txt index c70e9b64d..21d2dce98 100644 --- a/tests/long/60.bzip2/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/60.bzip2/ref/x86/linux/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 845010 # Simulator instruction rate (inst/s) -host_mem_usage 227416 # Number of bytes of host memory used -host_seconds 5546.52 # Real time elapsed on the host -host_tick_rate 1067976230 # Simulator tick rate (ticks/s) +host_inst_rate 980837 # Simulator instruction rate (inst/s) +host_mem_usage 231100 # Number of bytes of host memory used +host_seconds 4778.43 # Real time elapsed on the host +host_tick_rate 1239642391 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 4686862651 # Number of instructions simulated sim_seconds 5.923548 # Number of seconds simulated @@ -200,8 +200,24 @@ system.cpu.l2cache.warmup_cycle 1324806325000 # C system.cpu.l2cache.writebacks 1174631 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.numCycles 11847096156 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.num_busy_cycles 11847096156 # Number of busy cycles +system.cpu.num_conditional_control_insts 182173305 # number of instructions that are conditional controls +system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses +system.cpu.num_fp_insts 0 # number of float instructions +system.cpu.num_fp_register_reads 0 # number of times the floating registers were read +system.cpu.num_fp_register_writes 0 # number of times the floating registers were written +system.cpu.num_func_calls 0 # number of times a function call or return occured +system.cpu.num_idle_cycles 0 # Number of idle cycles system.cpu.num_insts 4686862651 # Number of instructions executed -system.cpu.num_refs 1677713086 # Number of memory references +system.cpu.num_int_alu_accesses 4686862580 # Number of integer alu accesses +system.cpu.num_int_insts 4686862580 # number of integer instructions +system.cpu.num_int_register_reads 14008880122 # number of times the integer registers were read +system.cpu.num_int_register_writes 4679057393 # number of times the integer registers were written +system.cpu.num_load_insts 1239184749 # Number of load instructions +system.cpu.num_mem_refs 1677713086 # number of memory refs +system.cpu.num_store_insts 438528337 # Number of store instructions system.cpu.workload.PROG:num_syscalls 46 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/config.ini b/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/config.ini index 389a82884..8ab14c5fa 100644 --- a/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/config.ini +++ b/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/config.ini @@ -1,13 +1,22 @@ [root] type=Root children=system -dummy=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem mem_mode=atomic physmem=system.physmem +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 [system.cpu] type=InOrderCPU diff --git a/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/simout b/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/simout index 6bea6bb9d..2bd9f8140 100755 --- a/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/simout +++ b/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jan 24 2011 21:05:28 -M5 revision Unknown -M5 started Jan 24 2011 21:05:32 -M5 executing on m55-002.pool +M5 compiled Feb 7 2011 01:47:18 +M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip +M5 started Feb 7 2011 01:47:37 +M5 executing on burrito command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/inorder-timing Couldn't unlink build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/inorder-timing/smred.sav Couldn't unlink build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/inorder-timing/smred.sv2 diff --git a/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt index 81e378671..bb16b8b96 100644 --- a/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 66004 # Simulator instruction rate (inst/s) -host_mem_usage 1421192 # Number of bytes of host memory used -host_seconds 1392.38 # Real time elapsed on the host -host_tick_rate 29109416 # Simulator tick rate (ticks/s) +host_inst_rate 25888 # Simulator instruction rate (inst/s) +host_mem_usage 1480704 # Number of bytes of host memory used +host_seconds 3550.03 # Real time elapsed on the host +host_tick_rate 11417230 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 91903057 # Number of instructions simulated sim_seconds 0.040531 # Number of seconds simulated @@ -272,6 +272,8 @@ system.cpu.l2cache.total_refs 7072 # To system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.numCycles 81062947 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.runCycles 74310489 # Number of cycles cpu stages are processed. system.cpu.smtCommittedInsts 0 # Number of SMT Instructions Simulated (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode diff --git a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini index 02074cf40..01f3bf111 100644 --- a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini @@ -1,13 +1,22 @@ [root] type=Root children=system -dummy=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem mem_mode=atomic physmem=system.physmem +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 [system.cpu] type=DerivO3CPU diff --git a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/simout b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/simout index 6d564a58f..b9f2d3d21 100755 --- a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/simout @@ -5,11 +5,13 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jan 17 2011 16:24:53 -M5 revision f72d94f8c275 7839 default qtip tip outgoing.patch qbase -M5 started Jan 17 2011 16:30:09 -M5 executing on zizzer +M5 compiled Feb 7 2011 01:47:18 +M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip +M5 started Feb 7 2011 01:47:48 +M5 executing on burrito command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/o3-timing +Couldn't unlink build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/o3-timing/smred.sav +Couldn't unlink build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/o3-timing/smred.sv2 Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stats.txt index 6e4f9aea5..2fcd0832c 100644 --- a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 134338 # Simulator instruction rate (inst/s) -host_mem_usage 210480 # Number of bytes of host memory used -host_seconds 626.63 # Real time elapsed on the host -host_tick_rate 64841631 # Simulator tick rate (ticks/s) +host_inst_rate 68515 # Simulator instruction rate (inst/s) +host_mem_usage 230924 # Number of bytes of host memory used +host_seconds 1228.63 # Real time elapsed on the host +host_tick_rate 33070698 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 84179709 # Number of instructions simulated sim_seconds 0.040632 # Number of seconds simulated @@ -37,6 +37,9 @@ system.cpu.commit.COM:committed_per_cycle::min_value 0 system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::total 73022923 # Number of insts commited each cycle system.cpu.commit.COM:count 91903055 # Number of instructions committed +system.cpu.commit.COM:fp_insts 6862061 # Number of committed floating point instructions. +system.cpu.commit.COM:function_calls 1029620 # Number of function calls committed. +system.cpu.commit.COM:int_insts 79581076 # Number of committed integer instructions. system.cpu.commit.COM:loads 19996198 # Number of loads committed system.cpu.commit.COM:membars 0 # Number of memory barriers committed system.cpu.commit.COM:refs 26497301 # Number of memory references committed @@ -171,6 +174,8 @@ system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Nu system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::total 81154458 # Number of instructions fetched each cycle (Total) +system.cpu.fp_regfile_reads 6156758 # number of floating regfile reads +system.cpu.fp_regfile_writes 6040765 # number of floating regfile writes system.cpu.icache.ReadReq_accesses 19059447 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_avg_miss_latency 15766.588953 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 11899.082569 # average ReadReq mshr miss latency @@ -270,6 +275,8 @@ system.cpu.iew.lsq.thread.0.squashedStores 4154704 # system.cpu.iew.memOrderViolationEvents 268955 # Number of memory order violations system.cpu.iew.predictedNotTakenIncorrect 456787 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedTakenIncorrect 1600647 # Number of branches that were predicted taken incorrectly +system.cpu.int_regfile_reads 137465323 # number of integer regfile reads +system.cpu.int_regfile_writes 75768353 # number of integer regfile writes system.cpu.ipc 1.035892 # IPC: Instructions Per Cycle system.cpu.ipc_total 1.035892 # IPC: Total IPC of All Threads system.cpu.iq.ISSUE:FU_type_0::No_OpClass 7 0.00% 0.00% # Type of FU issued @@ -361,6 +368,14 @@ system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::total 81154458 # Number of insts issued each cycle system.cpu.iq.ISSUE:rate 1.279986 # Inst issue rate +system.cpu.iq.fp_alu_accesses 8012478 # Number of floating point alu accesses +system.cpu.iq.fp_inst_queue_reads 15186691 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_wakeup_accesses 7058808 # Number of floating instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_writes 12278263 # Number of floating instruction queue writes +system.cpu.iq.int_alu_accesses 97954442 # Number of integer alu accesses +system.cpu.iq.int_inst_queue_reads 276254930 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_wakeup_accesses 92993062 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_writes 174004519 # Number of integer instruction queue writes system.cpu.iq.iqInstsAdded 135471680 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqInstsIssued 104015508 # Number of instructions issued system.cpu.iq.iqNonSpecInstsAdded 434 # Number of non-speculative instructions added to the IQ @@ -457,7 +472,11 @@ system.cpu.memDep0.conflictingLoads 17824866 # Nu system.cpu.memDep0.conflictingStores 5359806 # Number of conflicting stores. system.cpu.memDep0.insertedLoads 33850050 # Number of loads inserted to the mem dependence unit. system.cpu.memDep0.insertedStores 10655807 # Number of stores inserted to the mem dependence unit. +system.cpu.misc_regfile_reads 712336 # number of misc regfile reads +system.cpu.misc_regfile_writes 1 # number of misc regfile writes system.cpu.numCycles 81263024 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.rename.RENAME:BlockCycles 1835260 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 68427361 # Number of HB maps that are committed system.cpu.rename.RENAME:IQFullEvents 1124456 # Number of times rename has blocked due to IQ full @@ -470,10 +489,14 @@ system.cpu.rename.RENAME:RunCycles 28432140 # Nu system.cpu.rename.RENAME:SquashCycles 8131535 # Number of cycles rename is squashing system.cpu.rename.RENAME:UnblockCycles 2161646 # Number of cycles rename is unblocking system.cpu.rename.RENAME:UndoneMaps 47087306 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:fp_rename_lookups 11932541 # Number of floating rename lookups +system.cpu.rename.RENAME:int_rename_lookups 190714138 # Number of integer rename lookups system.cpu.rename.RENAME:serializeStallCycles 5198 # count of cycles rename stalled for serializing inst system.cpu.rename.RENAME:serializingInsts 467 # count of serializing insts renamed system.cpu.rename.RENAME:skidInsts 4785663 # count of insts added to the skid buffer system.cpu.rename.RENAME:tempSerializingInsts 456 # count of temporary serializing insts renamed +system.cpu.rob.rob_reads 218412469 # The number of ROB reads +system.cpu.rob.rob_writes 304705559 # The number of ROB writes system.cpu.timesIdled 2403 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 389 # Number of system calls diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/config.ini index a6e47a29e..1801d3968 100644 --- a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/config.ini +++ b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/config.ini @@ -1,13 +1,22 @@ [root] type=Root children=system -dummy=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem mem_mode=atomic physmem=system.physmem +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 [system.cpu] type=AtomicSimpleCPU @@ -57,7 +66,7 @@ egid=100 env= errout=cerr euid=100 -executable=/chips/pd/randd/dist/cpu2000/binaries/alpha/tru64/twolf +executable=/dist/m5/cpu2000/binaries/alpha/tru64/twolf gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/simerr b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/simerr index 67f69f09d..79a2396a6 100755 --- a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/simerr +++ b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/simerr @@ -1,5 +1,11 @@ warn: Sockets disabled, not accepting gdb connections For more information see: http://www.m5sim.org/warn/d946bea6 +warn: Prefetch instrutions is Alpha do not do anything +For more information see: http://www.m5sim.org/warn/3e0eccba +warn: Prefetch instrutions is Alpha do not do anything +For more information see: http://www.m5sim.org/warn/3e0eccba +warn: Prefetch instrutions is Alpha do not do anything +For more information see: http://www.m5sim.org/warn/3e0eccba warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...) For more information see: http://www.m5sim.org/warn/5c5b547f hack: be nice to actually delete the event here diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/simout b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/simout index dc1519d82..06628f244 100755 --- a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/simout +++ b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/simout @@ -1,5 +1,3 @@ -Redirecting stdout to build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-atomic/simout -Redirecting stderr to build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-atomic/simerr M5 Simulator System Copyright (c) 2001-2008 @@ -7,11 +5,13 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Nov 2 2010 21:30:55 -M5 revision 0af3760102ec+ 7713+ default qtip ext/alpha_prefetch.patch tip -M5 started Nov 2 2010 21:32:41 -M5 executing on aus-bc2-b15 +M5 compiled Feb 7 2011 01:47:18 +M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip +M5 started Feb 7 2011 01:47:38 +M5 executing on burrito command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-atomic +Couldn't unlink build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-atomic/smred.sav +Couldn't unlink build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-atomic/smred.sv2 Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt index 50ef29969..3667c8fef 100644 --- a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt +++ b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 4196549 # Simulator instruction rate (inst/s) -host_mem_usage 235848 # Number of bytes of host memory used -host_seconds 21.90 # Real time elapsed on the host -host_tick_rate 2098254960 # Simulator tick rate (ticks/s) +host_inst_rate 1609489 # Simulator instruction rate (inst/s) +host_mem_usage 222008 # Number of bytes of host memory used +host_seconds 57.10 # Real time elapsed on the host +host_tick_rate 804741446 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 91903056 # Number of instructions simulated sim_seconds 0.045952 # Number of seconds simulated @@ -43,8 +43,24 @@ system.cpu.itb.write_hits 0 # DT system.cpu.itb.write_misses 0 # DTB write misses system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.numCycles 91903136 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.num_busy_cycles 91903136 # Number of busy cycles +system.cpu.num_conditional_control_insts 7465012 # number of instructions that are conditional controls +system.cpu.num_fp_alu_accesses 6862064 # Number of float alu accesses +system.cpu.num_fp_insts 6862064 # number of float instructions +system.cpu.num_fp_register_reads 6071661 # number of times the floating registers were read +system.cpu.num_fp_register_writes 5851888 # number of times the floating registers were written +system.cpu.num_func_calls 2059216 # number of times a function call or return occured +system.cpu.num_idle_cycles 0 # Number of idle cycles system.cpu.num_insts 91903056 # Number of instructions executed -system.cpu.num_refs 26497334 # Number of memory references +system.cpu.num_int_alu_accesses 79581109 # Number of integer alu accesses +system.cpu.num_int_insts 79581109 # number of integer instructions +system.cpu.num_int_register_reads 115028592 # number of times the integer registers were read +system.cpu.num_int_register_writes 62575473 # number of times the integer registers were written +system.cpu.num_load_insts 19996208 # Number of load instructions +system.cpu.num_mem_refs 26497334 # number of memory refs +system.cpu.num_store_insts 6501126 # Number of store instructions system.cpu.workload.PROG:num_syscalls 389 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.ini b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.ini index 92176625f..cab9a523d 100644 --- a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.ini @@ -1,13 +1,22 @@ [root] type=Root children=system -dummy=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem mem_mode=atomic physmem=system.physmem +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 [system.cpu] type=TimingSimpleCPU @@ -157,7 +166,7 @@ egid=100 env= errout=cerr euid=100 -executable=/chips/pd/randd/dist/cpu2000/binaries/alpha/tru64/twolf +executable=/dist/m5/cpu2000/binaries/alpha/tru64/twolf gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/simerr b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/simerr index 67f69f09d..79a2396a6 100755 --- a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/simerr +++ b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/simerr @@ -1,5 +1,11 @@ warn: Sockets disabled, not accepting gdb connections For more information see: http://www.m5sim.org/warn/d946bea6 +warn: Prefetch instrutions is Alpha do not do anything +For more information see: http://www.m5sim.org/warn/3e0eccba +warn: Prefetch instrutions is Alpha do not do anything +For more information see: http://www.m5sim.org/warn/3e0eccba +warn: Prefetch instrutions is Alpha do not do anything +For more information see: http://www.m5sim.org/warn/3e0eccba warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...) For more information see: http://www.m5sim.org/warn/5c5b547f hack: be nice to actually delete the event here diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/simout b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/simout index 4d237e859..5503045c3 100755 --- a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/simout +++ b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/simout @@ -1,5 +1,3 @@ -Redirecting stdout to build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-timing/simout -Redirecting stderr to build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-timing/simerr M5 Simulator System Copyright (c) 2001-2008 @@ -7,11 +5,13 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Nov 2 2010 21:30:55 -M5 revision 0af3760102ec+ 7713+ default qtip ext/alpha_prefetch.patch tip -M5 started Nov 2 2010 22:35:14 -M5 executing on aus-bc2-b15 +M5 compiled Feb 7 2011 01:47:18 +M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip +M5 started Feb 7 2011 01:47:48 +M5 executing on burrito command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-timing +Couldn't unlink build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-timing/smred.sav +Couldn't unlink build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-timing/smred.sv2 Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/stats.txt index 90176f56c..2aaa18b18 100644 --- a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 2386222 # Simulator instruction rate (inst/s) -host_mem_usage 243572 # Number of bytes of host memory used -host_seconds 38.51 # Real time elapsed on the host -host_tick_rate 3083013039 # Simulator tick rate (ticks/s) +host_inst_rate 559604 # Simulator instruction rate (inst/s) +host_mem_usage 229724 # Number of bytes of host memory used +host_seconds 164.23 # Real time elapsed on the host +host_tick_rate 723015392 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 91903056 # Number of instructions simulated sim_seconds 0.118740 # Number of seconds simulated @@ -232,8 +232,24 @@ system.cpu.l2cache.warmup_cycle 0 # Cy system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.numCycles 237480098 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.num_busy_cycles 237480098 # Number of busy cycles +system.cpu.num_conditional_control_insts 7465012 # number of instructions that are conditional controls +system.cpu.num_fp_alu_accesses 6862064 # Number of float alu accesses +system.cpu.num_fp_insts 6862064 # number of float instructions +system.cpu.num_fp_register_reads 6071661 # number of times the floating registers were read +system.cpu.num_fp_register_writes 5851888 # number of times the floating registers were written +system.cpu.num_func_calls 2059216 # number of times a function call or return occured +system.cpu.num_idle_cycles 0 # Number of idle cycles system.cpu.num_insts 91903056 # Number of instructions executed -system.cpu.num_refs 26497334 # Number of memory references +system.cpu.num_int_alu_accesses 79581109 # Number of integer alu accesses +system.cpu.num_int_insts 79581109 # number of integer instructions +system.cpu.num_int_register_reads 115028592 # number of times the integer registers were read +system.cpu.num_int_register_writes 62575473 # number of times the integer registers were written +system.cpu.num_load_insts 19996208 # Number of load instructions +system.cpu.num_mem_refs 26497334 # number of memory refs +system.cpu.num_store_insts 6501126 # Number of store instructions system.cpu.workload.PROG:num_syscalls 389 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/70.twolf/ref/arm/linux/o3-timing/config.ini b/tests/long/70.twolf/ref/arm/linux/o3-timing/config.ini index 95580ac45..f95eb4d89 100644 --- a/tests/long/70.twolf/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/70.twolf/ref/arm/linux/o3-timing/config.ini @@ -1,13 +1,22 @@ [root] type=Root children=system -dummy=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem mem_mode=atomic physmem=system.physmem +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 [system.cpu] type=DerivO3CPU @@ -484,7 +493,7 @@ egid=100 env= errout=cerr euid=100 -executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/twolf +executable=/dist/m5/cpu2000/binaries/arm/linux/twolf gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/70.twolf/ref/arm/linux/o3-timing/simout b/tests/long/70.twolf/ref/arm/linux/o3-timing/simout index 832370508..46dd2c791 100755 --- a/tests/long/70.twolf/ref/arm/linux/o3-timing/simout +++ b/tests/long/70.twolf/ref/arm/linux/o3-timing/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jan 11 2011 18:16:01 -M5 revision b39a8457b332 7816 default ext/o3_regressions.patch qtip tip -M5 started Jan 12 2011 04:18:31 -M5 executing on u200439-lin.austin.arm.com +M5 compiled Feb 7 2011 01:56:16 +M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip +M5 started Feb 7 2011 02:00:24 +M5 executing on burrito command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/70.twolf/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/fast/long/70.twolf/arm/linux/o3-timing Couldn't unlink build/ARM_SE/tests/fast/long/70.twolf/arm/linux/o3-timing/smred.sav Couldn't unlink build/ARM_SE/tests/fast/long/70.twolf/arm/linux/o3-timing/smred.sv2 diff --git a/tests/long/70.twolf/ref/arm/linux/o3-timing/stats.txt b/tests/long/70.twolf/ref/arm/linux/o3-timing/stats.txt index a8b50fb87..21ada4fbc 100644 --- a/tests/long/70.twolf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/70.twolf/ref/arm/linux/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 96216 # Simulator instruction rate (inst/s) -host_mem_usage 255460 # Number of bytes of host memory used -host_seconds 1920.75 # Real time elapsed on the host -host_tick_rate 78000522 # Simulator tick rate (ticks/s) +host_inst_rate 61621 # Simulator instruction rate (inst/s) +host_mem_usage 241964 # Number of bytes of host memory used +host_seconds 2999.07 # Real time elapsed on the host +host_tick_rate 49955205 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 184806751 # Number of instructions simulated sim_seconds 0.149819 # Number of seconds simulated @@ -37,6 +37,9 @@ system.cpu.commit.COM:committed_per_cycle::min_value 0 system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::total 285162307 # Number of insts commited each cycle system.cpu.commit.COM:count 184806751 # Number of instructions committed +system.cpu.commit.COM:fp_insts 1730659 # Number of committed floating point instructions. +system.cpu.commit.COM:function_calls 0 # Number of function calls committed. +system.cpu.commit.COM:int_insts 146860811 # Number of committed integer instructions. system.cpu.commit.COM:loads 29554611 # Number of loads committed system.cpu.commit.COM:membars 0 # Number of memory barriers committed system.cpu.commit.COM:refs 42081439 # Number of memory references committed @@ -171,6 +174,8 @@ system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Nu system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::total 299566319 # Number of instructions fetched each cycle (Total) +system.cpu.fp_regfile_reads 2799107 # number of floating regfile reads +system.cpu.fp_regfile_writes 2446180 # number of floating regfile writes system.cpu.icache.ReadReq_accesses 24416320 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_avg_miss_latency 25129.997165 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 21979.962430 # average ReadReq mshr miss latency @@ -270,6 +275,8 @@ system.cpu.iew.lsq.thread.0.squashedStores 2461724 # system.cpu.iew.memOrderViolationEvents 295230 # Number of memory order violations system.cpu.iew.predictedNotTakenIncorrect 1407561 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedTakenIncorrect 11669168 # Number of branches that were predicted taken incorrectly +system.cpu.int_regfile_reads 457836856 # number of integer regfile reads +system.cpu.int_regfile_writes 195349958 # number of integer regfile writes system.cpu.ipc 0.616766 # IPC: Instructions Per Cycle system.cpu.ipc_total 0.616766 # IPC: Total IPC of All Threads system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued @@ -361,6 +368,14 @@ system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::total 299566319 # Number of insts issued each cycle system.cpu.iq.ISSUE:rate 0.711320 # Inst issue rate +system.cpu.iq.fp_alu_accesses 1965612 # Number of floating point alu accesses +system.cpu.iq.fp_inst_queue_reads 3923910 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_wakeup_accesses 1824312 # Number of floating instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_writes 2255873 # Number of floating instruction queue writes +system.cpu.iq.int_alu_accesses 212345848 # Number of integer alu accesses +system.cpu.iq.int_inst_queue_reads 723342864 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_wakeup_accesses 197666637 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_writes 240391153 # Number of integer instruction queue writes system.cpu.iq.iqInstsAdded 220060942 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqInstsIssued 213138842 # Number of instructions issued system.cpu.iq.iqNonSpecInstsAdded 1668755 # Number of non-speculative instructions added to the IQ @@ -463,7 +478,11 @@ system.cpu.memDep0.conflictingLoads 3889323 # Nu system.cpu.memDep0.conflictingStores 2640936 # Number of conflicting stores. system.cpu.memDep0.insertedLoads 37075609 # Number of loads inserted to the mem dependence unit. system.cpu.memDep0.insertedStores 14988552 # Number of stores inserted to the mem dependence unit. +system.cpu.misc_regfile_reads 328971278 # number of misc regfile reads +system.cpu.misc_regfile_writes 4891827 # number of misc regfile writes system.cpu.numCycles 299638437 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.rename.RENAME:BlockCycles 3074 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 178683528 # Number of HB maps that are committed system.cpu.rename.RENAME:IQFullEvents 2322 # Number of times rename has blocked due to IQ full @@ -476,10 +495,14 @@ system.cpu.rename.RENAME:RunCycles 190277990 # Nu system.cpu.rename.RENAME:SquashCycles 14404012 # Number of cycles rename is squashing system.cpu.rename.RENAME:UnblockCycles 1750038 # Number of cycles rename is unblocking system.cpu.rename.RENAME:UndoneMaps 71145762 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:fp_rename_lookups 14827185 # Number of floating rename lookups +system.cpu.rename.RENAME:int_rename_lookups 586253105 # Number of integer rename lookups system.cpu.rename.RENAME:serializeStallCycles 19853445 # count of cycles rename stalled for serializing inst system.cpu.rename.RENAME:serializingInsts 2086015 # count of serializing insts renamed system.cpu.rename.RENAME:skidInsts 2928694 # count of insts added to the skid buffer system.cpu.rename.RENAME:tempSerializingInsts 1863087 # count of temporary serializing insts renamed +system.cpu.rob.rob_reads 506291228 # The number of ROB reads +system.cpu.rob.rob_writes 457856948 # The number of ROB writes system.cpu.timesIdled 1363 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 400 # Number of system calls diff --git a/tests/long/70.twolf/ref/arm/linux/simple-atomic/config.ini b/tests/long/70.twolf/ref/arm/linux/simple-atomic/config.ini index 9f4b7679d..283406dc2 100644 --- a/tests/long/70.twolf/ref/arm/linux/simple-atomic/config.ini +++ b/tests/long/70.twolf/ref/arm/linux/simple-atomic/config.ini @@ -1,13 +1,22 @@ [root] type=Root children=system -dummy=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem mem_mode=atomic physmem=system.physmem +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 [system.cpu] type=AtomicSimpleCPU @@ -52,12 +61,12 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=twolf smred -cwd=build/ARM_SE/tests/opt/long/70.twolf/arm/linux/simple-atomic +cwd=build/ARM_SE/tests/fast/long/70.twolf/arm/linux/simple-atomic egid=100 env= errout=cerr euid=100 -executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/twolf +executable=/dist/m5/cpu2000/binaries/arm/linux/twolf gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/70.twolf/ref/arm/linux/simple-atomic/simout b/tests/long/70.twolf/ref/arm/linux/simple-atomic/simout index 4f3382663..c50fadfb0 100755 --- a/tests/long/70.twolf/ref/arm/linux/simple-atomic/simout +++ b/tests/long/70.twolf/ref/arm/linux/simple-atomic/simout @@ -5,13 +5,13 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Oct 11 2010 18:37:23 -M5 revision c4e3d74d9a68 7726 default ext/mp_boot.patch qtip tip -M5 started Oct 11 2010 19:22:41 -M5 executing on aus-bc3-b4 -command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/70.twolf/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/opt/long/70.twolf/arm/linux/simple-atomic -Couldn't unlink build/ARM_SE/tests/opt/long/70.twolf/arm/linux/simple-atomic/smred.sav -Couldn't unlink build/ARM_SE/tests/opt/long/70.twolf/arm/linux/simple-atomic/smred.sv2 +M5 compiled Feb 7 2011 01:56:16 +M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip +M5 started Feb 7 2011 01:56:35 +M5 executing on burrito +command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/70.twolf/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/fast/long/70.twolf/arm/linux/simple-atomic +Couldn't unlink build/ARM_SE/tests/fast/long/70.twolf/arm/linux/simple-atomic/smred.sav +Couldn't unlink build/ARM_SE/tests/fast/long/70.twolf/arm/linux/simple-atomic/smred.sv2 Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/70.twolf/ref/arm/linux/simple-atomic/stats.txt b/tests/long/70.twolf/ref/arm/linux/simple-atomic/stats.txt index 45e4b8820..4a204d0cd 100644 --- a/tests/long/70.twolf/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/70.twolf/ref/arm/linux/simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 2742393 # Simulator instruction rate (inst/s) -host_mem_usage 257424 # Number of bytes of host memory used -host_seconds 68.12 # Real time elapsed on the host -host_tick_rate 1499949275 # Simulator tick rate (ticks/s) +host_inst_rate 1012006 # Simulator instruction rate (inst/s) +host_mem_usage 232796 # Number of bytes of host memory used +host_seconds 184.60 # Real time elapsed on the host +host_tick_rate 553516772 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 186818826 # Number of instructions simulated sim_seconds 0.102181 # Number of seconds simulated @@ -53,8 +53,24 @@ system.cpu.itb.write_hits 0 # DT system.cpu.itb.write_misses 0 # DTB write misses system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.numCycles 204361469 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.num_busy_cycles 204361469 # Number of busy cycles +system.cpu.num_conditional_control_insts 0 # number of instructions that are conditional controls +system.cpu.num_fp_alu_accesses 1752310 # Number of float alu accesses +system.cpu.num_fp_insts 1752310 # number of float instructions +system.cpu.num_fp_register_reads 2822225 # number of times the floating registers were read +system.cpu.num_fp_register_writes 2378039 # number of times the floating registers were written +system.cpu.num_func_calls 0 # number of times a function call or return occured +system.cpu.num_idle_cycles 0 # Number of idle cycles system.cpu.num_insts 186818826 # Number of instructions executed -system.cpu.num_refs 42511846 # Number of memory references +system.cpu.num_int_alu_accesses 148453796 # Number of integer alu accesses +system.cpu.num_int_insts 148453796 # number of integer instructions +system.cpu.num_int_register_reads 440904784 # number of times the integer registers were read +system.cpu.num_int_register_writes 179338779 # number of times the integer registers were written +system.cpu.num_load_insts 29867211 # Number of load instructions +system.cpu.num_mem_refs 42511846 # number of memory refs +system.cpu.num_store_insts 12644635 # Number of store instructions system.cpu.workload.PROG:num_syscalls 400 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/70.twolf/ref/arm/linux/simple-timing/config.ini b/tests/long/70.twolf/ref/arm/linux/simple-timing/config.ini index c7e80818a..d150b1761 100644 --- a/tests/long/70.twolf/ref/arm/linux/simple-timing/config.ini +++ b/tests/long/70.twolf/ref/arm/linux/simple-timing/config.ini @@ -1,13 +1,22 @@ [root] type=Root children=system -dummy=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem mem_mode=atomic physmem=system.physmem +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 [system.cpu] type=TimingSimpleCPU @@ -152,12 +161,12 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=twolf smred -cwd=build/ARM_SE/tests/opt/long/70.twolf/arm/linux/simple-timing +cwd=build/ARM_SE/tests/fast/long/70.twolf/arm/linux/simple-timing egid=100 env= errout=cerr euid=100 -executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/twolf +executable=/dist/m5/cpu2000/binaries/arm/linux/twolf gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/70.twolf/ref/arm/linux/simple-timing/simerr b/tests/long/70.twolf/ref/arm/linux/simple-timing/simerr index eabe42249..83ecbdfc0 100755 --- a/tests/long/70.twolf/ref/arm/linux/simple-timing/simerr +++ b/tests/long/70.twolf/ref/arm/linux/simple-timing/simerr @@ -1,3 +1,13 @@ warn: Sockets disabled, not accepting gdb connections For more information see: http://www.m5sim.org/warn/d946bea6 +warn: Complete acc isn't called on normal stores in O3. +For more information see: http://www.m5sim.org/warn/138d8573 +warn: Complete acc isn't called on normal stores in O3. +For more information see: http://www.m5sim.org/warn/138d8573 +warn: Complete acc isn't called on normal stores in O3. +For more information see: http://www.m5sim.org/warn/138d8573 +warn: Complete acc isn't called on normal stores in O3. +For more information see: http://www.m5sim.org/warn/138d8573 +warn: Complete acc isn't called on normal stores in O3. +For more information see: http://www.m5sim.org/warn/138d8573 hack: be nice to actually delete the event here diff --git a/tests/long/70.twolf/ref/arm/linux/simple-timing/simout b/tests/long/70.twolf/ref/arm/linux/simple-timing/simout index 60b3eda0f..5cb7e11c7 100755 --- a/tests/long/70.twolf/ref/arm/linux/simple-timing/simout +++ b/tests/long/70.twolf/ref/arm/linux/simple-timing/simout @@ -5,13 +5,13 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Oct 11 2010 18:37:23 -M5 revision c4e3d74d9a68 7726 default ext/mp_boot.patch qtip tip -M5 started Oct 11 2010 19:00:18 -M5 executing on aus-bc3-b4 -command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/70.twolf/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/opt/long/70.twolf/arm/linux/simple-timing -Couldn't unlink build/ARM_SE/tests/opt/long/70.twolf/arm/linux/simple-timing/smred.sav -Couldn't unlink build/ARM_SE/tests/opt/long/70.twolf/arm/linux/simple-timing/smred.sv2 +M5 compiled Feb 7 2011 01:56:16 +M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip +M5 started Feb 7 2011 01:56:24 +M5 executing on burrito +command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/70.twolf/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/fast/long/70.twolf/arm/linux/simple-timing +Couldn't unlink build/ARM_SE/tests/fast/long/70.twolf/arm/linux/simple-timing/smred.sav +Couldn't unlink build/ARM_SE/tests/fast/long/70.twolf/arm/linux/simple-timing/smred.sv2 Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/70.twolf/ref/arm/linux/simple-timing/stats.txt b/tests/long/70.twolf/ref/arm/linux/simple-timing/stats.txt index b971df920..715b30669 100644 --- a/tests/long/70.twolf/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/70.twolf/ref/arm/linux/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 709254 # Simulator instruction rate (inst/s) -host_mem_usage 265144 # Number of bytes of host memory used -host_seconds 262.72 # Real time elapsed on the host -host_tick_rate 883179772 # Simulator tick rate (ticks/s) +host_inst_rate 504285 # Simulator instruction rate (inst/s) +host_mem_usage 240500 # Number of bytes of host memory used +host_seconds 369.50 # Real time elapsed on the host +host_tick_rate 627947562 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 186333855 # Number of instructions simulated sim_seconds 0.232028 # Number of seconds simulated @@ -242,8 +242,24 @@ system.cpu.l2cache.warmup_cycle 0 # Cy system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.numCycles 464055342 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.num_busy_cycles 464055342 # Number of busy cycles +system.cpu.num_conditional_control_insts 0 # number of instructions that are conditional controls +system.cpu.num_fp_alu_accesses 1752310 # Number of float alu accesses +system.cpu.num_fp_insts 1752310 # number of float instructions +system.cpu.num_fp_register_reads 2822225 # number of times the floating registers were read +system.cpu.num_fp_register_writes 2378039 # number of times the floating registers were written +system.cpu.num_func_calls 0 # number of times a function call or return occured +system.cpu.num_idle_cycles 0 # Number of idle cycles system.cpu.num_insts 186333855 # Number of instructions executed -system.cpu.num_refs 42511846 # Number of memory references +system.cpu.num_int_alu_accesses 148453796 # Number of integer alu accesses +system.cpu.num_int_insts 148453796 # number of integer instructions +system.cpu.num_int_register_reads 470866018 # number of times the integer registers were read +system.cpu.num_int_register_writes 179570637 # number of times the integer registers were written +system.cpu.num_load_insts 29867211 # Number of load instructions +system.cpu.num_mem_refs 42511846 # number of memory refs +system.cpu.num_store_insts 12644635 # Number of store instructions system.cpu.workload.PROG:num_syscalls 400 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/config.ini b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/config.ini index 1b0da48ab..c1dd735f6 100644 --- a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/config.ini +++ b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/config.ini @@ -1,13 +1,22 @@ [root] type=Root children=system -dummy=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem mem_mode=atomic physmem=system.physmem +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 [system.cpu] type=AtomicSimpleCPU @@ -57,7 +66,7 @@ egid=100 env= errout=cerr euid=100 -executable=/proj/aatl_perfmod_arch/m5_binaries/cpu2000/binaries/sparc/linux/twolf +executable=/dist/m5/cpu2000/binaries/sparc/linux/twolf gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/simout b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/simout index 30e9edddf..f4dfd8899 100755 --- a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/simout +++ b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/simout @@ -5,11 +5,13 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 25 2010 03:11:27 -M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip -M5 started Feb 25 2010 03:35:37 -M5 executing on SC2B0619 +M5 compiled Feb 7 2011 02:13:30 +M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip +M5 started Feb 7 2011 02:13:39 +M5 executing on burrito command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-atomic -re tests/run.py build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-atomic +Couldn't unlink build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-atomic/smred.sav +Couldn't unlink build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-atomic/smred.sv2 Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/stats.txt b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/stats.txt index ec86f0831..5f3549812 100644 --- a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/stats.txt +++ b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1979245 # Simulator instruction rate (inst/s) -host_mem_usage 190260 # Number of bytes of host memory used -host_seconds 97.74 # Real time elapsed on the host -host_tick_rate 989625806 # Simulator tick rate (ticks/s) +host_inst_rate 1142521 # Simulator instruction rate (inst/s) +host_mem_usage 224208 # Number of bytes of host memory used +host_seconds 169.31 # Real time elapsed on the host +host_tick_rate 571263026 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 193444769 # Number of instructions simulated sim_seconds 0.096723 # Number of seconds simulated @@ -11,8 +11,24 @@ sim_ticks 96722951500 # Nu system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.numCycles 193445904 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.num_busy_cycles 193445904 # Number of busy cycles +system.cpu.num_conditional_control_insts 0 # number of instructions that are conditional controls +system.cpu.num_fp_alu_accesses 1970372 # Number of float alu accesses +system.cpu.num_fp_insts 1970372 # number of float instructions +system.cpu.num_fp_register_reads 3181089 # number of times the floating registers were read +system.cpu.num_fp_register_writes 2974850 # number of times the floating registers were written +system.cpu.num_func_calls 0 # number of times a function call or return occured +system.cpu.num_idle_cycles 0 # Number of idle cycles system.cpu.num_insts 193444769 # Number of instructions executed -system.cpu.num_refs 76733959 # Number of memory references +system.cpu.num_int_alu_accesses 167974818 # Number of integer alu accesses +system.cpu.num_int_insts 167974818 # number of integer instructions +system.cpu.num_int_register_reads 352386257 # number of times the integer registers were read +system.cpu.num_int_register_writes 163703467 # number of times the integer registers were written +system.cpu.num_load_insts 57735092 # Number of load instructions +system.cpu.num_mem_refs 76733959 # number of memory refs +system.cpu.num_store_insts 18998867 # Number of store instructions system.cpu.workload.PROG:num_syscalls 401 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-timing/config.ini b/tests/long/70.twolf/ref/sparc/linux/simple-timing/config.ini index dc0731aa6..c8439f7fb 100644 --- a/tests/long/70.twolf/ref/sparc/linux/simple-timing/config.ini +++ b/tests/long/70.twolf/ref/sparc/linux/simple-timing/config.ini @@ -1,13 +1,22 @@ [root] type=Root children=system -dummy=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem mem_mode=atomic physmem=system.physmem +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 [system.cpu] type=TimingSimpleCPU @@ -152,7 +161,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=twolf smred -cwd=build/SPARC_SE/tests/opt/long/70.twolf/sparc/linux/simple-timing +cwd=build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-timing egid=100 env= errout=cerr diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-timing/simout b/tests/long/70.twolf/ref/sparc/linux/simple-timing/simout index a4fbf8115..a4abb12dd 100755 --- a/tests/long/70.twolf/ref/sparc/linux/simple-timing/simout +++ b/tests/long/70.twolf/ref/sparc/linux/simple-timing/simout @@ -1,5 +1,3 @@ -Redirecting stdout to build/SPARC_SE/tests/opt/long/70.twolf/sparc/linux/simple-timing/simout -Redirecting stderr to build/SPARC_SE/tests/opt/long/70.twolf/sparc/linux/simple-timing/simerr M5 Simulator System Copyright (c) 2001-2008 @@ -7,13 +5,13 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Aug 26 2010 13:03:41 -M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix -M5 started Aug 26 2010 13:03:51 -M5 executing on zizzer -command line: build/SPARC_SE/m5.opt -d build/SPARC_SE/tests/opt/long/70.twolf/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/opt/long/70.twolf/sparc/linux/simple-timing -Couldn't unlink build/SPARC_SE/tests/opt/long/70.twolf/sparc/linux/simple-timing/smred.sav -Couldn't unlink build/SPARC_SE/tests/opt/long/70.twolf/sparc/linux/simple-timing/smred.sv2 +M5 compiled Feb 7 2011 02:13:30 +M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip +M5 started Feb 7 2011 02:14:19 +M5 executing on burrito +command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-timing +Couldn't unlink build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-timing/smred.sav +Couldn't unlink build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-timing/smred.sv2 Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-timing/stats.txt b/tests/long/70.twolf/ref/sparc/linux/simple-timing/stats.txt index 46f688248..f02c69451 100644 --- a/tests/long/70.twolf/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/long/70.twolf/ref/sparc/linux/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 953366 # Simulator instruction rate (inst/s) -host_mem_usage 216056 # Number of bytes of host memory used -host_seconds 202.91 # Real time elapsed on the host -host_tick_rate 1333500122 # Simulator tick rate (ticks/s) +host_inst_rate 498703 # Simulator instruction rate (inst/s) +host_mem_usage 231920 # Number of bytes of host memory used +host_seconds 387.90 # Real time elapsed on the host +host_tick_rate 697549821 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 193444769 # Number of instructions simulated sim_seconds 0.270577 # Number of seconds simulated @@ -209,8 +209,24 @@ system.cpu.l2cache.warmup_cycle 0 # Cy system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.numCycles 541153920 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.num_busy_cycles 541153920 # Number of busy cycles +system.cpu.num_conditional_control_insts 0 # number of instructions that are conditional controls +system.cpu.num_fp_alu_accesses 1970372 # Number of float alu accesses +system.cpu.num_fp_insts 1970372 # number of float instructions +system.cpu.num_fp_register_reads 3181089 # number of times the floating registers were read +system.cpu.num_fp_register_writes 2974850 # number of times the floating registers were written +system.cpu.num_func_calls 0 # number of times a function call or return occured +system.cpu.num_idle_cycles 0 # Number of idle cycles system.cpu.num_insts 193444769 # Number of instructions executed -system.cpu.num_refs 76733959 # Number of memory references +system.cpu.num_int_alu_accesses 167974818 # Number of integer alu accesses +system.cpu.num_int_insts 167974818 # number of integer instructions +system.cpu.num_int_register_reads 352386257 # number of times the integer registers were read +system.cpu.num_int_register_writes 163703466 # number of times the integer registers were written +system.cpu.num_load_insts 57735092 # Number of load instructions +system.cpu.num_mem_refs 76733959 # number of memory refs +system.cpu.num_store_insts 18998867 # Number of store instructions system.cpu.workload.PROG:num_syscalls 401 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/70.twolf/ref/x86/linux/o3-timing/config.ini b/tests/long/70.twolf/ref/x86/linux/o3-timing/config.ini index 64a0645d8..78a8cbd6c 100644 --- a/tests/long/70.twolf/ref/x86/linux/o3-timing/config.ini +++ b/tests/long/70.twolf/ref/x86/linux/o3-timing/config.ini @@ -10,6 +10,13 @@ type=System children=cpu membus physmem mem_mode=atomic physmem=system.physmem +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 [system.cpu] type=DerivO3CPU @@ -481,7 +488,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=twolf smred -cwd=build/X86_SE/tests/opt/long/70.twolf/x86/linux/o3-timing +cwd=build/X86_SE/tests/fast/long/70.twolf/x86/linux/o3-timing egid=100 env= errout=cerr diff --git a/tests/long/70.twolf/ref/x86/linux/o3-timing/simout b/tests/long/70.twolf/ref/x86/linux/o3-timing/simout index 4773ac641..e89403a2f 100755 --- a/tests/long/70.twolf/ref/x86/linux/o3-timing/simout +++ b/tests/long/70.twolf/ref/x86/linux/o3-timing/simout @@ -5,13 +5,13 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jan 31 2011 16:34:44 -M5 revision 1b98eea40540 7883 default qtip tip x86o3regressions.patch -M5 started Jan 31 2011 16:34:46 +M5 compiled Feb 7 2011 02:32:07 +M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip +M5 started Feb 7 2011 02:32:12 M5 executing on burrito -command line: build/X86_SE/m5.opt -d build/X86_SE/tests/opt/long/70.twolf/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/opt/long/70.twolf/x86/linux/o3-timing -Couldn't unlink build/X86_SE/tests/opt/long/70.twolf/x86/linux/o3-timing/smred.sav -Couldn't unlink build/X86_SE/tests/opt/long/70.twolf/x86/linux/o3-timing/smred.sv2 +command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/70.twolf/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/fast/long/70.twolf/x86/linux/o3-timing +Couldn't unlink build/X86_SE/tests/fast/long/70.twolf/x86/linux/o3-timing/smred.sav +Couldn't unlink build/X86_SE/tests/fast/long/70.twolf/x86/linux/o3-timing/smred.sv2 Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/70.twolf/ref/x86/linux/o3-timing/stats.txt b/tests/long/70.twolf/ref/x86/linux/o3-timing/stats.txt index daddf87eb..58c1a1259 100644 --- a/tests/long/70.twolf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/70.twolf/ref/x86/linux/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 118559 # Simulator instruction rate (inst/s) -host_mem_usage 239716 # Number of bytes of host memory used -host_seconds 1867.12 # Real time elapsed on the host -host_tick_rate 68319429 # Simulator tick rate (ticks/s) +host_inst_rate 87424 # Simulator instruction rate (inst/s) +host_mem_usage 240332 # Number of bytes of host memory used +host_seconds 2532.06 # Real time elapsed on the host +host_tick_rate 50378144 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 221363017 # Number of instructions simulated sim_seconds 0.127561 # Number of seconds simulated @@ -37,6 +37,9 @@ system.cpu.commit.COM:committed_per_cycle::min_value 0 system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::total 243992167 # Number of insts commited each cycle system.cpu.commit.COM:count 221363017 # Number of instructions committed +system.cpu.commit.COM:fp_insts 2162459 # Number of committed floating point instructions. +system.cpu.commit.COM:function_calls 0 # Number of function calls committed. +system.cpu.commit.COM:int_insts 220339606 # Number of committed integer instructions. system.cpu.commit.COM:loads 56649590 # Number of loads committed system.cpu.commit.COM:membars 0 # Number of memory barriers committed system.cpu.commit.COM:refs 77165306 # Number of memory references committed @@ -150,6 +153,8 @@ system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Nu system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::total 254996147 # Number of instructions fetched each cycle (Total) +system.cpu.fp_regfile_reads 3212472 # number of floating regfile reads +system.cpu.fp_regfile_writes 2049220 # number of floating regfile writes system.cpu.icache.ReadReq_accesses 20440935 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_avg_miss_latency 25661.556820 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 22374.875175 # average ReadReq mshr miss latency @@ -249,6 +254,8 @@ system.cpu.iew.lsq.thread.0.squashedStores 5084805 # system.cpu.iew.memOrderViolationEvents 879354 # Number of memory order violations system.cpu.iew.predictedNotTakenIncorrect 151398 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedTakenIncorrect 3505125 # Number of branches that were predicted taken incorrectly +system.cpu.int_regfile_reads 614135119 # number of integer regfile reads +system.cpu.int_regfile_writes 252115460 # number of integer regfile writes system.cpu.ipc 0.867678 # IPC: Instructions Per Cycle system.cpu.ipc_total 0.867678 # IPC: Total IPC of All Threads system.cpu.iq.ISSUE:FU_type_0::No_OpClass 1180294 0.48% 0.48% # Type of FU issued @@ -340,6 +347,14 @@ system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 system.cpu.iq.ISSUE:issued_per_cycle::max_value 7 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::total 254996147 # Number of insts issued each cycle system.cpu.iq.ISSUE:rate 0.970662 # Inst issue rate +system.cpu.iq.fp_alu_accesses 2542426 # Number of floating point alu accesses +system.cpu.iq.fp_inst_queue_reads 5084249 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_wakeup_accesses 2387245 # Number of floating instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_writes 3193021 # Number of floating instruction queue writes +system.cpu.iq.int_alu_accesses 243954502 # Number of integer alu accesses +system.cpu.iq.int_inst_queue_reads 745226741 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_wakeup_accesses 239072108 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_writes 358869082 # Number of integer instruction queue writes system.cpu.iq.iqInstsAdded 291512819 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqInstsIssued 247636323 # Number of instructions issued system.cpu.iq.iqNonSpecInstsAdded 1275 # Number of non-speculative instructions added to the IQ @@ -420,7 +435,11 @@ system.cpu.memDep0.conflictingLoads 21807942 # Nu system.cpu.memDep0.conflictingStores 4495847 # Number of conflicting stores. system.cpu.memDep0.insertedLoads 75869162 # Number of loads inserted to the mem dependence unit. system.cpu.memDep0.insertedStores 25600521 # Number of stores inserted to the mem dependence unit. +system.cpu.misc_regfile_reads 125958118 # number of misc regfile reads +system.cpu.misc_regfile_writes 844 # number of misc regfile writes system.cpu.numCycles 255121086 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.rename.RENAME:BlockCycles 1303093 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 234363409 # Number of HB maps that are committed system.cpu.rename.RENAME:IQFullEvents 2662460 # Number of times rename has blocked due to IQ full @@ -433,10 +452,14 @@ system.cpu.rename.RENAME:RunCycles 180705413 # Nu system.cpu.rename.RENAME:SquashCycles 11003980 # Number of cycles rename is squashing system.cpu.rename.RENAME:UnblockCycles 4387817 # Number of cycles rename is unblocking system.cpu.rename.RENAME:UndoneMaps 97598616 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:fp_rename_lookups 7191870 # Number of floating rename lookups +system.cpu.rename.RENAME:int_rename_lookups 956102004 # Number of integer rename lookups system.cpu.rename.RENAME:serializeStallCycles 16547 # count of cycles rename stalled for serializing inst system.cpu.rename.RENAME:serializingInsts 1274 # count of serializing insts renamed system.cpu.rename.RENAME:skidInsts 8156807 # count of insts added to the skid buffer system.cpu.rename.RENAME:tempSerializingInsts 1279 # count of temporary serializing insts renamed +system.cpu.rob.rob_reads 535181849 # The number of ROB reads +system.cpu.rob.rob_writes 594057529 # The number of ROB writes system.cpu.timesIdled 2349 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 400 # Number of system calls diff --git a/tests/long/70.twolf/ref/x86/linux/simple-atomic/config.ini b/tests/long/70.twolf/ref/x86/linux/simple-atomic/config.ini index 4d12813eb..adbeb371c 100644 --- a/tests/long/70.twolf/ref/x86/linux/simple-atomic/config.ini +++ b/tests/long/70.twolf/ref/x86/linux/simple-atomic/config.ini @@ -10,6 +10,13 @@ type=System children=cpu membus physmem mem_mode=atomic physmem=system.physmem +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 [system.cpu] type=AtomicSimpleCPU @@ -54,7 +61,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=twolf smred -cwd=build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-atomic +cwd=build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-atomic egid=100 env= errout=cerr diff --git a/tests/long/70.twolf/ref/x86/linux/simple-atomic/simout b/tests/long/70.twolf/ref/x86/linux/simple-atomic/simout index bf0a55710..3569c883b 100755 --- a/tests/long/70.twolf/ref/x86/linux/simple-atomic/simout +++ b/tests/long/70.twolf/ref/x86/linux/simple-atomic/simout @@ -5,13 +5,13 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jan 31 2011 14:03:49 -M5 revision aa283c8952a9 7880 default qtip stupdstats.patch tip -M5 started Jan 31 2011 14:03:51 +M5 compiled Feb 7 2011 02:32:07 +M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip +M5 started Feb 7 2011 02:36:47 M5 executing on burrito -command line: build/X86_SE/m5.opt -d build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-atomic -Couldn't unlink build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-atomic/smred.sav -Couldn't unlink build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-atomic/smred.sv2 +command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-atomic +Couldn't unlink build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-atomic/smred.sav +Couldn't unlink build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-atomic/smred.sv2 Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/70.twolf/ref/x86/linux/simple-atomic/stats.txt b/tests/long/70.twolf/ref/x86/linux/simple-atomic/stats.txt index 6fd518d60..da648dcbf 100644 --- a/tests/long/70.twolf/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/long/70.twolf/ref/x86/linux/simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 925477 # Simulator instruction rate (inst/s) -host_mem_usage 227168 # Number of bytes of host memory used -host_seconds 239.19 # Real time elapsed on the host -host_tick_rate 549329374 # Simulator tick rate (ticks/s) +host_inst_rate 777141 # Simulator instruction rate (inst/s) +host_mem_usage 230844 # Number of bytes of host memory used +host_seconds 284.84 # Real time elapsed on the host +host_tick_rate 461282227 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 221363018 # Number of instructions simulated sim_seconds 0.131393 # Number of seconds simulated @@ -11,8 +11,24 @@ sim_ticks 131393100000 # Nu system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.numCycles 262786201 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.num_busy_cycles 262786201 # Number of busy cycles +system.cpu.num_conditional_control_insts 8268471 # number of instructions that are conditional controls +system.cpu.num_fp_alu_accesses 2162459 # Number of float alu accesses +system.cpu.num_fp_insts 2162459 # number of float instructions +system.cpu.num_fp_register_reads 3037165 # number of times the floating registers were read +system.cpu.num_fp_register_writes 1831403 # number of times the floating registers were written +system.cpu.num_func_calls 0 # number of times a function call or return occured +system.cpu.num_idle_cycles 0 # Number of idle cycles system.cpu.num_insts 221363018 # Number of instructions executed -system.cpu.num_refs 77165306 # Number of memory references +system.cpu.num_int_alu_accesses 220339607 # Number of integer alu accesses +system.cpu.num_int_insts 220339607 # number of integer instructions +system.cpu.num_int_register_reads 686620674 # number of times the integer registers were read +system.cpu.num_int_register_writes 232532006 # number of times the integer registers were written +system.cpu.num_load_insts 56649590 # Number of load instructions +system.cpu.num_mem_refs 77165306 # number of memory refs +system.cpu.num_store_insts 20515716 # Number of store instructions system.cpu.workload.PROG:num_syscalls 400 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/70.twolf/ref/x86/linux/simple-timing/config.ini b/tests/long/70.twolf/ref/x86/linux/simple-timing/config.ini index bf2ab6302..2709fd0f4 100644 --- a/tests/long/70.twolf/ref/x86/linux/simple-timing/config.ini +++ b/tests/long/70.twolf/ref/x86/linux/simple-timing/config.ini @@ -10,6 +10,13 @@ type=System children=cpu membus physmem mem_mode=atomic physmem=system.physmem +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 [system.cpu] type=TimingSimpleCPU @@ -154,7 +161,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=twolf smred -cwd=build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-timing +cwd=build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-timing egid=100 env= errout=cerr diff --git a/tests/long/70.twolf/ref/x86/linux/simple-timing/simout b/tests/long/70.twolf/ref/x86/linux/simple-timing/simout index 8e7b2eaae..31ab1843b 100755 --- a/tests/long/70.twolf/ref/x86/linux/simple-timing/simout +++ b/tests/long/70.twolf/ref/x86/linux/simple-timing/simout @@ -5,13 +5,13 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jan 31 2011 14:03:49 -M5 revision aa283c8952a9 7880 default qtip stupdstats.patch tip -M5 started Jan 31 2011 14:03:51 +M5 compiled Feb 7 2011 02:32:07 +M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip +M5 started Feb 7 2011 02:32:24 M5 executing on burrito -command line: build/X86_SE/m5.opt -d build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-timing -Couldn't unlink build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-timing/smred.sav -Couldn't unlink build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-timing/smred.sv2 +command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-timing +Couldn't unlink build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-timing/smred.sav +Couldn't unlink build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-timing/smred.sv2 Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/70.twolf/ref/x86/linux/simple-timing/stats.txt b/tests/long/70.twolf/ref/x86/linux/simple-timing/stats.txt index a9095b1f2..ebc389a3a 100644 --- a/tests/long/70.twolf/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/70.twolf/ref/x86/linux/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 704710 # Simulator instruction rate (inst/s) -host_mem_usage 234884 # Number of bytes of host memory used -host_seconds 314.12 # Real time elapsed on the host -host_tick_rate 798933117 # Simulator tick rate (ticks/s) +host_inst_rate 446836 # Simulator instruction rate (inst/s) +host_mem_usage 238556 # Number of bytes of host memory used +host_seconds 495.40 # Real time elapsed on the host +host_tick_rate 506580174 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 221363018 # Number of instructions simulated sim_seconds 0.250961 # Number of seconds simulated @@ -200,8 +200,24 @@ system.cpu.l2cache.warmup_cycle 0 # Cy system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.numCycles 501921262 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.num_busy_cycles 501921262 # Number of busy cycles +system.cpu.num_conditional_control_insts 8268471 # number of instructions that are conditional controls +system.cpu.num_fp_alu_accesses 2162459 # Number of float alu accesses +system.cpu.num_fp_insts 2162459 # number of float instructions +system.cpu.num_fp_register_reads 3037165 # number of times the floating registers were read +system.cpu.num_fp_register_writes 1831403 # number of times the floating registers were written +system.cpu.num_func_calls 0 # number of times a function call or return occured +system.cpu.num_idle_cycles 0 # Number of idle cycles system.cpu.num_insts 221363018 # Number of instructions executed -system.cpu.num_refs 77165306 # Number of memory references +system.cpu.num_int_alu_accesses 220339607 # Number of integer alu accesses +system.cpu.num_int_insts 220339607 # number of integer instructions +system.cpu.num_int_register_reads 686620674 # number of times the integer registers were read +system.cpu.num_int_register_writes 232532006 # number of times the integer registers were written +system.cpu.num_load_insts 56649590 # Number of load instructions +system.cpu.num_mem_refs 77165306 # number of memory refs +system.cpu.num_store_insts 20515716 # Number of store instructions system.cpu.workload.PROG:num_syscalls 400 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.ini b/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.ini index 41396e67d..cc2f70a95 100644 --- a/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.ini +++ b/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.ini @@ -1,7 +1,9 @@ [root] type=Root children=system -dummy=0 +time_sync_enable=false +time_sync_period=200000000 +time_sync_spin_threshold=200000 [system] type=SparcSystem @@ -9,27 +11,35 @@ children=bridge cpu disk0 hypervisor_desc intrctrl iobus membus nvram partition_ boot_cpu_frequency=1 boot_osflags=a hypervisor_addr=1099243257856 -hypervisor_bin=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/binaries/q_new.bin +hypervisor_bin=/dist/m5/system/binaries/q_new.bin hypervisor_desc=system.hypervisor_desc hypervisor_desc_addr=133446500352 -hypervisor_desc_bin=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/binaries/1up-hv.bin +hypervisor_desc_bin=/dist/m5/system/binaries/1up-hv.bin init_param=0 kernel= +load_addr_mask=1099511627775 mem_mode=atomic nvram=system.nvram nvram_addr=133429198848 -nvram_bin=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/binaries/nvram1 +nvram_bin=/dist/m5/system/binaries/nvram1 openboot_addr=1099243716608 -openboot_bin=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/binaries/openboot_new.bin +openboot_bin=/dist/m5/system/binaries/openboot_new.bin partition_desc=system.partition_desc partition_desc_addr=133445976064 -partition_desc_bin=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/binaries/1up-md.bin +partition_desc_bin=/dist/m5/system/binaries/1up-md.bin physmem=system.physmem readfile=tests/halt.sh reset_addr=1099243192320 -reset_bin=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/binaries/reset_new.bin +reset_bin=/dist/m5/system/binaries/reset_new.bin rom=system.rom symbolfile= +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 [system.bridge] type=Bridge @@ -110,7 +120,7 @@ table_size=65536 [system.disk0.image.child] type=RawDiskImage -image_file=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/disks/disk.s10hw2 +image_file=/dist/m5/system/disks/disk.s10hw2 read_only=true [system.hypervisor_desc] diff --git a/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simout b/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simout index fc75aba24..fe4ad698b 100755 --- a/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simout +++ b/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 25 2010 03:38:31 -M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip -M5 started Feb 25 2010 03:38:45 -M5 executing on SC2B0619 +M5 compiled Feb 7 2011 02:10:38 +M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip +M5 started Feb 7 2011 02:10:45 +M5 executing on burrito command line: build/SPARC_FS/m5.fast -d build/SPARC_FS/tests/fast/long/80.solaris-boot/sparc/solaris/t1000-simple-atomic -re tests/run.py build/SPARC_FS/tests/fast/long/80.solaris-boot/sparc/solaris/t1000-simple-atomic Global frequency set at 2000000000 ticks per second info: No kernel set for full system simulation. Assuming you know what you're doing... diff --git a/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stats.txt b/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stats.txt index 16e4b5160..d05ca1e9f 100644 --- a/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stats.txt +++ b/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 2688852 # Simulator instruction rate (inst/s) -host_mem_usage 490548 # Number of bytes of host memory used -host_seconds 829.04 # Real time elapsed on the host -host_tick_rate 2694420 # Simulator tick rate (ticks/s) +host_inst_rate 1272725 # Simulator instruction rate (inst/s) +host_mem_usage 524564 # Number of bytes of host memory used +host_seconds 1751.49 # Real time elapsed on the host +host_tick_rate 1275361 # Simulator tick rate (ticks/s) sim_freq 2000000000 # Frequency of simulated ticks sim_insts 2229160714 # Number of instructions simulated sim_seconds 1.116889 # Number of seconds simulated @@ -13,7 +13,23 @@ system.cpu.kern.inst.arm 0 # nu system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.numCycles 2233777513 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.num_busy_cycles 2233777513 # Number of busy cycles +system.cpu.num_conditional_control_insts 0 # number of instructions that are conditional controls +system.cpu.num_fp_alu_accesses 14608322 # Number of float alu accesses +system.cpu.num_fp_insts 14608322 # number of float instructions +system.cpu.num_fp_register_reads 35401841 # number of times the floating registers were read +system.cpu.num_fp_register_writes 22917558 # number of times the floating registers were written +system.cpu.num_func_calls 0 # number of times a function call or return occured +system.cpu.num_idle_cycles 0 # Number of idle cycles system.cpu.num_insts 2229160714 # Number of instructions executed -system.cpu.num_refs 547951940 # Number of memory references +system.cpu.num_int_alu_accesses 1839325658 # Number of integer alu accesses +system.cpu.num_int_insts 1839325658 # number of integer instructions +system.cpu.num_int_register_reads 4304894311 # number of times the integer registers were read +system.cpu.num_int_register_writes 2108336490 # number of times the integer registers were written +system.cpu.num_load_insts 349807670 # Number of load instructions +system.cpu.num_mem_refs 547951940 # number of memory refs +system.cpu.num_store_insts 198144270 # Number of store instructions ---------- End Simulation Statistics ---------- |