diff options
Diffstat (limited to 'tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt')
| -rw-r--r-- | tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt | 80 |
1 files changed, 40 insertions, 40 deletions
diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt b/tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt index cd20f37b3..cd104d2c8 100644 --- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt +++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt @@ -8,10 +8,10 @@ global.BPredUnit.condIncorrect 425 # Nu global.BPredUnit.condPredicted 1184 # Number of conditional branches predicted global.BPredUnit.lookups 2013 # Number of BP lookups global.BPredUnit.usedRAS 270 # Number of times the RAS was used to get a target. -host_inst_rate 44115 # Simulator instruction rate (inst/s) -host_mem_usage 194668 # Number of bytes of host memory used +host_inst_rate 44727 # Simulator instruction rate (inst/s) +host_mem_usage 151980 # Number of bytes of host memory used host_seconds 0.13 # Real time elapsed on the host -host_tick_rate 41555653 # Simulator tick rate (ticks/s) +host_tick_rate 42091644 # Simulator tick rate (ticks/s) memdepunit.memDep.conflictingLoads 22 # Number of conflicting loads. memdepunit.memDep.conflictingStores 117 # Number of conflicting stores. memdepunit.memDep.insertedLoads 2013 # Number of loads inserted to the mem dependence unit. @@ -51,61 +51,61 @@ system.cpu.committedInsts 5623 # Nu system.cpu.committedInsts_total 5623 # Number of Instructions Simulated system.cpu.cpi 1.886360 # CPI: Cycles Per Instruction system.cpu.cpi_total 1.886360 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 1531 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 14760.204082 # average ReadReq miss latency +system.cpu.dcache.ReadReq_accesses 1566 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 10875.939850 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency 8494.897959 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_hits 1433 # number of ReadReq hits system.cpu.dcache.ReadReq_miss_latency 1446500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.064010 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 98 # number of ReadReq misses +system.cpu.dcache.ReadReq_miss_rate 0.084930 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 133 # number of ReadReq misses system.cpu.dcache.ReadReq_mshr_hits 35 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_miss_latency 832500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.064010 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate 0.062580 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 98 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_accesses 528 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 36879.310345 # average WriteReq miss latency +system.cpu.dcache.WriteReq_accesses 812 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 8648.247978 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency 7436.781609 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_hits 441 # number of WriteReq hits system.cpu.dcache.WriteReq_miss_latency 3208500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.164773 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 87 # number of WriteReq misses +system.cpu.dcache.WriteReq_miss_rate 0.456897 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 371 # number of WriteReq misses system.cpu.dcache.WriteReq_mshr_hits 284 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_miss_latency 647000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.164773 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate 0.107143 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 87 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 11.111765 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 11.188235 # Average number of references to valid blocks. system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 2059 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 25162.162162 # average overall miss latency +system.cpu.dcache.demand_accesses 2378 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 9236.111111 # average overall miss latency system.cpu.dcache.demand_avg_mshr_miss_latency 7997.297297 # average overall mshr miss latency system.cpu.dcache.demand_hits 1874 # number of demand (read+write) hits system.cpu.dcache.demand_miss_latency 4655000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.089849 # miss rate for demand accesses -system.cpu.dcache.demand_misses 185 # number of demand (read+write) misses +system.cpu.dcache.demand_miss_rate 0.211943 # miss rate for demand accesses +system.cpu.dcache.demand_misses 504 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 319 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_miss_latency 1479500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.089849 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate 0.077796 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 185 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 2059 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 25162.162162 # average overall miss latency +system.cpu.dcache.overall_accesses 2378 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 9236.111111 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 7997.297297 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 1874 # number of overall hits system.cpu.dcache.overall_miss_latency 4655000 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.089849 # miss rate for overall accesses -system.cpu.dcache.overall_misses 185 # number of overall misses +system.cpu.dcache.overall_miss_rate 0.211943 # miss rate for overall accesses +system.cpu.dcache.overall_misses 504 # number of overall misses system.cpu.dcache.overall_mshr_hits 319 # number of overall MSHR hits system.cpu.dcache.overall_mshr_miss_latency 1479500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.089849 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate 0.077796 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 185 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses @@ -122,7 +122,7 @@ system.cpu.dcache.replacements 0 # nu system.cpu.dcache.sampled_refs 170 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.tagsinuse 107.937594 # Cycle average of tags in use -system.cpu.dcache.total_refs 1889 # Total number of references to valid blocks. +system.cpu.dcache.total_refs 1902 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks system.cpu.decode.DECODE:BlockedCycles 463 # Number of cycles decode is blocked @@ -171,16 +171,16 @@ system.cpu.fetch.rateDist.min_value 0 system.cpu.fetch.rateDist.max_value 8 system.cpu.fetch.rateDist.end_dist -system.cpu.icache.ReadReq_accesses 1530 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 10214.516129 # average ReadReq miss latency +system.cpu.icache.ReadReq_accesses 1565 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 9178.260870 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 6606.451613 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_hits 1220 # number of ReadReq hits system.cpu.icache.ReadReq_miss_latency 3166500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.202614 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 310 # number of ReadReq misses +system.cpu.icache.ReadReq_miss_rate 0.220447 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 345 # number of ReadReq misses system.cpu.icache.ReadReq_mshr_hits 35 # number of ReadReq MSHR hits system.cpu.icache.ReadReq_mshr_miss_latency 2048000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.202614 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate 0.198083 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 310 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked @@ -190,31 +190,31 @@ system.cpu.icache.blocked_no_targets 0 # nu system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 1530 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 10214.516129 # average overall miss latency +system.cpu.icache.demand_accesses 1565 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 9178.260870 # average overall miss latency system.cpu.icache.demand_avg_mshr_miss_latency 6606.451613 # average overall mshr miss latency system.cpu.icache.demand_hits 1220 # number of demand (read+write) hits system.cpu.icache.demand_miss_latency 3166500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.202614 # miss rate for demand accesses -system.cpu.icache.demand_misses 310 # number of demand (read+write) misses +system.cpu.icache.demand_miss_rate 0.220447 # miss rate for demand accesses +system.cpu.icache.demand_misses 345 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 35 # number of demand (read+write) MSHR hits system.cpu.icache.demand_mshr_miss_latency 2048000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.202614 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate 0.198083 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 310 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 1530 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 10214.516129 # average overall miss latency +system.cpu.icache.overall_accesses 1565 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 9178.260870 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 6606.451613 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.icache.overall_hits 1220 # number of overall hits system.cpu.icache.overall_miss_latency 3166500 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.202614 # miss rate for overall accesses -system.cpu.icache.overall_misses 310 # number of overall misses +system.cpu.icache.overall_miss_rate 0.220447 # miss rate for overall accesses +system.cpu.icache.overall_misses 345 # number of overall misses system.cpu.icache.overall_mshr_hits 35 # number of overall MSHR hits system.cpu.icache.overall_mshr_miss_latency 2048000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.202614 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate 0.198083 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 310 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses |