diff options
Diffstat (limited to 'tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt')
| -rw-r--r-- | tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt | 42 |
1 files changed, 21 insertions, 21 deletions
diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt b/tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt index 608fb0be9..0426166d9 100644 --- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt +++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt @@ -8,10 +8,10 @@ global.BPredUnit.condIncorrect 443 # Nu global.BPredUnit.condPredicted 1570 # Number of conditional branches predicted global.BPredUnit.lookups 5322 # Number of BP lookups global.BPredUnit.usedRAS 2820 # Number of times the RAS was used to get a target. -host_inst_rate 1288 # Simulator instruction rate (inst/s) -host_mem_usage 180572 # Number of bytes of host memory used -host_seconds 4.37 # Real time elapsed on the host -host_tick_rate 322418 # Simulator tick rate (ticks/s) +host_inst_rate 9098 # Simulator instruction rate (inst/s) +host_mem_usage 180112 # Number of bytes of host memory used +host_seconds 0.62 # Real time elapsed on the host +host_tick_rate 2277354 # Simulator tick rate (ticks/s) memdepunit.memDep.conflictingLoads 27 # Number of conflicting loads. memdepunit.memDep.conflictingStores 144 # Number of conflicting stores. memdepunit.memDep.insertedLoads 3819 # Number of loads inserted to the mem dependence unit. @@ -98,7 +98,7 @@ system.cpu.dcache.no_allocate_misses 0 # Nu system.cpu.dcache.overall_accesses 2409 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 5958.666667 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 6120.796512 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 1986 # number of overall hits system.cpu.dcache.overall_miss_latency 2520516 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.175592 # miss rate for overall accesses @@ -195,7 +195,7 @@ system.cpu.icache.no_allocate_misses 0 # Nu system.cpu.icache.overall_accesses 6541 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 5110.042601 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 4297.762058 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.icache.overall_hits 6095 # number of overall hits system.cpu.icache.overall_miss_latency 2279079 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.068185 # miss rate for overall accesses @@ -269,20 +269,20 @@ system.cpu.ipc 0.003993 # IP system.cpu.ipc_total 0.003993 # IPC: Total IPC of All Threads system.cpu.iq.ISSUE:FU_type_0 13960 # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.start_dist -(null) 2 0.01% # Type of FU issued -IntAlu 8277 59.29% # Type of FU issued -IntMult 1 0.01% # Type of FU issued -IntDiv 0 0.00% # Type of FU issued -FloatAdd 2 0.01% # Type of FU issued -FloatCmp 0 0.00% # Type of FU issued -FloatCvt 0 0.00% # Type of FU issued -FloatMult 0 0.00% # Type of FU issued -FloatDiv 0 0.00% # Type of FU issued -FloatSqrt 0 0.00% # Type of FU issued -MemRead 3509 25.14% # Type of FU issued -MemWrite 2169 15.54% # Type of FU issued -IprAccess 0 0.00% # Type of FU issued -InstPrefetch 0 0.00% # Type of FU issued + (null) 2 0.01% # Type of FU issued + IntAlu 8277 59.29% # Type of FU issued + IntMult 1 0.01% # Type of FU issued + IntDiv 0 0.00% # Type of FU issued + FloatAdd 2 0.01% # Type of FU issued + FloatCmp 0 0.00% # Type of FU issued + FloatCvt 0 0.00% # Type of FU issued + FloatMult 0 0.00% # Type of FU issued + FloatDiv 0 0.00% # Type of FU issued + FloatSqrt 0 0.00% # Type of FU issued + MemRead 3509 25.14% # Type of FU issued + MemWrite 2169 15.54% # Type of FU issued + IprAccess 0 0.00% # Type of FU issued + InstPrefetch 0 0.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.end_dist system.cpu.iq.ISSUE:fu_busy_cnt 93 # FU busy when requested system.cpu.iq.ISSUE:fu_busy_rate 0.006662 # FU busy rate (busy events/executed inst) @@ -360,7 +360,7 @@ system.cpu.l2cache.no_allocate_misses 0 # Nu system.cpu.l2cache.overall_accesses 483 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 4537.301455 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 2307.006237 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 2 # number of overall hits system.cpu.l2cache.overall_miss_latency 2182442 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 0.995859 # miss rate for overall accesses |