diff options
Diffstat (limited to 'tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt')
| -rw-r--r-- | tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt | 30 |
1 files changed, 15 insertions, 15 deletions
diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt b/tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt index ce1ae8d6f..00f26425a 100644 --- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt +++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt @@ -8,10 +8,10 @@ global.BPredUnit.condIncorrect 409 # Nu global.BPredUnit.condPredicted 1184 # Number of conditional branches predicted global.BPredUnit.lookups 2029 # Number of BP lookups global.BPredUnit.usedRAS 277 # Number of times the RAS was used to get a target. -host_inst_rate 9351 # Simulator instruction rate (inst/s) -host_mem_usage 180452 # Number of bytes of host memory used -host_seconds 0.60 # Real time elapsed on the host -host_tick_rate 7988790 # Simulator tick rate (ticks/s) +host_inst_rate 84357 # Simulator instruction rate (inst/s) +host_mem_usage 197344 # Number of bytes of host memory used +host_seconds 0.07 # Real time elapsed on the host +host_tick_rate 71887995 # Simulator tick rate (ticks/s) memdepunit.memDep.conflictingLoads 23 # Number of conflicting loads. memdepunit.memDep.conflictingStores 124 # Number of conflicting stores. memdepunit.memDep.insertedLoads 2030 # Number of loads inserted to the mem dependence unit. @@ -49,8 +49,8 @@ system.cpu.commit.commitNonSpecStalls 17 # Th system.cpu.commit.commitSquashedInsts 4234 # The number of squashed insts skipped by commit system.cpu.committedInsts 5623 # Number of Instructions Simulated system.cpu.committedInsts_total 5623 # Number of Instructions Simulated -system.cpu.cpi 1.680420 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.680420 # CPI: Total CPI of All Threads +system.cpu.cpi 1.709586 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.709586 # CPI: Total CPI of All Threads system.cpu.dcache.ReadReq_accesses 1535 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_avg_miss_latency 10443.877551 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency 6357.142857 # average ReadReq mshr miss latency @@ -152,10 +152,10 @@ system.cpu.fetch.Cycles 3746 # Nu system.cpu.fetch.IcacheSquashes 226 # Number of outstanding Icache misses that were squashed system.cpu.fetch.Insts 12519 # Number of instructions fetch has processed system.cpu.fetch.SquashCycles 469 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.214732 # Number of branch fetches per cycle +system.cpu.fetch.branchRate 0.211068 # Number of branch fetches per cycle system.cpu.fetch.icacheStallCycles 1542 # Number of cycles fetch is stalled on an Icache miss system.cpu.fetch.predictedBranches 839 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 1.324902 # Number of inst fetches per cycle +system.cpu.fetch.rate 1.302299 # Number of inst fetches per cycle system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist.samples 9449 system.cpu.fetch.rateDist.min_value 0 @@ -234,10 +234,10 @@ system.cpu.icache.tagsinuse 164.253671 # Cy system.cpu.icache.total_refs 1211 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 110443 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.idleCycles 164 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.iew.EXEC:branches 1199 # Number of branches executed system.cpu.iew.EXEC:nop 72 # number of nop insts executed -system.cpu.iew.EXEC:rate 0.848450 # Inst execution rate +system.cpu.iew.EXEC:rate 0.833975 # Inst execution rate system.cpu.iew.EXEC:refs 2660 # number of memory reference insts executed system.cpu.iew.EXEC:stores 1006 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed @@ -247,7 +247,7 @@ system.cpu.iew.WB:fanout 0.742905 # av system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.iew.WB:producers 4031 # num instructions producing a value -system.cpu.iew.WB:rate 0.811091 # insts written-back per cycle +system.cpu.iew.WB:rate 0.797254 # insts written-back per cycle system.cpu.iew.WB:sent 7781 # cumulative count of insts sent to commit system.cpu.iew.branchMispredicts 401 # Number of branch mispredicts detected at execute system.cpu.iew.iewBlockCycles 4 # Number of cycles IEW is blocking @@ -277,8 +277,8 @@ system.cpu.iew.lsq.thread.0.squashedStores 424 # system.cpu.iew.memOrderViolationEvents 68 # Number of memory order violations system.cpu.iew.predictedNotTakenIncorrect 295 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedTakenIncorrect 106 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 0.595089 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.595089 # IPC: Total IPC of All Threads +system.cpu.ipc 0.584937 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.584937 # IPC: Total IPC of All Threads system.cpu.iq.ISSUE:FU_type_0 8383 # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.start_dist No_OpClass 2 0.02% # Type of FU issued @@ -329,7 +329,7 @@ system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 system.cpu.iq.ISSUE:issued_per_cycle.end_dist -system.cpu.iq.ISSUE:rate 0.887184 # Inst issue rate +system.cpu.iq.ISSUE:rate 0.872048 # Inst issue rate system.cpu.iq.iqInstsAdded 9901 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqInstsIssued 8383 # Number of instructions issued system.cpu.iq.iqNonSpecInstsAdded 23 # Number of non-speculative instructions added to the IQ @@ -421,7 +421,7 @@ system.cpu.l2cache.tagsinuse 218.025629 # Cy system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.numCycles 9449 # number of cpu cycles simulated +system.cpu.numCycles 9613 # number of cpu cycles simulated system.cpu.rename.RENAME:BlockCycles 50 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 4051 # Number of HB maps that are committed system.cpu.rename.RENAME:IdleCycles 6291 # Number of cycles rename is idle |