diff options
Diffstat (limited to 'tests/quick/00.hello/ref/alpha/linux/o3-timing/stats.txt')
| -rw-r--r-- | tests/quick/00.hello/ref/alpha/linux/o3-timing/stats.txt | 676 |
1 files changed, 339 insertions, 337 deletions
diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/00.hello/ref/alpha/linux/o3-timing/stats.txt index 42ab89f68..50d6ec22a 100644 --- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/stats.txt +++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/stats.txt @@ -1,33 +1,33 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000012 # Number of seconds simulated -sim_ticks 12357500 # Number of ticks simulated +sim_ticks 12002500 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 108363 # Simulator instruction rate (inst/s) -host_tick_rate 209619317 # Simulator tick rate (ticks/s) -host_mem_usage 192840 # Number of bytes of host memory used -host_seconds 0.06 # Real time elapsed on the host +host_inst_rate 25819 # Simulator instruction rate (inst/s) +host_tick_rate 48521023 # Simulator tick rate (ticks/s) +host_mem_usage 243716 # Number of bytes of host memory used +host_seconds 0.25 # Real time elapsed on the host sim_insts 6386 # Number of instructions simulated system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 1750 # DTB read hits -system.cpu.dtb.read_misses 36 # DTB read misses +system.cpu.dtb.read_hits 1863 # DTB read hits +system.cpu.dtb.read_misses 45 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 1786 # DTB read accesses -system.cpu.dtb.write_hits 1011 # DTB write hits -system.cpu.dtb.write_misses 25 # DTB write misses +system.cpu.dtb.read_accesses 1908 # DTB read accesses +system.cpu.dtb.write_hits 1047 # DTB write hits +system.cpu.dtb.write_misses 28 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 1036 # DTB write accesses -system.cpu.dtb.data_hits 2761 # DTB hits -system.cpu.dtb.data_misses 61 # DTB misses +system.cpu.dtb.write_accesses 1075 # DTB write accesses +system.cpu.dtb.data_hits 2910 # DTB hits +system.cpu.dtb.data_misses 73 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 2822 # DTB accesses -system.cpu.itb.fetch_hits 1711 # ITB hits -system.cpu.itb.fetch_misses 33 # ITB misses +system.cpu.dtb.data_accesses 2983 # DTB accesses +system.cpu.itb.fetch_hits 2044 # ITB hits +system.cpu.itb.fetch_misses 29 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 1744 # ITB accesses +system.cpu.itb.fetch_accesses 2073 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -41,243 +41,245 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 24716 # number of cpu cycles simulated +system.cpu.numCycles 24006 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 2180 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 1297 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 443 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 1765 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 670 # Number of BTB hits +system.cpu.BPredUnit.lookups 2516 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 1462 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 458 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 1947 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 723 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 306 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 65 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 1711 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 12863 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2180 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 976 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 2325 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 482 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 33 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.CacheLines 1711 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 248 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 12915 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.995974 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.389736 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 372 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 67 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 7155 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 14481 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2516 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 1095 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 2626 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1554 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 1112 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 24 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 631 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 2044 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 318 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 12602 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.149103 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.531397 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 10590 82.00% 82.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 233 1.80% 83.80% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 211 1.63% 85.44% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 179 1.39% 86.82% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 229 1.77% 88.59% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 156 1.21% 89.80% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 218 1.69% 91.49% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 125 0.97% 92.46% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 974 7.54% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 9976 79.16% 79.16% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 274 2.17% 81.34% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 231 1.83% 83.17% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 220 1.75% 84.92% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 235 1.86% 86.78% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 176 1.40% 88.18% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 257 2.04% 90.22% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 141 1.12% 91.33% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1092 8.67% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 12915 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.088202 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.520432 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 8780 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 1035 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 2228 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 47 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 825 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 181 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 75 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 12021 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 209 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 825 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 8928 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 337 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 406 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 2118 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 301 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 11616 # Number of instructions processed by rename -system.cpu.rename.IQFullEvents 8 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 260 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 8669 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 14615 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 14598 # Number of integer rename lookups +system.cpu.fetch.rateDist::total 12602 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.104807 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.603224 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 7976 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 1126 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 2455 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 69 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 976 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 216 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 85 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 13403 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 215 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 976 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 8164 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 432 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 358 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 2326 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 346 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 12866 # Number of instructions processed by rename +system.cpu.rename.IQFullEvents 11 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 291 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 9599 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 16086 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 16069 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 17 # Number of floating rename lookups system.cpu.rename.CommittedMaps 4583 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 4086 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 5016 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 28 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 22 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 754 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2144 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1195 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 0 # Number of conflicting loads. +system.cpu.rename.skidInsts 881 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2397 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1265 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 4 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 10562 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 25 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 9108 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 25 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 3797 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 2286 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 8 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 12915 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.705226 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.305176 # Number of insts issued each cycle +system.cpu.iq.iqInstsAdded 11578 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 27 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 9768 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 45 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 4900 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 2850 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 10 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 12602 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.775115 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.397410 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 8840 68.45% 68.45% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1652 12.79% 81.24% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 1039 8.04% 89.28% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 684 5.30% 94.58% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 367 2.84% 97.42% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 198 1.53% 98.95% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 88 0.68% 99.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 36 0.28% 99.91% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 11 0.09% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 8516 67.58% 67.58% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1470 11.66% 79.24% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 1066 8.46% 87.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 684 5.43% 93.13% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 441 3.50% 96.63% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 254 2.02% 98.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 129 1.02% 99.67% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 30 0.24% 99.90% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 12 0.10% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 12915 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 12602 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 1 1.14% 1.14% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 1.14% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 1.14% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.14% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.14% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.14% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 1.14% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.14% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 1.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 1.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.14% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 52 59.09% 60.23% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 35 39.77% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 13 12.38% 12.38% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 12.38% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 12.38% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 12.38% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 12.38% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 12.38% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 12.38% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 12.38% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 12.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 12.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 12.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 12.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 12.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 12.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 12.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 12.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 12.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 12.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 12.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 12.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 12.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 12.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 12.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 12.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 12.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 12.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 12.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 12.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 12.38% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 54 51.43% 63.81% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 38 36.19% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 6174 67.79% 67.81% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 1 0.01% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 67.84% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.84% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.84% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.84% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.84% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.84% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 1875 20.59% 88.43% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1054 11.57% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 6583 67.39% 67.41% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 1 0.01% 67.42% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.42% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 67.44% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.44% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.44% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.44% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.44% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.44% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2078 21.27% 88.72% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1102 11.28% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 9108 # Type of FU issued -system.cpu.iq.rate 0.368506 # Inst issue rate -system.cpu.iq.fu_busy_cnt 88 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.009662 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 31223 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 14386 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 8549 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 9768 # Type of FU issued +system.cpu.iq.rate 0.406898 # Inst issue rate +system.cpu.iq.fu_busy_cnt 105 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.010749 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 32267 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 16511 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 8987 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 21 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 10 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 10 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 9183 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 9860 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 11 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 44 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 61 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 959 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 6 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 16 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 330 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 1212 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 21 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 400 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 825 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 67 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 9 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 10669 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 193 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2144 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1195 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 25 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 7 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 976 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 150 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 8 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 11685 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 148 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 2397 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1265 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 27 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 5 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 16 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 125 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 304 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 429 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 8837 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 1794 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 271 # Number of squashed instructions skipped in execute +system.cpu.iew.memOrderViolationEvents 21 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 118 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 327 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 445 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 9324 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 1918 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 444 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 82 # number of nop insts executed -system.cpu.iew.exec_refs 2832 # number of memory reference insts executed -system.cpu.iew.exec_branches 1424 # Number of branches executed -system.cpu.iew.exec_stores 1038 # Number of stores executed -system.cpu.iew.exec_rate 0.357542 # Inst execution rate -system.cpu.iew.wb_sent 8658 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 8559 # cumulative count of insts written-back -system.cpu.iew.wb_producers 4429 # num instructions producing a value -system.cpu.iew.wb_consumers 5952 # num instructions consuming a value +system.cpu.iew.exec_nop 80 # number of nop insts executed +system.cpu.iew.exec_refs 2995 # number of memory reference insts executed +system.cpu.iew.exec_branches 1503 # Number of branches executed +system.cpu.iew.exec_stores 1077 # Number of stores executed +system.cpu.iew.exec_rate 0.388403 # Inst execution rate +system.cpu.iew.wb_sent 9127 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 8997 # cumulative count of insts written-back +system.cpu.iew.wb_producers 4717 # num instructions producing a value +system.cpu.iew.wb_consumers 6401 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.346294 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.744120 # average fanout of values written-back +system.cpu.iew.wb_rate 0.374781 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.736916 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 6403 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 4249 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 5279 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 369 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 12090 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.529611 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.331978 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 380 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 11626 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.550748 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.411308 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 9222 76.28% 76.28% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1613 13.34% 89.62% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 453 3.75% 93.37% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 264 2.18% 95.55% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 157 1.30% 96.85% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 121 1.00% 97.85% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 88 0.73% 98.58% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 45 0.37% 98.95% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 127 1.05% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 8945 76.94% 76.94% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1414 12.16% 89.10% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 463 3.98% 93.08% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 244 2.10% 95.18% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 156 1.34% 96.53% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 87 0.75% 97.27% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 110 0.95% 98.22% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 44 0.38% 98.60% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 163 1.40% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 12090 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 11626 # Number of insts commited each cycle system.cpu.commit.count 6403 # Number of instructions committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.commit.refs 2050 # Number of memory references committed @@ -287,50 +289,50 @@ system.cpu.commit.branches 1051 # Nu system.cpu.commit.fp_insts 10 # Number of committed floating point instructions. system.cpu.commit.int_insts 6321 # Number of committed integer instructions. system.cpu.commit.function_calls 127 # Number of function calls committed. -system.cpu.commit.bw_lim_events 127 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 163 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 22264 # The number of ROB reads -system.cpu.rob.rob_writes 22135 # The number of ROB writes -system.cpu.timesIdled 240 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 11801 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 22794 # The number of ROB reads +system.cpu.rob.rob_writes 24351 # The number of ROB writes +system.cpu.timesIdled 230 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 11404 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 6386 # Number of Instructions Simulated system.cpu.committedInsts_total 6386 # Number of Instructions Simulated -system.cpu.cpi 3.870341 # CPI: Cycles Per Instruction -system.cpu.cpi_total 3.870341 # CPI: Total CPI of All Threads -system.cpu.ipc 0.258375 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.258375 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 11291 # number of integer regfile reads -system.cpu.int_regfile_writes 6385 # number of integer regfile writes +system.cpu.cpi 3.759161 # CPI: Cycles Per Instruction +system.cpu.cpi_total 3.759161 # CPI: Total CPI of All Threads +system.cpu.ipc 0.266017 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.266017 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 11850 # number of integer regfile reads +system.cpu.int_regfile_writes 6735 # number of integer regfile writes system.cpu.fp_regfile_reads 8 # number of floating regfile reads system.cpu.fp_regfile_writes 2 # number of floating regfile writes system.cpu.misc_regfile_reads 1 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 157.666490 # Cycle average of tags in use -system.cpu.icache.total_refs 1301 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 307 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 4.237785 # Average number of references to valid blocks. +system.cpu.icache.tagsinuse 159.654959 # Cycle average of tags in use +system.cpu.icache.total_refs 1612 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 311 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 5.183280 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 157.666490 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.076986 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 1301 # number of ReadReq hits -system.cpu.icache.demand_hits 1301 # number of demand (read+write) hits -system.cpu.icache.overall_hits 1301 # number of overall hits -system.cpu.icache.ReadReq_misses 410 # number of ReadReq misses -system.cpu.icache.demand_misses 410 # number of demand (read+write) misses -system.cpu.icache.overall_misses 410 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 14727000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 14727000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 14727000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 1711 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 1711 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 1711 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.239626 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.239626 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.239626 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 35919.512195 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 35919.512195 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 35919.512195 # average overall miss latency +system.cpu.icache.occ_blocks::0 159.654959 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.077957 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits 1612 # number of ReadReq hits +system.cpu.icache.demand_hits 1612 # number of demand (read+write) hits +system.cpu.icache.overall_hits 1612 # number of overall hits +system.cpu.icache.ReadReq_misses 432 # number of ReadReq misses +system.cpu.icache.demand_misses 432 # number of demand (read+write) misses +system.cpu.icache.overall_misses 432 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 15402000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 15402000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 15402000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses 2044 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 2044 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 2044 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate 0.211350 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate 0.211350 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate 0.211350 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency 35652.777778 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency 35652.777778 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 35652.777778 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -340,59 +342,59 @@ system.cpu.icache.avg_blocked_cycles::no_targets no_value system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 103 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 103 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 103 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 307 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 307 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 307 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_hits 121 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits 121 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 121 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses 311 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 311 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 311 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 10832000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 10832000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 10832000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 10985500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 10985500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 10985500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.179427 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.179427 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.179427 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 35283.387622 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 35283.387622 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 35283.387622 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_rate 0.152153 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate 0.152153 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate 0.152153 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency 35323.151125 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 35323.151125 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 35323.151125 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 109.940770 # Cycle average of tags in use -system.cpu.dcache.total_refs 2064 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 109.289403 # Cycle average of tags in use +system.cpu.dcache.total_refs 2155 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 174 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 11.862069 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 12.385057 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 109.940770 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.026841 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 1555 # number of ReadReq hits +system.cpu.dcache.occ_blocks::0 109.289403 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.026682 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits 1646 # number of ReadReq hits system.cpu.dcache.WriteReq_hits 509 # number of WriteReq hits -system.cpu.dcache.demand_hits 2064 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 2064 # number of overall hits -system.cpu.dcache.ReadReq_misses 150 # number of ReadReq misses +system.cpu.dcache.demand_hits 2155 # number of demand (read+write) hits +system.cpu.dcache.overall_hits 2155 # number of overall hits +system.cpu.dcache.ReadReq_misses 155 # number of ReadReq misses system.cpu.dcache.WriteReq_misses 356 # number of WriteReq misses -system.cpu.dcache.demand_misses 506 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 506 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 5422000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 12468000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency 17890000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 17890000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 1705 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses 511 # number of demand (read+write) misses +system.cpu.dcache.overall_misses 511 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 5502500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 12467500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency 17970000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 17970000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses 1801 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses 865 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 2570 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 2570 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.087977 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses 2666 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses 2666 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate 0.086063 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate 0.411561 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate 0.196887 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.196887 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 36146.666667 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 35022.471910 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency 35355.731225 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 35355.731225 # average overall miss latency +system.cpu.dcache.demand_miss_rate 0.191673 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate 0.191673 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency 35500 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 35021.067416 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency 35166.340509 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 35166.340509 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -402,63 +404,63 @@ system.cpu.dcache.avg_blocked_cycles::no_targets no_value system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 49 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits 54 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits 283 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits 332 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 332 # number of overall MSHR hits +system.cpu.dcache.demand_mshr_hits 337 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 337 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses 101 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses 73 # number of WriteReq MSHR misses system.cpu.dcache.demand_mshr_misses 174 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses 174 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 3659000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 2619500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 6278500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 6278500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 3654000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 2611500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 6265500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 6265500 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.059238 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate 0.056080 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate 0.084393 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.067704 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.067704 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 36227.722772 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35883.561644 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 36083.333333 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 36083.333333 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate 0.065266 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate 0.065266 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 36178.217822 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35773.972603 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 36008.620690 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 36008.620690 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 219.485914 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 221.186144 # Cycle average of tags in use system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 407 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.002457 # Average number of references to valid blocks. +system.cpu.l2cache.sampled_refs 411 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.002433 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 219.485914 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.006698 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 221.186144 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.006750 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits 1 # number of ReadReq hits system.cpu.l2cache.demand_hits 1 # number of demand (read+write) hits system.cpu.l2cache.overall_hits 1 # number of overall hits -system.cpu.l2cache.ReadReq_misses 407 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses 411 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses 73 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 480 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 480 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 14004500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 2518000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 16522500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 16522500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 408 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.demand_misses 484 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses 484 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency 14128000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 2513500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency 16641500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency 16641500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses 412 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses 73 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 481 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 481 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.997549 # miss rate for ReadReq accesses +system.cpu.l2cache.demand_accesses 485 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses 485 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate 0.997573 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.997921 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.997921 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 34409.090909 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 34493.150685 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 34421.875000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 34421.875000 # average overall miss latency +system.cpu.l2cache.demand_miss_rate 0.997938 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate 0.997938 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency 34374.695864 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 34431.506849 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency 34383.264463 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 34383.264463 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -470,24 +472,24 @@ system.cpu.l2cache.cache_copies 0 # nu system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 407 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses 411 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses 73 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 480 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 480 # number of overall MSHR misses +system.cpu.l2cache.demand_mshr_misses 484 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses 484 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 12710000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 2291000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 15001000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 15001000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 12819000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 2286000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 15105000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 15105000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.997549 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.997573 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.997921 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.997921 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31228.501229 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31383.561644 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31252.083333 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31252.083333 # average overall mshr miss latency +system.cpu.l2cache.demand_mshr_miss_rate 0.997938 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate 0.997938 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31189.781022 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31315.068493 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31208.677686 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31208.677686 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions |