diff options
Diffstat (limited to 'tests/quick/00.hello/ref/alpha/linux/o3-timing/stats.txt')
| -rw-r--r-- | tests/quick/00.hello/ref/alpha/linux/o3-timing/stats.txt | 332 |
1 files changed, 166 insertions, 166 deletions
diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/00.hello/ref/alpha/linux/o3-timing/stats.txt index 614787416..6483a471a 100644 --- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/stats.txt +++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 83889 # Simulator instruction rate (inst/s) -host_mem_usage 205772 # Number of bytes of host memory used -host_seconds 0.08 # Real time elapsed on the host -host_tick_rate 161742329 # Simulator tick rate (ticks/s) +host_inst_rate 150919 # Simulator instruction rate (inst/s) +host_mem_usage 203704 # Number of bytes of host memory used +host_seconds 0.04 # Real time elapsed on the host +host_tick_rate 290889761 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 6386 # Number of instructions simulated sim_seconds 0.000012 # Number of seconds simulated @@ -16,38 +16,38 @@ system.cpu.BPredUnit.condIncorrect 443 # Nu system.cpu.BPredUnit.condPredicted 1297 # Number of conditional branches predicted system.cpu.BPredUnit.lookups 2180 # Number of BP lookups system.cpu.BPredUnit.usedRAS 306 # Number of times the RAS was used to get a target. -system.cpu.commit.COM:branches 1051 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 127 # number cycles where commit BW limit reached -system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle::samples 12090 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::mean 0.529611 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::stdev 1.331978 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::0 9222 76.28% 76.28% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::1 1613 13.34% 89.62% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::2 453 3.75% 93.37% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::3 264 2.18% 95.55% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::4 157 1.30% 96.85% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::5 121 1.00% 97.85% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::6 88 0.73% 98.58% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::7 45 0.37% 98.95% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::8 127 1.05% 100.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::total 12090 # Number of insts commited each cycle -system.cpu.commit.COM:count 6403 # Number of instructions committed -system.cpu.commit.COM:fp_insts 10 # Number of committed floating point instructions. -system.cpu.commit.COM:function_calls 127 # Number of function calls committed. -system.cpu.commit.COM:int_insts 6321 # Number of committed integer instructions. -system.cpu.commit.COM:loads 1185 # Number of loads committed -system.cpu.commit.COM:membars 0 # Number of memory barriers committed -system.cpu.commit.COM:refs 2050 # Number of memory references committed -system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed system.cpu.commit.branchMispredicts 369 # The number of times a branch was mispredicted +system.cpu.commit.branches 1051 # Number of branches committed +system.cpu.commit.bw_lim_events 127 # number cycles where commit BW limit reached +system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits system.cpu.commit.commitCommittedInsts 6403 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.commitSquashedInsts 4249 # The number of squashed insts skipped by commit +system.cpu.commit.committed_per_cycle::samples 12090 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.529611 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.331978 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 9222 76.28% 76.28% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1613 13.34% 89.62% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 453 3.75% 93.37% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 264 2.18% 95.55% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 157 1.30% 96.85% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 121 1.00% 97.85% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 88 0.73% 98.58% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 45 0.37% 98.95% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 127 1.05% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 12090 # Number of insts commited each cycle +system.cpu.commit.count 6403 # Number of instructions committed +system.cpu.commit.fp_insts 10 # Number of committed floating point instructions. +system.cpu.commit.function_calls 127 # Number of function calls committed. +system.cpu.commit.int_insts 6321 # Number of committed integer instructions. +system.cpu.commit.loads 1185 # Number of loads committed +system.cpu.commit.membars 0 # Number of memory barriers committed +system.cpu.commit.refs 2050 # Number of memory references committed +system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.committedInsts 6386 # Number of Instructions Simulated system.cpu.committedInsts_total 6386 # Number of Instructions Simulated system.cpu.cpi 3.870341 # CPI: Cycles Per Instruction @@ -96,8 +96,8 @@ system.cpu.dcache.demand_mshr_misses 174 # nu system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.026841 # Average percentage of cache occupancy system.cpu.dcache.occ_blocks::0 109.940770 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.026841 # Average percentage of cache occupancy system.cpu.dcache.overall_accesses 2570 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 35355.731225 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 36083.333333 # average overall mshr miss latency @@ -119,15 +119,15 @@ system.cpu.dcache.tagsinuse 109.940770 # Cy system.cpu.dcache.total_refs 2064 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 1035 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 75 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 181 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 12021 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 8780 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 2228 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 825 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 209 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 47 # Number of cycles decode is unblocking +system.cpu.decode.BlockedCycles 1035 # Number of cycles decode is blocked +system.cpu.decode.BranchMispred 75 # Number of times decode detected a branch misprediction +system.cpu.decode.BranchResolved 181 # Number of times decode resolved a branch +system.cpu.decode.DecodedInsts 12021 # Number of instructions handled by decode +system.cpu.decode.IdleCycles 8780 # Number of cycles decode is idle +system.cpu.decode.RunCycles 2228 # Number of cycles decode is running +system.cpu.decode.SquashCycles 825 # Number of cycles decode is squashing +system.cpu.decode.SquashedInsts 209 # Number of squashed instructions handled by decode +system.cpu.decode.UnblockCycles 47 # Number of cycles decode is unblocking system.cpu.dtb.data_accesses 2822 # DTB accesses system.cpu.dtb.data_acv 0 # DTB access violations system.cpu.dtb.data_hits 2761 # DTB hits @@ -207,8 +207,8 @@ system.cpu.icache.demand_mshr_misses 307 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.076986 # Average percentage of cache occupancy system.cpu.icache.occ_blocks::0 157.666490 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.076986 # Average percentage of cache occupancy system.cpu.icache.overall_accesses 1711 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 35919.512195 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 35283.387622 # average overall mshr miss latency @@ -231,21 +231,13 @@ system.cpu.icache.total_refs 1301 # To system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idleCycles 11801 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 1424 # Number of branches executed -system.cpu.iew.EXEC:nop 82 # number of nop insts executed -system.cpu.iew.EXEC:rate 0.357542 # Inst execution rate -system.cpu.iew.EXEC:refs 2832 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 1038 # Number of stores executed -system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 5952 # num instructions consuming a value -system.cpu.iew.WB:count 8559 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.744120 # average fanout of values written-back -system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 4429 # num instructions producing a value -system.cpu.iew.WB:rate 0.346294 # insts written-back per cycle -system.cpu.iew.WB:sent 8658 # cumulative count of insts sent to commit system.cpu.iew.branchMispredicts 429 # Number of branch mispredicts detected at execute +system.cpu.iew.exec_branches 1424 # Number of branches executed +system.cpu.iew.exec_nop 82 # number of nop insts executed +system.cpu.iew.exec_rate 0.357542 # Inst execution rate +system.cpu.iew.exec_refs 2832 # number of memory reference insts executed +system.cpu.iew.exec_stores 1038 # Number of stores executed +system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.iewBlockCycles 67 # Number of cycles IEW is blocking system.cpu.iew.iewDispLoadInsts 2144 # Number of dispatched load instructions system.cpu.iew.iewDispNonSpecInsts 25 # Number of dispatched non-speculative instructions @@ -273,103 +265,93 @@ system.cpu.iew.lsq.thread.0.squashedStores 330 # system.cpu.iew.memOrderViolationEvents 16 # Number of memory order violations system.cpu.iew.predictedNotTakenIncorrect 304 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedTakenIncorrect 125 # Number of branches that were predicted taken incorrectly +system.cpu.iew.wb_consumers 5952 # num instructions consuming a value +system.cpu.iew.wb_count 8559 # cumulative count of insts written-back +system.cpu.iew.wb_fanout 0.744120 # average fanout of values written-back +system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ +system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ +system.cpu.iew.wb_producers 4429 # num instructions producing a value +system.cpu.iew.wb_rate 0.346294 # insts written-back per cycle +system.cpu.iew.wb_sent 8658 # cumulative count of insts sent to commit system.cpu.int_regfile_reads 11291 # number of integer regfile reads system.cpu.int_regfile_writes 6385 # number of integer regfile writes system.cpu.ipc 0.258375 # IPC: Instructions Per Cycle system.cpu.ipc_total 0.258375 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntAlu 6174 67.79% 67.81% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntMult 1 0.01% 67.82% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatAdd 2 0.02% 67.84% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 67.84% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 67.84% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 67.84% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 67.84% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 67.84% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 67.84% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 67.84% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 67.84% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 67.84% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 67.84% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 67.84% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 67.84% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 67.84% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 67.84% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 67.84% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 67.84% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 67.84% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 67.84% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 67.84% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 67.84% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 67.84% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 67.84% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 67.84% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 67.84% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 67.84% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemRead 1875 20.59% 88.43% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemWrite 1054 11.57% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::total 9108 # Type of FU issued -system.cpu.iq.ISSUE:fu_busy_cnt 88 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.009662 # FU busy rate (busy events/executed inst) -system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntAlu 1 1.14% 1.14% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 1.14% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 1.14% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 1.14% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 1.14% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 1.14% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 1.14% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 1.14% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 1.14% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 1.14% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 1.14% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 1.14% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 1.14% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 1.14% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 1.14% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 1.14% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 1.14% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 1.14% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 1.14% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 1.14% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 1.14% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 1.14% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 1.14% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 1.14% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 1.14% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 1.14% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 1.14% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 1.14% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 1.14% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemRead 52 59.09% 60.23% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemWrite 35 39.77% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:issued_per_cycle::samples 12915 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::mean 0.705226 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.305176 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::0 8840 68.45% 68.45% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::1 1652 12.79% 81.24% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::2 1039 8.04% 89.28% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::3 684 5.30% 94.58% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::4 367 2.84% 97.42% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::5 198 1.53% 98.95% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::6 88 0.68% 99.64% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::7 36 0.28% 99.91% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::8 11 0.09% 100.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::total 12915 # Number of insts issued each cycle -system.cpu.iq.ISSUE:rate 0.368506 # Inst issue rate +system.cpu.iq.FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 6174 67.79% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 1 0.01% 67.82% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 67.84% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.84% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.84% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.84% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.84% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.84% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 1875 20.59% 88.43% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1054 11.57% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::total 9108 # Type of FU issued system.cpu.iq.fp_alu_accesses 11 # Number of floating point alu accesses system.cpu.iq.fp_inst_queue_reads 21 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_wakeup_accesses 10 # Number of floating instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_writes 10 # Number of floating instruction queue writes +system.cpu.iq.fu_busy_cnt 88 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.009662 # FU busy rate (busy events/executed inst) +system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 1 1.14% 1.14% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 1.14% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 1.14% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.14% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.14% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.14% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 1.14% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.14% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 1.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 1.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.14% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 52 59.09% 60.23% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 35 39.77% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.int_alu_accesses 9183 # Number of integer alu accesses system.cpu.iq.int_inst_queue_reads 31223 # Number of integer instruction queue reads system.cpu.iq.int_inst_queue_wakeup_accesses 8549 # Number of integer instruction queue wakeup accesses @@ -381,6 +363,24 @@ system.cpu.iq.iqSquashedInstsExamined 3797 # Nu system.cpu.iq.iqSquashedInstsIssued 25 # Number of squashed instructions issued system.cpu.iq.iqSquashedNonSpecRemoved 8 # Number of squashed non-spec instructions that were removed system.cpu.iq.iqSquashedOperandsExamined 2286 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.issued_per_cycle::samples 12915 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.705226 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.305176 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 8840 68.45% 68.45% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1652 12.79% 81.24% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 1039 8.04% 89.28% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 684 5.30% 94.58% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 367 2.84% 97.42% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 198 1.53% 98.95% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 88 0.68% 99.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 36 0.28% 99.91% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 11 0.09% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 12915 # Number of insts issued each cycle +system.cpu.iq.rate 0.368506 # Inst issue rate system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_hits 0 # DTB hits @@ -438,8 +438,8 @@ system.cpu.l2cache.demand_mshr_misses 480 # nu system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.006698 # Average percentage of cache occupancy system.cpu.l2cache.occ_blocks::0 219.485914 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.006698 # Average percentage of cache occupancy system.cpu.l2cache.overall_accesses 481 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 34421.875000 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 31252.083333 # average overall mshr miss latency @@ -470,27 +470,27 @@ system.cpu.misc_regfile_writes 1 # nu system.cpu.numCycles 24716 # number of cpu cycles simulated system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.rename.RENAME:BlockCycles 337 # Number of cycles rename is blocking -system.cpu.rename.RENAME:CommittedMaps 4583 # Number of HB maps that are committed -system.cpu.rename.RENAME:IQFullEvents 8 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 8928 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 260 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:RenameLookups 14615 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 11616 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 8669 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 2118 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 825 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 301 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 4086 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:fp_rename_lookups 17 # Number of floating rename lookups -system.cpu.rename.RENAME:int_rename_lookups 14598 # Number of integer rename lookups -system.cpu.rename.RENAME:serializeStallCycles 406 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 28 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 754 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 22 # count of temporary serializing insts renamed +system.cpu.rename.BlockCycles 337 # Number of cycles rename is blocking +system.cpu.rename.CommittedMaps 4583 # Number of HB maps that are committed +system.cpu.rename.IQFullEvents 8 # Number of times rename has blocked due to IQ full +system.cpu.rename.IdleCycles 8928 # Number of cycles rename is idle +system.cpu.rename.LSQFullEvents 260 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenameLookups 14615 # Number of register rename lookups that rename has made +system.cpu.rename.RenamedInsts 11616 # Number of instructions processed by rename +system.cpu.rename.RenamedOperands 8669 # Number of destination operands rename has renamed +system.cpu.rename.RunCycles 2118 # Number of cycles rename is running +system.cpu.rename.SquashCycles 825 # Number of cycles rename is squashing +system.cpu.rename.UnblockCycles 301 # Number of cycles rename is unblocking +system.cpu.rename.UndoneMaps 4086 # Number of HB maps that are undone due to squashing +system.cpu.rename.fp_rename_lookups 17 # Number of floating rename lookups +system.cpu.rename.int_rename_lookups 14598 # Number of integer rename lookups +system.cpu.rename.serializeStallCycles 406 # count of cycles rename stalled for serializing inst +system.cpu.rename.serializingInsts 28 # count of serializing insts renamed +system.cpu.rename.skidInsts 754 # count of insts added to the skid buffer +system.cpu.rename.tempSerializingInsts 22 # count of temporary serializing insts renamed system.cpu.rob.rob_reads 22264 # The number of ROB reads system.cpu.rob.rob_writes 22135 # The number of ROB writes system.cpu.timesIdled 240 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.workload.PROG:num_syscalls 17 # Number of system calls +system.cpu.workload.num_syscalls 17 # Number of system calls ---------- End Simulation Statistics ---------- |