diff options
Diffstat (limited to 'tests/quick/00.hello/ref/alpha/linux/o3-timing')
3 files changed, 19 insertions, 13 deletions
diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini b/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini index 9978c29e9..1b5a762f3 100644 --- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini +++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini @@ -109,7 +109,7 @@ hash_delay=1 latency=1000 max_miss_count=0 mshrs=10 -prefetch_cache_check_push=true +num_cpus=1 prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 @@ -281,7 +281,7 @@ hash_delay=1 latency=1000 max_miss_count=0 mshrs=10 -prefetch_cache_check_push=true +num_cpus=1 prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 @@ -316,7 +316,7 @@ hash_delay=1 latency=1000 max_miss_count=0 mshrs=10 -prefetch_cache_check_push=true +num_cpus=1 prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 @@ -358,7 +358,7 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello +executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/alpha/linux/hello gid=100 input=cin max_stack_size=67108864 diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/simout b/tests/quick/00.hello/ref/alpha/linux/o3-timing/simout index 207a844c8..0bdde157a 100755 --- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/simout +++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/simout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jul 6 2009 11:03:45 -M5 revision d3635cac686a 6289 default ruby_refs.diff qtip tip -M5 started Jul 6 2009 11:11:06 -M5 executing on maize -command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/o3-timing +M5 compiled Feb 24 2010 23:12:54 +M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip +M5 started Feb 25 2010 01:04:08 +M5 executing on SC2B0619 +command line: build/ALPHA_SE_MOESI_hammer/m5.fast -d build/ALPHA_SE_MOESI_hammer/tests/fast/quick/00.hello/alpha/linux/o3-timing -re tests/run.py build/ALPHA_SE_MOESI_hammer/tests/fast/quick/00.hello/alpha/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/00.hello/ref/alpha/linux/o3-timing/stats.txt index 584bdfccf..7fffd3b0b 100644 --- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/stats.txt +++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 76035 # Simulator instruction rate (inst/s) -host_mem_usage 189864 # Number of bytes of host memory used -host_seconds 0.08 # Real time elapsed on the host -host_tick_rate 148017846 # Simulator tick rate (ticks/s) +host_inst_rate 104903 # Simulator instruction rate (inst/s) +host_mem_usage 190976 # Number of bytes of host memory used +host_seconds 0.06 # Real time elapsed on the host +host_tick_rate 203948336 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 6386 # Number of instructions simulated sim_seconds 0.000012 # Number of seconds simulated @@ -93,6 +93,8 @@ system.cpu.dcache.demand_mshr_misses 188 # nu system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.occ_%::0 0.026922 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 110.270477 # Average occupied blocks per context system.cpu.dcache.overall_accesses 2658 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 34900.722022 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 36010.638298 # average overall mshr miss latency @@ -199,6 +201,8 @@ system.cpu.icache.demand_mshr_misses 307 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.icache.occ_%::0 0.077417 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 158.550695 # Average occupied blocks per context system.cpu.icache.overall_accesses 1802 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 35400.943396 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 35286.644951 # average overall mshr miss latency @@ -387,6 +391,8 @@ system.cpu.l2cache.demand_mshr_misses 480 # nu system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.occ_%::0 0.006558 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 214.901533 # Average occupied blocks per context system.cpu.l2cache.overall_accesses 481 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 34440.625000 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 31275 # average overall mshr miss latency |