diff options
Diffstat (limited to 'tests/quick/00.hello/ref/alpha/linux/simple-atomic/m5stats.txt')
| -rw-r--r-- | tests/quick/00.hello/ref/alpha/linux/simple-atomic/m5stats.txt | 34 |
1 files changed, 17 insertions, 17 deletions
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/m5stats.txt b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/m5stats.txt index c89057e77..6f4810c44 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/m5stats.txt +++ b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/m5stats.txt @@ -1,34 +1,34 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 274181 # Simulator instruction rate (inst/s) -host_mem_usage 172576 # Number of bytes of host memory used -host_seconds 0.02 # Real time elapsed on the host -host_tick_rate 135418658 # Simulator tick rate (ticks/s) +host_inst_rate 74368 # Simulator instruction rate (inst/s) +host_mem_usage 201628 # Number of bytes of host memory used +host_seconds 0.09 # Real time elapsed on the host +host_tick_rate 37260110 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 5641 # Number of instructions simulated +sim_insts 6315 # Number of instructions simulated sim_seconds 0.000003 # Number of seconds simulated -sim_ticks 2833500 # Number of ticks simulated -system.cpu.dtb.accesses 1801 # DTB accesses +sim_ticks 3170500 # Number of ticks simulated +system.cpu.dtb.accesses 2040 # DTB accesses system.cpu.dtb.acv 0 # DTB access violations -system.cpu.dtb.hits 1791 # DTB hits +system.cpu.dtb.hits 2030 # DTB hits system.cpu.dtb.misses 10 # DTB misses -system.cpu.dtb.read_accesses 986 # DTB read accesses +system.cpu.dtb.read_accesses 1175 # DTB read accesses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_hits 979 # DTB read hits +system.cpu.dtb.read_hits 1168 # DTB read hits system.cpu.dtb.read_misses 7 # DTB read misses -system.cpu.dtb.write_accesses 815 # DTB write accesses +system.cpu.dtb.write_accesses 865 # DTB write accesses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_hits 812 # DTB write hits +system.cpu.dtb.write_hits 862 # DTB write hits system.cpu.dtb.write_misses 3 # DTB write misses system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.itb.accesses 5668 # ITB accesses +system.cpu.itb.accesses 6342 # ITB accesses system.cpu.itb.acv 0 # ITB acv -system.cpu.itb.hits 5651 # ITB hits +system.cpu.itb.hits 6325 # ITB hits system.cpu.itb.misses 17 # ITB misses system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 5668 # number of cpu cycles simulated -system.cpu.num_insts 5641 # Number of instructions executed -system.cpu.num_refs 1801 # Number of memory references +system.cpu.numCycles 6342 # number of cpu cycles simulated +system.cpu.num_insts 6315 # Number of instructions executed +system.cpu.num_refs 2040 # Number of memory references system.cpu.workload.PROG:num_syscalls 17 # Number of system calls ---------- End Simulation Statistics ---------- |