diff options
Diffstat (limited to 'tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/ruby.stats')
| -rw-r--r-- | tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/ruby.stats | 617 |
1 files changed, 617 insertions, 0 deletions
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/ruby.stats b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/ruby.stats new file mode 100644 index 000000000..0defa99bd --- /dev/null +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/ruby.stats @@ -0,0 +1,617 @@ + +================ Begin RubySystem Configuration Print ================ + +RubySystem config: + random_seed: 1234 + randomization: 0 + cycle_period: 1 + block_size_bytes: 64 + block_size_bits: 6 + memory_size_bytes: 134217728 + memory_size_bits: 27 + +Network Configuration +--------------------- +network: SIMPLE_NETWORK +topology: + +virtual_net_0: active, unordered +virtual_net_1: active, unordered +virtual_net_2: active, unordered +virtual_net_3: inactive +virtual_net_4: inactive +virtual_net_5: inactive +virtual_net_6: inactive +virtual_net_7: inactive +virtual_net_8: inactive +virtual_net_9: inactive + + +Profiler Configuration +---------------------- +periodic_stats_period: 1000000 + +================ End RubySystem Configuration Print ================ + + +Real time: Jan/28/2010 13:57:44 + +Profiler Stats +-------------- +Elapsed_time_in_seconds: 1 +Elapsed_time_in_minutes: 0.0166667 +Elapsed_time_in_hours: 0.000277778 +Elapsed_time_in_days: 1.15741e-05 + +Virtual_time_in_seconds: 0.95 +Virtual_time_in_minutes: 0.0158333 +Virtual_time_in_hours: 0.000263889 +Virtual_time_in_days: 1.09954e-05 + +Ruby_current_time: 275313 +Ruby_start_time: 0 +Ruby_cycles: 275313 + +mbytes_resident: 34.4609 +mbytes_total: 34.4688 +resident_ratio: 1 + +Total_misses: 0 +total_misses: 0 [ 0 ] +user_misses: 0 [ 0 ] +supervisor_misses: 0 [ 0 ] + +ruby_cycles_executed: 275314 [ 275314 ] + +transactions_started: 0 [ 0 ] +transactions_ended: 0 [ 0 ] +cycles_per_transaction: 0 [ 0 ] +misses_per_transaction: 0 [ 0 ] + + +Busy Controller Counts: +L1Cache-0:0 +L2Cache-0:0 +Directory-0:0 + + +Busy Bank Count:0 + +sequencer_requests_outstanding: [binsize: 1 max: 1 count: 8465 average: 1 | standard deviation: 0 | 0 8465 ] + +All Non-Zero Cycle Demand Cache Accesses +---------------------------------------- +miss_latency: [binsize: 2 max: 281 count: 8464 average: 31.5275 | standard deviation: 62.4195 | 0 6974 0 0 0 0 0 0 0 30 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 156 439 246 330 220 8 7 9 11 3 2 9 4 5 1 0 0 1 1 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 0 1 0 0 0 0 1 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_1: [binsize: 2 max: 269 count: 6414 average: 20.6784 | standard deviation: 51.1007 | 0 5723 0 0 0 0 0 0 0 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 59 203 95 191 106 4 5 4 6 2 1 1 1 4 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_2: [binsize: 2 max: 281 count: 1185 average: 82.5848 | standard deviation: 82.5677 | 0 602 0 0 0 0 0 0 0 13 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 64 191 73 123 92 4 2 3 3 1 1 7 2 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_3: [binsize: 2 max: 215 count: 865 average: 42.0289 | standard deviation: 69.8546 | 0 649 0 0 0 0 0 0 0 12 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 33 45 78 16 22 0 0 2 2 0 0 1 1 1 0 0 0 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] + +All Non-Zero Cycle SW Prefetch Requests +------------------------------------ +prefetch_latency: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +prefetch_latency_L2Miss:[binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +Request vs. RubySystem State Profile +-------------------------------- + + +filter_action: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + +Message Delayed Cycles +---------------------- +Total_delay_cycles: [binsize: 1 max: 30 count: 9645 average: 0.0134785 | standard deviation: 0.509043 | 9637 0 0 0 0 0 0 0 0 0 4 0 0 0 0 0 0 0 0 0 3 0 0 0 0 0 0 0 0 0 1 ] +Total_nonPF_delay_cycles: [binsize: 1 max: 0 count: 6920 average: 0 | standard deviation: 0 | 6920 ] + virtual_network_0_delay_cycles: [binsize: 1 max: 30 count: 2725 average: 0.0477064 | standard deviation: 0.956852 | 2717 0 0 0 0 0 0 0 0 0 4 0 0 0 0 0 0 0 0 0 3 0 0 0 0 0 0 0 0 0 1 ] + virtual_network_1_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + virtual_network_2_delay_cycles: [binsize: 1 max: 0 count: 1041 average: 0 | standard deviation: 0 | 1041 ] + virtual_network_3_delay_cycles: [binsize: 1 max: 0 count: 5879 average: 0 | standard deviation: 0 | 5879 ] + virtual_network_4_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + virtual_network_5_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + virtual_network_6_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + virtual_network_7_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + virtual_network_8_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + virtual_network_9_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + +Resource Usage +-------------- +page_size: 4096 +user_time: 0 +system_time: 0 +page_reclaims: 7392 +page_faults: 2212 +swaps: 0 +block_inputs: 0 +block_outputs: 0 + +Network Stats +------------- + +switch_0_inlinks: 2 +switch_0_outlinks: 2 +links_utilized_percent_switch_0: 0.0889147 + links_utilized_percent_switch_0_link_0: 0.0675913 bw: 640000 base_latency: 1 + links_utilized_percent_switch_0_link_1: 0.110238 bw: 160000 base_latency: 1 + + outgoing_messages_switch_0_link_0_Request_Control: 1041 8328 [ 1041 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_0_Response_Data: 1490 107280 [ 0 1490 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_0_Response_Control: 436 3488 [ 0 436 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Control: 1490 11920 [ 1490 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Response_Control: 1699 13592 [ 0 900 799 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Writeback_Data: 288 20736 [ 147 141 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Writeback_Control: 289 2312 [ 289 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + +switch_1_inlinks: 2 +switch_1_outlinks: 2 +links_utilized_percent_switch_1: 0.228653 + links_utilized_percent_switch_1_link_0: 0.0938114 bw: 640000 base_latency: 1 + links_utilized_percent_switch_1_link_1: 0.363495 bw: 160000 base_latency: 1 + + outgoing_messages_switch_1_link_0_Control: 1490 11920 [ 1490 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_Response_Data: 1460 105120 [ 0 1460 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_Response_Control: 3151 25208 [ 0 2352 799 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_Writeback_Data: 288 20736 [ 147 141 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_Writeback_Control: 289 2312 [ 289 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Control: 1460 11680 [ 1460 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Request_Control: 1041 8328 [ 1041 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Response_Data: 1767 127224 [ 0 1767 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Response_Control: 1611 12888 [ 0 1611 0 0 0 0 0 0 0 0 ] base_latency: 1 + +switch_2_inlinks: 2 +switch_2_outlinks: 2 +links_utilized_percent_switch_2: 0.144145 + links_utilized_percent_switch_2_link_0: 0.0232826 bw: 640000 base_latency: 1 + links_utilized_percent_switch_2_link_1: 0.265007 bw: 160000 base_latency: 1 + + outgoing_messages_switch_2_link_0_Control: 1460 11680 [ 1460 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_0_Response_Data: 277 19944 [ 0 277 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_0_Response_Control: 1175 9400 [ 0 1175 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Response_Data: 1460 105120 [ 0 1460 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Response_Control: 1452 11616 [ 0 1452 0 0 0 0 0 0 0 0 ] base_latency: 1 + +switch_3_inlinks: 3 +switch_3_outlinks: 3 +links_utilized_percent_switch_3: 0.246247 + links_utilized_percent_switch_3_link_0: 0.270365 bw: 160000 base_latency: 1 + links_utilized_percent_switch_3_link_1: 0.375246 bw: 160000 base_latency: 1 + links_utilized_percent_switch_3_link_2: 0.0931304 bw: 160000 base_latency: 1 + + outgoing_messages_switch_3_link_0_Request_Control: 1041 8328 [ 1041 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_0_Response_Data: 1490 107280 [ 0 1490 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_0_Response_Control: 436 3488 [ 0 436 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_1_Control: 1490 11920 [ 1490 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_1_Response_Data: 1460 105120 [ 0 1460 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_1_Response_Control: 3151 25208 [ 0 2352 799 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_1_Writeback_Data: 288 20736 [ 147 141 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_1_Writeback_Control: 289 2312 [ 289 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_2_Control: 1460 11680 [ 1460 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_2_Response_Data: 277 19944 [ 0 277 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_2_Response_Control: 1175 9400 [ 0 1175 0 0 0 0 0 0 0 0 ] base_latency: 1 + +Cache Stats: system.ruby.network.topology.ext_links0.ext_node.sequencer.icache + system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_misses: 0 + system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_demand_misses: 0 + system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_prefetches: 0 + system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_sw_prefetches: 0 + system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_hw_prefetches: 0 + system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_misses_per_transaction: nan + + system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + +Cache Stats: system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache + system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_misses: 0 + system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_demand_misses: 0 + system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_prefetches: 0 + system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_sw_prefetches: 0 + system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_hw_prefetches: 0 + system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_misses_per_transaction: nan + + system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + + --- L1Cache 0 --- + - Event Counts - +Load 1185 +Ifetch 6414 +Store 865 +Inv 1041 +L1_Replacement 1354 +Fwd_GETX 0 +Fwd_GETS 0 +Fwd_GET_INSTR 0 +Data 0 +Data_Exclusive 583 +DataS_fromL1 0 +Data_all_Acks 907 +Ack 0 +Ack_all 0 +WB_Ack 436 + + - Transitions - +NP Load 525 +NP Ifetch 646 +NP Store 191 +NP Inv 356 +NP L1_Replacement 0 <-- + +I Load 58 +I Ifetch 45 +I Store 25 +I Inv 0 <-- +I L1_Replacement 556 + +S Load 0 <-- +S Ifetch 5723 +S Store 0 <-- +S Inv 325 +S L1_Replacement 362 + +E Load 454 +E Ifetch 0 <-- +E Store 71 +E Inv 219 +E L1_Replacement 291 +E Fwd_GETX 0 <-- +E Fwd_GETS 0 <-- +E Fwd_GET_INSTR 0 <-- + +M Load 148 +M Ifetch 0 <-- +M Store 578 +M Inv 141 +M L1_Replacement 145 +M Fwd_GETX 0 <-- +M Fwd_GETS 0 <-- +M Fwd_GET_INSTR 0 <-- + +IS Load 0 <-- +IS Ifetch 0 <-- +IS Store 0 <-- +IS Inv 0 <-- +IS L1_Replacement 0 <-- +IS Data_Exclusive 583 +IS DataS_fromL1 0 <-- +IS Data_all_Acks 691 + +IM Load 0 <-- +IM Ifetch 0 <-- +IM Store 0 <-- +IM Inv 0 <-- +IM L1_Replacement 0 <-- +IM Data 0 <-- +IM Data_all_Acks 216 +IM Ack 0 <-- + +SM Load 0 <-- +SM Ifetch 0 <-- +SM Store 0 <-- +SM Inv 0 <-- +SM L1_Replacement 0 <-- +SM Ack 0 <-- +SM Ack_all 0 <-- + +IS_I Load 0 <-- +IS_I Ifetch 0 <-- +IS_I Store 0 <-- +IS_I Inv 0 <-- +IS_I L1_Replacement 0 <-- +IS_I Data_Exclusive 0 <-- +IS_I DataS_fromL1 0 <-- +IS_I Data_all_Acks 0 <-- + +M_I Load 0 <-- +M_I Ifetch 0 <-- +M_I Store 0 <-- +M_I Inv 0 <-- +M_I L1_Replacement 0 <-- +M_I Fwd_GETX 0 <-- +M_I Fwd_GETS 0 <-- +M_I Fwd_GET_INSTR 0 <-- +M_I WB_Ack 436 + +E_I Load 0 <-- +E_I Ifetch 0 <-- +E_I Store 0 <-- +E_I L1_Replacement 0 <-- + +Cache Stats: system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory + system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_misses: 0 + system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_demand_misses: 0 + system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_prefetches: 0 + system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_sw_prefetches: 0 + system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_hw_prefetches: 0 + system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_misses_per_transaction: nan + + system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + + --- L2Cache 0 --- + - Event Counts - +L1_GET_INSTR 691 +L1_GETS 592 +L1_GETX 220 +L1_UPGRADE 0 +L1_PUTX 436 +L1_PUTX_old 0 +Fwd_L1_GETX 0 +Fwd_L1_GETS 0 +Fwd_L1_GET_INSTR 0 +L2_Replacement 142 +L2_Replacement_clean 1310 +Mem_Data 1460 +Mem_Ack 1452 +WB_Data 141 +WB_Data_clean 0 +Ack 0 +Ack_all 900 +Unblock 0 +Unblock_Cancel 0 +Exclusive_Unblock 799 +MEM_Inv 0 + + - Transitions - +NP L1_GET_INSTR 686 +NP L1_GETS 570 +NP L1_GETX 204 +NP L1_PUTX 0 <-- +NP L1_PUTX_old 0 <-- + +SS L1_GET_INSTR 5 +SS L1_GETS 0 <-- +SS L1_GETX 0 <-- +SS L1_UPGRADE 0 <-- +SS L1_PUTX 0 <-- +SS L1_PUTX_old 0 <-- +SS L2_Replacement 0 <-- +SS L2_Replacement_clean 681 +SS MEM_Inv 0 <-- + +M L1_GET_INSTR 0 <-- +M L1_GETS 13 +M L1_GETX 12 +M L1_PUTX 0 <-- +M L1_PUTX_old 0 <-- +M L2_Replacement 134 +M L2_Replacement_clean 277 +M MEM_Inv 0 <-- + +MT L1_GET_INSTR 0 <-- +MT L1_GETS 0 <-- +MT L1_GETX 0 <-- +MT L1_PUTX 436 +MT L1_PUTX_old 0 <-- +MT L2_Replacement 8 +MT L2_Replacement_clean 352 +MT MEM_Inv 0 <-- + +M_I L1_GET_INSTR 0 <-- +M_I L1_GETS 9 +M_I L1_GETX 4 +M_I L1_UPGRADE 0 <-- +M_I L1_PUTX 0 <-- +M_I L1_PUTX_old 0 <-- +M_I Mem_Ack 1452 +M_I MEM_Inv 0 <-- + +MT_I L1_GET_INSTR 0 <-- +MT_I L1_GETS 0 <-- +MT_I L1_GETX 0 <-- +MT_I L1_UPGRADE 0 <-- +MT_I L1_PUTX 0 <-- +MT_I L1_PUTX_old 0 <-- +MT_I WB_Data 6 +MT_I WB_Data_clean 0 <-- +MT_I Ack_all 2 +MT_I MEM_Inv 0 <-- + +MCT_I L1_GET_INSTR 0 <-- +MCT_I L1_GETS 0 <-- +MCT_I L1_GETX 0 <-- +MCT_I L1_UPGRADE 0 <-- +MCT_I L1_PUTX 0 <-- +MCT_I L1_PUTX_old 0 <-- +MCT_I WB_Data 135 +MCT_I WB_Data_clean 0 <-- +MCT_I Ack_all 217 + +I_I L1_GET_INSTR 0 <-- +I_I L1_GETS 0 <-- +I_I L1_GETX 0 <-- +I_I L1_UPGRADE 0 <-- +I_I L1_PUTX 0 <-- +I_I L1_PUTX_old 0 <-- +I_I Ack 0 <-- +I_I Ack_all 681 + +S_I L1_GET_INSTR 0 <-- +S_I L1_GETS 0 <-- +S_I L1_GETX 0 <-- +S_I L1_UPGRADE 0 <-- +S_I L1_PUTX 0 <-- +S_I L1_PUTX_old 0 <-- +S_I Ack 0 <-- +S_I Ack_all 0 <-- +S_I MEM_Inv 0 <-- + +ISS L1_GET_INSTR 0 <-- +ISS L1_GETS 0 <-- +ISS L1_GETX 0 <-- +ISS L1_PUTX 0 <-- +ISS L1_PUTX_old 0 <-- +ISS L2_Replacement 0 <-- +ISS L2_Replacement_clean 0 <-- +ISS Mem_Data 570 +ISS MEM_Inv 0 <-- + +IS L1_GET_INSTR 0 <-- +IS L1_GETS 0 <-- +IS L1_GETX 0 <-- +IS L1_PUTX 0 <-- +IS L1_PUTX_old 0 <-- +IS L2_Replacement 0 <-- +IS L2_Replacement_clean 0 <-- +IS Mem_Data 686 +IS MEM_Inv 0 <-- + +IM L1_GET_INSTR 0 <-- +IM L1_GETS 0 <-- +IM L1_GETX 0 <-- +IM L1_PUTX 0 <-- +IM L1_PUTX_old 0 <-- +IM L2_Replacement 0 <-- +IM L2_Replacement_clean 0 <-- +IM Mem_Data 204 +IM MEM_Inv 0 <-- + +SS_MB L1_GET_INSTR 0 <-- +SS_MB L1_GETS 0 <-- +SS_MB L1_GETX 0 <-- +SS_MB L1_UPGRADE 0 <-- +SS_MB L1_PUTX 0 <-- +SS_MB L1_PUTX_old 0 <-- +SS_MB L2_Replacement 0 <-- +SS_MB L2_Replacement_clean 0 <-- +SS_MB Unblock_Cancel 0 <-- +SS_MB Exclusive_Unblock 0 <-- +SS_MB MEM_Inv 0 <-- + +MT_MB L1_GET_INSTR 0 <-- +MT_MB L1_GETS 0 <-- +MT_MB L1_GETX 0 <-- +MT_MB L1_UPGRADE 0 <-- +MT_MB L1_PUTX 0 <-- +MT_MB L1_PUTX_old 0 <-- +MT_MB L2_Replacement 0 <-- +MT_MB L2_Replacement_clean 0 <-- +MT_MB Unblock_Cancel 0 <-- +MT_MB Exclusive_Unblock 799 +MT_MB MEM_Inv 0 <-- + +M_MB L1_GET_INSTR 0 <-- +M_MB L1_GETS 0 <-- +M_MB L1_GETX 0 <-- +M_MB L1_UPGRADE 0 <-- +M_MB L1_PUTX 0 <-- +M_MB L1_PUTX_old 0 <-- +M_MB L2_Replacement 0 <-- +M_MB L2_Replacement_clean 0 <-- +M_MB Exclusive_Unblock 0 <-- +M_MB MEM_Inv 0 <-- + +MT_IIB L1_GET_INSTR 0 <-- +MT_IIB L1_GETS 0 <-- +MT_IIB L1_GETX 0 <-- +MT_IIB L1_UPGRADE 0 <-- +MT_IIB L1_PUTX 0 <-- +MT_IIB L1_PUTX_old 0 <-- +MT_IIB L2_Replacement 0 <-- +MT_IIB L2_Replacement_clean 0 <-- +MT_IIB WB_Data 0 <-- +MT_IIB WB_Data_clean 0 <-- +MT_IIB Unblock 0 <-- +MT_IIB MEM_Inv 0 <-- + +MT_IB L1_GET_INSTR 0 <-- +MT_IB L1_GETS 0 <-- +MT_IB L1_GETX 0 <-- +MT_IB L1_UPGRADE 0 <-- +MT_IB L1_PUTX 0 <-- +MT_IB L1_PUTX_old 0 <-- +MT_IB L2_Replacement 0 <-- +MT_IB L2_Replacement_clean 0 <-- +MT_IB WB_Data 0 <-- +MT_IB WB_Data_clean 0 <-- +MT_IB Unblock_Cancel 0 <-- +MT_IB MEM_Inv 0 <-- + +MT_SB L1_GET_INSTR 0 <-- +MT_SB L1_GETS 0 <-- +MT_SB L1_GETX 0 <-- +MT_SB L1_UPGRADE 0 <-- +MT_SB L1_PUTX 0 <-- +MT_SB L1_PUTX_old 0 <-- +MT_SB L2_Replacement 0 <-- +MT_SB L2_Replacement_clean 0 <-- +MT_SB Unblock 0 <-- +MT_SB MEM_Inv 0 <-- + +Memory controller: system.ruby.network.topology.ext_links2.ext_node.memBuffer: + memory_total_requests: 1737 + memory_reads: 1460 + memory_writes: 277 + memory_refreshes: 574 + memory_total_request_delays: 1092 + memory_delays_per_request: 0.62867 + memory_delays_in_input_queue: 133 + memory_delays_behind_head_of_bank_queue: 0 + memory_delays_stalled_at_head_of_bank_queue: 959 + memory_stalls_for_bank_busy: 199 + memory_stalls_for_random_busy: 0 + memory_stalls_for_anti_starvation: 0 + memory_stalls_for_arbitration: 32 + memory_stalls_for_bus: 236 + memory_stalls_for_tfaw: 0 + memory_stalls_for_read_write_turnaround: 492 + memory_stalls_for_read_read_turnaround: 0 + accesses_per_bank: 92 21 45 54 57 174 48 18 19 22 35 37 56 59 44 36 41 24 22 28 32 48 122 36 32 25 35 96 114 185 19 61 + + --- Directory 0 --- + - Event Counts - +Fetch 1460 +Data 277 +Memory_Data 1460 +Memory_Ack 277 +DMA_READ 0 +DMA_WRITE 0 +CleanReplacement 1175 + + - Transitions - +I Fetch 1460 +I DMA_READ 0 <-- +I DMA_WRITE 0 <-- + +ID Fetch 0 <-- +ID Data 0 <-- +ID Memory_Data 0 <-- +ID DMA_READ 0 <-- +ID DMA_WRITE 0 <-- + +ID_W Fetch 0 <-- +ID_W Data 0 <-- +ID_W Memory_Ack 0 <-- +ID_W DMA_READ 0 <-- +ID_W DMA_WRITE 0 <-- + +M Data 277 +M DMA_READ 0 <-- +M DMA_WRITE 0 <-- +M CleanReplacement 1175 + +IM Fetch 0 <-- +IM Data 0 <-- +IM Memory_Data 1460 +IM DMA_READ 0 <-- +IM DMA_WRITE 0 <-- + +MI Fetch 0 <-- +MI Data 0 <-- +MI Memory_Ack 277 +MI DMA_READ 0 <-- +MI DMA_WRITE 0 <-- + +M_DRD Data 0 <-- +M_DRD DMA_READ 0 <-- +M_DRD DMA_WRITE 0 <-- + +M_DRDI Fetch 0 <-- +M_DRDI Data 0 <-- +M_DRDI Memory_Ack 0 <-- +M_DRDI DMA_READ 0 <-- +M_DRDI DMA_WRITE 0 <-- + +M_DWR Data 0 <-- +M_DWR DMA_READ 0 <-- +M_DWR DMA_WRITE 0 <-- + +M_DWRI Fetch 0 <-- +M_DWRI Data 0 <-- +M_DWRI Memory_Ack 0 <-- +M_DWRI DMA_READ 0 <-- +M_DWRI DMA_WRITE 0 <-- + |