diff options
Diffstat (limited to 'tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory')
4 files changed, 1307 insertions, 1298 deletions
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/config.ini b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/config.ini index aceab6a24..756bebd28 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/config.ini +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/config.ini @@ -5,7 +5,7 @@ dummy=0 [system] type=System -children=cpu physmem ruby +children=cpu dir_cntrl0 l1_cntrl0 l2_cntrl0 physmem ruby mem_mode=timing physmem=system.physmem @@ -32,8 +32,8 @@ progress_interval=0 system=system tracer=system.cpu.tracer workload=system.cpu.workload -dcache_port=system.ruby.network.topology.ext_links0.ext_node.sequencer.port[1] -icache_port=system.ruby.network.topology.ext_links0.ext_node.sequencer.port[0] +dcache_port=system.l1_cntrl0.sequencer.port[1] +icache_port=system.l1_cntrl0.sequencer.port[0] [system.cpu.dtb] type=AlphaTLB @@ -54,7 +54,7 @@ egid=100 env= errout=cerr euid=100 -executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/alpha/linux/hello +executable=tests/test-progs/hello/bin/alpha/linux/hello gid=100 input=cin max_stack_size=67108864 @@ -65,6 +65,110 @@ simpoint=0 system=system uid=100 +[system.dir_cntrl0] +type=Directory_Controller +children=directory memBuffer +buffer_size=0 +directory=system.dir_cntrl0.directory +directory_latency=6 +memBuffer=system.dir_cntrl0.memBuffer +number_of_TBEs=256 +recycle_latency=10 +transitions_per_cycle=32 +version=0 + +[system.dir_cntrl0.directory] +type=RubyDirectoryMemory +map_levels=4 +numa_high_bit=6 +size=134217728 +use_map=false +version=0 + +[system.dir_cntrl0.memBuffer] +type=RubyMemoryControl +bank_bit_0=8 +bank_busy_time=11 +bank_queue_size=12 +banks_per_rank=8 +basic_bus_busy_time=2 +dimm_bit_0=12 +dimms_per_channel=2 +mem_bus_cycle_multiplier=10 +mem_ctl_latency=12 +mem_fixed_delay=0 +mem_random_arbitrate=0 +rank_bit_0=11 +rank_rank_delay=1 +ranks_per_dimm=2 +read_write_delay=2 +refresh_period=1560 +tFaw=0 +version=0 + +[system.l1_cntrl0] +type=L1Cache_Controller +children=sequencer +L1DcacheMemory=system.l1_cntrl0.sequencer.dcache +L1IcacheMemory=system.l1_cntrl0.sequencer.icache +buffer_size=0 +l2_select_num_bits=0 +number_of_TBEs=256 +recycle_latency=10 +request_latency=2 +sequencer=system.l1_cntrl0.sequencer +transitions_per_cycle=32 +version=0 + +[system.l1_cntrl0.sequencer] +type=RubySequencer +children=dcache icache +dcache=system.l1_cntrl0.sequencer.dcache +deadlock_threshold=500000 +icache=system.l1_cntrl0.sequencer.icache +max_outstanding_requests=16 +physmem=system.physmem +using_ruby_tester=false +version=0 +physMemPort=system.physmem.port[0] +port=system.cpu.icache_port system.cpu.dcache_port + +[system.l1_cntrl0.sequencer.dcache] +type=RubyCache +assoc=2 +latency=3 +replacement_policy=PSEUDO_LRU +size=256 +start_index_bit=6 + +[system.l1_cntrl0.sequencer.icache] +type=RubyCache +assoc=2 +latency=3 +replacement_policy=PSEUDO_LRU +size=256 +start_index_bit=6 + +[system.l2_cntrl0] +type=L2Cache_Controller +children=L2cacheMemory +L2cacheMemory=system.l2_cntrl0.L2cacheMemory +buffer_size=0 +number_of_TBEs=256 +recycle_latency=10 +request_latency=2 +response_latency=2 +transitions_per_cycle=32 +version=0 + +[system.l2_cntrl0.L2cacheMemory] +type=RubyCache +assoc=2 +latency=15 +replacement_policy=PSEUDO_LRU +size=512 +start_index_bit=6 + [system.physmem] type=PhysicalMemory file= @@ -73,7 +177,7 @@ latency_var=0 null=false range=0:134217727 zero=false -port=system.ruby.network.topology.ext_links0.ext_node.sequencer.physMemPort +port=system.l1_cntrl0.sequencer.physMemPort [system.ruby] type=RubySystem @@ -83,6 +187,7 @@ clock=1 debug=system.ruby.debug mem_size=134217728 network=system.ruby.network +no_mem_vec=false profiler=system.ruby.profiler random_seed=1234 randomization=false @@ -100,7 +205,7 @@ verbosity_string=none [system.ruby.network] type=SimpleNetwork children=topology -adaptive_routing=true +adaptive_routing=false buffer_size=0 control_msg_size=8 endpoint_bandwidth=10000 @@ -113,134 +218,34 @@ type=Topology children=ext_links0 ext_links1 ext_links2 int_links0 int_links1 int_links2 ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1 system.ruby.network.topology.ext_links2 int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1 system.ruby.network.topology.int_links2 +name=Crossbar num_int_nodes=4 print_config=false [system.ruby.network.topology.ext_links0] type=ExtLink -children=ext_node bw_multiplier=64 -ext_node=system.ruby.network.topology.ext_links0.ext_node +ext_node=system.l1_cntrl0 int_node=0 latency=1 weight=1 -[system.ruby.network.topology.ext_links0.ext_node] -type=L1Cache_Controller -children=sequencer -L1DcacheMemory=system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache -L1IcacheMemory=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache -buffer_size=0 -l2_select_num_bits=0 -number_of_TBEs=256 -recycle_latency=10 -request_latency=2 -sequencer=system.ruby.network.topology.ext_links0.ext_node.sequencer -transitions_per_cycle=32 -version=0 - -[system.ruby.network.topology.ext_links0.ext_node.sequencer] -type=RubySequencer -children=dcache icache -dcache=system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache -deadlock_threshold=500000 -icache=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache -max_outstanding_requests=16 -physmem=system.physmem -using_ruby_tester=false -version=0 -physMemPort=system.physmem.port[0] -port=system.cpu.icache_port system.cpu.dcache_port - -[system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache] -type=RubyCache -assoc=2 -latency=3 -replacement_policy=PSEUDO_LRU -size=256 - -[system.ruby.network.topology.ext_links0.ext_node.sequencer.icache] -type=RubyCache -assoc=2 -latency=3 -replacement_policy=PSEUDO_LRU -size=256 - [system.ruby.network.topology.ext_links1] type=ExtLink -children=ext_node bw_multiplier=64 -ext_node=system.ruby.network.topology.ext_links1.ext_node +ext_node=system.l2_cntrl0 int_node=1 latency=1 weight=1 -[system.ruby.network.topology.ext_links1.ext_node] -type=L2Cache_Controller -children=L2cacheMemory -L2cacheMemory=system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory -buffer_size=0 -number_of_TBEs=256 -recycle_latency=10 -request_latency=2 -response_latency=2 -transitions_per_cycle=32 -version=0 - -[system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory] -type=RubyCache -assoc=2 -latency=15 -replacement_policy=PSEUDO_LRU -size=512 - [system.ruby.network.topology.ext_links2] type=ExtLink -children=ext_node bw_multiplier=64 -ext_node=system.ruby.network.topology.ext_links2.ext_node +ext_node=system.dir_cntrl0 int_node=2 latency=1 weight=1 -[system.ruby.network.topology.ext_links2.ext_node] -type=Directory_Controller -children=directory memBuffer -buffer_size=0 -directory=system.ruby.network.topology.ext_links2.ext_node.directory -directory_latency=6 -memBuffer=system.ruby.network.topology.ext_links2.ext_node.memBuffer -number_of_TBEs=256 -recycle_latency=10 -transitions_per_cycle=32 -version=0 - -[system.ruby.network.topology.ext_links2.ext_node.directory] -type=RubyDirectoryMemory -size=134217728 -version=0 - -[system.ruby.network.topology.ext_links2.ext_node.memBuffer] -type=RubyMemoryControl -bank_bit_0=8 -bank_busy_time=11 -bank_queue_size=12 -banks_per_rank=8 -basic_bus_busy_time=2 -dimm_bit_0=12 -dimms_per_channel=2 -mem_bus_cycle_multiplier=10 -mem_ctl_latency=12 -mem_fixed_delay=0 -mem_random_arbitrate=0 -rank_bit_0=11 -rank_rank_delay=1 -ranks_per_dimm=2 -read_write_delay=2 -refresh_period=1560 -tFaw=0 -version=0 - [system.ruby.network.topology.int_links0] type=IntLink bw_multiplier=16 diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/ruby.stats b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/ruby.stats index 89d0c3194..c3c1c36bf 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/ruby.stats +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/ruby.stats @@ -13,7 +13,7 @@ RubySystem config: Network Configuration --------------------- network: SIMPLE_NETWORK -topology: +topology: Crossbar virtual_net_0: active, unordered virtual_net_1: active, unordered @@ -34,40 +34,29 @@ periodic_stats_period: 1000000 ================ End RubySystem Configuration Print ================ -Real time: Jan/28/2010 15:08:14 +Real time: Aug/05/2010 10:35:39 Profiler Stats -------------- -Elapsed_time_in_seconds: 1 -Elapsed_time_in_minutes: 0.0166667 -Elapsed_time_in_hours: 0.000277778 -Elapsed_time_in_days: 1.15741e-05 +Elapsed_time_in_seconds: 0 +Elapsed_time_in_minutes: 0 +Elapsed_time_in_hours: 0 +Elapsed_time_in_days: 0 -Virtual_time_in_seconds: 0.8 -Virtual_time_in_minutes: 0.0133333 -Virtual_time_in_hours: 0.000222222 -Virtual_time_in_days: 9.25926e-06 +Virtual_time_in_seconds: 0.44 +Virtual_time_in_minutes: 0.00733333 +Virtual_time_in_hours: 0.000122222 +Virtual_time_in_days: 5.09259e-06 Ruby_current_time: 223854 Ruby_start_time: 0 Ruby_cycles: 223854 -mbytes_resident: 34.6055 -mbytes_total: 34.6133 +mbytes_resident: 34.9609 +mbytes_total: 34.9688 resident_ratio: 1 -Total_misses: 0 -total_misses: 0 [ 0 ] -user_misses: 0 [ 0 ] -supervisor_misses: 0 [ 0 ] - -ruby_cycles_executed: 223855 [ 223855 ] - -transactions_started: 0 [ 0 ] -transactions_ended: 0 [ 0 ] -cycles_per_transaction: 0 [ 0 ] -misses_per_transaction: 0 [ 0 ] - +ruby_cycles_executed: [ 223855 ] Busy Controller Counts: L2Cache-0:0 @@ -82,9 +71,23 @@ sequencer_requests_outstanding: [binsize: 1 max: 1 count: 8465 average: 1 | All Non-Zero Cycle Demand Cache Accesses ---------------------------------------- miss_latency: [binsize: 2 max: 276 count: 8464 average: 25.4478 | standard deviation: 56.39 | 0 7102 0 0 0 0 0 0 0 188 60 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 251 197 238 187 165 13 4 20 3 7 5 4 3 3 1 0 1 1 1 0 0 1 0 1 0 0 0 3 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_1: [binsize: 2 max: 276 count: 6414 average: 17.9724 | standard deviation: 47.359 | 0 5768 0 0 0 0 0 0 0 76 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 153 110 113 93 66 5 3 16 1 3 0 1 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 2 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_2: [binsize: 2 max: 259 count: 1185 average: 62.838 | standard deviation: 78.9565 | 0 660 0 0 0 0 0 0 0 112 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 98 55 84 84 63 2 1 3 2 3 5 3 2 2 0 0 1 0 1 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_3: [binsize: 2 max: 227 count: 865 average: 29.6555 | standard deviation: 60.051 | 0 674 0 0 0 0 0 0 0 0 60 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 32 41 10 36 6 0 1 0 1 0 0 1 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_IFETCH: [binsize: 2 max: 276 count: 6414 average: 17.9724 | standard deviation: 47.359 | 0 5768 0 0 0 0 0 0 0 76 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 153 110 113 93 66 5 3 16 1 3 0 1 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 2 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_LD: [binsize: 2 max: 259 count: 1185 average: 62.838 | standard deviation: 78.9565 | 0 660 0 0 0 0 0 0 0 112 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 98 55 84 84 63 2 1 3 2 3 5 3 2 2 0 0 1 0 1 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_ST: [binsize: 2 max: 227 count: 865 average: 29.6555 | standard deviation: 60.051 | 0 674 0 0 0 0 0 0 0 0 60 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 32 41 10 36 6 0 1 0 1 0 0 1 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_NULL: [binsize: 2 max: 276 count: 8464 average: 25.4478 | standard deviation: 56.39 | 0 7102 0 0 0 0 0 0 0 188 60 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 251 197 238 187 165 13 4 20 3 7 5 4 3 3 1 0 1 1 1 0 0 1 0 1 0 0 0 3 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_wCC_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +imcomplete_wCC_Times: 0 +miss_latency_dir_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_dir_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_dir_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_dir_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +imcomplete_dir_Times: 0 +miss_latency_IFETCH_NULL: [binsize: 2 max: 276 count: 6414 average: 17.9724 | standard deviation: 47.359 | 0 5768 0 0 0 0 0 0 0 76 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 153 110 113 93 66 5 3 16 1 3 0 1 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 2 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_LD_NULL: [binsize: 2 max: 259 count: 1185 average: 62.838 | standard deviation: 78.9565 | 0 660 0 0 0 0 0 0 0 112 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 98 55 84 84 63 2 1 3 2 3 5 3 2 2 0 0 1 0 1 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_ST_NULL: [binsize: 2 max: 227 count: 865 average: 29.6555 | standard deviation: 60.051 | 0 674 0 0 0 0 0 0 0 0 60 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 32 41 10 36 6 0 1 0 1 0 0 1 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] All Non-Zero Cycle SW Prefetch Requests ------------------------------------ @@ -116,8 +119,8 @@ Resource Usage page_size: 4096 user_time: 0 system_time: 0 -page_reclaims: 7397 -page_faults: 2249 +page_reclaims: 7630 +page_faults: 2184 swaps: 0 block_inputs: 0 block_outputs: 0 @@ -125,6 +128,14 @@ block_outputs: 0 Network Stats ------------- +total_msg_count_Request_Control: 7428 59424 +total_msg_count_Response_Data: 6684 481248 +total_msg_count_ResponseL2hit_Data: 744 53568 +total_msg_count_Writeback_Data: 4644 334368 +total_msg_count_Writeback_Control: 17424 139392 +total_msg_count_Unblock_Control: 7428 59424 +total_msgs: 44352 total_bytes: 1127424 + switch_0_inlinks: 2 switch_0_outlinks: 2 links_utilized_percent_switch_0: 0.219641 @@ -190,972 +201,966 @@ links_utilized_percent_switch_3: 0.349752 outgoing_messages_switch_3_link_2_Writeback_Control: 2002 16016 [ 0 1098 904 0 0 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_3_link_2_Unblock_Control: 1114 8912 [ 0 0 1114 0 0 0 0 0 0 0 ] base_latency: 1 -Cache Stats: system.ruby.network.topology.ext_links0.ext_node.sequencer.icache - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_misses: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_demand_misses: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_hw_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_misses_per_transaction: nan +Cache Stats: system.l1_cntrl0.sequencer.icache + system.l1_cntrl0.sequencer.icache_total_misses: 0 + system.l1_cntrl0.sequencer.icache_total_demand_misses: 0 + system.l1_cntrl0.sequencer.icache_total_prefetches: 0 + system.l1_cntrl0.sequencer.icache_total_sw_prefetches: 0 + system.l1_cntrl0.sequencer.icache_total_hw_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] -Cache Stats: system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_misses: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_demand_misses: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_hw_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_misses_per_transaction: nan +Cache Stats: system.l1_cntrl0.sequencer.dcache + system.l1_cntrl0.sequencer.dcache_total_misses: 0 + system.l1_cntrl0.sequencer.dcache_total_demand_misses: 0 + system.l1_cntrl0.sequencer.dcache_total_prefetches: 0 + system.l1_cntrl0.sequencer.dcache_total_sw_prefetches: 0 + system.l1_cntrl0.sequencer.dcache_total_hw_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - --- L1Cache 0 --- + --- L1Cache --- - Event Counts - -Load 1185 -Ifetch 6414 -Store 865 -L1_Replacement 1379 -Own_GETX 0 -Fwd_GETX 0 -Fwd_GETS 0 -Fwd_DMA 0 -Inv 0 -Ack 0 -Data 0 -Exclusive_Data 1362 -Writeback_Ack 0 -Writeback_Ack_Data 1354 -Writeback_Nack 0 -All_acks 191 -Use_Timeout 1361 +Load [1185 ] 1185 +Ifetch [6414 ] 6414 +Store [865 ] 865 +L1_Replacement [1379 ] 1379 +Own_GETX [0 ] 0 +Fwd_GETX [0 ] 0 +Fwd_GETS [0 ] 0 +Fwd_DMA [0 ] 0 +Inv [0 ] 0 +Ack [0 ] 0 +Data [0 ] 0 +Exclusive_Data [1362 ] 1362 +Writeback_Ack [0 ] 0 +Writeback_Ack_Data [1354 ] 1354 +Writeback_Nack [0 ] 0 +All_acks [191 ] 191 +Use_Timeout [1361 ] 1361 - Transitions - -I Load 525 -I Ifetch 646 -I Store 191 -I L1_Replacement 0 <-- -I Inv 0 <-- - -S Load 0 <-- -S Ifetch 0 <-- -S Store 0 <-- -S L1_Replacement 0 <-- -S Fwd_GETS 0 <-- -S Fwd_DMA 0 <-- -S Inv 0 <-- - -O Load 0 <-- -O Ifetch 0 <-- -O Store 0 <-- -O L1_Replacement 0 <-- -O Fwd_GETX 0 <-- -O Fwd_GETS 0 <-- -O Fwd_DMA 0 <-- - -M Load 308 -M Ifetch 3484 -M Store 51 -M L1_Replacement 1086 -M Fwd_GETX 0 <-- -M Fwd_GETS 0 <-- -M Fwd_DMA 0 <-- - -M_W Load 111 -M_W Ifetch 2284 -M_W Store 27 -M_W L1_Replacement 17 -M_W Own_GETX 0 <-- -M_W Fwd_GETX 0 <-- -M_W Fwd_GETS 0 <-- -M_W Fwd_DMA 0 <-- -M_W Inv 0 <-- -M_W Use_Timeout 1143 - -MM Load 234 -MM Ifetch 0 <-- -MM Store 339 -MM L1_Replacement 268 -MM Fwd_GETX 0 <-- -MM Fwd_GETS 0 <-- -MM Fwd_DMA 0 <-- - -MM_W Load 7 -MM_W Ifetch 0 <-- -MM_W Store 257 -MM_W L1_Replacement 8 -MM_W Own_GETX 0 <-- -MM_W Fwd_GETX 0 <-- -MM_W Fwd_GETS 0 <-- -MM_W Fwd_DMA 0 <-- -MM_W Inv 0 <-- -MM_W Use_Timeout 218 - -IM Load 0 <-- -IM Ifetch 0 <-- -IM Store 0 <-- -IM L1_Replacement 0 <-- -IM Inv 0 <-- -IM Ack 0 <-- -IM Data 0 <-- -IM Exclusive_Data 191 - -SM Load 0 <-- -SM Ifetch 0 <-- -SM Store 0 <-- -SM L1_Replacement 0 <-- -SM Fwd_GETS 0 <-- -SM Fwd_DMA 0 <-- -SM Inv 0 <-- -SM Ack 0 <-- -SM Data 0 <-- -SM Exclusive_Data 0 <-- - -OM Load 0 <-- -OM Ifetch 0 <-- -OM Store 0 <-- -OM L1_Replacement 0 <-- -OM Own_GETX 0 <-- -OM Fwd_GETX 0 <-- -OM Fwd_GETS 0 <-- -OM Fwd_DMA 0 <-- -OM Ack 0 <-- -OM All_acks 191 - -IS Load 0 <-- -IS Ifetch 0 <-- -IS Store 0 <-- -IS L1_Replacement 0 <-- -IS Inv 0 <-- -IS Data 0 <-- -IS Exclusive_Data 1171 - -SI Load 0 <-- -SI Ifetch 0 <-- -SI Store 0 <-- -SI L1_Replacement 0 <-- -SI Fwd_GETS 0 <-- -SI Fwd_DMA 0 <-- -SI Inv 0 <-- -SI Writeback_Ack 0 <-- -SI Writeback_Ack_Data 0 <-- -SI Writeback_Nack 0 <-- - -OI Load 0 <-- -OI Ifetch 0 <-- -OI Store 0 <-- -OI L1_Replacement 0 <-- -OI Fwd_GETX 0 <-- -OI Fwd_GETS 0 <-- -OI Fwd_DMA 0 <-- -OI Writeback_Ack 0 <-- -OI Writeback_Ack_Data 0 <-- -OI Writeback_Nack 0 <-- - -MI Load 0 <-- -MI Ifetch 0 <-- -MI Store 0 <-- -MI L1_Replacement 0 <-- -MI Fwd_GETX 0 <-- -MI Fwd_GETS 0 <-- -MI Fwd_DMA 0 <-- -MI Writeback_Ack 0 <-- -MI Writeback_Ack_Data 1354 -MI Writeback_Nack 0 <-- - -II Load 0 <-- -II Ifetch 0 <-- -II Store 0 <-- -II L1_Replacement 0 <-- -II Inv 0 <-- -II Writeback_Ack 0 <-- -II Writeback_Ack_Data 0 <-- -II Writeback_Nack 0 <-- - -Cache Stats: system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory - system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_misses: 0 - system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_demand_misses: 0 - system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_prefetches: 0 - system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_hw_prefetches: 0 - system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_misses_per_transaction: nan - - system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - - --- L2Cache 0 --- +I Load [525 ] 525 +I Ifetch [646 ] 646 +I Store [191 ] 191 +I L1_Replacement [0 ] 0 +I Inv [0 ] 0 + +S Load [0 ] 0 +S Ifetch [0 ] 0 +S Store [0 ] 0 +S L1_Replacement [0 ] 0 +S Fwd_GETS [0 ] 0 +S Fwd_DMA [0 ] 0 +S Inv [0 ] 0 + +O Load [0 ] 0 +O Ifetch [0 ] 0 +O Store [0 ] 0 +O L1_Replacement [0 ] 0 +O Fwd_GETX [0 ] 0 +O Fwd_GETS [0 ] 0 +O Fwd_DMA [0 ] 0 + +M Load [308 ] 308 +M Ifetch [3484 ] 3484 +M Store [51 ] 51 +M L1_Replacement [1086 ] 1086 +M Fwd_GETX [0 ] 0 +M Fwd_GETS [0 ] 0 +M Fwd_DMA [0 ] 0 + +M_W Load [111 ] 111 +M_W Ifetch [2284 ] 2284 +M_W Store [27 ] 27 +M_W L1_Replacement [17 ] 17 +M_W Own_GETX [0 ] 0 +M_W Fwd_GETX [0 ] 0 +M_W Fwd_GETS [0 ] 0 +M_W Fwd_DMA [0 ] 0 +M_W Inv [0 ] 0 +M_W Use_Timeout [1143 ] 1143 + +MM Load [234 ] 234 +MM Ifetch [0 ] 0 +MM Store [339 ] 339 +MM L1_Replacement [268 ] 268 +MM Fwd_GETX [0 ] 0 +MM Fwd_GETS [0 ] 0 +MM Fwd_DMA [0 ] 0 + +MM_W Load [7 ] 7 +MM_W Ifetch [0 ] 0 +MM_W Store [257 ] 257 +MM_W L1_Replacement [8 ] 8 +MM_W Own_GETX [0 ] 0 +MM_W Fwd_GETX [0 ] 0 +MM_W Fwd_GETS [0 ] 0 +MM_W Fwd_DMA [0 ] 0 +MM_W Inv [0 ] 0 +MM_W Use_Timeout [218 ] 218 + +IM Load [0 ] 0 +IM Ifetch [0 ] 0 +IM Store [0 ] 0 +IM L1_Replacement [0 ] 0 +IM Inv [0 ] 0 +IM Ack [0 ] 0 +IM Data [0 ] 0 +IM Exclusive_Data [191 ] 191 + +SM Load [0 ] 0 +SM Ifetch [0 ] 0 +SM Store [0 ] 0 +SM L1_Replacement [0 ] 0 +SM Fwd_GETS [0 ] 0 +SM Fwd_DMA [0 ] 0 +SM Inv [0 ] 0 +SM Ack [0 ] 0 +SM Data [0 ] 0 +SM Exclusive_Data [0 ] 0 + +OM Load [0 ] 0 +OM Ifetch [0 ] 0 +OM Store [0 ] 0 +OM L1_Replacement [0 ] 0 +OM Own_GETX [0 ] 0 +OM Fwd_GETX [0 ] 0 +OM Fwd_GETS [0 ] 0 +OM Fwd_DMA [0 ] 0 +OM Ack [0 ] 0 +OM All_acks [191 ] 191 + +IS Load [0 ] 0 +IS Ifetch [0 ] 0 +IS Store [0 ] 0 +IS L1_Replacement [0 ] 0 +IS Inv [0 ] 0 +IS Data [0 ] 0 +IS Exclusive_Data [1171 ] 1171 + +SI Load [0 ] 0 +SI Ifetch [0 ] 0 +SI Store [0 ] 0 +SI L1_Replacement [0 ] 0 +SI Fwd_GETS [0 ] 0 +SI Fwd_DMA [0 ] 0 +SI Inv [0 ] 0 +SI Writeback_Ack [0 ] 0 +SI Writeback_Ack_Data [0 ] 0 +SI Writeback_Nack [0 ] 0 + +OI Load [0 ] 0 +OI Ifetch [0 ] 0 +OI Store [0 ] 0 +OI L1_Replacement [0 ] 0 +OI Fwd_GETX [0 ] 0 +OI Fwd_GETS [0 ] 0 +OI Fwd_DMA [0 ] 0 +OI Writeback_Ack [0 ] 0 +OI Writeback_Ack_Data [0 ] 0 +OI Writeback_Nack [0 ] 0 + +MI Load [0 ] 0 +MI Ifetch [0 ] 0 +MI Store [0 ] 0 +MI L1_Replacement [0 ] 0 +MI Fwd_GETX [0 ] 0 +MI Fwd_GETS [0 ] 0 +MI Fwd_DMA [0 ] 0 +MI Writeback_Ack [0 ] 0 +MI Writeback_Ack_Data [1354 ] 1354 +MI Writeback_Nack [0 ] 0 + +II Load [0 ] 0 +II Ifetch [0 ] 0 +II Store [0 ] 0 +II L1_Replacement [0 ] 0 +II Inv [0 ] 0 +II Writeback_Ack [0 ] 0 +II Writeback_Ack_Data [0 ] 0 +II Writeback_Nack [0 ] 0 + +Cache Stats: system.l2_cntrl0.L2cacheMemory + system.l2_cntrl0.L2cacheMemory_total_misses: 0 + system.l2_cntrl0.L2cacheMemory_total_demand_misses: 0 + system.l2_cntrl0.L2cacheMemory_total_prefetches: 0 + system.l2_cntrl0.L2cacheMemory_total_sw_prefetches: 0 + system.l2_cntrl0.L2cacheMemory_total_hw_prefetches: 0 + + + --- L2Cache --- - Event Counts - -L1_GETS 1171 -L1_GETX 191 -L1_PUTO 0 -L1_PUTX 1354 -L1_PUTS_only 0 -L1_PUTS 0 -Fwd_GETX 0 -Fwd_GETS 0 -Fwd_DMA 0 -Own_GETX 0 -Inv 0 -IntAck 0 -ExtAck 0 -All_Acks 131 -Data 131 -Data_Exclusive 983 -L1_WBCLEANDATA 1059 -L1_WBDIRTYDATA 295 -Writeback_Ack 1098 -Writeback_Nack 0 -Unblock 0 -Exclusive_Unblock 1362 -L2_Replacement 1098 +L1_GETS [1171 ] 1171 +L1_GETX [191 ] 191 +L1_PUTO [0 ] 0 +L1_PUTX [1354 ] 1354 +L1_PUTS_only [0 ] 0 +L1_PUTS [0 ] 0 +Fwd_GETX [0 ] 0 +Fwd_GETS [0 ] 0 +Fwd_DMA [0 ] 0 +Own_GETX [0 ] 0 +Inv [0 ] 0 +IntAck [0 ] 0 +ExtAck [0 ] 0 +All_Acks [131 ] 131 +Data [131 ] 131 +Data_Exclusive [983 ] 983 +L1_WBCLEANDATA [1059 ] 1059 +L1_WBDIRTYDATA [295 ] 295 +Writeback_Ack [1098 ] 1098 +Writeback_Nack [0 ] 0 +Unblock [0 ] 0 +Exclusive_Unblock [1362 ] 1362 +L2_Replacement [1098 ] 1098 - Transitions - -NP L1_GETS 983 -NP L1_GETX 131 -NP L1_PUTO 0 <-- -NP L1_PUTX 0 <-- -NP L1_PUTS 0 <-- -NP Inv 0 <-- - -I L1_GETS 0 <-- -I L1_GETX 0 <-- -I L1_PUTO 0 <-- -I L1_PUTX 0 <-- -I L1_PUTS 0 <-- -I Inv 0 <-- -I L2_Replacement 0 <-- - -ILS L1_GETS 0 <-- -ILS L1_GETX 0 <-- -ILS L1_PUTO 0 <-- -ILS L1_PUTX 0 <-- -ILS L1_PUTS_only 0 <-- -ILS L1_PUTS 0 <-- -ILS Inv 0 <-- -ILS L2_Replacement 0 <-- - -ILX L1_GETS 0 <-- -ILX L1_GETX 0 <-- -ILX L1_PUTO 0 <-- -ILX L1_PUTX 1354 -ILX L1_PUTS_only 0 <-- -ILX L1_PUTS 0 <-- -ILX Fwd_GETX 0 <-- -ILX Fwd_GETS 0 <-- -ILX Fwd_DMA 0 <-- -ILX Inv 0 <-- -ILX Data 0 <-- -ILX L2_Replacement 0 <-- - -ILO L1_GETS 0 <-- -ILO L1_GETX 0 <-- -ILO L1_PUTO 0 <-- -ILO L1_PUTX 0 <-- -ILO L1_PUTS 0 <-- -ILO Fwd_GETX 0 <-- -ILO Fwd_GETS 0 <-- -ILO Fwd_DMA 0 <-- -ILO Inv 0 <-- -ILO Data 0 <-- -ILO L2_Replacement 0 <-- - -ILOX L1_GETS 0 <-- -ILOX L1_GETX 0 <-- -ILOX L1_PUTO 0 <-- -ILOX L1_PUTX 0 <-- -ILOX L1_PUTS 0 <-- -ILOX Fwd_GETX 0 <-- -ILOX Fwd_GETS 0 <-- -ILOX Fwd_DMA 0 <-- -ILOX Data 0 <-- - -ILOS L1_GETS 0 <-- -ILOS L1_GETX 0 <-- -ILOS L1_PUTO 0 <-- -ILOS L1_PUTX 0 <-- -ILOS L1_PUTS_only 0 <-- -ILOS L1_PUTS 0 <-- -ILOS Fwd_GETX 0 <-- -ILOS Fwd_GETS 0 <-- -ILOS Fwd_DMA 0 <-- -ILOS Data 0 <-- -ILOS L2_Replacement 0 <-- - -ILOSX L1_GETS 0 <-- -ILOSX L1_GETX 0 <-- -ILOSX L1_PUTO 0 <-- -ILOSX L1_PUTX 0 <-- -ILOSX L1_PUTS_only 0 <-- -ILOSX L1_PUTS 0 <-- -ILOSX Fwd_GETX 0 <-- -ILOSX Fwd_GETS 0 <-- -ILOSX Fwd_DMA 0 <-- -ILOSX Data 0 <-- - -S L1_GETS 0 <-- -S L1_GETX 0 <-- -S L1_PUTX 0 <-- -S L1_PUTS 0 <-- -S Inv 0 <-- -S L2_Replacement 0 <-- - -O L1_GETS 0 <-- -O L1_GETX 0 <-- -O L1_PUTX 0 <-- -O Fwd_GETX 0 <-- -O Fwd_GETS 0 <-- -O Fwd_DMA 0 <-- -O L2_Replacement 0 <-- - -OLS L1_GETS 0 <-- -OLS L1_GETX 0 <-- -OLS L1_PUTX 0 <-- -OLS L1_PUTS_only 0 <-- -OLS L1_PUTS 0 <-- -OLS Fwd_GETX 0 <-- -OLS Fwd_GETS 0 <-- -OLS Fwd_DMA 0 <-- -OLS L2_Replacement 0 <-- - -OLSX L1_GETS 0 <-- -OLSX L1_GETX 0 <-- -OLSX L1_PUTO 0 <-- -OLSX L1_PUTX 0 <-- -OLSX L1_PUTS_only 0 <-- -OLSX L1_PUTS 0 <-- -OLSX Fwd_GETX 0 <-- -OLSX Fwd_GETS 0 <-- -OLSX Fwd_DMA 0 <-- -OLSX L2_Replacement 0 <-- - -SLS L1_GETS 0 <-- -SLS L1_GETX 0 <-- -SLS L1_PUTX 0 <-- -SLS L1_PUTS_only 0 <-- -SLS L1_PUTS 0 <-- -SLS Inv 0 <-- -SLS L2_Replacement 0 <-- - -M L1_GETS 188 -M L1_GETX 60 -M L1_PUTO 0 <-- -M L1_PUTX 0 <-- -M L1_PUTS 0 <-- -M Fwd_GETX 0 <-- -M Fwd_GETS 0 <-- -M Fwd_DMA 0 <-- -M L2_Replacement 1098 - -IFGX L1_GETS 0 <-- -IFGX L1_GETX 0 <-- -IFGX L1_PUTO 0 <-- -IFGX L1_PUTX 0 <-- -IFGX L1_PUTS_only 0 <-- -IFGX L1_PUTS 0 <-- -IFGX Fwd_GETX 0 <-- -IFGX Fwd_GETS 0 <-- -IFGX Fwd_DMA 0 <-- -IFGX Inv 0 <-- -IFGX Data 0 <-- -IFGX Data_Exclusive 0 <-- -IFGX L2_Replacement 0 <-- - -IFGS L1_GETS 0 <-- -IFGS L1_GETX 0 <-- -IFGS L1_PUTO 0 <-- -IFGS L1_PUTX 0 <-- -IFGS L1_PUTS_only 0 <-- -IFGS L1_PUTS 0 <-- -IFGS Fwd_GETX 0 <-- -IFGS Fwd_GETS 0 <-- -IFGS Fwd_DMA 0 <-- -IFGS Inv 0 <-- -IFGS Data 0 <-- -IFGS Data_Exclusive 0 <-- -IFGS L2_Replacement 0 <-- - -ISFGS L1_GETS 0 <-- -ISFGS L1_GETX 0 <-- -ISFGS L1_PUTO 0 <-- -ISFGS L1_PUTX 0 <-- -ISFGS L1_PUTS_only 0 <-- -ISFGS L1_PUTS 0 <-- -ISFGS Fwd_GETX 0 <-- -ISFGS Fwd_GETS 0 <-- -ISFGS Fwd_DMA 0 <-- -ISFGS Inv 0 <-- -ISFGS Data 0 <-- -ISFGS L2_Replacement 0 <-- - -IFGXX L1_GETS 0 <-- -IFGXX L1_GETX 0 <-- -IFGXX L1_PUTO 0 <-- -IFGXX L1_PUTX 0 <-- -IFGXX L1_PUTS_only 0 <-- -IFGXX L1_PUTS 0 <-- -IFGXX Fwd_GETX 0 <-- -IFGXX Fwd_GETS 0 <-- -IFGXX Fwd_DMA 0 <-- -IFGXX Inv 0 <-- -IFGXX IntAck 0 <-- -IFGXX All_Acks 0 <-- -IFGXX Data_Exclusive 0 <-- -IFGXX L2_Replacement 0 <-- - -OFGX L1_GETS 0 <-- -OFGX L1_GETX 0 <-- -OFGX L1_PUTO 0 <-- -OFGX L1_PUTX 0 <-- -OFGX L1_PUTS_only 0 <-- -OFGX L1_PUTS 0 <-- -OFGX Fwd_GETX 0 <-- -OFGX Fwd_GETS 0 <-- -OFGX Fwd_DMA 0 <-- -OFGX Inv 0 <-- -OFGX L2_Replacement 0 <-- - -OLSF L1_GETS 0 <-- -OLSF L1_GETX 0 <-- -OLSF L1_PUTO 0 <-- -OLSF L1_PUTX 0 <-- -OLSF L1_PUTS_only 0 <-- -OLSF L1_PUTS 0 <-- -OLSF Fwd_GETX 0 <-- -OLSF Fwd_GETS 0 <-- -OLSF Fwd_DMA 0 <-- -OLSF Inv 0 <-- -OLSF IntAck 0 <-- -OLSF All_Acks 0 <-- -OLSF L2_Replacement 0 <-- - -ILOW L1_GETS 0 <-- -ILOW L1_GETX 0 <-- -ILOW L1_PUTO 0 <-- -ILOW L1_PUTX 0 <-- -ILOW L1_PUTS_only 0 <-- -ILOW L1_PUTS 0 <-- -ILOW Fwd_GETX 0 <-- -ILOW Fwd_GETS 0 <-- -ILOW Fwd_DMA 0 <-- -ILOW Inv 0 <-- -ILOW L1_WBCLEANDATA 0 <-- -ILOW L1_WBDIRTYDATA 0 <-- -ILOW Unblock 0 <-- -ILOW L2_Replacement 0 <-- - -ILOXW L1_GETS 0 <-- -ILOXW L1_GETX 0 <-- -ILOXW L1_PUTO 0 <-- -ILOXW L1_PUTX 0 <-- -ILOXW L1_PUTS_only 0 <-- -ILOXW L1_PUTS 0 <-- -ILOXW Fwd_GETX 0 <-- -ILOXW Fwd_GETS 0 <-- -ILOXW Fwd_DMA 0 <-- -ILOXW Inv 0 <-- -ILOXW L1_WBCLEANDATA 0 <-- -ILOXW L1_WBDIRTYDATA 0 <-- -ILOXW Unblock 0 <-- -ILOXW L2_Replacement 0 <-- - -ILOSW L1_GETS 0 <-- -ILOSW L1_GETX 0 <-- -ILOSW L1_PUTO 0 <-- -ILOSW L1_PUTX 0 <-- -ILOSW L1_PUTS_only 0 <-- -ILOSW L1_PUTS 0 <-- -ILOSW Fwd_GETX 0 <-- -ILOSW Fwd_GETS 0 <-- -ILOSW Fwd_DMA 0 <-- -ILOSW Inv 0 <-- -ILOSW L1_WBCLEANDATA 0 <-- -ILOSW L1_WBDIRTYDATA 0 <-- -ILOSW Unblock 0 <-- -ILOSW L2_Replacement 0 <-- - -ILOSXW L1_GETS 0 <-- -ILOSXW L1_GETX 0 <-- -ILOSXW L1_PUTO 0 <-- -ILOSXW L1_PUTX 0 <-- -ILOSXW L1_PUTS_only 0 <-- -ILOSXW L1_PUTS 0 <-- -ILOSXW Fwd_GETX 0 <-- -ILOSXW Fwd_GETS 0 <-- -ILOSXW Fwd_DMA 0 <-- -ILOSXW Inv 0 <-- -ILOSXW L1_WBCLEANDATA 0 <-- -ILOSXW L1_WBDIRTYDATA 0 <-- -ILOSXW Unblock 0 <-- -ILOSXW L2_Replacement 0 <-- - -SLSW L1_GETS 0 <-- -SLSW L1_GETX 0 <-- -SLSW L1_PUTO 0 <-- -SLSW L1_PUTX 0 <-- -SLSW L1_PUTS_only 0 <-- -SLSW L1_PUTS 0 <-- -SLSW Fwd_GETX 0 <-- -SLSW Fwd_GETS 0 <-- -SLSW Fwd_DMA 0 <-- -SLSW Inv 0 <-- -SLSW Unblock 0 <-- -SLSW L2_Replacement 0 <-- - -OLSW L1_GETS 0 <-- -OLSW L1_GETX 0 <-- -OLSW L1_PUTO 0 <-- -OLSW L1_PUTX 0 <-- -OLSW L1_PUTS_only 0 <-- -OLSW L1_PUTS 0 <-- -OLSW Fwd_GETX 0 <-- -OLSW Fwd_GETS 0 <-- -OLSW Fwd_DMA 0 <-- -OLSW Inv 0 <-- -OLSW Unblock 0 <-- -OLSW L2_Replacement 0 <-- - -ILSW L1_GETS 0 <-- -ILSW L1_GETX 0 <-- -ILSW L1_PUTO 0 <-- -ILSW L1_PUTX 0 <-- -ILSW L1_PUTS_only 0 <-- -ILSW L1_PUTS 0 <-- -ILSW Fwd_GETX 0 <-- -ILSW Fwd_GETS 0 <-- -ILSW Fwd_DMA 0 <-- -ILSW Inv 0 <-- -ILSW L1_WBCLEANDATA 0 <-- -ILSW Unblock 0 <-- -ILSW L2_Replacement 0 <-- - -IW L1_GETS 0 <-- -IW L1_GETX 0 <-- -IW L1_PUTO 0 <-- -IW L1_PUTX 0 <-- -IW L1_PUTS_only 0 <-- -IW L1_PUTS 0 <-- -IW Fwd_GETX 0 <-- -IW Fwd_GETS 0 <-- -IW Fwd_DMA 0 <-- -IW Inv 0 <-- -IW L1_WBCLEANDATA 0 <-- -IW L2_Replacement 0 <-- - -OW L1_GETS 0 <-- -OW L1_GETX 0 <-- -OW L1_PUTO 0 <-- -OW L1_PUTX 0 <-- -OW L1_PUTS_only 0 <-- -OW L1_PUTS 0 <-- -OW Fwd_GETX 0 <-- -OW Fwd_GETS 0 <-- -OW Fwd_DMA 0 <-- -OW Inv 0 <-- -OW Unblock 0 <-- -OW L2_Replacement 0 <-- - -SW L1_GETS 0 <-- -SW L1_GETX 0 <-- -SW L1_PUTO 0 <-- -SW L1_PUTX 0 <-- -SW L1_PUTS_only 0 <-- -SW L1_PUTS 0 <-- -SW Fwd_GETX 0 <-- -SW Fwd_GETS 0 <-- -SW Fwd_DMA 0 <-- -SW Inv 0 <-- -SW Unblock 0 <-- -SW L2_Replacement 0 <-- - -OXW L1_GETS 0 <-- -OXW L1_GETX 0 <-- -OXW L1_PUTO 0 <-- -OXW L1_PUTX 0 <-- -OXW L1_PUTS_only 0 <-- -OXW L1_PUTS 0 <-- -OXW Fwd_GETX 0 <-- -OXW Fwd_GETS 0 <-- -OXW Fwd_DMA 0 <-- -OXW Inv 0 <-- -OXW Unblock 0 <-- -OXW L2_Replacement 0 <-- - -OLSXW L1_GETS 0 <-- -OLSXW L1_GETX 0 <-- -OLSXW L1_PUTO 0 <-- -OLSXW L1_PUTX 0 <-- -OLSXW L1_PUTS_only 0 <-- -OLSXW L1_PUTS 0 <-- -OLSXW Fwd_GETX 0 <-- -OLSXW Fwd_GETS 0 <-- -OLSXW Fwd_DMA 0 <-- -OLSXW Inv 0 <-- -OLSXW Unblock 0 <-- -OLSXW L2_Replacement 0 <-- - -ILXW L1_GETS 0 <-- -ILXW L1_GETX 0 <-- -ILXW L1_PUTO 0 <-- -ILXW L1_PUTX 0 <-- -ILXW L1_PUTS_only 0 <-- -ILXW L1_PUTS 0 <-- -ILXW Fwd_GETX 0 <-- -ILXW Fwd_GETS 0 <-- -ILXW Fwd_DMA 0 <-- -ILXW Inv 0 <-- -ILXW Data 0 <-- -ILXW L1_WBCLEANDATA 1059 -ILXW L1_WBDIRTYDATA 295 -ILXW Unblock 0 <-- -ILXW L2_Replacement 0 <-- - -IFLS L1_GETS 0 <-- -IFLS L1_GETX 0 <-- -IFLS L1_PUTO 0 <-- -IFLS L1_PUTX 0 <-- -IFLS L1_PUTS_only 0 <-- -IFLS L1_PUTS 0 <-- -IFLS Fwd_GETX 0 <-- -IFLS Fwd_GETS 0 <-- -IFLS Fwd_DMA 0 <-- -IFLS Inv 0 <-- -IFLS Unblock 0 <-- -IFLS L2_Replacement 0 <-- - -IFLO L1_GETS 0 <-- -IFLO L1_GETX 0 <-- -IFLO L1_PUTO 0 <-- -IFLO L1_PUTX 0 <-- -IFLO L1_PUTS_only 0 <-- -IFLO L1_PUTS 0 <-- -IFLO Fwd_GETX 0 <-- -IFLO Fwd_GETS 0 <-- -IFLO Fwd_DMA 0 <-- -IFLO Inv 0 <-- -IFLO Unblock 0 <-- -IFLO L2_Replacement 0 <-- - -IFLOX L1_GETS 0 <-- -IFLOX L1_GETX 0 <-- -IFLOX L1_PUTO 0 <-- -IFLOX L1_PUTX 0 <-- -IFLOX L1_PUTS_only 0 <-- -IFLOX L1_PUTS 0 <-- -IFLOX Fwd_GETX 0 <-- -IFLOX Fwd_GETS 0 <-- -IFLOX Fwd_DMA 0 <-- -IFLOX Inv 0 <-- -IFLOX Unblock 0 <-- -IFLOX Exclusive_Unblock 0 <-- -IFLOX L2_Replacement 0 <-- - -IFLOXX L1_GETS 0 <-- -IFLOXX L1_GETX 0 <-- -IFLOXX L1_PUTO 0 <-- -IFLOXX L1_PUTX 0 <-- -IFLOXX L1_PUTS_only 0 <-- -IFLOXX L1_PUTS 0 <-- -IFLOXX Fwd_GETX 0 <-- -IFLOXX Fwd_GETS 0 <-- -IFLOXX Fwd_DMA 0 <-- -IFLOXX Inv 0 <-- -IFLOXX Unblock 0 <-- -IFLOXX Exclusive_Unblock 0 <-- -IFLOXX L2_Replacement 0 <-- - -IFLOSX L1_GETS 0 <-- -IFLOSX L1_GETX 0 <-- -IFLOSX L1_PUTO 0 <-- -IFLOSX L1_PUTX 0 <-- -IFLOSX L1_PUTS_only 0 <-- -IFLOSX L1_PUTS 0 <-- -IFLOSX Fwd_GETX 0 <-- -IFLOSX Fwd_GETS 0 <-- -IFLOSX Fwd_DMA 0 <-- -IFLOSX Inv 0 <-- -IFLOSX Unblock 0 <-- -IFLOSX Exclusive_Unblock 0 <-- -IFLOSX L2_Replacement 0 <-- - -IFLXO L1_GETS 0 <-- -IFLXO L1_GETX 0 <-- -IFLXO L1_PUTO 0 <-- -IFLXO L1_PUTX 0 <-- -IFLXO L1_PUTS_only 0 <-- -IFLXO L1_PUTS 0 <-- -IFLXO Fwd_GETX 0 <-- -IFLXO Fwd_GETS 0 <-- -IFLXO Fwd_DMA 0 <-- -IFLXO Inv 0 <-- -IFLXO Exclusive_Unblock 0 <-- -IFLXO L2_Replacement 0 <-- - -IGS L1_GETS 0 <-- -IGS L1_GETX 0 <-- -IGS L1_PUTO 0 <-- -IGS L1_PUTX 0 <-- -IGS L1_PUTS_only 0 <-- -IGS L1_PUTS 0 <-- -IGS Fwd_GETX 0 <-- -IGS Fwd_GETS 0 <-- -IGS Fwd_DMA 0 <-- -IGS Own_GETX 0 <-- -IGS Inv 0 <-- -IGS Data 0 <-- -IGS Data_Exclusive 983 -IGS Unblock 0 <-- -IGS Exclusive_Unblock 983 -IGS L2_Replacement 0 <-- - -IGM L1_GETS 0 <-- -IGM L1_GETX 0 <-- -IGM L1_PUTO 0 <-- -IGM L1_PUTX 0 <-- -IGM L1_PUTS_only 0 <-- -IGM L1_PUTS 0 <-- -IGM Fwd_GETX 0 <-- -IGM Fwd_GETS 0 <-- -IGM Fwd_DMA 0 <-- -IGM Own_GETX 0 <-- -IGM Inv 0 <-- -IGM ExtAck 0 <-- -IGM Data 131 -IGM Data_Exclusive 0 <-- -IGM L2_Replacement 0 <-- - -IGMLS L1_GETS 0 <-- -IGMLS L1_GETX 0 <-- -IGMLS L1_PUTO 0 <-- -IGMLS L1_PUTX 0 <-- -IGMLS L1_PUTS_only 0 <-- -IGMLS L1_PUTS 0 <-- -IGMLS Inv 0 <-- -IGMLS IntAck 0 <-- -IGMLS ExtAck 0 <-- -IGMLS All_Acks 0 <-- -IGMLS Data 0 <-- -IGMLS Data_Exclusive 0 <-- -IGMLS L2_Replacement 0 <-- - -IGMO L1_GETS 0 <-- -IGMO L1_GETX 0 <-- -IGMO L1_PUTO 0 <-- -IGMO L1_PUTX 0 <-- -IGMO L1_PUTS_only 0 <-- -IGMO L1_PUTS 0 <-- -IGMO Fwd_GETX 0 <-- -IGMO Fwd_GETS 0 <-- -IGMO Fwd_DMA 0 <-- -IGMO Own_GETX 0 <-- -IGMO ExtAck 0 <-- -IGMO All_Acks 131 -IGMO Exclusive_Unblock 131 -IGMO L2_Replacement 0 <-- - -IGMIO L1_GETS 0 <-- -IGMIO L1_GETX 0 <-- -IGMIO L1_PUTO 0 <-- -IGMIO L1_PUTX 0 <-- -IGMIO L1_PUTS_only 0 <-- -IGMIO L1_PUTS 0 <-- -IGMIO Fwd_GETX 0 <-- -IGMIO Fwd_GETS 0 <-- -IGMIO Fwd_DMA 0 <-- -IGMIO Own_GETX 0 <-- -IGMIO ExtAck 0 <-- -IGMIO All_Acks 0 <-- - -OGMIO L1_GETS 0 <-- -OGMIO L1_GETX 0 <-- -OGMIO L1_PUTO 0 <-- -OGMIO L1_PUTX 0 <-- -OGMIO L1_PUTS_only 0 <-- -OGMIO L1_PUTS 0 <-- -OGMIO Fwd_GETX 0 <-- -OGMIO Fwd_GETS 0 <-- -OGMIO Fwd_DMA 0 <-- -OGMIO Own_GETX 0 <-- -OGMIO ExtAck 0 <-- -OGMIO All_Acks 0 <-- - -IGMIOF L1_GETS 0 <-- -IGMIOF L1_GETX 0 <-- -IGMIOF L1_PUTO 0 <-- -IGMIOF L1_PUTX 0 <-- -IGMIOF L1_PUTS_only 0 <-- -IGMIOF L1_PUTS 0 <-- -IGMIOF IntAck 0 <-- -IGMIOF All_Acks 0 <-- -IGMIOF Data_Exclusive 0 <-- - -IGMIOFS L1_GETS 0 <-- -IGMIOFS L1_GETX 0 <-- -IGMIOFS L1_PUTO 0 <-- -IGMIOFS L1_PUTX 0 <-- -IGMIOFS L1_PUTS_only 0 <-- -IGMIOFS L1_PUTS 0 <-- -IGMIOFS Fwd_GETX 0 <-- -IGMIOFS Fwd_GETS 0 <-- -IGMIOFS Fwd_DMA 0 <-- -IGMIOFS Inv 0 <-- -IGMIOFS Data 0 <-- -IGMIOFS L2_Replacement 0 <-- - -OGMIOF L1_GETS 0 <-- -OGMIOF L1_GETX 0 <-- -OGMIOF L1_PUTO 0 <-- -OGMIOF L1_PUTX 0 <-- -OGMIOF L1_PUTS_only 0 <-- -OGMIOF L1_PUTS 0 <-- -OGMIOF IntAck 0 <-- -OGMIOF All_Acks 0 <-- - -II L1_GETS 0 <-- -II L1_GETX 0 <-- -II L1_PUTO 0 <-- -II L1_PUTX 0 <-- -II L1_PUTS_only 0 <-- -II L1_PUTS 0 <-- -II IntAck 0 <-- -II All_Acks 0 <-- - -MM L1_GETS 0 <-- -MM L1_GETX 0 <-- -MM L1_PUTO 0 <-- -MM L1_PUTX 0 <-- -MM L1_PUTS_only 0 <-- -MM L1_PUTS 0 <-- -MM Fwd_GETX 0 <-- -MM Fwd_GETS 0 <-- -MM Fwd_DMA 0 <-- -MM Inv 0 <-- -MM Exclusive_Unblock 60 -MM L2_Replacement 0 <-- - -SS L1_GETS 0 <-- -SS L1_GETX 0 <-- -SS L1_PUTO 0 <-- -SS L1_PUTX 0 <-- -SS L1_PUTS_only 0 <-- -SS L1_PUTS 0 <-- -SS Fwd_GETX 0 <-- -SS Fwd_GETS 0 <-- -SS Fwd_DMA 0 <-- -SS Inv 0 <-- -SS Unblock 0 <-- -SS L2_Replacement 0 <-- - -OO L1_GETS 0 <-- -OO L1_GETX 0 <-- -OO L1_PUTO 0 <-- -OO L1_PUTX 0 <-- -OO L1_PUTS_only 0 <-- -OO L1_PUTS 0 <-- -OO Fwd_GETX 0 <-- -OO Fwd_GETS 0 <-- -OO Fwd_DMA 0 <-- -OO Inv 0 <-- -OO Unblock 0 <-- -OO Exclusive_Unblock 188 -OO L2_Replacement 0 <-- - -OLSS L1_GETS 0 <-- -OLSS L1_GETX 0 <-- -OLSS L1_PUTO 0 <-- -OLSS L1_PUTX 0 <-- -OLSS L1_PUTS_only 0 <-- -OLSS L1_PUTS 0 <-- -OLSS Fwd_GETX 0 <-- -OLSS Fwd_GETS 0 <-- -OLSS Fwd_DMA 0 <-- -OLSS Inv 0 <-- -OLSS Unblock 0 <-- -OLSS L2_Replacement 0 <-- - -OLSXS L1_GETS 0 <-- -OLSXS L1_GETX 0 <-- -OLSXS L1_PUTO 0 <-- -OLSXS L1_PUTX 0 <-- -OLSXS L1_PUTS_only 0 <-- -OLSXS L1_PUTS 0 <-- -OLSXS Fwd_GETX 0 <-- -OLSXS Fwd_GETS 0 <-- -OLSXS Fwd_DMA 0 <-- -OLSXS Inv 0 <-- -OLSXS Unblock 0 <-- -OLSXS L2_Replacement 0 <-- - -SLSS L1_GETS 0 <-- -SLSS L1_GETX 0 <-- -SLSS L1_PUTO 0 <-- -SLSS L1_PUTX 0 <-- -SLSS L1_PUTS_only 0 <-- -SLSS L1_PUTS 0 <-- -SLSS Fwd_GETX 0 <-- -SLSS Fwd_GETS 0 <-- -SLSS Fwd_DMA 0 <-- -SLSS Inv 0 <-- -SLSS Unblock 0 <-- -SLSS L2_Replacement 0 <-- - -OI L1_GETS 0 <-- -OI L1_GETX 0 <-- -OI L1_PUTO 0 <-- -OI L1_PUTX 0 <-- -OI L1_PUTS_only 0 <-- -OI L1_PUTS 0 <-- -OI Fwd_GETX 0 <-- -OI Fwd_GETS 0 <-- -OI Fwd_DMA 0 <-- -OI Writeback_Ack 0 <-- -OI Writeback_Nack 0 <-- -OI L2_Replacement 0 <-- - -MI L1_GETS 0 <-- -MI L1_GETX 0 <-- -MI L1_PUTO 0 <-- -MI L1_PUTX 0 <-- -MI L1_PUTS_only 0 <-- -MI L1_PUTS 0 <-- -MI Fwd_GETX 0 <-- -MI Fwd_GETS 0 <-- -MI Fwd_DMA 0 <-- -MI Writeback_Ack 1098 -MI L2_Replacement 0 <-- - -MII L1_GETS 0 <-- -MII L1_GETX 0 <-- -MII L1_PUTO 0 <-- -MII L1_PUTX 0 <-- -MII L1_PUTS_only 0 <-- -MII L1_PUTS 0 <-- -MII Writeback_Ack 0 <-- -MII Writeback_Nack 0 <-- -MII L2_Replacement 0 <-- - -OLSI L1_GETS 0 <-- -OLSI L1_GETX 0 <-- -OLSI L1_PUTO 0 <-- -OLSI L1_PUTX 0 <-- -OLSI L1_PUTS_only 0 <-- -OLSI L1_PUTS 0 <-- -OLSI Fwd_GETX 0 <-- -OLSI Fwd_GETS 0 <-- -OLSI Fwd_DMA 0 <-- -OLSI Writeback_Ack 0 <-- -OLSI L2_Replacement 0 <-- - -ILSI L1_GETS 0 <-- -ILSI L1_GETX 0 <-- -ILSI L1_PUTO 0 <-- -ILSI L1_PUTX 0 <-- -ILSI L1_PUTS_only 0 <-- -ILSI L1_PUTS 0 <-- -ILSI IntAck 0 <-- -ILSI All_Acks 0 <-- -ILSI Writeback_Ack 0 <-- -ILSI L2_Replacement 0 <-- - -Memory controller: system.ruby.network.topology.ext_links2.ext_node.memBuffer: +NP L1_GETS [983 ] 983 +NP L1_GETX [131 ] 131 +NP L1_PUTO [0 ] 0 +NP L1_PUTX [0 ] 0 +NP L1_PUTS [0 ] 0 +NP Inv [0 ] 0 + +I L1_GETS [0 ] 0 +I L1_GETX [0 ] 0 +I L1_PUTO [0 ] 0 +I L1_PUTX [0 ] 0 +I L1_PUTS [0 ] 0 +I Inv [0 ] 0 +I L2_Replacement [0 ] 0 + +ILS L1_GETS [0 ] 0 +ILS L1_GETX [0 ] 0 +ILS L1_PUTO [0 ] 0 +ILS L1_PUTX [0 ] 0 +ILS L1_PUTS_only [0 ] 0 +ILS L1_PUTS [0 ] 0 +ILS Inv [0 ] 0 +ILS L2_Replacement [0 ] 0 + +ILX L1_GETS [0 ] 0 +ILX L1_GETX [0 ] 0 +ILX L1_PUTO [0 ] 0 +ILX L1_PUTX [1354 ] 1354 +ILX L1_PUTS_only [0 ] 0 +ILX L1_PUTS [0 ] 0 +ILX Fwd_GETX [0 ] 0 +ILX Fwd_GETS [0 ] 0 +ILX Fwd_DMA [0 ] 0 +ILX Inv [0 ] 0 +ILX Data [0 ] 0 +ILX L2_Replacement [0 ] 0 + +ILO L1_GETS [0 ] 0 +ILO L1_GETX [0 ] 0 +ILO L1_PUTO [0 ] 0 +ILO L1_PUTX [0 ] 0 +ILO L1_PUTS [0 ] 0 +ILO Fwd_GETX [0 ] 0 +ILO Fwd_GETS [0 ] 0 +ILO Fwd_DMA [0 ] 0 +ILO Inv [0 ] 0 +ILO Data [0 ] 0 +ILO L2_Replacement [0 ] 0 + +ILOX L1_GETS [0 ] 0 +ILOX L1_GETX [0 ] 0 +ILOX L1_PUTO [0 ] 0 +ILOX L1_PUTX [0 ] 0 +ILOX L1_PUTS [0 ] 0 +ILOX Fwd_GETX [0 ] 0 +ILOX Fwd_GETS [0 ] 0 +ILOX Fwd_DMA [0 ] 0 +ILOX Data [0 ] 0 + +ILOS L1_GETS [0 ] 0 +ILOS L1_GETX [0 ] 0 +ILOS L1_PUTO [0 ] 0 +ILOS L1_PUTX [0 ] 0 +ILOS L1_PUTS_only [0 ] 0 +ILOS L1_PUTS [0 ] 0 +ILOS Fwd_GETX [0 ] 0 +ILOS Fwd_GETS [0 ] 0 +ILOS Fwd_DMA [0 ] 0 +ILOS Data [0 ] 0 +ILOS L2_Replacement [0 ] 0 + +ILOSX L1_GETS [0 ] 0 +ILOSX L1_GETX [0 ] 0 +ILOSX L1_PUTO [0 ] 0 +ILOSX L1_PUTX [0 ] 0 +ILOSX L1_PUTS_only [0 ] 0 +ILOSX L1_PUTS [0 ] 0 +ILOSX Fwd_GETX [0 ] 0 +ILOSX Fwd_GETS [0 ] 0 +ILOSX Fwd_DMA [0 ] 0 +ILOSX Data [0 ] 0 + +S L1_GETS [0 ] 0 +S L1_GETX [0 ] 0 +S L1_PUTX [0 ] 0 +S L1_PUTS [0 ] 0 +S Inv [0 ] 0 +S L2_Replacement [0 ] 0 + +O L1_GETS [0 ] 0 +O L1_GETX [0 ] 0 +O L1_PUTX [0 ] 0 +O Fwd_GETX [0 ] 0 +O Fwd_GETS [0 ] 0 +O Fwd_DMA [0 ] 0 +O L2_Replacement [0 ] 0 + +OLS L1_GETS [0 ] 0 +OLS L1_GETX [0 ] 0 +OLS L1_PUTX [0 ] 0 +OLS L1_PUTS_only [0 ] 0 +OLS L1_PUTS [0 ] 0 +OLS Fwd_GETX [0 ] 0 +OLS Fwd_GETS [0 ] 0 +OLS Fwd_DMA [0 ] 0 +OLS L2_Replacement [0 ] 0 + +OLSX L1_GETS [0 ] 0 +OLSX L1_GETX [0 ] 0 +OLSX L1_PUTO [0 ] 0 +OLSX L1_PUTX [0 ] 0 +OLSX L1_PUTS_only [0 ] 0 +OLSX L1_PUTS [0 ] 0 +OLSX Fwd_GETX [0 ] 0 +OLSX Fwd_GETS [0 ] 0 +OLSX Fwd_DMA [0 ] 0 +OLSX L2_Replacement [0 ] 0 + +SLS L1_GETS [0 ] 0 +SLS L1_GETX [0 ] 0 +SLS L1_PUTX [0 ] 0 +SLS L1_PUTS_only [0 ] 0 +SLS L1_PUTS [0 ] 0 +SLS Inv [0 ] 0 +SLS L2_Replacement [0 ] 0 + +M L1_GETS [188 ] 188 +M L1_GETX [60 ] 60 +M L1_PUTO [0 ] 0 +M L1_PUTX [0 ] 0 +M L1_PUTS [0 ] 0 +M Fwd_GETX [0 ] 0 +M Fwd_GETS [0 ] 0 +M Fwd_DMA [0 ] 0 +M L2_Replacement [1098 ] 1098 + +IFGX L1_GETS [0 ] 0 +IFGX L1_GETX [0 ] 0 +IFGX L1_PUTO [0 ] 0 +IFGX L1_PUTX [0 ] 0 +IFGX L1_PUTS_only [0 ] 0 +IFGX L1_PUTS [0 ] 0 +IFGX Fwd_GETX [0 ] 0 +IFGX Fwd_GETS [0 ] 0 +IFGX Fwd_DMA [0 ] 0 +IFGX Inv [0 ] 0 +IFGX Data [0 ] 0 +IFGX Data_Exclusive [0 ] 0 +IFGX L2_Replacement [0 ] 0 + +IFGS L1_GETS [0 ] 0 +IFGS L1_GETX [0 ] 0 +IFGS L1_PUTO [0 ] 0 +IFGS L1_PUTX [0 ] 0 +IFGS L1_PUTS_only [0 ] 0 +IFGS L1_PUTS [0 ] 0 +IFGS Fwd_GETX [0 ] 0 +IFGS Fwd_GETS [0 ] 0 +IFGS Fwd_DMA [0 ] 0 +IFGS Inv [0 ] 0 +IFGS Data [0 ] 0 +IFGS Data_Exclusive [0 ] 0 +IFGS L2_Replacement [0 ] 0 + +ISFGS L1_GETS [0 ] 0 +ISFGS L1_GETX [0 ] 0 +ISFGS L1_PUTO [0 ] 0 +ISFGS L1_PUTX [0 ] 0 +ISFGS L1_PUTS_only [0 ] 0 +ISFGS L1_PUTS [0 ] 0 +ISFGS Fwd_GETX [0 ] 0 +ISFGS Fwd_GETS [0 ] 0 +ISFGS Fwd_DMA [0 ] 0 +ISFGS Inv [0 ] 0 +ISFGS Data [0 ] 0 +ISFGS L2_Replacement [0 ] 0 + +IFGXX L1_GETS [0 ] 0 +IFGXX L1_GETX [0 ] 0 +IFGXX L1_PUTO [0 ] 0 +IFGXX L1_PUTX [0 ] 0 +IFGXX L1_PUTS_only [0 ] 0 +IFGXX L1_PUTS [0 ] 0 +IFGXX Fwd_GETX [0 ] 0 +IFGXX Fwd_GETS [0 ] 0 +IFGXX Fwd_DMA [0 ] 0 +IFGXX Inv [0 ] 0 +IFGXX IntAck [0 ] 0 +IFGXX All_Acks [0 ] 0 +IFGXX Data_Exclusive [0 ] 0 +IFGXX L2_Replacement [0 ] 0 + +OFGX L1_GETS [0 ] 0 +OFGX L1_GETX [0 ] 0 +OFGX L1_PUTO [0 ] 0 +OFGX L1_PUTX [0 ] 0 +OFGX L1_PUTS_only [0 ] 0 +OFGX L1_PUTS [0 ] 0 +OFGX Fwd_GETX [0 ] 0 +OFGX Fwd_GETS [0 ] 0 +OFGX Fwd_DMA [0 ] 0 +OFGX Inv [0 ] 0 +OFGX L2_Replacement [0 ] 0 + +OLSF L1_GETS [0 ] 0 +OLSF L1_GETX [0 ] 0 +OLSF L1_PUTO [0 ] 0 +OLSF L1_PUTX [0 ] 0 +OLSF L1_PUTS_only [0 ] 0 +OLSF L1_PUTS [0 ] 0 +OLSF Fwd_GETX [0 ] 0 +OLSF Fwd_GETS [0 ] 0 +OLSF Fwd_DMA [0 ] 0 +OLSF Inv [0 ] 0 +OLSF IntAck [0 ] 0 +OLSF All_Acks [0 ] 0 +OLSF L2_Replacement [0 ] 0 + +ILOW L1_GETS [0 ] 0 +ILOW L1_GETX [0 ] 0 +ILOW L1_PUTO [0 ] 0 +ILOW L1_PUTX [0 ] 0 +ILOW L1_PUTS_only [0 ] 0 +ILOW L1_PUTS [0 ] 0 +ILOW Fwd_GETX [0 ] 0 +ILOW Fwd_GETS [0 ] 0 +ILOW Fwd_DMA [0 ] 0 +ILOW Inv [0 ] 0 +ILOW L1_WBCLEANDATA [0 ] 0 +ILOW L1_WBDIRTYDATA [0 ] 0 +ILOW Unblock [0 ] 0 +ILOW L2_Replacement [0 ] 0 + +ILOXW L1_GETS [0 ] 0 +ILOXW L1_GETX [0 ] 0 +ILOXW L1_PUTO [0 ] 0 +ILOXW L1_PUTX [0 ] 0 +ILOXW L1_PUTS_only [0 ] 0 +ILOXW L1_PUTS [0 ] 0 +ILOXW Fwd_GETX [0 ] 0 +ILOXW Fwd_GETS [0 ] 0 +ILOXW Fwd_DMA [0 ] 0 +ILOXW Inv [0 ] 0 +ILOXW L1_WBCLEANDATA [0 ] 0 +ILOXW L1_WBDIRTYDATA [0 ] 0 +ILOXW Unblock [0 ] 0 +ILOXW L2_Replacement [0 ] 0 + +ILOSW L1_GETS [0 ] 0 +ILOSW L1_GETX [0 ] 0 +ILOSW L1_PUTO [0 ] 0 +ILOSW L1_PUTX [0 ] 0 +ILOSW L1_PUTS_only [0 ] 0 +ILOSW L1_PUTS [0 ] 0 +ILOSW Fwd_GETX [0 ] 0 +ILOSW Fwd_GETS [0 ] 0 +ILOSW Fwd_DMA [0 ] 0 +ILOSW Inv [0 ] 0 +ILOSW L1_WBCLEANDATA [0 ] 0 +ILOSW L1_WBDIRTYDATA [0 ] 0 +ILOSW Unblock [0 ] 0 +ILOSW L2_Replacement [0 ] 0 + +ILOSXW L1_GETS [0 ] 0 +ILOSXW L1_GETX [0 ] 0 +ILOSXW L1_PUTO [0 ] 0 +ILOSXW L1_PUTX [0 ] 0 +ILOSXW L1_PUTS_only [0 ] 0 +ILOSXW L1_PUTS [0 ] 0 +ILOSXW Fwd_GETX [0 ] 0 +ILOSXW Fwd_GETS [0 ] 0 +ILOSXW Fwd_DMA [0 ] 0 +ILOSXW Inv [0 ] 0 +ILOSXW L1_WBCLEANDATA [0 ] 0 +ILOSXW L1_WBDIRTYDATA [0 ] 0 +ILOSXW Unblock [0 ] 0 +ILOSXW L2_Replacement [0 ] 0 + +SLSW L1_GETS [0 ] 0 +SLSW L1_GETX [0 ] 0 +SLSW L1_PUTO [0 ] 0 +SLSW L1_PUTX [0 ] 0 +SLSW L1_PUTS_only [0 ] 0 +SLSW L1_PUTS [0 ] 0 +SLSW Fwd_GETX [0 ] 0 +SLSW Fwd_GETS [0 ] 0 +SLSW Fwd_DMA [0 ] 0 +SLSW Inv [0 ] 0 +SLSW Unblock [0 ] 0 +SLSW L2_Replacement [0 ] 0 + +OLSW L1_GETS [0 ] 0 +OLSW L1_GETX [0 ] 0 +OLSW L1_PUTO [0 ] 0 +OLSW L1_PUTX [0 ] 0 +OLSW L1_PUTS_only [0 ] 0 +OLSW L1_PUTS [0 ] 0 +OLSW Fwd_GETX [0 ] 0 +OLSW Fwd_GETS [0 ] 0 +OLSW Fwd_DMA [0 ] 0 +OLSW Inv [0 ] 0 +OLSW Unblock [0 ] 0 +OLSW L2_Replacement [0 ] 0 + +ILSW L1_GETS [0 ] 0 +ILSW L1_GETX [0 ] 0 +ILSW L1_PUTO [0 ] 0 +ILSW L1_PUTX [0 ] 0 +ILSW L1_PUTS_only [0 ] 0 +ILSW L1_PUTS [0 ] 0 +ILSW Fwd_GETX [0 ] 0 +ILSW Fwd_GETS [0 ] 0 +ILSW Fwd_DMA [0 ] 0 +ILSW Inv [0 ] 0 +ILSW L1_WBCLEANDATA [0 ] 0 +ILSW Unblock [0 ] 0 +ILSW L2_Replacement [0 ] 0 + +IW L1_GETS [0 ] 0 +IW L1_GETX [0 ] 0 +IW L1_PUTO [0 ] 0 +IW L1_PUTX [0 ] 0 +IW L1_PUTS_only [0 ] 0 +IW L1_PUTS [0 ] 0 +IW Fwd_GETX [0 ] 0 +IW Fwd_GETS [0 ] 0 +IW Fwd_DMA [0 ] 0 +IW Inv [0 ] 0 +IW L1_WBCLEANDATA [0 ] 0 +IW L2_Replacement [0 ] 0 + +OW L1_GETS [0 ] 0 +OW L1_GETX [0 ] 0 +OW L1_PUTO [0 ] 0 +OW L1_PUTX [0 ] 0 +OW L1_PUTS_only [0 ] 0 +OW L1_PUTS [0 ] 0 +OW Fwd_GETX [0 ] 0 +OW Fwd_GETS [0 ] 0 +OW Fwd_DMA [0 ] 0 +OW Inv [0 ] 0 +OW Unblock [0 ] 0 +OW L2_Replacement [0 ] 0 + +SW L1_GETS [0 ] 0 +SW L1_GETX [0 ] 0 +SW L1_PUTO [0 ] 0 +SW L1_PUTX [0 ] 0 +SW L1_PUTS_only [0 ] 0 +SW L1_PUTS [0 ] 0 +SW Fwd_GETX [0 ] 0 +SW Fwd_GETS [0 ] 0 +SW Fwd_DMA [0 ] 0 +SW Inv [0 ] 0 +SW Unblock [0 ] 0 +SW L2_Replacement [0 ] 0 + +OXW L1_GETS [0 ] 0 +OXW L1_GETX [0 ] 0 +OXW L1_PUTO [0 ] 0 +OXW L1_PUTX [0 ] 0 +OXW L1_PUTS_only [0 ] 0 +OXW L1_PUTS [0 ] 0 +OXW Fwd_GETX [0 ] 0 +OXW Fwd_GETS [0 ] 0 +OXW Fwd_DMA [0 ] 0 +OXW Inv [0 ] 0 +OXW Unblock [0 ] 0 +OXW L2_Replacement [0 ] 0 + +OLSXW L1_GETS [0 ] 0 +OLSXW L1_GETX [0 ] 0 +OLSXW L1_PUTO [0 ] 0 +OLSXW L1_PUTX [0 ] 0 +OLSXW L1_PUTS_only [0 ] 0 +OLSXW L1_PUTS [0 ] 0 +OLSXW Fwd_GETX [0 ] 0 +OLSXW Fwd_GETS [0 ] 0 +OLSXW Fwd_DMA [0 ] 0 +OLSXW Inv [0 ] 0 +OLSXW Unblock [0 ] 0 +OLSXW L2_Replacement [0 ] 0 + +ILXW L1_GETS [0 ] 0 +ILXW L1_GETX [0 ] 0 +ILXW L1_PUTO [0 ] 0 +ILXW L1_PUTX [0 ] 0 +ILXW L1_PUTS_only [0 ] 0 +ILXW L1_PUTS [0 ] 0 +ILXW Fwd_GETX [0 ] 0 +ILXW Fwd_GETS [0 ] 0 +ILXW Fwd_DMA [0 ] 0 +ILXW Inv [0 ] 0 +ILXW Data [0 ] 0 +ILXW L1_WBCLEANDATA [1059 ] 1059 +ILXW L1_WBDIRTYDATA [295 ] 295 +ILXW Unblock [0 ] 0 +ILXW L2_Replacement [0 ] 0 + +IFLS L1_GETS [0 ] 0 +IFLS L1_GETX [0 ] 0 +IFLS L1_PUTO [0 ] 0 +IFLS L1_PUTX [0 ] 0 +IFLS L1_PUTS_only [0 ] 0 +IFLS L1_PUTS [0 ] 0 +IFLS Fwd_GETX [0 ] 0 +IFLS Fwd_GETS [0 ] 0 +IFLS Fwd_DMA [0 ] 0 +IFLS Inv [0 ] 0 +IFLS Unblock [0 ] 0 +IFLS L2_Replacement [0 ] 0 + +IFLO L1_GETS [0 ] 0 +IFLO L1_GETX [0 ] 0 +IFLO L1_PUTO [0 ] 0 +IFLO L1_PUTX [0 ] 0 +IFLO L1_PUTS_only [0 ] 0 +IFLO L1_PUTS [0 ] 0 +IFLO Fwd_GETX [0 ] 0 +IFLO Fwd_GETS [0 ] 0 +IFLO Fwd_DMA [0 ] 0 +IFLO Inv [0 ] 0 +IFLO Unblock [0 ] 0 +IFLO L2_Replacement [0 ] 0 + +IFLOX L1_GETS [0 ] 0 +IFLOX L1_GETX [0 ] 0 +IFLOX L1_PUTO [0 ] 0 +IFLOX L1_PUTX [0 ] 0 +IFLOX L1_PUTS_only [0 ] 0 +IFLOX L1_PUTS [0 ] 0 +IFLOX Fwd_GETX [0 ] 0 +IFLOX Fwd_GETS [0 ] 0 +IFLOX Fwd_DMA [0 ] 0 +IFLOX Inv [0 ] 0 +IFLOX Unblock [0 ] 0 +IFLOX Exclusive_Unblock [0 ] 0 +IFLOX L2_Replacement [0 ] 0 + +IFLOXX L1_GETS [0 ] 0 +IFLOXX L1_GETX [0 ] 0 +IFLOXX L1_PUTO [0 ] 0 +IFLOXX L1_PUTX [0 ] 0 +IFLOXX L1_PUTS_only [0 ] 0 +IFLOXX L1_PUTS [0 ] 0 +IFLOXX Fwd_GETX [0 ] 0 +IFLOXX Fwd_GETS [0 ] 0 +IFLOXX Fwd_DMA [0 ] 0 +IFLOXX Inv [0 ] 0 +IFLOXX Unblock [0 ] 0 +IFLOXX Exclusive_Unblock [0 ] 0 +IFLOXX L2_Replacement [0 ] 0 + +IFLOSX L1_GETS [0 ] 0 +IFLOSX L1_GETX [0 ] 0 +IFLOSX L1_PUTO [0 ] 0 +IFLOSX L1_PUTX [0 ] 0 +IFLOSX L1_PUTS_only [0 ] 0 +IFLOSX L1_PUTS [0 ] 0 +IFLOSX Fwd_GETX [0 ] 0 +IFLOSX Fwd_GETS [0 ] 0 +IFLOSX Fwd_DMA [0 ] 0 +IFLOSX Inv [0 ] 0 +IFLOSX Unblock [0 ] 0 +IFLOSX Exclusive_Unblock [0 ] 0 +IFLOSX L2_Replacement [0 ] 0 + +IFLXO L1_GETS [0 ] 0 +IFLXO L1_GETX [0 ] 0 +IFLXO L1_PUTO [0 ] 0 +IFLXO L1_PUTX [0 ] 0 +IFLXO L1_PUTS_only [0 ] 0 +IFLXO L1_PUTS [0 ] 0 +IFLXO Fwd_GETX [0 ] 0 +IFLXO Fwd_GETS [0 ] 0 +IFLXO Fwd_DMA [0 ] 0 +IFLXO Inv [0 ] 0 +IFLXO Exclusive_Unblock [0 ] 0 +IFLXO L2_Replacement [0 ] 0 + +IGS L1_GETS [0 ] 0 +IGS L1_GETX [0 ] 0 +IGS L1_PUTO [0 ] 0 +IGS L1_PUTX [0 ] 0 +IGS L1_PUTS_only [0 ] 0 +IGS L1_PUTS [0 ] 0 +IGS Fwd_GETX [0 ] 0 +IGS Fwd_GETS [0 ] 0 +IGS Fwd_DMA [0 ] 0 +IGS Own_GETX [0 ] 0 +IGS Inv [0 ] 0 +IGS Data [0 ] 0 +IGS Data_Exclusive [983 ] 983 +IGS Unblock [0 ] 0 +IGS Exclusive_Unblock [983 ] 983 +IGS L2_Replacement [0 ] 0 + +IGM L1_GETS [0 ] 0 +IGM L1_GETX [0 ] 0 +IGM L1_PUTO [0 ] 0 +IGM L1_PUTX [0 ] 0 +IGM L1_PUTS_only [0 ] 0 +IGM L1_PUTS [0 ] 0 +IGM Fwd_GETX [0 ] 0 +IGM Fwd_GETS [0 ] 0 +IGM Fwd_DMA [0 ] 0 +IGM Own_GETX [0 ] 0 +IGM Inv [0 ] 0 +IGM ExtAck [0 ] 0 +IGM Data [131 ] 131 +IGM Data_Exclusive [0 ] 0 +IGM L2_Replacement [0 ] 0 + +IGMLS L1_GETS [0 ] 0 +IGMLS L1_GETX [0 ] 0 +IGMLS L1_PUTO [0 ] 0 +IGMLS L1_PUTX [0 ] 0 +IGMLS L1_PUTS_only [0 ] 0 +IGMLS L1_PUTS [0 ] 0 +IGMLS Inv [0 ] 0 +IGMLS IntAck [0 ] 0 +IGMLS ExtAck [0 ] 0 +IGMLS All_Acks [0 ] 0 +IGMLS Data [0 ] 0 +IGMLS Data_Exclusive [0 ] 0 +IGMLS L2_Replacement [0 ] 0 + +IGMO L1_GETS [0 ] 0 +IGMO L1_GETX [0 ] 0 +IGMO L1_PUTO [0 ] 0 +IGMO L1_PUTX [0 ] 0 +IGMO L1_PUTS_only [0 ] 0 +IGMO L1_PUTS [0 ] 0 +IGMO Fwd_GETX [0 ] 0 +IGMO Fwd_GETS [0 ] 0 +IGMO Fwd_DMA [0 ] 0 +IGMO Own_GETX [0 ] 0 +IGMO ExtAck [0 ] 0 +IGMO All_Acks [131 ] 131 +IGMO Exclusive_Unblock [131 ] 131 +IGMO L2_Replacement [0 ] 0 + +IGMIO L1_GETS [0 ] 0 +IGMIO L1_GETX [0 ] 0 +IGMIO L1_PUTO [0 ] 0 +IGMIO L1_PUTX [0 ] 0 +IGMIO L1_PUTS_only [0 ] 0 +IGMIO L1_PUTS [0 ] 0 +IGMIO Fwd_GETX [0 ] 0 +IGMIO Fwd_GETS [0 ] 0 +IGMIO Fwd_DMA [0 ] 0 +IGMIO Own_GETX [0 ] 0 +IGMIO ExtAck [0 ] 0 +IGMIO All_Acks [0 ] 0 + +OGMIO L1_GETS [0 ] 0 +OGMIO L1_GETX [0 ] 0 +OGMIO L1_PUTO [0 ] 0 +OGMIO L1_PUTX [0 ] 0 +OGMIO L1_PUTS_only [0 ] 0 +OGMIO L1_PUTS [0 ] 0 +OGMIO Fwd_GETX [0 ] 0 +OGMIO Fwd_GETS [0 ] 0 +OGMIO Fwd_DMA [0 ] 0 +OGMIO Own_GETX [0 ] 0 +OGMIO ExtAck [0 ] 0 +OGMIO All_Acks [0 ] 0 + +IGMIOF L1_GETS [0 ] 0 +IGMIOF L1_GETX [0 ] 0 +IGMIOF L1_PUTO [0 ] 0 +IGMIOF L1_PUTX [0 ] 0 +IGMIOF L1_PUTS_only [0 ] 0 +IGMIOF L1_PUTS [0 ] 0 +IGMIOF IntAck [0 ] 0 +IGMIOF All_Acks [0 ] 0 +IGMIOF Data_Exclusive [0 ] 0 + +IGMIOFS L1_GETS [0 ] 0 +IGMIOFS L1_GETX [0 ] 0 +IGMIOFS L1_PUTO [0 ] 0 +IGMIOFS L1_PUTX [0 ] 0 +IGMIOFS L1_PUTS_only [0 ] 0 +IGMIOFS L1_PUTS [0 ] 0 +IGMIOFS Fwd_GETX [0 ] 0 +IGMIOFS Fwd_GETS [0 ] 0 +IGMIOFS Fwd_DMA [0 ] 0 +IGMIOFS Inv [0 ] 0 +IGMIOFS Data [0 ] 0 +IGMIOFS L2_Replacement [0 ] 0 + +OGMIOF L1_GETS [0 ] 0 +OGMIOF L1_GETX [0 ] 0 +OGMIOF L1_PUTO [0 ] 0 +OGMIOF L1_PUTX [0 ] 0 +OGMIOF L1_PUTS_only [0 ] 0 +OGMIOF L1_PUTS [0 ] 0 +OGMIOF IntAck [0 ] 0 +OGMIOF All_Acks [0 ] 0 + +II L1_GETS [0 ] 0 +II L1_GETX [0 ] 0 +II L1_PUTO [0 ] 0 +II L1_PUTX [0 ] 0 +II L1_PUTS_only [0 ] 0 +II L1_PUTS [0 ] 0 +II IntAck [0 ] 0 +II All_Acks [0 ] 0 + +MM L1_GETS [0 ] 0 +MM L1_GETX [0 ] 0 +MM L1_PUTO [0 ] 0 +MM L1_PUTX [0 ] 0 +MM L1_PUTS_only [0 ] 0 +MM L1_PUTS [0 ] 0 +MM Fwd_GETX [0 ] 0 +MM Fwd_GETS [0 ] 0 +MM Fwd_DMA [0 ] 0 +MM Inv [0 ] 0 +MM Exclusive_Unblock [60 ] 60 +MM L2_Replacement [0 ] 0 + +SS L1_GETS [0 ] 0 +SS L1_GETX [0 ] 0 +SS L1_PUTO [0 ] 0 +SS L1_PUTX [0 ] 0 +SS L1_PUTS_only [0 ] 0 +SS L1_PUTS [0 ] 0 +SS Fwd_GETX [0 ] 0 +SS Fwd_GETS [0 ] 0 +SS Fwd_DMA [0 ] 0 +SS Inv [0 ] 0 +SS Unblock [0 ] 0 +SS L2_Replacement [0 ] 0 + +OO L1_GETS [0 ] 0 +OO L1_GETX [0 ] 0 +OO L1_PUTO [0 ] 0 +OO L1_PUTX [0 ] 0 +OO L1_PUTS_only [0 ] 0 +OO L1_PUTS [0 ] 0 +OO Fwd_GETX [0 ] 0 +OO Fwd_GETS [0 ] 0 +OO Fwd_DMA [0 ] 0 +OO Inv [0 ] 0 +OO Unblock [0 ] 0 +OO Exclusive_Unblock [188 ] 188 +OO L2_Replacement [0 ] 0 + +OLSS L1_GETS [0 ] 0 +OLSS L1_GETX [0 ] 0 +OLSS L1_PUTO [0 ] 0 +OLSS L1_PUTX [0 ] 0 +OLSS L1_PUTS_only [0 ] 0 +OLSS L1_PUTS [0 ] 0 +OLSS Fwd_GETX [0 ] 0 +OLSS Fwd_GETS [0 ] 0 +OLSS Fwd_DMA [0 ] 0 +OLSS Inv [0 ] 0 +OLSS Unblock [0 ] 0 +OLSS L2_Replacement [0 ] 0 + +OLSXS L1_GETS [0 ] 0 +OLSXS L1_GETX [0 ] 0 +OLSXS L1_PUTO [0 ] 0 +OLSXS L1_PUTX [0 ] 0 +OLSXS L1_PUTS_only [0 ] 0 +OLSXS L1_PUTS [0 ] 0 +OLSXS Fwd_GETX [0 ] 0 +OLSXS Fwd_GETS [0 ] 0 +OLSXS Fwd_DMA [0 ] 0 +OLSXS Inv [0 ] 0 +OLSXS Unblock [0 ] 0 +OLSXS L2_Replacement [0 ] 0 + +SLSS L1_GETS [0 ] 0 +SLSS L1_GETX [0 ] 0 +SLSS L1_PUTO [0 ] 0 +SLSS L1_PUTX [0 ] 0 +SLSS L1_PUTS_only [0 ] 0 +SLSS L1_PUTS [0 ] 0 +SLSS Fwd_GETX [0 ] 0 +SLSS Fwd_GETS [0 ] 0 +SLSS Fwd_DMA [0 ] 0 +SLSS Inv [0 ] 0 +SLSS Unblock [0 ] 0 +SLSS L2_Replacement [0 ] 0 + +OI L1_GETS [0 ] 0 +OI L1_GETX [0 ] 0 +OI L1_PUTO [0 ] 0 +OI L1_PUTX [0 ] 0 +OI L1_PUTS_only [0 ] 0 +OI L1_PUTS [0 ] 0 +OI Fwd_GETX [0 ] 0 +OI Fwd_GETS [0 ] 0 +OI Fwd_DMA [0 ] 0 +OI Writeback_Ack [0 ] 0 +OI Writeback_Nack [0 ] 0 +OI L2_Replacement [0 ] 0 + +MI L1_GETS [0 ] 0 +MI L1_GETX [0 ] 0 +MI L1_PUTO [0 ] 0 +MI L1_PUTX [0 ] 0 +MI L1_PUTS_only [0 ] 0 +MI L1_PUTS [0 ] 0 +MI Fwd_GETX [0 ] 0 +MI Fwd_GETS [0 ] 0 +MI Fwd_DMA [0 ] 0 +MI Writeback_Ack [1098 ] 1098 +MI L2_Replacement [0 ] 0 + +MII L1_GETS [0 ] 0 +MII L1_GETX [0 ] 0 +MII L1_PUTO [0 ] 0 +MII L1_PUTX [0 ] 0 +MII L1_PUTS_only [0 ] 0 +MII L1_PUTS [0 ] 0 +MII Writeback_Ack [0 ] 0 +MII Writeback_Nack [0 ] 0 +MII L2_Replacement [0 ] 0 + +OLSI L1_GETS [0 ] 0 +OLSI L1_GETX [0 ] 0 +OLSI L1_PUTO [0 ] 0 +OLSI L1_PUTX [0 ] 0 +OLSI L1_PUTS_only [0 ] 0 +OLSI L1_PUTS [0 ] 0 +OLSI Fwd_GETX [0 ] 0 +OLSI Fwd_GETS [0 ] 0 +OLSI Fwd_DMA [0 ] 0 +OLSI Writeback_Ack [0 ] 0 +OLSI L2_Replacement [0 ] 0 + +ILSI L1_GETS [0 ] 0 +ILSI L1_GETX [0 ] 0 +ILSI L1_PUTO [0 ] 0 +ILSI L1_PUTX [0 ] 0 +ILSI L1_PUTS_only [0 ] 0 +ILSI L1_PUTS [0 ] 0 +ILSI IntAck [0 ] 0 +ILSI All_Acks [0 ] 0 +ILSI Writeback_Ack [0 ] 0 +ILSI L2_Replacement [0 ] 0 + +Memory controller: system.dir_cntrl0.memBuffer: memory_total_requests: 1308 memory_reads: 1114 memory_writes: 194 @@ -1175,201 +1180,200 @@ Memory controller: system.ruby.network.topology.ext_links2.ext_node.memBuffer: memory_stalls_for_read_read_turnaround: 0 accesses_per_bank: 75 17 45 40 54 99 29 16 19 22 32 34 52 48 38 30 39 21 21 27 28 37 55 22 31 22 32 70 84 104 13 52 - --- Directory 0 --- + --- Directory --- - Event Counts - -GETX 131 -GETS 983 -PUTX 1098 -PUTO 0 -PUTO_SHARERS 0 -Unblock 0 -Last_Unblock 0 -Exclusive_Unblock 1114 -Clean_Writeback 904 -Dirty_Writeback 194 -Memory_Data 1114 -Memory_Ack 194 -DMA_READ 0 -DMA_WRITE 0 -Data 0 +GETX [131 ] 131 +GETS [983 ] 983 +PUTX [1098 ] 1098 +PUTO [0 ] 0 +PUTO_SHARERS [0 ] 0 +Unblock [0 ] 0 +Last_Unblock [0 ] 0 +Exclusive_Unblock [1114 ] 1114 +Clean_Writeback [904 ] 904 +Dirty_Writeback [194 ] 194 +Memory_Data [1114 ] 1114 +Memory_Ack [194 ] 194 +DMA_READ [0 ] 0 +DMA_WRITE [0 ] 0 +Data [0 ] 0 - Transitions - -I GETX 131 -I GETS 983 -I PUTX 0 <-- -I PUTO 0 <-- -I Memory_Data 0 <-- -I Memory_Ack 191 -I DMA_READ 0 <-- -I DMA_WRITE 0 <-- - -S GETX 0 <-- -S GETS 0 <-- -S PUTX 0 <-- -S PUTO 0 <-- -S Memory_Data 0 <-- -S Memory_Ack 0 <-- -S DMA_READ 0 <-- -S DMA_WRITE 0 <-- - -O GETX 0 <-- -O GETS 0 <-- -O PUTX 0 <-- -O PUTO 0 <-- -O PUTO_SHARERS 0 <-- -O Memory_Data 0 <-- -O Memory_Ack 0 <-- -O DMA_READ 0 <-- -O DMA_WRITE 0 <-- - -M GETX 0 <-- -M GETS 0 <-- -M PUTX 1098 -M PUTO 0 <-- -M PUTO_SHARERS 0 <-- -M Memory_Data 0 <-- -M Memory_Ack 0 <-- -M DMA_READ 0 <-- -M DMA_WRITE 0 <-- - -IS GETX 0 <-- -IS GETS 0 <-- -IS PUTX 0 <-- -IS PUTO 0 <-- -IS PUTO_SHARERS 0 <-- -IS Unblock 0 <-- -IS Exclusive_Unblock 983 -IS Memory_Data 983 -IS Memory_Ack 2 -IS DMA_READ 0 <-- -IS DMA_WRITE 0 <-- - -SS GETX 0 <-- -SS GETS 0 <-- -SS PUTX 0 <-- -SS PUTO 0 <-- -SS PUTO_SHARERS 0 <-- -SS Unblock 0 <-- -SS Last_Unblock 0 <-- -SS Memory_Data 0 <-- -SS Memory_Ack 0 <-- -SS DMA_READ 0 <-- -SS DMA_WRITE 0 <-- - -OO GETX 0 <-- -OO GETS 0 <-- -OO PUTX 0 <-- -OO PUTO 0 <-- -OO PUTO_SHARERS 0 <-- -OO Unblock 0 <-- -OO Last_Unblock 0 <-- -OO Memory_Data 0 <-- -OO Memory_Ack 0 <-- -OO DMA_READ 0 <-- -OO DMA_WRITE 0 <-- - -MO GETX 0 <-- -MO GETS 0 <-- -MO PUTX 0 <-- -MO PUTO 0 <-- -MO PUTO_SHARERS 0 <-- -MO Unblock 0 <-- -MO Exclusive_Unblock 0 <-- -MO Memory_Data 0 <-- -MO Memory_Ack 0 <-- -MO DMA_READ 0 <-- -MO DMA_WRITE 0 <-- - -MM GETX 0 <-- -MM GETS 0 <-- -MM PUTX 0 <-- -MM PUTO 0 <-- -MM PUTO_SHARERS 0 <-- -MM Exclusive_Unblock 131 -MM Memory_Data 131 -MM Memory_Ack 1 -MM DMA_READ 0 <-- -MM DMA_WRITE 0 <-- - - -MI GETX 0 <-- -MI GETS 0 <-- -MI PUTX 0 <-- -MI PUTO 0 <-- -MI PUTO_SHARERS 0 <-- -MI Unblock 0 <-- -MI Clean_Writeback 904 -MI Dirty_Writeback 194 -MI Memory_Data 0 <-- -MI Memory_Ack 0 <-- -MI DMA_READ 0 <-- -MI DMA_WRITE 0 <-- - -MIS GETX 0 <-- -MIS GETS 0 <-- -MIS PUTX 0 <-- -MIS PUTO 0 <-- -MIS PUTO_SHARERS 0 <-- -MIS Unblock 0 <-- -MIS Clean_Writeback 0 <-- -MIS Dirty_Writeback 0 <-- -MIS Memory_Data 0 <-- -MIS Memory_Ack 0 <-- -MIS DMA_READ 0 <-- -MIS DMA_WRITE 0 <-- - -OS GETX 0 <-- -OS GETS 0 <-- -OS PUTX 0 <-- -OS PUTO 0 <-- -OS PUTO_SHARERS 0 <-- -OS Unblock 0 <-- -OS Clean_Writeback 0 <-- -OS Dirty_Writeback 0 <-- -OS Memory_Data 0 <-- -OS Memory_Ack 0 <-- -OS DMA_READ 0 <-- -OS DMA_WRITE 0 <-- - -OSS GETX 0 <-- -OSS GETS 0 <-- -OSS PUTX 0 <-- -OSS PUTO 0 <-- -OSS PUTO_SHARERS 0 <-- -OSS Unblock 0 <-- -OSS Clean_Writeback 0 <-- -OSS Dirty_Writeback 0 <-- -OSS Memory_Data 0 <-- -OSS Memory_Ack 0 <-- -OSS DMA_READ 0 <-- -OSS DMA_WRITE 0 <-- - -XI_M GETX 0 <-- -XI_M GETS 0 <-- -XI_M PUTX 0 <-- -XI_M PUTO 0 <-- -XI_M PUTO_SHARERS 0 <-- -XI_M Memory_Data 0 <-- -XI_M Memory_Ack 0 <-- -XI_M DMA_READ 0 <-- -XI_M DMA_WRITE 0 <-- - -XI_U GETX 0 <-- -XI_U GETS 0 <-- -XI_U PUTX 0 <-- -XI_U PUTO 0 <-- -XI_U PUTO_SHARERS 0 <-- -XI_U Exclusive_Unblock 0 <-- -XI_U Memory_Ack 0 <-- -XI_U DMA_READ 0 <-- -XI_U DMA_WRITE 0 <-- - -OI_D GETX 0 <-- -OI_D GETS 0 <-- -OI_D PUTX 0 <-- -OI_D PUTO 0 <-- -OI_D PUTO_SHARERS 0 <-- -OI_D DMA_READ 0 <-- -OI_D DMA_WRITE 0 <-- -OI_D Data 0 <-- - +I GETX [131 ] 131 +I GETS [983 ] 983 +I PUTX [0 ] 0 +I PUTO [0 ] 0 +I Memory_Data [0 ] 0 +I Memory_Ack [191 ] 191 +I DMA_READ [0 ] 0 +I DMA_WRITE [0 ] 0 + +S GETX [0 ] 0 +S GETS [0 ] 0 +S PUTX [0 ] 0 +S PUTO [0 ] 0 +S Memory_Data [0 ] 0 +S Memory_Ack [0 ] 0 +S DMA_READ [0 ] 0 +S DMA_WRITE [0 ] 0 + +O GETX [0 ] 0 +O GETS [0 ] 0 +O PUTX [0 ] 0 +O PUTO [0 ] 0 +O PUTO_SHARERS [0 ] 0 +O Memory_Data [0 ] 0 +O Memory_Ack [0 ] 0 +O DMA_READ [0 ] 0 +O DMA_WRITE [0 ] 0 + +M GETX [0 ] 0 +M GETS [0 ] 0 +M PUTX [1098 ] 1098 +M PUTO [0 ] 0 +M PUTO_SHARERS [0 ] 0 +M Memory_Data [0 ] 0 +M Memory_Ack [0 ] 0 +M DMA_READ [0 ] 0 +M DMA_WRITE [0 ] 0 + +IS GETX [0 ] 0 +IS GETS [0 ] 0 +IS PUTX [0 ] 0 +IS PUTO [0 ] 0 +IS PUTO_SHARERS [0 ] 0 +IS Unblock [0 ] 0 +IS Exclusive_Unblock [983 ] 983 +IS Memory_Data [983 ] 983 +IS Memory_Ack [2 ] 2 +IS DMA_READ [0 ] 0 +IS DMA_WRITE [0 ] 0 + +SS GETX [0 ] 0 +SS GETS [0 ] 0 +SS PUTX [0 ] 0 +SS PUTO [0 ] 0 +SS PUTO_SHARERS [0 ] 0 +SS Unblock [0 ] 0 +SS Last_Unblock [0 ] 0 +SS Memory_Data [0 ] 0 +SS Memory_Ack [0 ] 0 +SS DMA_READ [0 ] 0 +SS DMA_WRITE [0 ] 0 + +OO GETX [0 ] 0 +OO GETS [0 ] 0 +OO PUTX [0 ] 0 +OO PUTO [0 ] 0 +OO PUTO_SHARERS [0 ] 0 +OO Unblock [0 ] 0 +OO Last_Unblock [0 ] 0 +OO Memory_Data [0 ] 0 +OO Memory_Ack [0 ] 0 +OO DMA_READ [0 ] 0 +OO DMA_WRITE [0 ] 0 + +MO GETX [0 ] 0 +MO GETS [0 ] 0 +MO PUTX [0 ] 0 +MO PUTO [0 ] 0 +MO PUTO_SHARERS [0 ] 0 +MO Unblock [0 ] 0 +MO Exclusive_Unblock [0 ] 0 +MO Memory_Data [0 ] 0 +MO Memory_Ack [0 ] 0 +MO DMA_READ [0 ] 0 +MO DMA_WRITE [0 ] 0 + +MM GETX [0 ] 0 +MM GETS [0 ] 0 +MM PUTX [0 ] 0 +MM PUTO [0 ] 0 +MM PUTO_SHARERS [0 ] 0 +MM Exclusive_Unblock [131 ] 131 +MM Memory_Data [131 ] 131 +MM Memory_Ack [1 ] 1 +MM DMA_READ [0 ] 0 +MM DMA_WRITE [0 ] 0 + + +MI GETX [0 ] 0 +MI GETS [0 ] 0 +MI PUTX [0 ] 0 +MI PUTO [0 ] 0 +MI PUTO_SHARERS [0 ] 0 +MI Unblock [0 ] 0 +MI Clean_Writeback [904 ] 904 +MI Dirty_Writeback [194 ] 194 +MI Memory_Data [0 ] 0 +MI Memory_Ack [0 ] 0 +MI DMA_READ [0 ] 0 +MI DMA_WRITE [0 ] 0 + +MIS GETX [0 ] 0 +MIS GETS [0 ] 0 +MIS PUTX [0 ] 0 +MIS PUTO [0 ] 0 +MIS PUTO_SHARERS [0 ] 0 +MIS Unblock [0 ] 0 +MIS Clean_Writeback [0 ] 0 +MIS Dirty_Writeback [0 ] 0 +MIS Memory_Data [0 ] 0 +MIS Memory_Ack [0 ] 0 +MIS DMA_READ [0 ] 0 +MIS DMA_WRITE [0 ] 0 + +OS GETX [0 ] 0 +OS GETS [0 ] 0 +OS PUTX [0 ] 0 +OS PUTO [0 ] 0 +OS PUTO_SHARERS [0 ] 0 +OS Unblock [0 ] 0 +OS Clean_Writeback [0 ] 0 +OS Dirty_Writeback [0 ] 0 +OS Memory_Data [0 ] 0 +OS Memory_Ack [0 ] 0 +OS DMA_READ [0 ] 0 +OS DMA_WRITE [0 ] 0 + +OSS GETX [0 ] 0 +OSS GETS [0 ] 0 +OSS PUTX [0 ] 0 +OSS PUTO [0 ] 0 +OSS PUTO_SHARERS [0 ] 0 +OSS Unblock [0 ] 0 +OSS Clean_Writeback [0 ] 0 +OSS Dirty_Writeback [0 ] 0 +OSS Memory_Data [0 ] 0 +OSS Memory_Ack [0 ] 0 +OSS DMA_READ [0 ] 0 +OSS DMA_WRITE [0 ] 0 + +XI_M GETX [0 ] 0 +XI_M GETS [0 ] 0 +XI_M PUTX [0 ] 0 +XI_M PUTO [0 ] 0 +XI_M PUTO_SHARERS [0 ] 0 +XI_M Memory_Data [0 ] 0 +XI_M Memory_Ack [0 ] 0 +XI_M DMA_READ [0 ] 0 +XI_M DMA_WRITE [0 ] 0 + +XI_U GETX [0 ] 0 +XI_U GETS [0 ] 0 +XI_U PUTX [0 ] 0 +XI_U PUTO [0 ] 0 +XI_U PUTO_SHARERS [0 ] 0 +XI_U Exclusive_Unblock [0 ] 0 +XI_U Memory_Ack [0 ] 0 +XI_U DMA_READ [0 ] 0 +XI_U DMA_WRITE [0 ] 0 + +OI_D GETX [0 ] 0 +OI_D GETS [0 ] 0 +OI_D PUTX [0 ] 0 +OI_D PUTO [0 ] 0 +OI_D PUTO_SHARERS [0 ] 0 +OI_D DMA_READ [0 ] 0 +OI_D DMA_WRITE [0 ] 0 +OI_D Data
\ No newline at end of file diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simout b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simout index a5c547a14..7e21d792f 100755 --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simout +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jan 28 2010 14:49:51 -M5 revision 6068d4fc30d3+ 6931+ default qtip tip brad/rubycfg_regress_udpate -M5 started Jan 28 2010 15:08:13 -M5 executing on svvint05 +M5 compiled Aug 5 2010 10:34:54 +M5 revision 1cd2a169499f+ 7535+ default brad/hammer_merge_gets qtip tip +M5 started Aug 5 2010 10:35:39 +M5 executing on svvint09 command line: build/ALPHA_SE_MOESI_CMP_directory/m5.fast -d build/ALPHA_SE_MOESI_CMP_directory/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_directory -re tests/run.py build/ALPHA_SE_MOESI_CMP_directory/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_directory Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt index f1675ef82..add084384 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 11859 # Simulator instruction rate (inst/s) -host_mem_usage 216064 # Number of bytes of host memory used -host_seconds 0.55 # Real time elapsed on the host -host_tick_rate 407003 # Simulator tick rate (ticks/s) +host_inst_rate 23717 # Simulator instruction rate (inst/s) +host_mem_usage 212528 # Number of bytes of host memory used +host_seconds 0.27 # Real time elapsed on the host +host_tick_rate 829037 # Simulator tick rate (ticks/s) sim_freq 1000000000 # Frequency of simulated ticks sim_insts 6404 # Number of instructions simulated sim_seconds 0.000224 # Number of seconds simulated |