diff options
Diffstat (limited to 'tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token')
5 files changed, 114 insertions, 91 deletions
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/config.ini b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/config.ini index 9d759f6bf..e664ed4cf 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/config.ini +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/config.ini @@ -7,8 +7,10 @@ time_sync_spin_threshold=100000 [system] type=System -children=cpu dir_cntrl0 l1_cntrl0 l2_cntrl0 physmem ruby +children=cpu dir_cntrl0 l1_cntrl0 l2_cntrl0 physmem ruby sys_port_proxy mem_mode=timing +memories=system.physmem +num_work_ids=16 physmem=system.physmem work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 @@ -17,6 +19,7 @@ work_cpus_ckpt_count=0 work_end_ckpt_count=0 work_end_exit_count=0 work_item_id=-1 +system_port=system.sys_port_proxy.port[0] [system.cpu] type=TimingSimpleCPU @@ -41,8 +44,8 @@ progress_interval=0 system=system tracer=system.cpu.tracer workload=system.cpu.workload -dcache_port=system.ruby.cpu_ruby_ports.port[1] -icache_port=system.ruby.cpu_ruby_ports.port[0] +dcache_port=system.l1_cntrl0.sequencer.port[1] +icache_port=system.l1_cntrl0.sequencer.port[0] [system.cpu.dtb] type=AlphaTLB @@ -63,7 +66,7 @@ egid=100 env= errout=cerr euid=100 -executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/alpha/linux/hello +executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello gid=100 input=cin max_stack_size=67108864 @@ -87,6 +90,7 @@ l2_select_num_bits=0 memBuffer=system.dir_cntrl0.memBuffer number_of_TBEs=256 recycle_latency=10 +ruby_system=system.ruby transitions_per_cycle=32 version=0 @@ -121,7 +125,7 @@ version=0 [system.l1_cntrl0] type=L1Cache_Controller -children=L1DcacheMemory L1IcacheMemory +children=L1DcacheMemory L1IcacheMemory sequencer L1DcacheMemory=system.l1_cntrl0.L1DcacheMemory L1IcacheMemory=system.l1_cntrl0.L1IcacheMemory N_tokens=2 @@ -136,13 +140,15 @@ no_mig_atomic=true number_of_TBEs=256 recycle_latency=10 retry_threshold=1 -sequencer=system.ruby.cpu_ruby_ports +ruby_system=system.ruby +sequencer=system.l1_cntrl0.sequencer transitions_per_cycle=32 version=0 [system.l1_cntrl0.L1DcacheMemory] type=RubyCache assoc=2 +is_icache=false latency=2 replacement_policy=PSEUDO_LRU size=256 @@ -151,11 +157,27 @@ start_index_bit=6 [system.l1_cntrl0.L1IcacheMemory] type=RubyCache assoc=2 +is_icache=false latency=2 replacement_policy=PSEUDO_LRU size=256 start_index_bit=6 +[system.l1_cntrl0.sequencer] +type=RubySequencer +access_phys_mem=true +dcache=system.l1_cntrl0.L1DcacheMemory +deadlock_threshold=500000 +icache=system.l1_cntrl0.L1IcacheMemory +max_outstanding_requests=16 +physmem=system.physmem +ruby_system=system.ruby +using_network_tester=false +using_ruby_tester=false +version=0 +physMemPort=system.physmem.port[0] +port=system.cpu.icache_port system.cpu.dcache_port + [system.l2_cntrl0] type=L2Cache_Controller children=L2cacheMemory @@ -168,12 +190,14 @@ l2_request_latency=5 l2_response_latency=5 number_of_TBEs=256 recycle_latency=10 +ruby_system=system.ruby transitions_per_cycle=32 version=0 [system.l2_cntrl0.L2cacheMemory] type=RubyCache assoc=2 +is_icache=false latency=10 replacement_policy=PSEUDO_LRU size=512 @@ -187,35 +211,18 @@ latency_var=0 null=false range=0:134217727 zero=false -port=system.ruby.cpu_ruby_ports.physMemPort +port=system.l1_cntrl0.sequencer.physMemPort system.sys_port_proxy.physMemPort [system.ruby] type=RubySystem -children=cpu_ruby_ports network profiler tracer +children=network profiler block_size_bytes=64 clock=1 mem_size=134217728 -network=system.ruby.network no_mem_vec=false -profiler=system.ruby.profiler random_seed=1234 randomization=false stats_filename=ruby.stats -tracer=system.ruby.tracer - -[system.ruby.cpu_ruby_ports] -type=RubySequencer -access_phys_mem=true -dcache=system.l1_cntrl0.L1DcacheMemory -deadlock_threshold=500000 -icache=system.l1_cntrl0.L1IcacheMemory -max_outstanding_requests=16 -physmem=system.physmem -using_network_tester=false -using_ruby_tester=false -version=0 -physMemPort=system.physmem.port[0] -port=system.cpu.icache_port system.cpu.dcache_port [system.ruby.network] type=SimpleNetwork @@ -225,6 +232,7 @@ buffer_size=0 control_msg_size=8 endpoint_bandwidth=1000 number_of_virtual_networks=10 +ruby_system=system.ruby topology=system.ruby.network.topology [system.ruby.network.topology] @@ -311,8 +319,16 @@ type=RubyProfiler all_instructions=false hot_lines=false num_of_sequencers=1 +ruby_system=system.ruby -[system.ruby.tracer] -type=RubyTracer -warmup_length=100000 +[system.sys_port_proxy] +type=RubyPortProxy +access_phys_mem=true +physmem=system.physmem +ruby_system=system.ruby +using_network_tester=false +using_ruby_tester=false +version=0 +physMemPort=system.physmem.port[1] +port=system.system_port diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/ruby.stats b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/ruby.stats index c3749a713..216172e7b 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/ruby.stats +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/ruby.stats @@ -34,7 +34,7 @@ periodic_stats_period: 1000000 ================ End RubySystem Configuration Print ================ -Real time: Apr/28/2011 15:03:53 +Real time: Jan/23/2012 04:22:26 Profiler Stats -------------- @@ -43,18 +43,18 @@ Elapsed_time_in_minutes: 0.0166667 Elapsed_time_in_hours: 0.000277778 Elapsed_time_in_days: 1.15741e-05 -Virtual_time_in_seconds: 0.55 -Virtual_time_in_minutes: 0.00916667 -Virtual_time_in_hours: 0.000152778 -Virtual_time_in_days: 6.36574e-06 +Virtual_time_in_seconds: 0.31 +Virtual_time_in_minutes: 0.00516667 +Virtual_time_in_hours: 8.61111e-05 +Virtual_time_in_days: 3.58796e-06 Ruby_current_time: 231701 Ruby_start_time: 0 Ruby_cycles: 231701 -mbytes_resident: 39.457 -mbytes_total: 222.211 -resident_ratio: 0.177618 +mbytes_resident: 44.0234 +mbytes_total: 212.691 +resident_ratio: 0.206983 ruby_cycles_executed: [ 231702 ] @@ -127,11 +127,11 @@ Resource Usage page_size: 4096 user_time: 0 system_time: 0 -page_reclaims: 11316 -page_faults: 0 +page_reclaims: 11434 +page_faults: 122 swaps: 0 -block_inputs: 0 -block_outputs: 0 +block_inputs: 21928 +block_outputs: 104 Network Stats ------------- @@ -1039,4 +1039,5 @@ DR_L Tokens [0 ] 0 DR_L Request_Timeout [0 ] 0 DR_L DMA_READ [0 ] 0 DR_L DMA_WRITE [0 ] 0 -DR_L DMA_WRITE_All_Tokens
\ No newline at end of file +DR_L DMA_WRITE_All_Tokens [0 ] 0 + diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simerr b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simerr index eabe42249..e45cd058f 100755 --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simerr +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simerr @@ -1,3 +1,2 @@ warn: Sockets disabled, not accepting gdb connections -For more information see: http://www.m5sim.org/warn/d946bea6 hack: be nice to actually delete the event here diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simout b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simout index 8c53e7b8f..6ef144b06 100755 --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simout +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simout @@ -1,14 +1,10 @@ -M5 Simulator System +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. -Copyright (c) 2001-2008 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled Apr 28 2011 15:03:17 -M5 started Apr 28 2011 15:03:52 -M5 executing on SC2B0617 -command line: build/ALPHA_SE_MOESI_CMP_token/m5.opt -d build/ALPHA_SE_MOESI_CMP_token/tests/opt/quick/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_token -re tests/run.py build/ALPHA_SE_MOESI_CMP_token/tests/opt/quick/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_token +gem5 compiled Jan 23 2012 03:50:16 +gem5 started Jan 23 2012 04:22:25 +gem5 executing on zizzer +command line: build/ALPHA_SE_MOESI_CMP_token/gem5.opt -d build/ALPHA_SE_MOESI_CMP_token/tests/opt/quick/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_token -re tests/run.py build/ALPHA_SE_MOESI_CMP_token/tests/opt/quick/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_token Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/stats.txt b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/stats.txt index a5ec386b7..4911f0b0e 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/stats.txt +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/stats.txt @@ -1,66 +1,77 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 32190 # Simulator instruction rate (inst/s) -host_mem_usage 227548 # Number of bytes of host memory used -host_seconds 0.20 # Real time elapsed on the host -host_tick_rate 1163713 # Simulator tick rate (ticks/s) -sim_freq 1000000000 # Frequency of simulated ticks -sim_insts 6404 # Number of instructions simulated sim_seconds 0.000232 # Number of seconds simulated sim_ticks 231701 # Number of ticks simulated -system.cpu.dtb.data_accesses 2060 # DTB accesses -system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_hits 2050 # DTB hits -system.cpu.dtb.data_misses 10 # DTB misses -system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.fetch_acv 0 # ITB acv +final_tick 231701 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000 # Frequency of simulated ticks +host_inst_rate 23819 # Simulator instruction rate (inst/s) +host_tick_rate 861729 # Simulator tick rate (ticks/s) +host_mem_usage 217800 # Number of bytes of host memory used +host_seconds 0.27 # Real time elapsed on the host +sim_insts 6404 # Number of instructions simulated +system.physmem.bytes_read 34460 # Number of bytes read from this memory +system.physmem.bytes_inst_read 25656 # Number of instructions bytes read from this memory +system.physmem.bytes_written 6696 # Number of bytes written to this memory +system.physmem.num_reads 7599 # Number of read requests responded to by this memory +system.physmem.num_writes 865 # Number of write requests responded to by this memory +system.physmem.num_other 0 # Number of other requests responded to by this memory +system.physmem.bw_read 148726160 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 110728914 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write 28899314 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total 177625474 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.read_accesses 1192 # DTB read accesses -system.cpu.dtb.read_acv 0 # DTB read access violations +system.cpu.dtb.fetch_acv 0 # ITB acv +system.cpu.dtb.fetch_accesses 0 # ITB accesses system.cpu.dtb.read_hits 1185 # DTB read hits system.cpu.dtb.read_misses 7 # DTB read misses -system.cpu.dtb.write_accesses 868 # DTB write accesses -system.cpu.dtb.write_acv 0 # DTB write access violations +system.cpu.dtb.read_acv 0 # DTB read access violations +system.cpu.dtb.read_accesses 1192 # DTB read accesses system.cpu.dtb.write_hits 865 # DTB write hits system.cpu.dtb.write_misses 3 # DTB write misses -system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.itb.data_acv 0 # DTB access violations -system.cpu.itb.data_hits 0 # DTB hits -system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.fetch_accesses 6432 # ITB accesses -system.cpu.itb.fetch_acv 0 # ITB acv +system.cpu.dtb.write_acv 0 # DTB write access violations +system.cpu.dtb.write_accesses 868 # DTB write accesses +system.cpu.dtb.data_hits 2050 # DTB hits +system.cpu.dtb.data_misses 10 # DTB misses +system.cpu.dtb.data_acv 0 # DTB access violations +system.cpu.dtb.data_accesses 2060 # DTB accesses system.cpu.itb.fetch_hits 6415 # ITB hits system.cpu.itb.fetch_misses 17 # ITB misses -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.read_acv 0 # DTB read access violations +system.cpu.itb.fetch_acv 0 # ITB acv +system.cpu.itb.fetch_accesses 6432 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.write_acv 0 # DTB write access violations +system.cpu.itb.read_acv 0 # DTB read access violations +system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.itb.write_acv 0 # DTB write access violations +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.data_hits 0 # DTB hits +system.cpu.itb.data_misses 0 # DTB misses +system.cpu.itb.data_acv 0 # DTB access violations +system.cpu.itb.data_accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 17 # Number of system calls system.cpu.numCycles 231701 # number of cpu cycles simulated -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.num_busy_cycles 231701 # Number of busy cycles -system.cpu.num_conditional_control_insts 750 # number of instructions that are conditional controls -system.cpu.num_fp_alu_accesses 10 # Number of float alu accesses -system.cpu.num_fp_insts 10 # number of float instructions -system.cpu.num_fp_register_reads 8 # number of times the floating registers were read -system.cpu.num_fp_register_writes 2 # number of times the floating registers were written -system.cpu.num_func_calls 251 # number of times a function call or return occured -system.cpu.num_idle_cycles 0 # Number of idle cycles +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.num_insts 6404 # Number of instructions executed system.cpu.num_int_alu_accesses 6331 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 10 # Number of float alu accesses +system.cpu.num_func_calls 251 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 750 # number of instructions that are conditional controls system.cpu.num_int_insts 6331 # number of integer instructions +system.cpu.num_fp_insts 10 # number of float instructions system.cpu.num_int_register_reads 8304 # number of times the integer registers were read system.cpu.num_int_register_writes 4581 # number of times the integer registers were written -system.cpu.num_load_insts 1192 # Number of load instructions +system.cpu.num_fp_register_reads 8 # number of times the floating registers were read +system.cpu.num_fp_register_writes 2 # number of times the floating registers were written system.cpu.num_mem_refs 2060 # number of memory refs +system.cpu.num_load_insts 1192 # Number of load instructions system.cpu.num_store_insts 868 # Number of store instructions -system.cpu.workload.num_syscalls 17 # Number of system calls +system.cpu.num_idle_cycles 0 # Number of idle cycles +system.cpu.num_busy_cycles 231701 # Number of busy cycles +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.idle_fraction 0 # Percentage of idle cycles ---------- End Simulation Statistics ---------- |