diff options
Diffstat (limited to 'tests/quick/00.hello/ref/alpha/linux/simple-timing')
| -rw-r--r-- | tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt | 106 | ||||
| -rw-r--r-- | tests/quick/00.hello/ref/alpha/linux/simple-timing/stdout | 8 |
2 files changed, 57 insertions, 57 deletions
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt b/tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt index 6914938e5..6ab4e0920 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt @@ -1,31 +1,31 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 152920 # Simulator instruction rate (inst/s) -host_mem_usage 166272 # Number of bytes of host memory used -host_seconds 0.04 # Real time elapsed on the host -host_tick_rate 221766 # Simulator tick rate (ticks/s) +host_inst_rate 8293 # Simulator instruction rate (inst/s) +host_mem_usage 179892 # Number of bytes of host memory used +host_seconds 0.68 # Real time elapsed on the host +host_tick_rate 2595779 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 5642 # Number of instructions simulated -sim_seconds 0.000000 # Number of seconds simulated -sim_ticks 8316 # Number of ticks simulated +sim_seconds 0.000002 # Number of seconds simulated +sim_ticks 1767066 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 979 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 3 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_miss_latency 3990.760870 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2990.760870 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_hits 887 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 276 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency 367150 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.093973 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 92 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 184 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 275150 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.093973 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 92 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 812 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 3 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 3977.109589 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2977.109589 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_hits 739 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 219 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 290329 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.089901 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses 73 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 146 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 217329 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.089901 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 73 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked @@ -37,29 +37,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 1791 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 3 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 2 # average overall mshr miss latency +system.cpu.dcache.demand_avg_miss_latency 3984.721212 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 2984.721212 # average overall mshr miss latency system.cpu.dcache.demand_hits 1626 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 495 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency 657479 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.092127 # miss rate for demand accesses system.cpu.dcache.demand_misses 165 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 330 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 492479 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.092127 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 165 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.overall_accesses 1791 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 3 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 2 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_miss_latency 3984.721212 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 2984.721212 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 1626 # number of overall hits -system.cpu.dcache.overall_miss_latency 495 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency 657479 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.092127 # miss rate for overall accesses system.cpu.dcache.overall_misses 165 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 330 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 492479 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.092127 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 165 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -76,18 +76,18 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.sampled_refs 165 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 107.125526 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 97.858233 # Cycle average of tags in use system.cpu.dcache.total_refs 1626 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks system.cpu.icache.ReadReq_accesses 5643 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 2.996390 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 1.996390 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_miss_latency 3980.490975 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 2980.490975 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_hits 5366 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 830 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency 1102596 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.049087 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 277 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 553 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 825596 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.049087 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 277 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked @@ -99,29 +99,29 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.demand_accesses 5643 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 2.996390 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 1.996390 # average overall mshr miss latency +system.cpu.icache.demand_avg_miss_latency 3980.490975 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 2980.490975 # average overall mshr miss latency system.cpu.icache.demand_hits 5366 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 830 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency 1102596 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.049087 # miss rate for demand accesses system.cpu.icache.demand_misses 277 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 553 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 825596 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.049087 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 277 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.overall_accesses 5643 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 2.996390 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 1.996390 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.icache.overall_avg_miss_latency 3980.490975 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 2980.490975 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency system.cpu.icache.overall_hits 5366 # number of overall hits -system.cpu.icache.overall_miss_latency 830 # number of overall miss cycles +system.cpu.icache.overall_miss_latency 1102596 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.049087 # miss rate for overall accesses system.cpu.icache.overall_misses 277 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 553 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 825596 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.049087 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 277 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -138,19 +138,19 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.icache.replacements 0 # number of replacements system.cpu.icache.sampled_refs 277 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 133.213539 # Cycle average of tags in use +system.cpu.icache.tagsinuse 122.802112 # Cycle average of tags in use system.cpu.icache.total_refs 5366 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.l2cache.ReadReq_accesses 442 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 2 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency 2984.340136 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1983.340136 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 1 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 882 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency 1316094 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 0.997738 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_misses 441 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 441 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 874653 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 0.997738 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 441 # number of ReadReq MSHR misses system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked @@ -162,29 +162,29 @@ system.cpu.l2cache.blocked_cycles_no_mshrs 0 # system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 442 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 2 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 1 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_miss_latency 2984.340136 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 1983.340136 # average overall mshr miss latency system.cpu.l2cache.demand_hits 1 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 882 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency 1316094 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate 0.997738 # miss rate for demand accesses system.cpu.l2cache.demand_misses 441 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 441 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 874653 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_rate 0.997738 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_misses 441 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.overall_accesses 442 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 2 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 1 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_miss_latency 2984.340136 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 1983.340136 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 1 # number of overall hits -system.cpu.l2cache.overall_miss_latency 882 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency 1316094 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 0.997738 # miss rate for overall accesses system.cpu.l2cache.overall_misses 441 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 441 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 874653 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_rate 0.997738 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_misses 441 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -201,12 +201,12 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.sampled_refs 441 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 240.276061 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 220.802916 # Cycle average of tags in use system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 8316 # number of cpu cycles simulated +system.cpu.numCycles 1767066 # number of cpu cycles simulated system.cpu.num_insts 5642 # Number of instructions executed system.cpu.num_refs 1792 # Number of memory references system.cpu.workload.PROG:num_syscalls 17 # Number of system calls diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing/stdout b/tests/quick/00.hello/ref/alpha/linux/simple-timing/stdout index 423c0b115..31db8804a 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing/stdout +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing/stdout @@ -6,8 +6,8 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Oct 10 2006 01:56:36 -M5 started Tue Oct 10 01:57:04 2006 +M5 compiled Oct 13 2006 16:07:10 +M5 started Fri Oct 13 16:08:16 2006 M5 executing on zizzer.eecs.umich.edu -command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/simple-timing tests/run.py quick/00.hello/alpha/linux/simple-timing -Exiting @ tick 8316 because target called exit() +command line: build/ALPHA_SE/m5.debug -d build/ALPHA_SE/tests/debug/quick/00.hello/alpha/linux/simple-timing tests/run.py quick/00.hello/alpha/linux/simple-timing +Exiting @ tick 1767066 because target called exit() |