diff options
Diffstat (limited to 'tests/quick/00.hello/ref/alpha/linux')
| -rwxr-xr-x | tests/quick/00.hello/ref/alpha/linux/o3-timing/simout | 6 | ||||
| -rw-r--r-- | tests/quick/00.hello/ref/alpha/linux/o3-timing/stats.txt | 11 |
2 files changed, 9 insertions, 8 deletions
diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/simout b/tests/quick/00.hello/ref/alpha/linux/o3-timing/simout index c56e2a305..7b6a1125b 100755 --- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/simout +++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/simout @@ -5,9 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Nov 15 2010 08:52:32 -M5 revision f440cdaf1c2d+ 7743+ default tip -M5 started Nov 15 2010 13:43:59 +M5 compiled Jan 17 2011 16:24:53 +M5 revision f72d94f8c275 7839 default qtip tip outgoing.patch qbase +M5 started Jan 17 2011 16:24:57 M5 executing on zizzer command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/o3-timing Global frequency set at 1000000000000 ticks per second diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/00.hello/ref/alpha/linux/o3-timing/stats.txt index 70e07c2b3..72be64488 100644 --- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/stats.txt +++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 34451 # Simulator instruction rate (inst/s) -host_mem_usage 203748 # Number of bytes of host memory used -host_seconds 0.19 # Real time elapsed on the host -host_tick_rate 66857161 # Simulator tick rate (ticks/s) +host_inst_rate 10121 # Simulator instruction rate (inst/s) +host_mem_usage 203516 # Number of bytes of host memory used +host_seconds 0.63 # Real time elapsed on the host +host_tick_rate 19665204 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 6386 # Number of instructions simulated sim_seconds 0.000012 # Number of seconds simulated @@ -143,9 +143,10 @@ system.cpu.dtb.write_hits 1051 # DT system.cpu.dtb.write_misses 25 # DTB write misses system.cpu.fetch.Branches 2222 # Number of branches that fetch encountered system.cpu.fetch.CacheLines 1774 # Number of cache lines fetched -system.cpu.fetch.Cycles 4193 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.Cycles 2385 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.IcacheSquashes 267 # Number of outstanding Icache misses that were squashed system.cpu.fetch.Insts 13186 # Number of instructions fetch has processed +system.cpu.fetch.MiscStallCycles 34 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.SquashCycles 503 # Number of cycles fetch has spent squashing system.cpu.fetch.branchRate 0.089503 # Number of branch fetches per cycle system.cpu.fetch.icacheStallCycles 1774 # Number of cycles fetch is stalled on an Icache miss |