diff options
Diffstat (limited to 'tests/quick/00.hello/ref/alpha/linux')
29 files changed, 5135 insertions, 850 deletions
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-atomic-ruby/config.ini b/tests/quick/00.hello/ref/alpha/linux/simple-atomic-ruby/config.ini deleted file mode 100644 index ab3ec5af6..000000000 --- a/tests/quick/00.hello/ref/alpha/linux/simple-atomic-ruby/config.ini +++ /dev/null @@ -1,97 +0,0 @@ -[root] -type=Root -children=system -dummy=0 - -[system] -type=System -children=cpu membus physmem -mem_mode=atomic -physmem=system.physmem - -[system.cpu] -type=AtomicSimpleCPU -children=dtb itb tracer workload -checker=Null -clock=500 -cpu_id=0 -defer_registration=false -do_checkpoint_insts=true -do_statistics_insts=true -dtb=system.cpu.dtb -function_trace=false -function_trace_start=0 -itb=system.cpu.itb -max_insts_all_threads=0 -max_insts_any_thread=0 -max_loads_all_threads=0 -max_loads_any_thread=0 -numThreads=1 -phase=0 -progress_interval=0 -simulate_data_stalls=false -simulate_inst_stalls=false -system=system -tracer=system.cpu.tracer -width=1 -workload=system.cpu.workload -dcache_port=system.membus.port[2] -icache_port=system.membus.port[1] - -[system.cpu.dtb] -type=AlphaTLB -size=64 - -[system.cpu.itb] -type=AlphaTLB -size=48 - -[system.cpu.tracer] -type=ExeTracer - -[system.cpu.workload] -type=LiveProcess -cmd=hello -cwd= -egid=100 -env= -errout=cerr -euid=100 -executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello -gid=100 -input=cin -max_stack_size=67108864 -output=cout -pid=100 -ppid=99 -simpoint=0 -system=system -uid=100 - -[system.membus] -type=Bus -block_size=64 -bus_id=0 -clock=1000 -header_cycles=1 -responder_set=false -width=64 -port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port - -[system.physmem] -type=RubyMemory -clock=1 -config_file=build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-atomic-ruby/ruby.config -debug=false -debug_file=ruby.debug -file= -latency=30000 -latency_var=0 -null=false -num_cpus=1 -phase=0 -range=0:134217727 -stats_file=ruby.stats -zero=false -port=system.membus.port[0] - diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-atomic-ruby/ruby.stats b/tests/quick/00.hello/ref/alpha/linux/simple-atomic-ruby/ruby.stats deleted file mode 100644 index 3d5408511..000000000 --- a/tests/quick/00.hello/ref/alpha/linux/simple-atomic-ruby/ruby.stats +++ /dev/null @@ -1,382 +0,0 @@ - -================ Begin RubySystem Configuration Print ================ - -RubySystem config: - random_seed: 952703 - randomization: 0 - tech_nm: 45 - freq_mhz: 3000 - block_size_bytes: 64 - block_size_bits: 6 - memory_size_bytes: 1073741824 - memory_size_bits: 30 -DMA_Controller config: DMAController_0 - version: 0 - buffer_size: 32 - dma_sequencer: DMASequencer_0 - number_of_TBEs: 128 - transitions_per_cycle: 32 -Directory_Controller config: DirectoryController_0 - version: 0 - buffer_size: 32 - directory_latency: 6 - directory_name: DirectoryMemory_0 - memory_controller_name: MemoryControl_0 - memory_latency: 158 - number_of_TBEs: 128 - recycle_latency: 10 - to_mem_ctrl_latency: 1 - transitions_per_cycle: 32 -L1Cache_Controller config: L1CacheController_0 - version: 0 - buffer_size: 32 - cache: l1u_0 - cache_response_latency: 12 - issue_latency: 2 - number_of_TBEs: 128 - sequencer: Sequencer_0 - transitions_per_cycle: 32 -Cache config: l1u_0 - controller: L1CacheController_0 - cache_associativity: 8 - num_cache_sets_bits: 2 - num_cache_sets: 4 - cache_set_size_bytes: 256 - cache_set_size_Kbytes: 0.25 - cache_set_size_Mbytes: 0.000244141 - cache_size_bytes: 2048 - cache_size_Kbytes: 2 - cache_size_Mbytes: 0.00195312 -DirectoryMemory Global Config: - number of directory memories: 1 - total memory size bytes: 1073741824 - total memory size bits: 30 -DirectoryMemory module config: DirectoryMemory_0 - controller: DirectoryController_0 - version: 0 - memory_bits: 30 - memory_size_bytes: 1073741824 - memory_size_Kbytes: 1.04858e+06 - memory_size_Mbytes: 1024 - memory_size_Gbytes: 1 -Seqeuncer config: Sequencer_0 - controller: L1CacheController_0 - version: 0 - max_outstanding_requests: 16 - deadlock_threshold: 500000 - -Network Configuration ---------------------- -network: SIMPLE_NETWORK -topology: theTopology - -virtual_net_0: active, ordered -virtual_net_1: active, ordered -virtual_net_2: active, ordered -virtual_net_3: inactive -virtual_net_4: active, ordered -virtual_net_5: active, ordered - ---- Begin Topology Print --- - -Topology print ONLY indicates the _NETWORK_ latency between two machines -It does NOT include the latency within the machines - -L1Cache-0 Network Latencies - L1Cache-0 -> Directory-0 net_lat: 7 - L1Cache-0 -> DMA-0 net_lat: 7 - -Directory-0 Network Latencies - Directory-0 -> L1Cache-0 net_lat: 7 - Directory-0 -> DMA-0 net_lat: 7 - -DMA-0 Network Latencies - DMA-0 -> L1Cache-0 net_lat: 7 - DMA-0 -> Directory-0 net_lat: 7 - ---- End Topology Print --- - -Profiler Configuration ----------------------- -periodic_stats_period: 1000000 - -================ End RubySystem Configuration Print ================ - - -Real time: Jul/06/2009 11:11:07 - -Profiler Stats --------------- -Elapsed_time_in_seconds: 1 -Elapsed_time_in_minutes: 0.0166667 -Elapsed_time_in_hours: 0.000277778 -Elapsed_time_in_days: 1.15741e-05 - -Virtual_time_in_seconds: 0.2 -Virtual_time_in_minutes: 0.00333333 -Virtual_time_in_hours: 5.55556e-05 -Virtual_time_in_days: 5.55556e-05 - -Ruby_current_time: 3215001 -Ruby_start_time: 1 -Ruby_cycles: 3215000 - -mbytes_resident: 144.742 -mbytes_total: 1329.5 -resident_ratio: 0.108872 - -Total_misses: 0 -total_misses: 0 [ 0 ] -user_misses: 0 [ 0 ] -supervisor_misses: 0 [ 0 ] - -instruction_executed: 1 [ 1 ] -ruby_cycles_executed: 3215001 [ 3215001 ] -cycles_per_instruction: 3.215e+06 [ 3.215e+06 ] -misses_per_thousand_instructions: 0 [ 0 ] - -transactions_started: 0 [ 0 ] -transactions_ended: 0 [ 0 ] -instructions_per_transaction: 0 [ 0 ] -cycles_per_transaction: 0 [ 0 ] -misses_per_transaction: 0 [ 0 ] - -L1D_cache cache stats: - L1D_cache_total_misses: 0 - L1D_cache_total_demand_misses: 0 - L1D_cache_total_prefetches: 0 - L1D_cache_total_sw_prefetches: 0 - L1D_cache_total_hw_prefetches: 0 - L1D_cache_misses_per_transaction: 0 - L1D_cache_misses_per_instruction: 0 - L1D_cache_instructions_per_misses: NaN - - L1D_cache_request_size: [binsize: log2 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - -L1I_cache cache stats: - L1I_cache_total_misses: 0 - L1I_cache_total_demand_misses: 0 - L1I_cache_total_prefetches: 0 - L1I_cache_total_sw_prefetches: 0 - L1I_cache_total_hw_prefetches: 0 - L1I_cache_misses_per_transaction: 0 - L1I_cache_misses_per_instruction: 0 - L1I_cache_instructions_per_misses: NaN - - L1I_cache_request_size: [binsize: log2 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - -L2_cache cache stats: - L2_cache_total_misses: 0 - L2_cache_total_demand_misses: 0 - L2_cache_total_prefetches: 0 - L2_cache_total_sw_prefetches: 0 - L2_cache_total_hw_prefetches: 0 - L2_cache_misses_per_transaction: 0 - L2_cache_misses_per_instruction: 0 - L2_cache_instructions_per_misses: NaN - - L2_cache_request_size: [binsize: log2 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - - -Busy Controller Counts: -L1Cache-0:0 -Directory-0:0 -DMA-0:0 - -Busy Bank Count:0 - -L1TBE_usage: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] -L2TBE_usage: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] -StopTable_usage: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] -sequencer_requests_outstanding: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] -store_buffer_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] -unique_blocks_in_store_buffer: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - -All Non-Zero Cycle Demand Cache Accesses ----------------------------------------- -miss_latency: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] -miss_latency_L2Miss: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - -All Non-Zero Cycle SW Prefetch Requests ------------------------------------- -prefetch_latency: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] -prefetch_latency_L2Miss:[binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] -multicast_retries: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] -gets_mask_prediction_count: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] -getx_mask_prediction_count: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] -explicit_training_mask: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - -Request vs. RubySystem State Profile --------------------------------- - - -filter_action: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - -Message Delayed Cycles ----------------------- -Total_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] -Total_nonPF_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - virtual_network_0_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - virtual_network_1_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - virtual_network_2_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - virtual_network_3_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - virtual_network_4_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - virtual_network_5_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - -Resource Usage --------------- -page_size: 4096 -user_time: 0 -system_time: 0 -page_reclaims: 37817 -page_faults: 0 -swaps: 0 -block_inputs: 0 -block_outputs: 40 - -Network Stats -------------- - -switch_0_inlinks: 2 -switch_0_outlinks: 2 -links_utilized_percent_switch_0: 0 - links_utilized_percent_switch_0_link_0: 0 bw: 640000 base_latency: 1 - links_utilized_percent_switch_0_link_1: 0 bw: 160000 base_latency: 1 - - -switch_1_inlinks: 2 -switch_1_outlinks: 2 -links_utilized_percent_switch_1: 0 - links_utilized_percent_switch_1_link_0: 0 bw: 640000 base_latency: 1 - links_utilized_percent_switch_1_link_1: 0 bw: 160000 base_latency: 1 - - -switch_2_inlinks: 2 -switch_2_outlinks: 2 -links_utilized_percent_switch_2: 0 - links_utilized_percent_switch_2_link_0: 0 bw: 640000 base_latency: 1 - links_utilized_percent_switch_2_link_1: 0 bw: 160000 base_latency: 1 - - -switch_3_inlinks: 3 -switch_3_outlinks: 3 -links_utilized_percent_switch_3: 0 - links_utilized_percent_switch_3_link_0: 0 bw: 160000 base_latency: 1 - links_utilized_percent_switch_3_link_1: 0 bw: 160000 base_latency: 1 - links_utilized_percent_switch_3_link_2: 0 bw: 160000 base_latency: 1 - - - --- DMA --- - - Event Counts - -ReadRequest 0 -WriteRequest 0 -Data 0 -Ack 0 - - - Transitions - -READY ReadRequest 0 <-- -READY WriteRequest 0 <-- - -BUSY_RD Data 0 <-- - -BUSY_WR Ack 0 <-- - - --- Directory --- - - Event Counts - -GETX 0 -GETS 0 -PUTX 0 -PUTX_NotOwner 0 -DMA_READ 0 -DMA_WRITE 0 -Memory_Data 0 -Memory_Ack 0 - - - Transitions - -I GETX 0 <-- -I PUTX_NotOwner 0 <-- -I DMA_READ 0 <-- -I DMA_WRITE 0 <-- - -M GETX 0 <-- -M PUTX 0 <-- -M PUTX_NotOwner 0 <-- -M DMA_READ 0 <-- -M DMA_WRITE 0 <-- - -M_DRD GETX 0 <-- -M_DRD PUTX 0 <-- - -M_DWR GETX 0 <-- -M_DWR PUTX 0 <-- - -M_DWRI Memory_Ack 0 <-- - -IM GETX 0 <-- -IM GETS 0 <-- -IM PUTX 0 <-- -IM PUTX_NotOwner 0 <-- -IM DMA_READ 0 <-- -IM DMA_WRITE 0 <-- -IM Memory_Data 0 <-- - -MI GETX 0 <-- -MI GETS 0 <-- -MI PUTX 0 <-- -MI PUTX_NotOwner 0 <-- -MI DMA_READ 0 <-- -MI DMA_WRITE 0 <-- -MI Memory_Ack 0 <-- - -ID GETX 0 <-- -ID GETS 0 <-- -ID PUTX 0 <-- -ID PUTX_NotOwner 0 <-- -ID DMA_READ 0 <-- -ID DMA_WRITE 0 <-- -ID Memory_Data 0 <-- - -ID_W GETX 0 <-- -ID_W GETS 0 <-- -ID_W PUTX 0 <-- -ID_W PUTX_NotOwner 0 <-- -ID_W DMA_READ 0 <-- -ID_W DMA_WRITE 0 <-- -ID_W Memory_Ack 0 <-- - - --- L1Cache --- - - Event Counts - -Load 0 -Ifetch 0 -Store 0 -Data 0 -Fwd_GETX 0 -Inv 0 -Replacement 0 -Writeback_Ack 0 -Writeback_Nack 0 - - - Transitions - -I Load 0 <-- -I Ifetch 0 <-- -I Store 0 <-- -I Inv 0 <-- -I Replacement 0 <-- - -II Writeback_Nack 0 <-- - -M Load 0 <-- -M Ifetch 0 <-- -M Store 0 <-- -M Fwd_GETX 0 <-- -M Inv 0 <-- -M Replacement 0 <-- - -MI Fwd_GETX 0 <-- -MI Inv 0 <-- -MI Writeback_Ack 0 <-- - -IS Data 0 <-- - -IM Data 0 <-- - diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-atomic-ruby/simerr b/tests/quick/00.hello/ref/alpha/linux/simple-atomic-ruby/simerr deleted file mode 100755 index 187d1a0ac..000000000 --- a/tests/quick/00.hello/ref/alpha/linux/simple-atomic-ruby/simerr +++ /dev/null @@ -1,23 +0,0 @@ -["-r", "tests/configs/../../src/mem/ruby/config/MI_example-homogeneous.rb", "-p", "1", "-m", "1", "-s", "1024"] -print config: 1 -Creating new MessageBuffer for 0 0 -Creating new MessageBuffer for 0 1 -Creating new MessageBuffer for 0 2 -Creating new MessageBuffer for 0 3 -Creating new MessageBuffer for 0 4 -Creating new MessageBuffer for 0 5 -Creating new MessageBuffer for 1 0 -Creating new MessageBuffer for 1 1 -Creating new MessageBuffer for 1 2 -Creating new MessageBuffer for 1 3 -Creating new MessageBuffer for 1 4 -Creating new MessageBuffer for 1 5 -Creating new MessageBuffer for 2 0 -Creating new MessageBuffer for 2 1 -Creating new MessageBuffer for 2 2 -Creating new MessageBuffer for 2 3 -Creating new MessageBuffer for 2 4 -Creating new MessageBuffer for 2 5 -warn: Sockets disabled, not accepting gdb connections -For more information see: http://www.m5sim.org/warn/d946bea6 -hack: be nice to actually delete the event here diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-atomic-ruby/simout b/tests/quick/00.hello/ref/alpha/linux/simple-atomic-ruby/simout deleted file mode 100755 index 71c530534..000000000 --- a/tests/quick/00.hello/ref/alpha/linux/simple-atomic-ruby/simout +++ /dev/null @@ -1,18 +0,0 @@ -M5 Simulator System - -Copyright (c) 2001-2008 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled Jul 6 2009 11:03:45 -M5 revision d3635cac686a 6289 default ruby_refs.diff qtip tip -M5 started Jul 6 2009 11:11:06 -M5 executing on maize -command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-atomic-ruby -re tests/run.py build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-atomic-ruby -Global frequency set at 1000000000000 ticks per second - Debug: Adding to filter: 'q' (Queue) -info: Entering event queue @ 0. Starting simulation... -info: Increasing stack size by one page. -Hello world! -Exiting @ tick 3215000 because target called exit() diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/config.ini b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/config.ini new file mode 100644 index 000000000..f712efbf6 --- /dev/null +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/config.ini @@ -0,0 +1,281 @@ +[root] +type=Root +children=system +dummy=0 + +[system] +type=System +children=cpu physmem ruby +mem_mode=timing +physmem=system.physmem + +[system.cpu] +type=TimingSimpleCPU +children=dtb itb tracer workload +checker=Null +clock=1 +cpu_id=0 +defer_registration=false +do_checkpoint_insts=true +do_statistics_insts=true +dtb=system.cpu.dtb +function_trace=false +function_trace_start=0 +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +phase=0 +progress_interval=0 +system=system +tracer=system.cpu.tracer +workload=system.cpu.workload +dcache_port=system.ruby.network.topology.ext_links0.ext_node.sequencer.port[1] +icache_port=system.ruby.network.topology.ext_links0.ext_node.sequencer.port[0] + +[system.cpu.dtb] +type=AlphaTLB +size=64 + +[system.cpu.itb] +type=AlphaTLB +size=48 + +[system.cpu.tracer] +type=ExeTracer + +[system.cpu.workload] +type=LiveProcess +cmd=hello +cwd= +egid=100 +env= +errout=cerr +euid=100 +executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/alpha/linux/hello +gid=100 +input=cin +max_stack_size=67108864 +output=cout +pid=100 +ppid=99 +simpoint=0 +system=system +uid=100 + +[system.physmem] +type=PhysicalMemory +file= +latency=30 +latency_var=0 +null=false +range=0:134217727 +zero=false +port=system.ruby.network.topology.ext_links0.ext_node.sequencer.physMemPort + +[system.ruby] +type=RubySystem +children=debug network profiler tracer +block_size_bytes=64 +clock=1 +debug=system.ruby.debug +mem_size=134217728 +network=system.ruby.network +profiler=system.ruby.profiler +random_seed=1234 +randomization=false +stats_filename=ruby.stats +tracer=system.ruby.tracer + +[system.ruby.debug] +type=RubyDebug +filter_string=none +output_filename=none +protocol_trace=false +start_time=1 +verbosity_string=none + +[system.ruby.network] +type=SimpleNetwork +children=topology +adaptive_routing=true +buffer_size=0 +control_msg_size=8 +endpoint_bandwidth=10000 +link_latency=1 +number_of_virtual_networks=10 +topology=system.ruby.network.topology + +[system.ruby.network.topology] +type=Topology +children=ext_links0 ext_links1 ext_links2 int_links0 int_links1 int_links2 +ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1 system.ruby.network.topology.ext_links2 +int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1 system.ruby.network.topology.int_links2 +num_int_nodes=4 +print_config=false + +[system.ruby.network.topology.ext_links0] +type=ExtLink +children=ext_node +bw_multiplier=64 +ext_node=system.ruby.network.topology.ext_links0.ext_node +int_node=0 +latency=1 +weight=1 + +[system.ruby.network.topology.ext_links0.ext_node] +type=L1Cache_Controller +children=sequencer +L1DcacheMemory=system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache +L1IcacheMemory=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache +buffer_size=0 +l1_request_latency=2 +l1_response_latency=2 +l2_select_num_bits=0 +number_of_TBEs=256 +recycle_latency=10 +sequencer=system.ruby.network.topology.ext_links0.ext_node.sequencer +to_l2_latency=1 +transitions_per_cycle=32 +version=0 + +[system.ruby.network.topology.ext_links0.ext_node.sequencer] +type=RubySequencer +children=dcache icache +dcache=system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache +deadlock_threshold=500000 +icache=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache +max_outstanding_requests=16 +physmem=system.physmem +using_ruby_tester=false +version=0 +physMemPort=system.physmem.port[0] +port=system.cpu.icache_port system.cpu.dcache_port + +[system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache] +type=RubyCache +assoc=2 +latency=3 +replacement_policy=PSEUDO_LRU +size=256 + +[system.ruby.network.topology.ext_links0.ext_node.sequencer.icache] +type=RubyCache +assoc=2 +latency=3 +replacement_policy=PSEUDO_LRU +size=256 + +[system.ruby.network.topology.ext_links1] +type=ExtLink +children=ext_node +bw_multiplier=64 +ext_node=system.ruby.network.topology.ext_links1.ext_node +int_node=1 +latency=1 +weight=1 + +[system.ruby.network.topology.ext_links1.ext_node] +type=L2Cache_Controller +children=L2cacheMemory +L2cacheMemory=system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory +buffer_size=0 +l2_request_latency=2 +l2_response_latency=2 +number_of_TBEs=256 +recycle_latency=10 +to_l1_latency=1 +transitions_per_cycle=32 +version=0 + +[system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory] +type=RubyCache +assoc=2 +latency=15 +replacement_policy=PSEUDO_LRU +size=512 + +[system.ruby.network.topology.ext_links2] +type=ExtLink +children=ext_node +bw_multiplier=64 +ext_node=system.ruby.network.topology.ext_links2.ext_node +int_node=2 +latency=1 +weight=1 + +[system.ruby.network.topology.ext_links2.ext_node] +type=Directory_Controller +children=directory memBuffer +buffer_size=0 +directory=system.ruby.network.topology.ext_links2.ext_node.directory +directory_latency=6 +memBuffer=system.ruby.network.topology.ext_links2.ext_node.memBuffer +number_of_TBEs=256 +recycle_latency=10 +to_mem_ctrl_latency=1 +transitions_per_cycle=32 +version=0 + +[system.ruby.network.topology.ext_links2.ext_node.directory] +type=RubyDirectoryMemory +size=134217728 +version=0 + +[system.ruby.network.topology.ext_links2.ext_node.memBuffer] +type=RubyMemoryControl +bank_bit_0=8 +bank_busy_time=11 +bank_queue_size=12 +banks_per_rank=8 +basic_bus_busy_time=2 +dimm_bit_0=12 +dimms_per_channel=2 +mem_bus_cycle_multiplier=10 +mem_ctl_latency=12 +mem_fixed_delay=0 +mem_random_arbitrate=0 +rank_bit_0=11 +rank_rank_delay=1 +ranks_per_dimm=2 +read_write_delay=2 +refresh_period=1560 +tFaw=0 +version=0 + +[system.ruby.network.topology.int_links0] +type=IntLink +bw_multiplier=16 +latency=1 +node_a=0 +node_b=3 +weight=1 + +[system.ruby.network.topology.int_links1] +type=IntLink +bw_multiplier=16 +latency=1 +node_a=1 +node_b=3 +weight=1 + +[system.ruby.network.topology.int_links2] +type=IntLink +bw_multiplier=16 +latency=1 +node_a=2 +node_b=3 +weight=1 + +[system.ruby.profiler] +type=RubyProfiler +all_instructions=false +hot_lines=false +num_of_sequencers=1 + +[system.ruby.tracer] +type=RubyTracer +warmup_length=100000 + diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/ruby.stats b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/ruby.stats new file mode 100644 index 000000000..0defa99bd --- /dev/null +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/ruby.stats @@ -0,0 +1,617 @@ + +================ Begin RubySystem Configuration Print ================ + +RubySystem config: + random_seed: 1234 + randomization: 0 + cycle_period: 1 + block_size_bytes: 64 + block_size_bits: 6 + memory_size_bytes: 134217728 + memory_size_bits: 27 + +Network Configuration +--------------------- +network: SIMPLE_NETWORK +topology: + +virtual_net_0: active, unordered +virtual_net_1: active, unordered +virtual_net_2: active, unordered +virtual_net_3: inactive +virtual_net_4: inactive +virtual_net_5: inactive +virtual_net_6: inactive +virtual_net_7: inactive +virtual_net_8: inactive +virtual_net_9: inactive + + +Profiler Configuration +---------------------- +periodic_stats_period: 1000000 + +================ End RubySystem Configuration Print ================ + + +Real time: Jan/28/2010 13:57:44 + +Profiler Stats +-------------- +Elapsed_time_in_seconds: 1 +Elapsed_time_in_minutes: 0.0166667 +Elapsed_time_in_hours: 0.000277778 +Elapsed_time_in_days: 1.15741e-05 + +Virtual_time_in_seconds: 0.95 +Virtual_time_in_minutes: 0.0158333 +Virtual_time_in_hours: 0.000263889 +Virtual_time_in_days: 1.09954e-05 + +Ruby_current_time: 275313 +Ruby_start_time: 0 +Ruby_cycles: 275313 + +mbytes_resident: 34.4609 +mbytes_total: 34.4688 +resident_ratio: 1 + +Total_misses: 0 +total_misses: 0 [ 0 ] +user_misses: 0 [ 0 ] +supervisor_misses: 0 [ 0 ] + +ruby_cycles_executed: 275314 [ 275314 ] + +transactions_started: 0 [ 0 ] +transactions_ended: 0 [ 0 ] +cycles_per_transaction: 0 [ 0 ] +misses_per_transaction: 0 [ 0 ] + + +Busy Controller Counts: +L1Cache-0:0 +L2Cache-0:0 +Directory-0:0 + + +Busy Bank Count:0 + +sequencer_requests_outstanding: [binsize: 1 max: 1 count: 8465 average: 1 | standard deviation: 0 | 0 8465 ] + +All Non-Zero Cycle Demand Cache Accesses +---------------------------------------- +miss_latency: [binsize: 2 max: 281 count: 8464 average: 31.5275 | standard deviation: 62.4195 | 0 6974 0 0 0 0 0 0 0 30 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 156 439 246 330 220 8 7 9 11 3 2 9 4 5 1 0 0 1 1 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 0 1 0 0 0 0 1 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_1: [binsize: 2 max: 269 count: 6414 average: 20.6784 | standard deviation: 51.1007 | 0 5723 0 0 0 0 0 0 0 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 59 203 95 191 106 4 5 4 6 2 1 1 1 4 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_2: [binsize: 2 max: 281 count: 1185 average: 82.5848 | standard deviation: 82.5677 | 0 602 0 0 0 0 0 0 0 13 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 64 191 73 123 92 4 2 3 3 1 1 7 2 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_3: [binsize: 2 max: 215 count: 865 average: 42.0289 | standard deviation: 69.8546 | 0 649 0 0 0 0 0 0 0 12 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 33 45 78 16 22 0 0 2 2 0 0 1 1 1 0 0 0 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] + +All Non-Zero Cycle SW Prefetch Requests +------------------------------------ +prefetch_latency: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +prefetch_latency_L2Miss:[binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +Request vs. RubySystem State Profile +-------------------------------- + + +filter_action: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + +Message Delayed Cycles +---------------------- +Total_delay_cycles: [binsize: 1 max: 30 count: 9645 average: 0.0134785 | standard deviation: 0.509043 | 9637 0 0 0 0 0 0 0 0 0 4 0 0 0 0 0 0 0 0 0 3 0 0 0 0 0 0 0 0 0 1 ] +Total_nonPF_delay_cycles: [binsize: 1 max: 0 count: 6920 average: 0 | standard deviation: 0 | 6920 ] + virtual_network_0_delay_cycles: [binsize: 1 max: 30 count: 2725 average: 0.0477064 | standard deviation: 0.956852 | 2717 0 0 0 0 0 0 0 0 0 4 0 0 0 0 0 0 0 0 0 3 0 0 0 0 0 0 0 0 0 1 ] + virtual_network_1_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + virtual_network_2_delay_cycles: [binsize: 1 max: 0 count: 1041 average: 0 | standard deviation: 0 | 1041 ] + virtual_network_3_delay_cycles: [binsize: 1 max: 0 count: 5879 average: 0 | standard deviation: 0 | 5879 ] + virtual_network_4_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + virtual_network_5_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + virtual_network_6_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + virtual_network_7_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + virtual_network_8_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + virtual_network_9_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + +Resource Usage +-------------- +page_size: 4096 +user_time: 0 +system_time: 0 +page_reclaims: 7392 +page_faults: 2212 +swaps: 0 +block_inputs: 0 +block_outputs: 0 + +Network Stats +------------- + +switch_0_inlinks: 2 +switch_0_outlinks: 2 +links_utilized_percent_switch_0: 0.0889147 + links_utilized_percent_switch_0_link_0: 0.0675913 bw: 640000 base_latency: 1 + links_utilized_percent_switch_0_link_1: 0.110238 bw: 160000 base_latency: 1 + + outgoing_messages_switch_0_link_0_Request_Control: 1041 8328 [ 1041 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_0_Response_Data: 1490 107280 [ 0 1490 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_0_Response_Control: 436 3488 [ 0 436 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Control: 1490 11920 [ 1490 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Response_Control: 1699 13592 [ 0 900 799 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Writeback_Data: 288 20736 [ 147 141 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Writeback_Control: 289 2312 [ 289 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + +switch_1_inlinks: 2 +switch_1_outlinks: 2 +links_utilized_percent_switch_1: 0.228653 + links_utilized_percent_switch_1_link_0: 0.0938114 bw: 640000 base_latency: 1 + links_utilized_percent_switch_1_link_1: 0.363495 bw: 160000 base_latency: 1 + + outgoing_messages_switch_1_link_0_Control: 1490 11920 [ 1490 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_Response_Data: 1460 105120 [ 0 1460 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_Response_Control: 3151 25208 [ 0 2352 799 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_Writeback_Data: 288 20736 [ 147 141 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_Writeback_Control: 289 2312 [ 289 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Control: 1460 11680 [ 1460 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Request_Control: 1041 8328 [ 1041 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Response_Data: 1767 127224 [ 0 1767 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Response_Control: 1611 12888 [ 0 1611 0 0 0 0 0 0 0 0 ] base_latency: 1 + +switch_2_inlinks: 2 +switch_2_outlinks: 2 +links_utilized_percent_switch_2: 0.144145 + links_utilized_percent_switch_2_link_0: 0.0232826 bw: 640000 base_latency: 1 + links_utilized_percent_switch_2_link_1: 0.265007 bw: 160000 base_latency: 1 + + outgoing_messages_switch_2_link_0_Control: 1460 11680 [ 1460 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_0_Response_Data: 277 19944 [ 0 277 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_0_Response_Control: 1175 9400 [ 0 1175 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Response_Data: 1460 105120 [ 0 1460 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Response_Control: 1452 11616 [ 0 1452 0 0 0 0 0 0 0 0 ] base_latency: 1 + +switch_3_inlinks: 3 +switch_3_outlinks: 3 +links_utilized_percent_switch_3: 0.246247 + links_utilized_percent_switch_3_link_0: 0.270365 bw: 160000 base_latency: 1 + links_utilized_percent_switch_3_link_1: 0.375246 bw: 160000 base_latency: 1 + links_utilized_percent_switch_3_link_2: 0.0931304 bw: 160000 base_latency: 1 + + outgoing_messages_switch_3_link_0_Request_Control: 1041 8328 [ 1041 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_0_Response_Data: 1490 107280 [ 0 1490 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_0_Response_Control: 436 3488 [ 0 436 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_1_Control: 1490 11920 [ 1490 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_1_Response_Data: 1460 105120 [ 0 1460 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_1_Response_Control: 3151 25208 [ 0 2352 799 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_1_Writeback_Data: 288 20736 [ 147 141 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_1_Writeback_Control: 289 2312 [ 289 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_2_Control: 1460 11680 [ 1460 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_2_Response_Data: 277 19944 [ 0 277 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_2_Response_Control: 1175 9400 [ 0 1175 0 0 0 0 0 0 0 0 ] base_latency: 1 + +Cache Stats: system.ruby.network.topology.ext_links0.ext_node.sequencer.icache + system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_misses: 0 + system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_demand_misses: 0 + system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_prefetches: 0 + system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_sw_prefetches: 0 + system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_hw_prefetches: 0 + system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_misses_per_transaction: nan + + system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + +Cache Stats: system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache + system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_misses: 0 + system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_demand_misses: 0 + system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_prefetches: 0 + system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_sw_prefetches: 0 + system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_hw_prefetches: 0 + system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_misses_per_transaction: nan + + system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + + --- L1Cache 0 --- + - Event Counts - +Load 1185 +Ifetch 6414 +Store 865 +Inv 1041 +L1_Replacement 1354 +Fwd_GETX 0 +Fwd_GETS 0 +Fwd_GET_INSTR 0 +Data 0 +Data_Exclusive 583 +DataS_fromL1 0 +Data_all_Acks 907 +Ack 0 +Ack_all 0 +WB_Ack 436 + + - Transitions - +NP Load 525 +NP Ifetch 646 +NP Store 191 +NP Inv 356 +NP L1_Replacement 0 <-- + +I Load 58 +I Ifetch 45 +I Store 25 +I Inv 0 <-- +I L1_Replacement 556 + +S Load 0 <-- +S Ifetch 5723 +S Store 0 <-- +S Inv 325 +S L1_Replacement 362 + +E Load 454 +E Ifetch 0 <-- +E Store 71 +E Inv 219 +E L1_Replacement 291 +E Fwd_GETX 0 <-- +E Fwd_GETS 0 <-- +E Fwd_GET_INSTR 0 <-- + +M Load 148 +M Ifetch 0 <-- +M Store 578 +M Inv 141 +M L1_Replacement 145 +M Fwd_GETX 0 <-- +M Fwd_GETS 0 <-- +M Fwd_GET_INSTR 0 <-- + +IS Load 0 <-- +IS Ifetch 0 <-- +IS Store 0 <-- +IS Inv 0 <-- +IS L1_Replacement 0 <-- +IS Data_Exclusive 583 +IS DataS_fromL1 0 <-- +IS Data_all_Acks 691 + +IM Load 0 <-- +IM Ifetch 0 <-- +IM Store 0 <-- +IM Inv 0 <-- +IM L1_Replacement 0 <-- +IM Data 0 <-- +IM Data_all_Acks 216 +IM Ack 0 <-- + +SM Load 0 <-- +SM Ifetch 0 <-- +SM Store 0 <-- +SM Inv 0 <-- +SM L1_Replacement 0 <-- +SM Ack 0 <-- +SM Ack_all 0 <-- + +IS_I Load 0 <-- +IS_I Ifetch 0 <-- +IS_I Store 0 <-- +IS_I Inv 0 <-- +IS_I L1_Replacement 0 <-- +IS_I Data_Exclusive 0 <-- +IS_I DataS_fromL1 0 <-- +IS_I Data_all_Acks 0 <-- + +M_I Load 0 <-- +M_I Ifetch 0 <-- +M_I Store 0 <-- +M_I Inv 0 <-- +M_I L1_Replacement 0 <-- +M_I Fwd_GETX 0 <-- +M_I Fwd_GETS 0 <-- +M_I Fwd_GET_INSTR 0 <-- +M_I WB_Ack 436 + +E_I Load 0 <-- +E_I Ifetch 0 <-- +E_I Store 0 <-- +E_I L1_Replacement 0 <-- + +Cache Stats: system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory + system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_misses: 0 + system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_demand_misses: 0 + system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_prefetches: 0 + system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_sw_prefetches: 0 + system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_hw_prefetches: 0 + system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_misses_per_transaction: nan + + system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + + --- L2Cache 0 --- + - Event Counts - +L1_GET_INSTR 691 +L1_GETS 592 +L1_GETX 220 +L1_UPGRADE 0 +L1_PUTX 436 +L1_PUTX_old 0 +Fwd_L1_GETX 0 +Fwd_L1_GETS 0 +Fwd_L1_GET_INSTR 0 +L2_Replacement 142 +L2_Replacement_clean 1310 +Mem_Data 1460 +Mem_Ack 1452 +WB_Data 141 +WB_Data_clean 0 +Ack 0 +Ack_all 900 +Unblock 0 +Unblock_Cancel 0 +Exclusive_Unblock 799 +MEM_Inv 0 + + - Transitions - +NP L1_GET_INSTR 686 +NP L1_GETS 570 +NP L1_GETX 204 +NP L1_PUTX 0 <-- +NP L1_PUTX_old 0 <-- + +SS L1_GET_INSTR 5 +SS L1_GETS 0 <-- +SS L1_GETX 0 <-- +SS L1_UPGRADE 0 <-- +SS L1_PUTX 0 <-- +SS L1_PUTX_old 0 <-- +SS L2_Replacement 0 <-- +SS L2_Replacement_clean 681 +SS MEM_Inv 0 <-- + +M L1_GET_INSTR 0 <-- +M L1_GETS 13 +M L1_GETX 12 +M L1_PUTX 0 <-- +M L1_PUTX_old 0 <-- +M L2_Replacement 134 +M L2_Replacement_clean 277 +M MEM_Inv 0 <-- + +MT L1_GET_INSTR 0 <-- +MT L1_GETS 0 <-- +MT L1_GETX 0 <-- +MT L1_PUTX 436 +MT L1_PUTX_old 0 <-- +MT L2_Replacement 8 +MT L2_Replacement_clean 352 +MT MEM_Inv 0 <-- + +M_I L1_GET_INSTR 0 <-- +M_I L1_GETS 9 +M_I L1_GETX 4 +M_I L1_UPGRADE 0 <-- +M_I L1_PUTX 0 <-- +M_I L1_PUTX_old 0 <-- +M_I Mem_Ack 1452 +M_I MEM_Inv 0 <-- + +MT_I L1_GET_INSTR 0 <-- +MT_I L1_GETS 0 <-- +MT_I L1_GETX 0 <-- +MT_I L1_UPGRADE 0 <-- +MT_I L1_PUTX 0 <-- +MT_I L1_PUTX_old 0 <-- +MT_I WB_Data 6 +MT_I WB_Data_clean 0 <-- +MT_I Ack_all 2 +MT_I MEM_Inv 0 <-- + +MCT_I L1_GET_INSTR 0 <-- +MCT_I L1_GETS 0 <-- +MCT_I L1_GETX 0 <-- +MCT_I L1_UPGRADE 0 <-- +MCT_I L1_PUTX 0 <-- +MCT_I L1_PUTX_old 0 <-- +MCT_I WB_Data 135 +MCT_I WB_Data_clean 0 <-- +MCT_I Ack_all 217 + +I_I L1_GET_INSTR 0 <-- +I_I L1_GETS 0 <-- +I_I L1_GETX 0 <-- +I_I L1_UPGRADE 0 <-- +I_I L1_PUTX 0 <-- +I_I L1_PUTX_old 0 <-- +I_I Ack 0 <-- +I_I Ack_all 681 + +S_I L1_GET_INSTR 0 <-- +S_I L1_GETS 0 <-- +S_I L1_GETX 0 <-- +S_I L1_UPGRADE 0 <-- +S_I L1_PUTX 0 <-- +S_I L1_PUTX_old 0 <-- +S_I Ack 0 <-- +S_I Ack_all 0 <-- +S_I MEM_Inv 0 <-- + +ISS L1_GET_INSTR 0 <-- +ISS L1_GETS 0 <-- +ISS L1_GETX 0 <-- +ISS L1_PUTX 0 <-- +ISS L1_PUTX_old 0 <-- +ISS L2_Replacement 0 <-- +ISS L2_Replacement_clean 0 <-- +ISS Mem_Data 570 +ISS MEM_Inv 0 <-- + +IS L1_GET_INSTR 0 <-- +IS L1_GETS 0 <-- +IS L1_GETX 0 <-- +IS L1_PUTX 0 <-- +IS L1_PUTX_old 0 <-- +IS L2_Replacement 0 <-- +IS L2_Replacement_clean 0 <-- +IS Mem_Data 686 +IS MEM_Inv 0 <-- + +IM L1_GET_INSTR 0 <-- +IM L1_GETS 0 <-- +IM L1_GETX 0 <-- +IM L1_PUTX 0 <-- +IM L1_PUTX_old 0 <-- +IM L2_Replacement 0 <-- +IM L2_Replacement_clean 0 <-- +IM Mem_Data 204 +IM MEM_Inv 0 <-- + +SS_MB L1_GET_INSTR 0 <-- +SS_MB L1_GETS 0 <-- +SS_MB L1_GETX 0 <-- +SS_MB L1_UPGRADE 0 <-- +SS_MB L1_PUTX 0 <-- +SS_MB L1_PUTX_old 0 <-- +SS_MB L2_Replacement 0 <-- +SS_MB L2_Replacement_clean 0 <-- +SS_MB Unblock_Cancel 0 <-- +SS_MB Exclusive_Unblock 0 <-- +SS_MB MEM_Inv 0 <-- + +MT_MB L1_GET_INSTR 0 <-- +MT_MB L1_GETS 0 <-- +MT_MB L1_GETX 0 <-- +MT_MB L1_UPGRADE 0 <-- +MT_MB L1_PUTX 0 <-- +MT_MB L1_PUTX_old 0 <-- +MT_MB L2_Replacement 0 <-- +MT_MB L2_Replacement_clean 0 <-- +MT_MB Unblock_Cancel 0 <-- +MT_MB Exclusive_Unblock 799 +MT_MB MEM_Inv 0 <-- + +M_MB L1_GET_INSTR 0 <-- +M_MB L1_GETS 0 <-- +M_MB L1_GETX 0 <-- +M_MB L1_UPGRADE 0 <-- +M_MB L1_PUTX 0 <-- +M_MB L1_PUTX_old 0 <-- +M_MB L2_Replacement 0 <-- +M_MB L2_Replacement_clean 0 <-- +M_MB Exclusive_Unblock 0 <-- +M_MB MEM_Inv 0 <-- + +MT_IIB L1_GET_INSTR 0 <-- +MT_IIB L1_GETS 0 <-- +MT_IIB L1_GETX 0 <-- +MT_IIB L1_UPGRADE 0 <-- +MT_IIB L1_PUTX 0 <-- +MT_IIB L1_PUTX_old 0 <-- +MT_IIB L2_Replacement 0 <-- +MT_IIB L2_Replacement_clean 0 <-- +MT_IIB WB_Data 0 <-- +MT_IIB WB_Data_clean 0 <-- +MT_IIB Unblock 0 <-- +MT_IIB MEM_Inv 0 <-- + +MT_IB L1_GET_INSTR 0 <-- +MT_IB L1_GETS 0 <-- +MT_IB L1_GETX 0 <-- +MT_IB L1_UPGRADE 0 <-- +MT_IB L1_PUTX 0 <-- +MT_IB L1_PUTX_old 0 <-- +MT_IB L2_Replacement 0 <-- +MT_IB L2_Replacement_clean 0 <-- +MT_IB WB_Data 0 <-- +MT_IB WB_Data_clean 0 <-- +MT_IB Unblock_Cancel 0 <-- +MT_IB MEM_Inv 0 <-- + +MT_SB L1_GET_INSTR 0 <-- +MT_SB L1_GETS 0 <-- +MT_SB L1_GETX 0 <-- +MT_SB L1_UPGRADE 0 <-- +MT_SB L1_PUTX 0 <-- +MT_SB L1_PUTX_old 0 <-- +MT_SB L2_Replacement 0 <-- +MT_SB L2_Replacement_clean 0 <-- +MT_SB Unblock 0 <-- +MT_SB MEM_Inv 0 <-- + +Memory controller: system.ruby.network.topology.ext_links2.ext_node.memBuffer: + memory_total_requests: 1737 + memory_reads: 1460 + memory_writes: 277 + memory_refreshes: 574 + memory_total_request_delays: 1092 + memory_delays_per_request: 0.62867 + memory_delays_in_input_queue: 133 + memory_delays_behind_head_of_bank_queue: 0 + memory_delays_stalled_at_head_of_bank_queue: 959 + memory_stalls_for_bank_busy: 199 + memory_stalls_for_random_busy: 0 + memory_stalls_for_anti_starvation: 0 + memory_stalls_for_arbitration: 32 + memory_stalls_for_bus: 236 + memory_stalls_for_tfaw: 0 + memory_stalls_for_read_write_turnaround: 492 + memory_stalls_for_read_read_turnaround: 0 + accesses_per_bank: 92 21 45 54 57 174 48 18 19 22 35 37 56 59 44 36 41 24 22 28 32 48 122 36 32 25 35 96 114 185 19 61 + + --- Directory 0 --- + - Event Counts - +Fetch 1460 +Data 277 +Memory_Data 1460 +Memory_Ack 277 +DMA_READ 0 +DMA_WRITE 0 +CleanReplacement 1175 + + - Transitions - +I Fetch 1460 +I DMA_READ 0 <-- +I DMA_WRITE 0 <-- + +ID Fetch 0 <-- +ID Data 0 <-- +ID Memory_Data 0 <-- +ID DMA_READ 0 <-- +ID DMA_WRITE 0 <-- + +ID_W Fetch 0 <-- +ID_W Data 0 <-- +ID_W Memory_Ack 0 <-- +ID_W DMA_READ 0 <-- +ID_W DMA_WRITE 0 <-- + +M Data 277 +M DMA_READ 0 <-- +M DMA_WRITE 0 <-- +M CleanReplacement 1175 + +IM Fetch 0 <-- +IM Data 0 <-- +IM Memory_Data 1460 +IM DMA_READ 0 <-- +IM DMA_WRITE 0 <-- + +MI Fetch 0 <-- +MI Data 0 <-- +MI Memory_Ack 277 +MI DMA_READ 0 <-- +MI DMA_WRITE 0 <-- + +M_DRD Data 0 <-- +M_DRD DMA_READ 0 <-- +M_DRD DMA_WRITE 0 <-- + +M_DRDI Fetch 0 <-- +M_DRDI Data 0 <-- +M_DRDI Memory_Ack 0 <-- +M_DRDI DMA_READ 0 <-- +M_DRDI DMA_WRITE 0 <-- + +M_DWR Data 0 <-- +M_DWR DMA_READ 0 <-- +M_DWR DMA_WRITE 0 <-- + +M_DWRI Fetch 0 <-- +M_DWRI Data 0 <-- +M_DWRI Memory_Ack 0 <-- +M_DWRI DMA_READ 0 <-- +M_DWRI DMA_WRITE 0 <-- + diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/simerr b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/simerr new file mode 100755 index 000000000..eabe42249 --- /dev/null +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/simerr @@ -0,0 +1,3 @@ +warn: Sockets disabled, not accepting gdb connections +For more information see: http://www.m5sim.org/warn/d946bea6 +hack: be nice to actually delete the event here diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/simout b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/simout new file mode 100755 index 000000000..37377ab3d --- /dev/null +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/simout @@ -0,0 +1,17 @@ +M5 Simulator System + +Copyright (c) 2001-2008 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Jan 28 2010 13:54:58 +M5 revision 6068d4fc30d3+ 6931+ default qtip tip brad/rubycfg_regress_udpate +M5 started Jan 28 2010 13:57:42 +M5 executing on svvint03 +command line: build/ALPHA_SE_MESI_CMP_directory/m5.fast -d build/ALPHA_SE_MESI_CMP_directory/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby-MESI_CMP_directory -re tests/run.py build/ALPHA_SE_MESI_CMP_directory/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby-MESI_CMP_directory +Global frequency set at 1000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. +Hello world! +Exiting @ tick 275313 because target called exit() diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-atomic-ruby/stats.txt b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/stats.txt index 41e38be4d..edabafa0b 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-atomic-ruby/stats.txt +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 105206 # Simulator instruction rate (inst/s) -host_mem_usage 1361416 # Number of bytes of host memory used -host_seconds 0.06 # Real time elapsed on the host -host_tick_rate 52654853 # Simulator tick rate (ticks/s) -sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 8106 # Simulator instruction rate (inst/s) +host_mem_usage 215916 # Number of bytes of host memory used +host_seconds 0.79 # Real time elapsed on the host +host_tick_rate 348501 # Simulator tick rate (ticks/s) +sim_freq 1000000000 # Frequency of simulated ticks sim_insts 6404 # Number of instructions simulated -sim_seconds 0.000003 # Number of seconds simulated -sim_ticks 3215000 # Number of ticks simulated +sim_seconds 0.000275 # Number of seconds simulated +sim_ticks 275313 # Number of ticks simulated system.cpu.dtb.data_accesses 2060 # DTB accesses system.cpu.dtb.data_acv 0 # DTB access violations system.cpu.dtb.data_hits 2050 # DTB hits @@ -29,9 +29,9 @@ system.cpu.itb.data_accesses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_hits 0 # DTB hits system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.fetch_accesses 6431 # ITB accesses +system.cpu.itb.fetch_accesses 6432 # ITB accesses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_hits 6414 # ITB hits +system.cpu.itb.fetch_hits 6415 # ITB hits system.cpu.itb.fetch_misses 17 # ITB misses system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.read_acv 0 # DTB read access violations @@ -42,7 +42,7 @@ system.cpu.itb.write_acv 0 # DT system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 6431 # number of cpu cycles simulated +system.cpu.numCycles 275313 # number of cpu cycles simulated system.cpu.num_insts 6404 # Number of instructions executed system.cpu.num_refs 2060 # Number of memory references system.cpu.workload.PROG:num_syscalls 17 # Number of system calls diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/config.ini b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/config.ini new file mode 100644 index 000000000..aceab6a24 --- /dev/null +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/config.ini @@ -0,0 +1,277 @@ +[root] +type=Root +children=system +dummy=0 + +[system] +type=System +children=cpu physmem ruby +mem_mode=timing +physmem=system.physmem + +[system.cpu] +type=TimingSimpleCPU +children=dtb itb tracer workload +checker=Null +clock=1 +cpu_id=0 +defer_registration=false +do_checkpoint_insts=true +do_statistics_insts=true +dtb=system.cpu.dtb +function_trace=false +function_trace_start=0 +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +phase=0 +progress_interval=0 +system=system +tracer=system.cpu.tracer +workload=system.cpu.workload +dcache_port=system.ruby.network.topology.ext_links0.ext_node.sequencer.port[1] +icache_port=system.ruby.network.topology.ext_links0.ext_node.sequencer.port[0] + +[system.cpu.dtb] +type=AlphaTLB +size=64 + +[system.cpu.itb] +type=AlphaTLB +size=48 + +[system.cpu.tracer] +type=ExeTracer + +[system.cpu.workload] +type=LiveProcess +cmd=hello +cwd= +egid=100 +env= +errout=cerr +euid=100 +executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/alpha/linux/hello +gid=100 +input=cin +max_stack_size=67108864 +output=cout +pid=100 +ppid=99 +simpoint=0 +system=system +uid=100 + +[system.physmem] +type=PhysicalMemory +file= +latency=30 +latency_var=0 +null=false +range=0:134217727 +zero=false +port=system.ruby.network.topology.ext_links0.ext_node.sequencer.physMemPort + +[system.ruby] +type=RubySystem +children=debug network profiler tracer +block_size_bytes=64 +clock=1 +debug=system.ruby.debug +mem_size=134217728 +network=system.ruby.network +profiler=system.ruby.profiler +random_seed=1234 +randomization=false +stats_filename=ruby.stats +tracer=system.ruby.tracer + +[system.ruby.debug] +type=RubyDebug +filter_string=none +output_filename=none +protocol_trace=false +start_time=1 +verbosity_string=none + +[system.ruby.network] +type=SimpleNetwork +children=topology +adaptive_routing=true +buffer_size=0 +control_msg_size=8 +endpoint_bandwidth=10000 +link_latency=1 +number_of_virtual_networks=10 +topology=system.ruby.network.topology + +[system.ruby.network.topology] +type=Topology +children=ext_links0 ext_links1 ext_links2 int_links0 int_links1 int_links2 +ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1 system.ruby.network.topology.ext_links2 +int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1 system.ruby.network.topology.int_links2 +num_int_nodes=4 +print_config=false + +[system.ruby.network.topology.ext_links0] +type=ExtLink +children=ext_node +bw_multiplier=64 +ext_node=system.ruby.network.topology.ext_links0.ext_node +int_node=0 +latency=1 +weight=1 + +[system.ruby.network.topology.ext_links0.ext_node] +type=L1Cache_Controller +children=sequencer +L1DcacheMemory=system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache +L1IcacheMemory=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache +buffer_size=0 +l2_select_num_bits=0 +number_of_TBEs=256 +recycle_latency=10 +request_latency=2 +sequencer=system.ruby.network.topology.ext_links0.ext_node.sequencer +transitions_per_cycle=32 +version=0 + +[system.ruby.network.topology.ext_links0.ext_node.sequencer] +type=RubySequencer +children=dcache icache +dcache=system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache +deadlock_threshold=500000 +icache=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache +max_outstanding_requests=16 +physmem=system.physmem +using_ruby_tester=false +version=0 +physMemPort=system.physmem.port[0] +port=system.cpu.icache_port system.cpu.dcache_port + +[system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache] +type=RubyCache +assoc=2 +latency=3 +replacement_policy=PSEUDO_LRU +size=256 + +[system.ruby.network.topology.ext_links0.ext_node.sequencer.icache] +type=RubyCache +assoc=2 +latency=3 +replacement_policy=PSEUDO_LRU +size=256 + +[system.ruby.network.topology.ext_links1] +type=ExtLink +children=ext_node +bw_multiplier=64 +ext_node=system.ruby.network.topology.ext_links1.ext_node +int_node=1 +latency=1 +weight=1 + +[system.ruby.network.topology.ext_links1.ext_node] +type=L2Cache_Controller +children=L2cacheMemory +L2cacheMemory=system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory +buffer_size=0 +number_of_TBEs=256 +recycle_latency=10 +request_latency=2 +response_latency=2 +transitions_per_cycle=32 +version=0 + +[system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory] +type=RubyCache +assoc=2 +latency=15 +replacement_policy=PSEUDO_LRU +size=512 + +[system.ruby.network.topology.ext_links2] +type=ExtLink +children=ext_node +bw_multiplier=64 +ext_node=system.ruby.network.topology.ext_links2.ext_node +int_node=2 +latency=1 +weight=1 + +[system.ruby.network.topology.ext_links2.ext_node] +type=Directory_Controller +children=directory memBuffer +buffer_size=0 +directory=system.ruby.network.topology.ext_links2.ext_node.directory +directory_latency=6 +memBuffer=system.ruby.network.topology.ext_links2.ext_node.memBuffer +number_of_TBEs=256 +recycle_latency=10 +transitions_per_cycle=32 +version=0 + +[system.ruby.network.topology.ext_links2.ext_node.directory] +type=RubyDirectoryMemory +size=134217728 +version=0 + +[system.ruby.network.topology.ext_links2.ext_node.memBuffer] +type=RubyMemoryControl +bank_bit_0=8 +bank_busy_time=11 +bank_queue_size=12 +banks_per_rank=8 +basic_bus_busy_time=2 +dimm_bit_0=12 +dimms_per_channel=2 +mem_bus_cycle_multiplier=10 +mem_ctl_latency=12 +mem_fixed_delay=0 +mem_random_arbitrate=0 +rank_bit_0=11 +rank_rank_delay=1 +ranks_per_dimm=2 +read_write_delay=2 +refresh_period=1560 +tFaw=0 +version=0 + +[system.ruby.network.topology.int_links0] +type=IntLink +bw_multiplier=16 +latency=1 +node_a=0 +node_b=3 +weight=1 + +[system.ruby.network.topology.int_links1] +type=IntLink +bw_multiplier=16 +latency=1 +node_a=1 +node_b=3 +weight=1 + +[system.ruby.network.topology.int_links2] +type=IntLink +bw_multiplier=16 +latency=1 +node_a=2 +node_b=3 +weight=1 + +[system.ruby.profiler] +type=RubyProfiler +all_instructions=false +hot_lines=false +num_of_sequencers=1 + +[system.ruby.tracer] +type=RubyTracer +warmup_length=100000 + diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/ruby.stats b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/ruby.stats new file mode 100644 index 000000000..89d0c3194 --- /dev/null +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/ruby.stats @@ -0,0 +1,1375 @@ + +================ Begin RubySystem Configuration Print ================ + +RubySystem config: + random_seed: 1234 + randomization: 0 + cycle_period: 1 + block_size_bytes: 64 + block_size_bits: 6 + memory_size_bytes: 134217728 + memory_size_bits: 27 + +Network Configuration +--------------------- +network: SIMPLE_NETWORK +topology: + +virtual_net_0: active, unordered +virtual_net_1: active, unordered +virtual_net_2: active, unordered +virtual_net_3: inactive +virtual_net_4: inactive +virtual_net_5: inactive +virtual_net_6: inactive +virtual_net_7: inactive +virtual_net_8: inactive +virtual_net_9: inactive + + +Profiler Configuration +---------------------- +periodic_stats_period: 1000000 + +================ End RubySystem Configuration Print ================ + + +Real time: Jan/28/2010 15:08:14 + +Profiler Stats +-------------- +Elapsed_time_in_seconds: 1 +Elapsed_time_in_minutes: 0.0166667 +Elapsed_time_in_hours: 0.000277778 +Elapsed_time_in_days: 1.15741e-05 + +Virtual_time_in_seconds: 0.8 +Virtual_time_in_minutes: 0.0133333 +Virtual_time_in_hours: 0.000222222 +Virtual_time_in_days: 9.25926e-06 + +Ruby_current_time: 223854 +Ruby_start_time: 0 +Ruby_cycles: 223854 + +mbytes_resident: 34.6055 +mbytes_total: 34.6133 +resident_ratio: 1 + +Total_misses: 0 +total_misses: 0 [ 0 ] +user_misses: 0 [ 0 ] +supervisor_misses: 0 [ 0 ] + +ruby_cycles_executed: 223855 [ 223855 ] + +transactions_started: 0 [ 0 ] +transactions_ended: 0 [ 0 ] +cycles_per_transaction: 0 [ 0 ] +misses_per_transaction: 0 [ 0 ] + + +Busy Controller Counts: +L2Cache-0:0 +L1Cache-0:0 + +Directory-0:0 + +Busy Bank Count:0 + +sequencer_requests_outstanding: [binsize: 1 max: 1 count: 8465 average: 1 | standard deviation: 0 | 0 8465 ] + +All Non-Zero Cycle Demand Cache Accesses +---------------------------------------- +miss_latency: [binsize: 2 max: 276 count: 8464 average: 25.4478 | standard deviation: 56.39 | 0 7102 0 0 0 0 0 0 0 188 60 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 251 197 238 187 165 13 4 20 3 7 5 4 3 3 1 0 1 1 1 0 0 1 0 1 0 0 0 3 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_1: [binsize: 2 max: 276 count: 6414 average: 17.9724 | standard deviation: 47.359 | 0 5768 0 0 0 0 0 0 0 76 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 153 110 113 93 66 5 3 16 1 3 0 1 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 2 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_2: [binsize: 2 max: 259 count: 1185 average: 62.838 | standard deviation: 78.9565 | 0 660 0 0 0 0 0 0 0 112 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 98 55 84 84 63 2 1 3 2 3 5 3 2 2 0 0 1 0 1 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_3: [binsize: 2 max: 227 count: 865 average: 29.6555 | standard deviation: 60.051 | 0 674 0 0 0 0 0 0 0 0 60 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 32 41 10 36 6 0 1 0 1 0 0 1 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] + +All Non-Zero Cycle SW Prefetch Requests +------------------------------------ +prefetch_latency: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +prefetch_latency_L2Miss:[binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +Request vs. RubySystem State Profile +-------------------------------- + + +filter_action: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + +Message Delayed Cycles +---------------------- +Total_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +Total_nonPF_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + virtual_network_0_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + virtual_network_1_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + virtual_network_2_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + virtual_network_3_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + virtual_network_4_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + virtual_network_5_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + virtual_network_6_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + virtual_network_7_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + virtual_network_8_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + virtual_network_9_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + +Resource Usage +-------------- +page_size: 4096 +user_time: 0 +system_time: 0 +page_reclaims: 7397 +page_faults: 2249 +swaps: 0 +block_inputs: 0 +block_outputs: 0 + +Network Stats +------------- + +switch_0_inlinks: 2 +switch_0_outlinks: 2 +links_utilized_percent_switch_0: 0.219641 + links_utilized_percent_switch_0_link_0: 0.0760094 bw: 640000 base_latency: 1 + links_utilized_percent_switch_0_link_1: 0.363272 bw: 160000 base_latency: 1 + + outgoing_messages_switch_0_link_0_Response_Data: 1114 80208 [ 0 0 1114 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_0_ResponseL2hit_Data: 248 17856 [ 0 0 248 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_0_Writeback_Control: 1354 10832 [ 1354 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Request_Control: 1362 10896 [ 1362 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Writeback_Data: 1354 97488 [ 0 0 1354 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Writeback_Control: 1354 10832 [ 1354 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Unblock_Control: 1362 10896 [ 0 0 1362 0 0 0 0 0 0 0 ] base_latency: 1 + +switch_1_inlinks: 2 +switch_1_outlinks: 2 +links_utilized_percent_switch_1: 0.295226 + links_utilized_percent_switch_1_link_0: 0.152935 bw: 640000 base_latency: 1 + links_utilized_percent_switch_1_link_1: 0.437517 bw: 160000 base_latency: 1 + + outgoing_messages_switch_1_link_0_Request_Control: 1362 10896 [ 1362 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_Response_Data: 1114 80208 [ 0 0 1114 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_Writeback_Data: 1354 97488 [ 0 0 1354 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_Writeback_Control: 2452 19616 [ 1354 1098 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_Unblock_Control: 1362 10896 [ 0 0 1362 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Request_Control: 1114 8912 [ 0 1114 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Response_Data: 1114 80208 [ 0 0 1114 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_ResponseL2hit_Data: 248 17856 [ 0 0 248 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Writeback_Data: 194 13968 [ 0 0 194 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Writeback_Control: 3356 26848 [ 1354 1098 904 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Unblock_Control: 1114 8912 [ 0 0 1114 0 0 0 0 0 0 0 ] base_latency: 1 + +switch_2_inlinks: 2 +switch_2_outlinks: 2 +links_utilized_percent_switch_2: 0.140918 + links_utilized_percent_switch_2_link_0: 0.03337 bw: 640000 base_latency: 1 + links_utilized_percent_switch_2_link_1: 0.248466 bw: 160000 base_latency: 1 + + outgoing_messages_switch_2_link_0_Request_Control: 1114 8912 [ 0 1114 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_0_Writeback_Data: 194 13968 [ 0 0 194 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_0_Writeback_Control: 2002 16016 [ 0 1098 904 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_0_Unblock_Control: 1114 8912 [ 0 0 1114 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Response_Data: 1114 80208 [ 0 0 1114 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Writeback_Control: 1098 8784 [ 0 1098 0 0 0 0 0 0 0 0 ] base_latency: 1 + +switch_3_inlinks: 3 +switch_3_outlinks: 3 +links_utilized_percent_switch_3: 0.349752 + links_utilized_percent_switch_3_link_0: 0.304037 bw: 160000 base_latency: 1 + links_utilized_percent_switch_3_link_1: 0.611738 bw: 160000 base_latency: 1 + links_utilized_percent_switch_3_link_2: 0.13348 bw: 160000 base_latency: 1 + + outgoing_messages_switch_3_link_0_Response_Data: 1114 80208 [ 0 0 1114 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_0_ResponseL2hit_Data: 248 17856 [ 0 0 248 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_0_Writeback_Control: 1354 10832 [ 1354 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_1_Request_Control: 1362 10896 [ 1362 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_1_Response_Data: 1114 80208 [ 0 0 1114 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_1_Writeback_Data: 1354 97488 [ 0 0 1354 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_1_Writeback_Control: 2452 19616 [ 1354 1098 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_1_Unblock_Control: 1362 10896 [ 0 0 1362 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_2_Request_Control: 1114 8912 [ 0 1114 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_2_Writeback_Data: 194 13968 [ 0 0 194 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_2_Writeback_Control: 2002 16016 [ 0 1098 904 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_2_Unblock_Control: 1114 8912 [ 0 0 1114 0 0 0 0 0 0 0 ] base_latency: 1 + +Cache Stats: system.ruby.network.topology.ext_links0.ext_node.sequencer.icache + system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_misses: 0 + system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_demand_misses: 0 + system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_prefetches: 0 + system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_sw_prefetches: 0 + system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_hw_prefetches: 0 + system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_misses_per_transaction: nan + + system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + +Cache Stats: system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache + system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_misses: 0 + system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_demand_misses: 0 + system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_prefetches: 0 + system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_sw_prefetches: 0 + system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_hw_prefetches: 0 + system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_misses_per_transaction: nan + + system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + + --- L1Cache 0 --- + - Event Counts - +Load 1185 +Ifetch 6414 +Store 865 +L1_Replacement 1379 +Own_GETX 0 +Fwd_GETX 0 +Fwd_GETS 0 +Fwd_DMA 0 +Inv 0 +Ack 0 +Data 0 +Exclusive_Data 1362 +Writeback_Ack 0 +Writeback_Ack_Data 1354 +Writeback_Nack 0 +All_acks 191 +Use_Timeout 1361 + + - Transitions - +I Load 525 +I Ifetch 646 +I Store 191 +I L1_Replacement 0 <-- +I Inv 0 <-- + +S Load 0 <-- +S Ifetch 0 <-- +S Store 0 <-- +S L1_Replacement 0 <-- +S Fwd_GETS 0 <-- +S Fwd_DMA 0 <-- +S Inv 0 <-- + +O Load 0 <-- +O Ifetch 0 <-- +O Store 0 <-- +O L1_Replacement 0 <-- +O Fwd_GETX 0 <-- +O Fwd_GETS 0 <-- +O Fwd_DMA 0 <-- + +M Load 308 +M Ifetch 3484 +M Store 51 +M L1_Replacement 1086 +M Fwd_GETX 0 <-- +M Fwd_GETS 0 <-- +M Fwd_DMA 0 <-- + +M_W Load 111 +M_W Ifetch 2284 +M_W Store 27 +M_W L1_Replacement 17 +M_W Own_GETX 0 <-- +M_W Fwd_GETX 0 <-- +M_W Fwd_GETS 0 <-- +M_W Fwd_DMA 0 <-- +M_W Inv 0 <-- +M_W Use_Timeout 1143 + +MM Load 234 +MM Ifetch 0 <-- +MM Store 339 +MM L1_Replacement 268 +MM Fwd_GETX 0 <-- +MM Fwd_GETS 0 <-- +MM Fwd_DMA 0 <-- + +MM_W Load 7 +MM_W Ifetch 0 <-- +MM_W Store 257 +MM_W L1_Replacement 8 +MM_W Own_GETX 0 <-- +MM_W Fwd_GETX 0 <-- +MM_W Fwd_GETS 0 <-- +MM_W Fwd_DMA 0 <-- +MM_W Inv 0 <-- +MM_W Use_Timeout 218 + +IM Load 0 <-- +IM Ifetch 0 <-- +IM Store 0 <-- +IM L1_Replacement 0 <-- +IM Inv 0 <-- +IM Ack 0 <-- +IM Data 0 <-- +IM Exclusive_Data 191 + +SM Load 0 <-- +SM Ifetch 0 <-- +SM Store 0 <-- +SM L1_Replacement 0 <-- +SM Fwd_GETS 0 <-- +SM Fwd_DMA 0 <-- +SM Inv 0 <-- +SM Ack 0 <-- +SM Data 0 <-- +SM Exclusive_Data 0 <-- + +OM Load 0 <-- +OM Ifetch 0 <-- +OM Store 0 <-- +OM L1_Replacement 0 <-- +OM Own_GETX 0 <-- +OM Fwd_GETX 0 <-- +OM Fwd_GETS 0 <-- +OM Fwd_DMA 0 <-- +OM Ack 0 <-- +OM All_acks 191 + +IS Load 0 <-- +IS Ifetch 0 <-- +IS Store 0 <-- +IS L1_Replacement 0 <-- +IS Inv 0 <-- +IS Data 0 <-- +IS Exclusive_Data 1171 + +SI Load 0 <-- +SI Ifetch 0 <-- +SI Store 0 <-- +SI L1_Replacement 0 <-- +SI Fwd_GETS 0 <-- +SI Fwd_DMA 0 <-- +SI Inv 0 <-- +SI Writeback_Ack 0 <-- +SI Writeback_Ack_Data 0 <-- +SI Writeback_Nack 0 <-- + +OI Load 0 <-- +OI Ifetch 0 <-- +OI Store 0 <-- +OI L1_Replacement 0 <-- +OI Fwd_GETX 0 <-- +OI Fwd_GETS 0 <-- +OI Fwd_DMA 0 <-- +OI Writeback_Ack 0 <-- +OI Writeback_Ack_Data 0 <-- +OI Writeback_Nack 0 <-- + +MI Load 0 <-- +MI Ifetch 0 <-- +MI Store 0 <-- +MI L1_Replacement 0 <-- +MI Fwd_GETX 0 <-- +MI Fwd_GETS 0 <-- +MI Fwd_DMA 0 <-- +MI Writeback_Ack 0 <-- +MI Writeback_Ack_Data 1354 +MI Writeback_Nack 0 <-- + +II Load 0 <-- +II Ifetch 0 <-- +II Store 0 <-- +II L1_Replacement 0 <-- +II Inv 0 <-- +II Writeback_Ack 0 <-- +II Writeback_Ack_Data 0 <-- +II Writeback_Nack 0 <-- + +Cache Stats: system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory + system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_misses: 0 + system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_demand_misses: 0 + system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_prefetches: 0 + system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_sw_prefetches: 0 + system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_hw_prefetches: 0 + system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_misses_per_transaction: nan + + system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + + --- L2Cache 0 --- + - Event Counts - +L1_GETS 1171 +L1_GETX 191 +L1_PUTO 0 +L1_PUTX 1354 +L1_PUTS_only 0 +L1_PUTS 0 +Fwd_GETX 0 +Fwd_GETS 0 +Fwd_DMA 0 +Own_GETX 0 +Inv 0 +IntAck 0 +ExtAck 0 +All_Acks 131 +Data 131 +Data_Exclusive 983 +L1_WBCLEANDATA 1059 +L1_WBDIRTYDATA 295 +Writeback_Ack 1098 +Writeback_Nack 0 +Unblock 0 +Exclusive_Unblock 1362 +L2_Replacement 1098 + + - Transitions - +NP L1_GETS 983 +NP L1_GETX 131 +NP L1_PUTO 0 <-- +NP L1_PUTX 0 <-- +NP L1_PUTS 0 <-- +NP Inv 0 <-- + +I L1_GETS 0 <-- +I L1_GETX 0 <-- +I L1_PUTO 0 <-- +I L1_PUTX 0 <-- +I L1_PUTS 0 <-- +I Inv 0 <-- +I L2_Replacement 0 <-- + +ILS L1_GETS 0 <-- +ILS L1_GETX 0 <-- +ILS L1_PUTO 0 <-- +ILS L1_PUTX 0 <-- +ILS L1_PUTS_only 0 <-- +ILS L1_PUTS 0 <-- +ILS Inv 0 <-- +ILS L2_Replacement 0 <-- + +ILX L1_GETS 0 <-- +ILX L1_GETX 0 <-- +ILX L1_PUTO 0 <-- +ILX L1_PUTX 1354 +ILX L1_PUTS_only 0 <-- +ILX L1_PUTS 0 <-- +ILX Fwd_GETX 0 <-- +ILX Fwd_GETS 0 <-- +ILX Fwd_DMA 0 <-- +ILX Inv 0 <-- +ILX Data 0 <-- +ILX L2_Replacement 0 <-- + +ILO L1_GETS 0 <-- +ILO L1_GETX 0 <-- +ILO L1_PUTO 0 <-- +ILO L1_PUTX 0 <-- +ILO L1_PUTS 0 <-- +ILO Fwd_GETX 0 <-- +ILO Fwd_GETS 0 <-- +ILO Fwd_DMA 0 <-- +ILO Inv 0 <-- +ILO Data 0 <-- +ILO L2_Replacement 0 <-- + +ILOX L1_GETS 0 <-- +ILOX L1_GETX 0 <-- +ILOX L1_PUTO 0 <-- +ILOX L1_PUTX 0 <-- +ILOX L1_PUTS 0 <-- +ILOX Fwd_GETX 0 <-- +ILOX Fwd_GETS 0 <-- +ILOX Fwd_DMA 0 <-- +ILOX Data 0 <-- + +ILOS L1_GETS 0 <-- +ILOS L1_GETX 0 <-- +ILOS L1_PUTO 0 <-- +ILOS L1_PUTX 0 <-- +ILOS L1_PUTS_only 0 <-- +ILOS L1_PUTS 0 <-- +ILOS Fwd_GETX 0 <-- +ILOS Fwd_GETS 0 <-- +ILOS Fwd_DMA 0 <-- +ILOS Data 0 <-- +ILOS L2_Replacement 0 <-- + +ILOSX L1_GETS 0 <-- +ILOSX L1_GETX 0 <-- +ILOSX L1_PUTO 0 <-- +ILOSX L1_PUTX 0 <-- +ILOSX L1_PUTS_only 0 <-- +ILOSX L1_PUTS 0 <-- +ILOSX Fwd_GETX 0 <-- +ILOSX Fwd_GETS 0 <-- +ILOSX Fwd_DMA 0 <-- +ILOSX Data 0 <-- + +S L1_GETS 0 <-- +S L1_GETX 0 <-- +S L1_PUTX 0 <-- +S L1_PUTS 0 <-- +S Inv 0 <-- +S L2_Replacement 0 <-- + +O L1_GETS 0 <-- +O L1_GETX 0 <-- +O L1_PUTX 0 <-- +O Fwd_GETX 0 <-- +O Fwd_GETS 0 <-- +O Fwd_DMA 0 <-- +O L2_Replacement 0 <-- + +OLS L1_GETS 0 <-- +OLS L1_GETX 0 <-- +OLS L1_PUTX 0 <-- +OLS L1_PUTS_only 0 <-- +OLS L1_PUTS 0 <-- +OLS Fwd_GETX 0 <-- +OLS Fwd_GETS 0 <-- +OLS Fwd_DMA 0 <-- +OLS L2_Replacement 0 <-- + +OLSX L1_GETS 0 <-- +OLSX L1_GETX 0 <-- +OLSX L1_PUTO 0 <-- +OLSX L1_PUTX 0 <-- +OLSX L1_PUTS_only 0 <-- +OLSX L1_PUTS 0 <-- +OLSX Fwd_GETX 0 <-- +OLSX Fwd_GETS 0 <-- +OLSX Fwd_DMA 0 <-- +OLSX L2_Replacement 0 <-- + +SLS L1_GETS 0 <-- +SLS L1_GETX 0 <-- +SLS L1_PUTX 0 <-- +SLS L1_PUTS_only 0 <-- +SLS L1_PUTS 0 <-- +SLS Inv 0 <-- +SLS L2_Replacement 0 <-- + +M L1_GETS 188 +M L1_GETX 60 +M L1_PUTO 0 <-- +M L1_PUTX 0 <-- +M L1_PUTS 0 <-- +M Fwd_GETX 0 <-- +M Fwd_GETS 0 <-- +M Fwd_DMA 0 <-- +M L2_Replacement 1098 + +IFGX L1_GETS 0 <-- +IFGX L1_GETX 0 <-- +IFGX L1_PUTO 0 <-- +IFGX L1_PUTX 0 <-- +IFGX L1_PUTS_only 0 <-- +IFGX L1_PUTS 0 <-- +IFGX Fwd_GETX 0 <-- +IFGX Fwd_GETS 0 <-- +IFGX Fwd_DMA 0 <-- +IFGX Inv 0 <-- +IFGX Data 0 <-- +IFGX Data_Exclusive 0 <-- +IFGX L2_Replacement 0 <-- + +IFGS L1_GETS 0 <-- +IFGS L1_GETX 0 <-- +IFGS L1_PUTO 0 <-- +IFGS L1_PUTX 0 <-- +IFGS L1_PUTS_only 0 <-- +IFGS L1_PUTS 0 <-- +IFGS Fwd_GETX 0 <-- +IFGS Fwd_GETS 0 <-- +IFGS Fwd_DMA 0 <-- +IFGS Inv 0 <-- +IFGS Data 0 <-- +IFGS Data_Exclusive 0 <-- +IFGS L2_Replacement 0 <-- + +ISFGS L1_GETS 0 <-- +ISFGS L1_GETX 0 <-- +ISFGS L1_PUTO 0 <-- +ISFGS L1_PUTX 0 <-- +ISFGS L1_PUTS_only 0 <-- +ISFGS L1_PUTS 0 <-- +ISFGS Fwd_GETX 0 <-- +ISFGS Fwd_GETS 0 <-- +ISFGS Fwd_DMA 0 <-- +ISFGS Inv 0 <-- +ISFGS Data 0 <-- +ISFGS L2_Replacement 0 <-- + +IFGXX L1_GETS 0 <-- +IFGXX L1_GETX 0 <-- +IFGXX L1_PUTO 0 <-- +IFGXX L1_PUTX 0 <-- +IFGXX L1_PUTS_only 0 <-- +IFGXX L1_PUTS 0 <-- +IFGXX Fwd_GETX 0 <-- +IFGXX Fwd_GETS 0 <-- +IFGXX Fwd_DMA 0 <-- +IFGXX Inv 0 <-- +IFGXX IntAck 0 <-- +IFGXX All_Acks 0 <-- +IFGXX Data_Exclusive 0 <-- +IFGXX L2_Replacement 0 <-- + +OFGX L1_GETS 0 <-- +OFGX L1_GETX 0 <-- +OFGX L1_PUTO 0 <-- +OFGX L1_PUTX 0 <-- +OFGX L1_PUTS_only 0 <-- +OFGX L1_PUTS 0 <-- +OFGX Fwd_GETX 0 <-- +OFGX Fwd_GETS 0 <-- +OFGX Fwd_DMA 0 <-- +OFGX Inv 0 <-- +OFGX L2_Replacement 0 <-- + +OLSF L1_GETS 0 <-- +OLSF L1_GETX 0 <-- +OLSF L1_PUTO 0 <-- +OLSF L1_PUTX 0 <-- +OLSF L1_PUTS_only 0 <-- +OLSF L1_PUTS 0 <-- +OLSF Fwd_GETX 0 <-- +OLSF Fwd_GETS 0 <-- +OLSF Fwd_DMA 0 <-- +OLSF Inv 0 <-- +OLSF IntAck 0 <-- +OLSF All_Acks 0 <-- +OLSF L2_Replacement 0 <-- + +ILOW L1_GETS 0 <-- +ILOW L1_GETX 0 <-- +ILOW L1_PUTO 0 <-- +ILOW L1_PUTX 0 <-- +ILOW L1_PUTS_only 0 <-- +ILOW L1_PUTS 0 <-- +ILOW Fwd_GETX 0 <-- +ILOW Fwd_GETS 0 <-- +ILOW Fwd_DMA 0 <-- +ILOW Inv 0 <-- +ILOW L1_WBCLEANDATA 0 <-- +ILOW L1_WBDIRTYDATA 0 <-- +ILOW Unblock 0 <-- +ILOW L2_Replacement 0 <-- + +ILOXW L1_GETS 0 <-- +ILOXW L1_GETX 0 <-- +ILOXW L1_PUTO 0 <-- +ILOXW L1_PUTX 0 <-- +ILOXW L1_PUTS_only 0 <-- +ILOXW L1_PUTS 0 <-- +ILOXW Fwd_GETX 0 <-- +ILOXW Fwd_GETS 0 <-- +ILOXW Fwd_DMA 0 <-- +ILOXW Inv 0 <-- +ILOXW L1_WBCLEANDATA 0 <-- +ILOXW L1_WBDIRTYDATA 0 <-- +ILOXW Unblock 0 <-- +ILOXW L2_Replacement 0 <-- + +ILOSW L1_GETS 0 <-- +ILOSW L1_GETX 0 <-- +ILOSW L1_PUTO 0 <-- +ILOSW L1_PUTX 0 <-- +ILOSW L1_PUTS_only 0 <-- +ILOSW L1_PUTS 0 <-- +ILOSW Fwd_GETX 0 <-- +ILOSW Fwd_GETS 0 <-- +ILOSW Fwd_DMA 0 <-- +ILOSW Inv 0 <-- +ILOSW L1_WBCLEANDATA 0 <-- +ILOSW L1_WBDIRTYDATA 0 <-- +ILOSW Unblock 0 <-- +ILOSW L2_Replacement 0 <-- + +ILOSXW L1_GETS 0 <-- +ILOSXW L1_GETX 0 <-- +ILOSXW L1_PUTO 0 <-- +ILOSXW L1_PUTX 0 <-- +ILOSXW L1_PUTS_only 0 <-- +ILOSXW L1_PUTS 0 <-- +ILOSXW Fwd_GETX 0 <-- +ILOSXW Fwd_GETS 0 <-- +ILOSXW Fwd_DMA 0 <-- +ILOSXW Inv 0 <-- +ILOSXW L1_WBCLEANDATA 0 <-- +ILOSXW L1_WBDIRTYDATA 0 <-- +ILOSXW Unblock 0 <-- +ILOSXW L2_Replacement 0 <-- + +SLSW L1_GETS 0 <-- +SLSW L1_GETX 0 <-- +SLSW L1_PUTO 0 <-- +SLSW L1_PUTX 0 <-- +SLSW L1_PUTS_only 0 <-- +SLSW L1_PUTS 0 <-- +SLSW Fwd_GETX 0 <-- +SLSW Fwd_GETS 0 <-- +SLSW Fwd_DMA 0 <-- +SLSW Inv 0 <-- +SLSW Unblock 0 <-- +SLSW L2_Replacement 0 <-- + +OLSW L1_GETS 0 <-- +OLSW L1_GETX 0 <-- +OLSW L1_PUTO 0 <-- +OLSW L1_PUTX 0 <-- +OLSW L1_PUTS_only 0 <-- +OLSW L1_PUTS 0 <-- +OLSW Fwd_GETX 0 <-- +OLSW Fwd_GETS 0 <-- +OLSW Fwd_DMA 0 <-- +OLSW Inv 0 <-- +OLSW Unblock 0 <-- +OLSW L2_Replacement 0 <-- + +ILSW L1_GETS 0 <-- +ILSW L1_GETX 0 <-- +ILSW L1_PUTO 0 <-- +ILSW L1_PUTX 0 <-- +ILSW L1_PUTS_only 0 <-- +ILSW L1_PUTS 0 <-- +ILSW Fwd_GETX 0 <-- +ILSW Fwd_GETS 0 <-- +ILSW Fwd_DMA 0 <-- +ILSW Inv 0 <-- +ILSW L1_WBCLEANDATA 0 <-- +ILSW Unblock 0 <-- +ILSW L2_Replacement 0 <-- + +IW L1_GETS 0 <-- +IW L1_GETX 0 <-- +IW L1_PUTO 0 <-- +IW L1_PUTX 0 <-- +IW L1_PUTS_only 0 <-- +IW L1_PUTS 0 <-- +IW Fwd_GETX 0 <-- +IW Fwd_GETS 0 <-- +IW Fwd_DMA 0 <-- +IW Inv 0 <-- +IW L1_WBCLEANDATA 0 <-- +IW L2_Replacement 0 <-- + +OW L1_GETS 0 <-- +OW L1_GETX 0 <-- +OW L1_PUTO 0 <-- +OW L1_PUTX 0 <-- +OW L1_PUTS_only 0 <-- +OW L1_PUTS 0 <-- +OW Fwd_GETX 0 <-- +OW Fwd_GETS 0 <-- +OW Fwd_DMA 0 <-- +OW Inv 0 <-- +OW Unblock 0 <-- +OW L2_Replacement 0 <-- + +SW L1_GETS 0 <-- +SW L1_GETX 0 <-- +SW L1_PUTO 0 <-- +SW L1_PUTX 0 <-- +SW L1_PUTS_only 0 <-- +SW L1_PUTS 0 <-- +SW Fwd_GETX 0 <-- +SW Fwd_GETS 0 <-- +SW Fwd_DMA 0 <-- +SW Inv 0 <-- +SW Unblock 0 <-- +SW L2_Replacement 0 <-- + +OXW L1_GETS 0 <-- +OXW L1_GETX 0 <-- +OXW L1_PUTO 0 <-- +OXW L1_PUTX 0 <-- +OXW L1_PUTS_only 0 <-- +OXW L1_PUTS 0 <-- +OXW Fwd_GETX 0 <-- +OXW Fwd_GETS 0 <-- +OXW Fwd_DMA 0 <-- +OXW Inv 0 <-- +OXW Unblock 0 <-- +OXW L2_Replacement 0 <-- + +OLSXW L1_GETS 0 <-- +OLSXW L1_GETX 0 <-- +OLSXW L1_PUTO 0 <-- +OLSXW L1_PUTX 0 <-- +OLSXW L1_PUTS_only 0 <-- +OLSXW L1_PUTS 0 <-- +OLSXW Fwd_GETX 0 <-- +OLSXW Fwd_GETS 0 <-- +OLSXW Fwd_DMA 0 <-- +OLSXW Inv 0 <-- +OLSXW Unblock 0 <-- +OLSXW L2_Replacement 0 <-- + +ILXW L1_GETS 0 <-- +ILXW L1_GETX 0 <-- +ILXW L1_PUTO 0 <-- +ILXW L1_PUTX 0 <-- +ILXW L1_PUTS_only 0 <-- +ILXW L1_PUTS 0 <-- +ILXW Fwd_GETX 0 <-- +ILXW Fwd_GETS 0 <-- +ILXW Fwd_DMA 0 <-- +ILXW Inv 0 <-- +ILXW Data 0 <-- +ILXW L1_WBCLEANDATA 1059 +ILXW L1_WBDIRTYDATA 295 +ILXW Unblock 0 <-- +ILXW L2_Replacement 0 <-- + +IFLS L1_GETS 0 <-- +IFLS L1_GETX 0 <-- +IFLS L1_PUTO 0 <-- +IFLS L1_PUTX 0 <-- +IFLS L1_PUTS_only 0 <-- +IFLS L1_PUTS 0 <-- +IFLS Fwd_GETX 0 <-- +IFLS Fwd_GETS 0 <-- +IFLS Fwd_DMA 0 <-- +IFLS Inv 0 <-- +IFLS Unblock 0 <-- +IFLS L2_Replacement 0 <-- + +IFLO L1_GETS 0 <-- +IFLO L1_GETX 0 <-- +IFLO L1_PUTO 0 <-- +IFLO L1_PUTX 0 <-- +IFLO L1_PUTS_only 0 <-- +IFLO L1_PUTS 0 <-- +IFLO Fwd_GETX 0 <-- +IFLO Fwd_GETS 0 <-- +IFLO Fwd_DMA 0 <-- +IFLO Inv 0 <-- +IFLO Unblock 0 <-- +IFLO L2_Replacement 0 <-- + +IFLOX L1_GETS 0 <-- +IFLOX L1_GETX 0 <-- +IFLOX L1_PUTO 0 <-- +IFLOX L1_PUTX 0 <-- +IFLOX L1_PUTS_only 0 <-- +IFLOX L1_PUTS 0 <-- +IFLOX Fwd_GETX 0 <-- +IFLOX Fwd_GETS 0 <-- +IFLOX Fwd_DMA 0 <-- +IFLOX Inv 0 <-- +IFLOX Unblock 0 <-- +IFLOX Exclusive_Unblock 0 <-- +IFLOX L2_Replacement 0 <-- + +IFLOXX L1_GETS 0 <-- +IFLOXX L1_GETX 0 <-- +IFLOXX L1_PUTO 0 <-- +IFLOXX L1_PUTX 0 <-- +IFLOXX L1_PUTS_only 0 <-- +IFLOXX L1_PUTS 0 <-- +IFLOXX Fwd_GETX 0 <-- +IFLOXX Fwd_GETS 0 <-- +IFLOXX Fwd_DMA 0 <-- +IFLOXX Inv 0 <-- +IFLOXX Unblock 0 <-- +IFLOXX Exclusive_Unblock 0 <-- +IFLOXX L2_Replacement 0 <-- + +IFLOSX L1_GETS 0 <-- +IFLOSX L1_GETX 0 <-- +IFLOSX L1_PUTO 0 <-- +IFLOSX L1_PUTX 0 <-- +IFLOSX L1_PUTS_only 0 <-- +IFLOSX L1_PUTS 0 <-- +IFLOSX Fwd_GETX 0 <-- +IFLOSX Fwd_GETS 0 <-- +IFLOSX Fwd_DMA 0 <-- +IFLOSX Inv 0 <-- +IFLOSX Unblock 0 <-- +IFLOSX Exclusive_Unblock 0 <-- +IFLOSX L2_Replacement 0 <-- + +IFLXO L1_GETS 0 <-- +IFLXO L1_GETX 0 <-- +IFLXO L1_PUTO 0 <-- +IFLXO L1_PUTX 0 <-- +IFLXO L1_PUTS_only 0 <-- +IFLXO L1_PUTS 0 <-- +IFLXO Fwd_GETX 0 <-- +IFLXO Fwd_GETS 0 <-- +IFLXO Fwd_DMA 0 <-- +IFLXO Inv 0 <-- +IFLXO Exclusive_Unblock 0 <-- +IFLXO L2_Replacement 0 <-- + +IGS L1_GETS 0 <-- +IGS L1_GETX 0 <-- +IGS L1_PUTO 0 <-- +IGS L1_PUTX 0 <-- +IGS L1_PUTS_only 0 <-- +IGS L1_PUTS 0 <-- +IGS Fwd_GETX 0 <-- +IGS Fwd_GETS 0 <-- +IGS Fwd_DMA 0 <-- +IGS Own_GETX 0 <-- +IGS Inv 0 <-- +IGS Data 0 <-- +IGS Data_Exclusive 983 +IGS Unblock 0 <-- +IGS Exclusive_Unblock 983 +IGS L2_Replacement 0 <-- + +IGM L1_GETS 0 <-- +IGM L1_GETX 0 <-- +IGM L1_PUTO 0 <-- +IGM L1_PUTX 0 <-- +IGM L1_PUTS_only 0 <-- +IGM L1_PUTS 0 <-- +IGM Fwd_GETX 0 <-- +IGM Fwd_GETS 0 <-- +IGM Fwd_DMA 0 <-- +IGM Own_GETX 0 <-- +IGM Inv 0 <-- +IGM ExtAck 0 <-- +IGM Data 131 +IGM Data_Exclusive 0 <-- +IGM L2_Replacement 0 <-- + +IGMLS L1_GETS 0 <-- +IGMLS L1_GETX 0 <-- +IGMLS L1_PUTO 0 <-- +IGMLS L1_PUTX 0 <-- +IGMLS L1_PUTS_only 0 <-- +IGMLS L1_PUTS 0 <-- +IGMLS Inv 0 <-- +IGMLS IntAck 0 <-- +IGMLS ExtAck 0 <-- +IGMLS All_Acks 0 <-- +IGMLS Data 0 <-- +IGMLS Data_Exclusive 0 <-- +IGMLS L2_Replacement 0 <-- + +IGMO L1_GETS 0 <-- +IGMO L1_GETX 0 <-- +IGMO L1_PUTO 0 <-- +IGMO L1_PUTX 0 <-- +IGMO L1_PUTS_only 0 <-- +IGMO L1_PUTS 0 <-- +IGMO Fwd_GETX 0 <-- +IGMO Fwd_GETS 0 <-- +IGMO Fwd_DMA 0 <-- +IGMO Own_GETX 0 <-- +IGMO ExtAck 0 <-- +IGMO All_Acks 131 +IGMO Exclusive_Unblock 131 +IGMO L2_Replacement 0 <-- + +IGMIO L1_GETS 0 <-- +IGMIO L1_GETX 0 <-- +IGMIO L1_PUTO 0 <-- +IGMIO L1_PUTX 0 <-- +IGMIO L1_PUTS_only 0 <-- +IGMIO L1_PUTS 0 <-- +IGMIO Fwd_GETX 0 <-- +IGMIO Fwd_GETS 0 <-- +IGMIO Fwd_DMA 0 <-- +IGMIO Own_GETX 0 <-- +IGMIO ExtAck 0 <-- +IGMIO All_Acks 0 <-- + +OGMIO L1_GETS 0 <-- +OGMIO L1_GETX 0 <-- +OGMIO L1_PUTO 0 <-- +OGMIO L1_PUTX 0 <-- +OGMIO L1_PUTS_only 0 <-- +OGMIO L1_PUTS 0 <-- +OGMIO Fwd_GETX 0 <-- +OGMIO Fwd_GETS 0 <-- +OGMIO Fwd_DMA 0 <-- +OGMIO Own_GETX 0 <-- +OGMIO ExtAck 0 <-- +OGMIO All_Acks 0 <-- + +IGMIOF L1_GETS 0 <-- +IGMIOF L1_GETX 0 <-- +IGMIOF L1_PUTO 0 <-- +IGMIOF L1_PUTX 0 <-- +IGMIOF L1_PUTS_only 0 <-- +IGMIOF L1_PUTS 0 <-- +IGMIOF IntAck 0 <-- +IGMIOF All_Acks 0 <-- +IGMIOF Data_Exclusive 0 <-- + +IGMIOFS L1_GETS 0 <-- +IGMIOFS L1_GETX 0 <-- +IGMIOFS L1_PUTO 0 <-- +IGMIOFS L1_PUTX 0 <-- +IGMIOFS L1_PUTS_only 0 <-- +IGMIOFS L1_PUTS 0 <-- +IGMIOFS Fwd_GETX 0 <-- +IGMIOFS Fwd_GETS 0 <-- +IGMIOFS Fwd_DMA 0 <-- +IGMIOFS Inv 0 <-- +IGMIOFS Data 0 <-- +IGMIOFS L2_Replacement 0 <-- + +OGMIOF L1_GETS 0 <-- +OGMIOF L1_GETX 0 <-- +OGMIOF L1_PUTO 0 <-- +OGMIOF L1_PUTX 0 <-- +OGMIOF L1_PUTS_only 0 <-- +OGMIOF L1_PUTS 0 <-- +OGMIOF IntAck 0 <-- +OGMIOF All_Acks 0 <-- + +II L1_GETS 0 <-- +II L1_GETX 0 <-- +II L1_PUTO 0 <-- +II L1_PUTX 0 <-- +II L1_PUTS_only 0 <-- +II L1_PUTS 0 <-- +II IntAck 0 <-- +II All_Acks 0 <-- + +MM L1_GETS 0 <-- +MM L1_GETX 0 <-- +MM L1_PUTO 0 <-- +MM L1_PUTX 0 <-- +MM L1_PUTS_only 0 <-- +MM L1_PUTS 0 <-- +MM Fwd_GETX 0 <-- +MM Fwd_GETS 0 <-- +MM Fwd_DMA 0 <-- +MM Inv 0 <-- +MM Exclusive_Unblock 60 +MM L2_Replacement 0 <-- + +SS L1_GETS 0 <-- +SS L1_GETX 0 <-- +SS L1_PUTO 0 <-- +SS L1_PUTX 0 <-- +SS L1_PUTS_only 0 <-- +SS L1_PUTS 0 <-- +SS Fwd_GETX 0 <-- +SS Fwd_GETS 0 <-- +SS Fwd_DMA 0 <-- +SS Inv 0 <-- +SS Unblock 0 <-- +SS L2_Replacement 0 <-- + +OO L1_GETS 0 <-- +OO L1_GETX 0 <-- +OO L1_PUTO 0 <-- +OO L1_PUTX 0 <-- +OO L1_PUTS_only 0 <-- +OO L1_PUTS 0 <-- +OO Fwd_GETX 0 <-- +OO Fwd_GETS 0 <-- +OO Fwd_DMA 0 <-- +OO Inv 0 <-- +OO Unblock 0 <-- +OO Exclusive_Unblock 188 +OO L2_Replacement 0 <-- + +OLSS L1_GETS 0 <-- +OLSS L1_GETX 0 <-- +OLSS L1_PUTO 0 <-- +OLSS L1_PUTX 0 <-- +OLSS L1_PUTS_only 0 <-- +OLSS L1_PUTS 0 <-- +OLSS Fwd_GETX 0 <-- +OLSS Fwd_GETS 0 <-- +OLSS Fwd_DMA 0 <-- +OLSS Inv 0 <-- +OLSS Unblock 0 <-- +OLSS L2_Replacement 0 <-- + +OLSXS L1_GETS 0 <-- +OLSXS L1_GETX 0 <-- +OLSXS L1_PUTO 0 <-- +OLSXS L1_PUTX 0 <-- +OLSXS L1_PUTS_only 0 <-- +OLSXS L1_PUTS 0 <-- +OLSXS Fwd_GETX 0 <-- +OLSXS Fwd_GETS 0 <-- +OLSXS Fwd_DMA 0 <-- +OLSXS Inv 0 <-- +OLSXS Unblock 0 <-- +OLSXS L2_Replacement 0 <-- + +SLSS L1_GETS 0 <-- +SLSS L1_GETX 0 <-- +SLSS L1_PUTO 0 <-- +SLSS L1_PUTX 0 <-- +SLSS L1_PUTS_only 0 <-- +SLSS L1_PUTS 0 <-- +SLSS Fwd_GETX 0 <-- +SLSS Fwd_GETS 0 <-- +SLSS Fwd_DMA 0 <-- +SLSS Inv 0 <-- +SLSS Unblock 0 <-- +SLSS L2_Replacement 0 <-- + +OI L1_GETS 0 <-- +OI L1_GETX 0 <-- +OI L1_PUTO 0 <-- +OI L1_PUTX 0 <-- +OI L1_PUTS_only 0 <-- +OI L1_PUTS 0 <-- +OI Fwd_GETX 0 <-- +OI Fwd_GETS 0 <-- +OI Fwd_DMA 0 <-- +OI Writeback_Ack 0 <-- +OI Writeback_Nack 0 <-- +OI L2_Replacement 0 <-- + +MI L1_GETS 0 <-- +MI L1_GETX 0 <-- +MI L1_PUTO 0 <-- +MI L1_PUTX 0 <-- +MI L1_PUTS_only 0 <-- +MI L1_PUTS 0 <-- +MI Fwd_GETX 0 <-- +MI Fwd_GETS 0 <-- +MI Fwd_DMA 0 <-- +MI Writeback_Ack 1098 +MI L2_Replacement 0 <-- + +MII L1_GETS 0 <-- +MII L1_GETX 0 <-- +MII L1_PUTO 0 <-- +MII L1_PUTX 0 <-- +MII L1_PUTS_only 0 <-- +MII L1_PUTS 0 <-- +MII Writeback_Ack 0 <-- +MII Writeback_Nack 0 <-- +MII L2_Replacement 0 <-- + +OLSI L1_GETS 0 <-- +OLSI L1_GETX 0 <-- +OLSI L1_PUTO 0 <-- +OLSI L1_PUTX 0 <-- +OLSI L1_PUTS_only 0 <-- +OLSI L1_PUTS 0 <-- +OLSI Fwd_GETX 0 <-- +OLSI Fwd_GETS 0 <-- +OLSI Fwd_DMA 0 <-- +OLSI Writeback_Ack 0 <-- +OLSI L2_Replacement 0 <-- + +ILSI L1_GETS 0 <-- +ILSI L1_GETX 0 <-- +ILSI L1_PUTO 0 <-- +ILSI L1_PUTX 0 <-- +ILSI L1_PUTS_only 0 <-- +ILSI L1_PUTS 0 <-- +ILSI IntAck 0 <-- +ILSI All_Acks 0 <-- +ILSI Writeback_Ack 0 <-- +ILSI L2_Replacement 0 <-- + +Memory controller: system.ruby.network.topology.ext_links2.ext_node.memBuffer: + memory_total_requests: 1308 + memory_reads: 1114 + memory_writes: 194 + memory_refreshes: 467 + memory_total_request_delays: 250 + memory_delays_per_request: 0.191131 + memory_delays_in_input_queue: 4 + memory_delays_behind_head_of_bank_queue: 0 + memory_delays_stalled_at_head_of_bank_queue: 246 + memory_stalls_for_bank_busy: 94 + memory_stalls_for_random_busy: 0 + memory_stalls_for_anti_starvation: 0 + memory_stalls_for_arbitration: 11 + memory_stalls_for_bus: 62 + memory_stalls_for_tfaw: 0 + memory_stalls_for_read_write_turnaround: 79 + memory_stalls_for_read_read_turnaround: 0 + accesses_per_bank: 75 17 45 40 54 99 29 16 19 22 32 34 52 48 38 30 39 21 21 27 28 37 55 22 31 22 32 70 84 104 13 52 + + --- Directory 0 --- + - Event Counts - +GETX 131 +GETS 983 +PUTX 1098 +PUTO 0 +PUTO_SHARERS 0 +Unblock 0 +Last_Unblock 0 +Exclusive_Unblock 1114 +Clean_Writeback 904 +Dirty_Writeback 194 +Memory_Data 1114 +Memory_Ack 194 +DMA_READ 0 +DMA_WRITE 0 +Data 0 + + - Transitions - +I GETX 131 +I GETS 983 +I PUTX 0 <-- +I PUTO 0 <-- +I Memory_Data 0 <-- +I Memory_Ack 191 +I DMA_READ 0 <-- +I DMA_WRITE 0 <-- + +S GETX 0 <-- +S GETS 0 <-- +S PUTX 0 <-- +S PUTO 0 <-- +S Memory_Data 0 <-- +S Memory_Ack 0 <-- +S DMA_READ 0 <-- +S DMA_WRITE 0 <-- + +O GETX 0 <-- +O GETS 0 <-- +O PUTX 0 <-- +O PUTO 0 <-- +O PUTO_SHARERS 0 <-- +O Memory_Data 0 <-- +O Memory_Ack 0 <-- +O DMA_READ 0 <-- +O DMA_WRITE 0 <-- + +M GETX 0 <-- +M GETS 0 <-- +M PUTX 1098 +M PUTO 0 <-- +M PUTO_SHARERS 0 <-- +M Memory_Data 0 <-- +M Memory_Ack 0 <-- +M DMA_READ 0 <-- +M DMA_WRITE 0 <-- + +IS GETX 0 <-- +IS GETS 0 <-- +IS PUTX 0 <-- +IS PUTO 0 <-- +IS PUTO_SHARERS 0 <-- +IS Unblock 0 <-- +IS Exclusive_Unblock 983 +IS Memory_Data 983 +IS Memory_Ack 2 +IS DMA_READ 0 <-- +IS DMA_WRITE 0 <-- + +SS GETX 0 <-- +SS GETS 0 <-- +SS PUTX 0 <-- +SS PUTO 0 <-- +SS PUTO_SHARERS 0 <-- +SS Unblock 0 <-- +SS Last_Unblock 0 <-- +SS Memory_Data 0 <-- +SS Memory_Ack 0 <-- +SS DMA_READ 0 <-- +SS DMA_WRITE 0 <-- + +OO GETX 0 <-- +OO GETS 0 <-- +OO PUTX 0 <-- +OO PUTO 0 <-- +OO PUTO_SHARERS 0 <-- +OO Unblock 0 <-- +OO Last_Unblock 0 <-- +OO Memory_Data 0 <-- +OO Memory_Ack 0 <-- +OO DMA_READ 0 <-- +OO DMA_WRITE 0 <-- + +MO GETX 0 <-- +MO GETS 0 <-- +MO PUTX 0 <-- +MO PUTO 0 <-- +MO PUTO_SHARERS 0 <-- +MO Unblock 0 <-- +MO Exclusive_Unblock 0 <-- +MO Memory_Data 0 <-- +MO Memory_Ack 0 <-- +MO DMA_READ 0 <-- +MO DMA_WRITE 0 <-- + +MM GETX 0 <-- +MM GETS 0 <-- +MM PUTX 0 <-- +MM PUTO 0 <-- +MM PUTO_SHARERS 0 <-- +MM Exclusive_Unblock 131 +MM Memory_Data 131 +MM Memory_Ack 1 +MM DMA_READ 0 <-- +MM DMA_WRITE 0 <-- + + +MI GETX 0 <-- +MI GETS 0 <-- +MI PUTX 0 <-- +MI PUTO 0 <-- +MI PUTO_SHARERS 0 <-- +MI Unblock 0 <-- +MI Clean_Writeback 904 +MI Dirty_Writeback 194 +MI Memory_Data 0 <-- +MI Memory_Ack 0 <-- +MI DMA_READ 0 <-- +MI DMA_WRITE 0 <-- + +MIS GETX 0 <-- +MIS GETS 0 <-- +MIS PUTX 0 <-- +MIS PUTO 0 <-- +MIS PUTO_SHARERS 0 <-- +MIS Unblock 0 <-- +MIS Clean_Writeback 0 <-- +MIS Dirty_Writeback 0 <-- +MIS Memory_Data 0 <-- +MIS Memory_Ack 0 <-- +MIS DMA_READ 0 <-- +MIS DMA_WRITE 0 <-- + +OS GETX 0 <-- +OS GETS 0 <-- +OS PUTX 0 <-- +OS PUTO 0 <-- +OS PUTO_SHARERS 0 <-- +OS Unblock 0 <-- +OS Clean_Writeback 0 <-- +OS Dirty_Writeback 0 <-- +OS Memory_Data 0 <-- +OS Memory_Ack 0 <-- +OS DMA_READ 0 <-- +OS DMA_WRITE 0 <-- + +OSS GETX 0 <-- +OSS GETS 0 <-- +OSS PUTX 0 <-- +OSS PUTO 0 <-- +OSS PUTO_SHARERS 0 <-- +OSS Unblock 0 <-- +OSS Clean_Writeback 0 <-- +OSS Dirty_Writeback 0 <-- +OSS Memory_Data 0 <-- +OSS Memory_Ack 0 <-- +OSS DMA_READ 0 <-- +OSS DMA_WRITE 0 <-- + +XI_M GETX 0 <-- +XI_M GETS 0 <-- +XI_M PUTX 0 <-- +XI_M PUTO 0 <-- +XI_M PUTO_SHARERS 0 <-- +XI_M Memory_Data 0 <-- +XI_M Memory_Ack 0 <-- +XI_M DMA_READ 0 <-- +XI_M DMA_WRITE 0 <-- + +XI_U GETX 0 <-- +XI_U GETS 0 <-- +XI_U PUTX 0 <-- +XI_U PUTO 0 <-- +XI_U PUTO_SHARERS 0 <-- +XI_U Exclusive_Unblock 0 <-- +XI_U Memory_Ack 0 <-- +XI_U DMA_READ 0 <-- +XI_U DMA_WRITE 0 <-- + +OI_D GETX 0 <-- +OI_D GETS 0 <-- +OI_D PUTX 0 <-- +OI_D PUTO 0 <-- +OI_D PUTO_SHARERS 0 <-- +OI_D DMA_READ 0 <-- +OI_D DMA_WRITE 0 <-- +OI_D Data 0 <-- + diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simerr b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simerr new file mode 100755 index 000000000..eabe42249 --- /dev/null +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simerr @@ -0,0 +1,3 @@ +warn: Sockets disabled, not accepting gdb connections +For more information see: http://www.m5sim.org/warn/d946bea6 +hack: be nice to actually delete the event here diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simout b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simout new file mode 100755 index 000000000..a5c547a14 --- /dev/null +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simout @@ -0,0 +1,17 @@ +M5 Simulator System + +Copyright (c) 2001-2008 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Jan 28 2010 14:49:51 +M5 revision 6068d4fc30d3+ 6931+ default qtip tip brad/rubycfg_regress_udpate +M5 started Jan 28 2010 15:08:13 +M5 executing on svvint05 +command line: build/ALPHA_SE_MOESI_CMP_directory/m5.fast -d build/ALPHA_SE_MOESI_CMP_directory/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_directory -re tests/run.py build/ALPHA_SE_MOESI_CMP_directory/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_directory +Global frequency set at 1000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. +Hello world! +Exiting @ tick 223854 because target called exit() diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt new file mode 100644 index 000000000..f1675ef82 --- /dev/null +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt @@ -0,0 +1,50 @@ + +---------- Begin Simulation Statistics ---------- +host_inst_rate 11859 # Simulator instruction rate (inst/s) +host_mem_usage 216064 # Number of bytes of host memory used +host_seconds 0.55 # Real time elapsed on the host +host_tick_rate 407003 # Simulator tick rate (ticks/s) +sim_freq 1000000000 # Frequency of simulated ticks +sim_insts 6404 # Number of instructions simulated +sim_seconds 0.000224 # Number of seconds simulated +sim_ticks 223854 # Number of ticks simulated +system.cpu.dtb.data_accesses 2060 # DTB accesses +system.cpu.dtb.data_acv 0 # DTB access violations +system.cpu.dtb.data_hits 2050 # DTB hits +system.cpu.dtb.data_misses 10 # DTB misses +system.cpu.dtb.fetch_accesses 0 # ITB accesses +system.cpu.dtb.fetch_acv 0 # ITB acv +system.cpu.dtb.fetch_hits 0 # ITB hits +system.cpu.dtb.fetch_misses 0 # ITB misses +system.cpu.dtb.read_accesses 1192 # DTB read accesses +system.cpu.dtb.read_acv 0 # DTB read access violations +system.cpu.dtb.read_hits 1185 # DTB read hits +system.cpu.dtb.read_misses 7 # DTB read misses +system.cpu.dtb.write_accesses 868 # DTB write accesses +system.cpu.dtb.write_acv 0 # DTB write access violations +system.cpu.dtb.write_hits 865 # DTB write hits +system.cpu.dtb.write_misses 3 # DTB write misses +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.itb.data_accesses 0 # DTB accesses +system.cpu.itb.data_acv 0 # DTB access violations +system.cpu.itb.data_hits 0 # DTB hits +system.cpu.itb.data_misses 0 # DTB misses +system.cpu.itb.fetch_accesses 6432 # ITB accesses +system.cpu.itb.fetch_acv 0 # ITB acv +system.cpu.itb.fetch_hits 6415 # ITB hits +system.cpu.itb.fetch_misses 17 # ITB misses +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.read_acv 0 # DTB read access violations +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.write_acv 0 # DTB write access violations +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.numCycles 223854 # number of cpu cycles simulated +system.cpu.num_insts 6404 # Number of instructions executed +system.cpu.num_refs 2060 # Number of memory references +system.cpu.workload.PROG:num_syscalls 17 # Number of system calls + +---------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/config.ini b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/config.ini new file mode 100644 index 000000000..1658b1622 --- /dev/null +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/config.ini @@ -0,0 +1,287 @@ +[root] +type=Root +children=system +dummy=0 + +[system] +type=System +children=cpu physmem ruby +mem_mode=timing +physmem=system.physmem + +[system.cpu] +type=TimingSimpleCPU +children=dtb itb tracer workload +checker=Null +clock=1 +cpu_id=0 +defer_registration=false +do_checkpoint_insts=true +do_statistics_insts=true +dtb=system.cpu.dtb +function_trace=false +function_trace_start=0 +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +phase=0 +progress_interval=0 +system=system +tracer=system.cpu.tracer +workload=system.cpu.workload +dcache_port=system.ruby.network.topology.ext_links0.ext_node.sequencer.port[1] +icache_port=system.ruby.network.topology.ext_links0.ext_node.sequencer.port[0] + +[system.cpu.dtb] +type=AlphaTLB +size=64 + +[system.cpu.itb] +type=AlphaTLB +size=48 + +[system.cpu.tracer] +type=ExeTracer + +[system.cpu.workload] +type=LiveProcess +cmd=hello +cwd= +egid=100 +env= +errout=cerr +euid=100 +executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/alpha/linux/hello +gid=100 +input=cin +max_stack_size=67108864 +output=cout +pid=100 +ppid=99 +simpoint=0 +system=system +uid=100 + +[system.physmem] +type=PhysicalMemory +file= +latency=30 +latency_var=0 +null=false +range=0:134217727 +zero=false +port=system.ruby.network.topology.ext_links0.ext_node.sequencer.physMemPort + +[system.ruby] +type=RubySystem +children=debug network profiler tracer +block_size_bytes=64 +clock=1 +debug=system.ruby.debug +mem_size=134217728 +network=system.ruby.network +profiler=system.ruby.profiler +random_seed=1234 +randomization=false +stats_filename=ruby.stats +tracer=system.ruby.tracer + +[system.ruby.debug] +type=RubyDebug +filter_string=none +output_filename=none +protocol_trace=false +start_time=1 +verbosity_string=none + +[system.ruby.network] +type=SimpleNetwork +children=topology +adaptive_routing=true +buffer_size=0 +control_msg_size=8 +endpoint_bandwidth=10000 +link_latency=1 +number_of_virtual_networks=10 +topology=system.ruby.network.topology + +[system.ruby.network.topology] +type=Topology +children=ext_links0 ext_links1 ext_links2 int_links0 int_links1 int_links2 +ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1 system.ruby.network.topology.ext_links2 +int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1 system.ruby.network.topology.int_links2 +num_int_nodes=4 +print_config=false + +[system.ruby.network.topology.ext_links0] +type=ExtLink +children=ext_node +bw_multiplier=64 +ext_node=system.ruby.network.topology.ext_links0.ext_node +int_node=0 +latency=1 +weight=1 + +[system.ruby.network.topology.ext_links0.ext_node] +type=L1Cache_Controller +children=sequencer +L1DcacheMemory=system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache +L1IcacheMemory=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache +N_tokens=2 +buffer_size=0 +dynamic_timeout_enabled=true +fixed_timeout_latency=300 +l1_request_latency=2 +l1_response_latency=2 +l2_select_num_bits=0 +number_of_TBEs=256 +recycle_latency=10 +retry_threshold=1 +sequencer=system.ruby.network.topology.ext_links0.ext_node.sequencer +transitions_per_cycle=32 +version=0 + +[system.ruby.network.topology.ext_links0.ext_node.sequencer] +type=RubySequencer +children=dcache icache +dcache=system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache +deadlock_threshold=500000 +icache=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache +max_outstanding_requests=16 +physmem=system.physmem +using_ruby_tester=false +version=0 +physMemPort=system.physmem.port[0] +port=system.cpu.icache_port system.cpu.dcache_port + +[system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache] +type=RubyCache +assoc=2 +latency=3 +replacement_policy=PSEUDO_LRU +size=256 + +[system.ruby.network.topology.ext_links0.ext_node.sequencer.icache] +type=RubyCache +assoc=2 +latency=3 +replacement_policy=PSEUDO_LRU +size=256 + +[system.ruby.network.topology.ext_links1] +type=ExtLink +children=ext_node +bw_multiplier=64 +ext_node=system.ruby.network.topology.ext_links1.ext_node +int_node=1 +latency=1 +weight=1 + +[system.ruby.network.topology.ext_links1.ext_node] +type=L2Cache_Controller +children=L2cacheMemory +L2cacheMemory=system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory +N_tokens=2 +buffer_size=0 +filtering_enabled=true +l2_request_latency=10 +l2_response_latency=10 +number_of_TBEs=256 +recycle_latency=10 +transitions_per_cycle=32 +version=0 + +[system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory] +type=RubyCache +assoc=2 +latency=15 +replacement_policy=PSEUDO_LRU +size=512 + +[system.ruby.network.topology.ext_links2] +type=ExtLink +children=ext_node +bw_multiplier=64 +ext_node=system.ruby.network.topology.ext_links2.ext_node +int_node=2 +latency=1 +weight=1 + +[system.ruby.network.topology.ext_links2.ext_node] +type=Directory_Controller +children=directory memBuffer +buffer_size=0 +directory=system.ruby.network.topology.ext_links2.ext_node.directory +directory_latency=6 +distributed_persistent=true +fixed_timeout_latency=300 +l2_select_num_bits=0 +memBuffer=system.ruby.network.topology.ext_links2.ext_node.memBuffer +number_of_TBEs=256 +recycle_latency=10 +transitions_per_cycle=32 +version=0 + +[system.ruby.network.topology.ext_links2.ext_node.directory] +type=RubyDirectoryMemory +size=134217728 +version=0 + +[system.ruby.network.topology.ext_links2.ext_node.memBuffer] +type=RubyMemoryControl +bank_bit_0=8 +bank_busy_time=11 +bank_queue_size=12 +banks_per_rank=8 +basic_bus_busy_time=2 +dimm_bit_0=12 +dimms_per_channel=2 +mem_bus_cycle_multiplier=10 +mem_ctl_latency=12 +mem_fixed_delay=0 +mem_random_arbitrate=0 +rank_bit_0=11 +rank_rank_delay=1 +ranks_per_dimm=2 +read_write_delay=2 +refresh_period=1560 +tFaw=0 +version=0 + +[system.ruby.network.topology.int_links0] +type=IntLink +bw_multiplier=16 +latency=1 +node_a=0 +node_b=3 +weight=1 + +[system.ruby.network.topology.int_links1] +type=IntLink +bw_multiplier=16 +latency=1 +node_a=1 +node_b=3 +weight=1 + +[system.ruby.network.topology.int_links2] +type=IntLink +bw_multiplier=16 +latency=1 +node_a=2 +node_b=3 +weight=1 + +[system.ruby.profiler] +type=RubyProfiler +all_instructions=false +hot_lines=false +num_of_sequencers=1 + +[system.ruby.tracer] +type=RubyTracer +warmup_length=100000 + diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/ruby.stats b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/ruby.stats new file mode 100644 index 000000000..ae58be613 --- /dev/null +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/ruby.stats @@ -0,0 +1,912 @@ + +================ Begin RubySystem Configuration Print ================ + +RubySystem config: + random_seed: 1234 + randomization: 0 + cycle_period: 1 + block_size_bytes: 64 + block_size_bits: 6 + memory_size_bytes: 134217728 + memory_size_bits: 27 + +Network Configuration +--------------------- +network: SIMPLE_NETWORK +topology: + +virtual_net_0: active, ordered +virtual_net_1: active, unordered +virtual_net_2: active, ordered +virtual_net_3: active, unordered +virtual_net_4: active, unordered +virtual_net_5: active, ordered +virtual_net_6: inactive +virtual_net_7: inactive +virtual_net_8: inactive +virtual_net_9: inactive + + +Profiler Configuration +---------------------- +periodic_stats_period: 1000000 + +================ End RubySystem Configuration Print ================ + + +Real time: Jan/28/2010 15:55:45 + +Profiler Stats +-------------- +Elapsed_time_in_seconds: 0 +Elapsed_time_in_minutes: 0 +Elapsed_time_in_hours: 0 +Elapsed_time_in_days: 0 + +Virtual_time_in_seconds: 0.43 +Virtual_time_in_minutes: 0.00716667 +Virtual_time_in_hours: 0.000119444 +Virtual_time_in_days: 4.97685e-06 + +Ruby_current_time: 236654 +Ruby_start_time: 0 +Ruby_cycles: 236654 + +mbytes_resident: 34.4141 +mbytes_total: 34.4219 +resident_ratio: 1 + +Total_misses: 0 +total_misses: 0 [ 0 ] +user_misses: 0 [ 0 ] +supervisor_misses: 0 [ 0 ] + +ruby_cycles_executed: 236655 [ 236655 ] + +transactions_started: 0 [ 0 ] +transactions_ended: 0 [ 0 ] +cycles_per_transaction: 0 [ 0 ] +misses_per_transaction: 0 [ 0 ] + + +Busy Controller Counts: +L1Cache-0:0 +L2Cache-0:0 +Directory-0:0 + + +Busy Bank Count:0 + +sequencer_requests_outstanding: [binsize: 1 max: 1 count: 8465 average: 1 | standard deviation: 0 | 0 8465 ] + +All Non-Zero Cycle Demand Cache Accesses +---------------------------------------- +miss_latency: [binsize: 2 max: 279 count: 8464 average: 26.9601 | standard deviation: 58.5578 | 0 7082 0 0 0 0 0 0 0 0 0 0 0 220 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 268 180 200 165 117 12 3 8 3 4 46 30 32 33 37 0 1 1 1 2 1 4 1 3 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 4 1 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_1: [binsize: 2 max: 279 count: 6414 average: 18.8457 | standard deviation: 49.2277 | 0 5768 0 0 0 0 0 0 0 0 0 0 0 55 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 125 84 121 94 59 8 2 4 1 3 20 12 18 22 8 0 1 0 0 0 0 2 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_2: [binsize: 2 max: 279 count: 1185 average: 66.1527 | standard deviation: 80.7635 | 0 660 0 0 0 0 0 0 0 0 0 0 0 99 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 112 56 67 56 46 4 0 3 2 0 24 12 14 10 10 0 0 0 1 1 1 2 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_3: [binsize: 2 max: 213 count: 865 average: 33.437 | standard deviation: 63.4371 | 0 654 0 0 0 0 0 0 0 0 0 0 0 66 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 40 12 15 12 0 1 1 0 1 2 6 0 1 19 0 0 1 0 1 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] + +All Non-Zero Cycle SW Prefetch Requests +------------------------------------ +prefetch_latency: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +prefetch_latency_L2Miss:[binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +Request vs. RubySystem State Profile +-------------------------------- + + +filter_action: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + +Message Delayed Cycles +---------------------- +Total_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +Total_nonPF_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + virtual_network_0_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + virtual_network_1_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + virtual_network_2_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + virtual_network_3_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + virtual_network_4_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + virtual_network_5_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + virtual_network_6_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + virtual_network_7_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + virtual_network_8_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + virtual_network_9_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + +Resource Usage +-------------- +page_size: 4096 +user_time: 0 +system_time: 0 +page_reclaims: 7348 +page_faults: 2239 +swaps: 0 +block_inputs: 0 +block_outputs: 0 + +Network Stats +------------- + +switch_0_inlinks: 2 +switch_0_outlinks: 2 +links_utilized_percent_switch_0: 0.164956 + links_utilized_percent_switch_0_link_0: 0.0658979 bw: 640000 base_latency: 1 + links_utilized_percent_switch_0_link_1: 0.264014 bw: 160000 base_latency: 1 + + outgoing_messages_switch_0_link_0_Response_Data: 1162 83664 [ 0 1162 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_0_ResponseL2hit_Data: 220 15840 [ 0 220 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_0_Response_Control: 38 304 [ 0 38 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Request_Control: 1382 11056 [ 0 0 0 0 1382 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Writeback_Data: 1220 87840 [ 0 1220 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Writeback_Control: 134 1072 [ 0 134 0 0 0 0 0 0 0 0 ] base_latency: 1 + +switch_1_inlinks: 2 +switch_1_outlinks: 2 +links_utilized_percent_switch_1: 0.0968503 + links_utilized_percent_switch_1_link_0: 0.0660035 bw: 640000 base_latency: 1 + links_utilized_percent_switch_1_link_1: 0.127697 bw: 160000 base_latency: 1 + + outgoing_messages_switch_1_link_0_Request_Control: 1382 11056 [ 0 0 0 0 1382 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_Writeback_Data: 1220 87840 [ 0 1220 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_Writeback_Control: 134 1072 [ 0 134 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Request_Control: 1180 9440 [ 0 0 0 1180 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_ResponseL2hit_Data: 220 15840 [ 0 220 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Response_Control: 38 304 [ 0 38 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Writeback_Data: 207 14904 [ 0 207 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Writeback_Control: 983 7864 [ 0 983 0 0 0 0 0 0 0 0 ] base_latency: 1 + +switch_2_inlinks: 2 +switch_2_outlinks: 2 +links_utilized_percent_switch_2: 0.12111 + links_utilized_percent_switch_2_link_0: 0.0212652 bw: 640000 base_latency: 1 + links_utilized_percent_switch_2_link_1: 0.220955 bw: 160000 base_latency: 1 + + outgoing_messages_switch_2_link_0_Request_Control: 1180 9440 [ 0 0 0 1180 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_0_Writeback_Data: 207 14904 [ 0 207 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_0_Writeback_Control: 983 7864 [ 0 983 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Response_Data: 1162 83664 [ 0 1162 0 0 0 0 0 0 0 0 ] base_latency: 1 + +switch_3_inlinks: 3 +switch_3_outlinks: 3 +links_utilized_percent_switch_3: 0.204222 + links_utilized_percent_switch_3_link_0: 0.263592 bw: 160000 base_latency: 1 + links_utilized_percent_switch_3_link_1: 0.264014 bw: 160000 base_latency: 1 + links_utilized_percent_switch_3_link_2: 0.0850609 bw: 160000 base_latency: 1 + + outgoing_messages_switch_3_link_0_Response_Data: 1162 83664 [ 0 1162 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_0_ResponseL2hit_Data: 220 15840 [ 0 220 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_0_Response_Control: 38 304 [ 0 38 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_1_Request_Control: 1382 11056 [ 0 0 0 0 1382 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_1_Writeback_Data: 1220 87840 [ 0 1220 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_1_Writeback_Control: 134 1072 [ 0 134 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_2_Request_Control: 1180 9440 [ 0 0 0 1180 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_2_Writeback_Data: 207 14904 [ 0 207 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_2_Writeback_Control: 983 7864 [ 0 983 0 0 0 0 0 0 0 0 ] base_latency: 1 + +Cache Stats: system.ruby.network.topology.ext_links0.ext_node.sequencer.icache + system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_misses: 0 + system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_demand_misses: 0 + system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_prefetches: 0 + system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_sw_prefetches: 0 + system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_hw_prefetches: 0 + system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_misses_per_transaction: nan + + system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + +Cache Stats: system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache + system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_misses: 0 + system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_demand_misses: 0 + system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_prefetches: 0 + system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_sw_prefetches: 0 + system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_hw_prefetches: 0 + system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_misses_per_transaction: nan + + system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + + --- L1Cache 0 --- + - Event Counts - +Load 1185 +Ifetch 6414 +Store 865 +L1_Replacement 1375 +Data_Shared 154 +Data_Owner 0 +Data_All_Tokens 1228 +Ack 38 +Ack_All_Tokens 0 +Transient_GETX 0 +Transient_Local_GETX 0 +Transient_GETS 0 +Transient_Local_GETS 0 +Transient_GETS_Last_Token 0 +Transient_Local_GETS_Last_Token 0 +Persistent_GETX 0 +Persistent_GETS 0 +Own_Lock_or_Unlock 0 +Request_Timeout 0 +Use_TimeoutStarverX 0 +Use_TimeoutStarverS 0 +Use_TimeoutNoStarvers 1227 + + - Transitions - +NP Load 525 +NP Ifetch 646 +NP Store 191 +NP Data_Shared 0 <-- +NP Data_Owner 0 <-- +NP Data_All_Tokens 0 <-- +NP Ack 0 <-- +NP Transient_GETX 0 <-- +NP Transient_Local_GETX 0 <-- +NP Transient_GETS 0 <-- +NP Transient_Local_GETS 0 <-- +NP Persistent_GETX 0 <-- +NP Persistent_GETS 0 <-- +NP Own_Lock_or_Unlock 0 <-- + +I Load 0 <-- +I Ifetch 0 <-- +I Store 0 <-- +I L1_Replacement 0 <-- +I Data_Shared 0 <-- +I Data_Owner 0 <-- +I Data_All_Tokens 0 <-- +I Ack 0 <-- +I Transient_GETX 0 <-- +I Transient_Local_GETX 0 <-- +I Transient_GETS 0 <-- +I Transient_Local_GETS 0 <-- +I Transient_GETS_Last_Token 0 <-- +I Transient_Local_GETS_Last_Token 0 <-- +I Persistent_GETX 0 <-- +I Persistent_GETS 0 <-- +I Own_Lock_or_Unlock 0 <-- + +S Load 166 +S Ifetch 314 +S Store 20 +S L1_Replacement 134 +S Data_Shared 0 <-- +S Data_Owner 0 <-- +S Data_All_Tokens 0 <-- +S Ack 0 <-- +S Transient_GETX 0 <-- +S Transient_Local_GETX 0 <-- +S Transient_GETS 0 <-- +S Transient_Local_GETS 0 <-- +S Transient_GETS_Last_Token 0 <-- +S Transient_Local_GETS_Last_Token 0 <-- +S Persistent_GETX 0 <-- +S Persistent_GETS 0 <-- +S Own_Lock_or_Unlock 0 <-- + +O Load 0 <-- +O Ifetch 0 <-- +O Store 0 <-- +O L1_Replacement 0 <-- +O Data_Shared 0 <-- +O Data_All_Tokens 0 <-- +O Ack 0 <-- +O Ack_All_Tokens 0 <-- +O Transient_GETX 0 <-- +O Transient_Local_GETX 0 <-- +O Transient_GETS 0 <-- +O Transient_Local_GETS 0 <-- +O Transient_GETS_Last_Token 0 <-- +O Transient_Local_GETS_Last_Token 0 <-- +O Persistent_GETX 0 <-- +O Persistent_GETS 0 <-- +O Own_Lock_or_Unlock 0 <-- + +M Load 184 +M Ifetch 3447 +M Store 33 +M L1_Replacement 952 +M Transient_GETX 0 <-- +M Transient_Local_GETX 0 <-- +M Transient_GETS 0 <-- +M Transient_Local_GETS 0 <-- +M Persistent_GETX 0 <-- +M Persistent_GETS 0 <-- +M Own_Lock_or_Unlock 0 <-- + +MM Load 221 +MM Ifetch 0 <-- +MM Store 333 +MM L1_Replacement 268 +MM Transient_GETX 0 <-- +MM Transient_Local_GETX 0 <-- +MM Transient_GETS 0 <-- +MM Transient_Local_GETS 0 <-- +MM Persistent_GETX 0 <-- +MM Persistent_GETS 0 <-- +MM Own_Lock_or_Unlock 0 <-- + +M_W Load 69 +M_W Ifetch 2007 +M_W Store 25 +M_W L1_Replacement 14 +M_W Transient_GETX 0 <-- +M_W Transient_Local_GETX 0 <-- +M_W Transient_GETS 0 <-- +M_W Transient_Local_GETS 0 <-- +M_W Persistent_GETX 0 <-- +M_W Persistent_GETS 0 <-- +M_W Own_Lock_or_Unlock 0 <-- +M_W Use_TimeoutStarverX 0 <-- +M_W Use_TimeoutStarverS 0 <-- +M_W Use_TimeoutNoStarvers 991 + +MM_W Load 20 +MM_W Ifetch 0 <-- +MM_W Store 263 +MM_W L1_Replacement 7 +MM_W Transient_GETX 0 <-- +MM_W Transient_Local_GETX 0 <-- +MM_W Transient_GETS 0 <-- +MM_W Transient_Local_GETS 0 <-- +MM_W Persistent_GETX 0 <-- +MM_W Persistent_GETS 0 <-- +MM_W Own_Lock_or_Unlock 0 <-- +MM_W Use_TimeoutStarverX 0 <-- +MM_W Use_TimeoutStarverS 0 <-- +MM_W Use_TimeoutNoStarvers 236 + +IM Load 0 <-- +IM Ifetch 0 <-- +IM Store 0 <-- +IM L1_Replacement 0 <-- +IM Data_Shared 0 <-- +IM Data_Owner 0 <-- +IM Data_All_Tokens 191 +IM Ack 7 +IM Transient_GETX 0 <-- +IM Transient_Local_GETX 0 <-- +IM Transient_GETS 0 <-- +IM Transient_Local_GETS 0 <-- +IM Transient_GETS_Last_Token 0 <-- +IM Transient_Local_GETS_Last_Token 0 <-- +IM Persistent_GETX 0 <-- +IM Persistent_GETS 0 <-- +IM Own_Lock_or_Unlock 0 <-- +IM Request_Timeout 0 <-- + +SM Load 0 <-- +SM Ifetch 0 <-- +SM Store 0 <-- +SM L1_Replacement 0 <-- +SM Data_Shared 0 <-- +SM Data_Owner 0 <-- +SM Data_All_Tokens 20 +SM Ack 0 <-- +SM Transient_GETX 0 <-- +SM Transient_Local_GETX 0 <-- +SM Transient_GETS 0 <-- +SM Transient_Local_GETS 0 <-- +SM Transient_GETS_Last_Token 0 <-- +SM Transient_Local_GETS_Last_Token 0 <-- +SM Persistent_GETX 0 <-- +SM Persistent_GETS 0 <-- +SM Own_Lock_or_Unlock 0 <-- +SM Request_Timeout 0 <-- + +OM Load 0 <-- +OM Ifetch 0 <-- +OM Store 0 <-- +OM L1_Replacement 0 <-- +OM Data_Shared 0 <-- +OM Data_All_Tokens 0 <-- +OM Ack 0 <-- +OM Ack_All_Tokens 0 <-- +OM Transient_GETX 0 <-- +OM Transient_Local_GETX 0 <-- +OM Transient_GETS 0 <-- +OM Transient_Local_GETS 0 <-- +OM Transient_GETS_Last_Token 0 <-- +OM Transient_Local_GETS_Last_Token 0 <-- +OM Persistent_GETX 0 <-- +OM Persistent_GETS 0 <-- +OM Own_Lock_or_Unlock 0 <-- +OM Request_Timeout 0 <-- + +IS Load 0 <-- +IS Ifetch 0 <-- +IS Store 0 <-- +IS L1_Replacement 0 <-- +IS Data_Shared 154 +IS Data_Owner 0 <-- +IS Data_All_Tokens 1017 +IS Ack 31 +IS Transient_GETX 0 <-- +IS Transient_Local_GETX 0 <-- +IS Transient_GETS 0 <-- +IS Transient_Local_GETS 0 <-- +IS Transient_GETS_Last_Token 0 <-- +IS Transient_Local_GETS_Last_Token 0 <-- +IS Persistent_GETX 0 <-- +IS Persistent_GETS 0 <-- +IS Own_Lock_or_Unlock 0 <-- +IS Request_Timeout 0 <-- + +I_L Load 0 <-- +I_L Ifetch 0 <-- +I_L Store 0 <-- +I_L L1_Replacement 0 <-- +I_L Data_Shared 0 <-- +I_L Data_Owner 0 <-- +I_L Data_All_Tokens 0 <-- +I_L Ack 0 <-- +I_L Transient_GETX 0 <-- +I_L Transient_Local_GETX 0 <-- +I_L Transient_GETS 0 <-- +I_L Transient_Local_GETS 0 <-- +I_L Transient_GETS_Last_Token 0 <-- +I_L Transient_Local_GETS_Last_Token 0 <-- +I_L Persistent_GETX 0 <-- +I_L Persistent_GETS 0 <-- +I_L Own_Lock_or_Unlock 0 <-- + +S_L Load 0 <-- +S_L Ifetch 0 <-- +S_L Store 0 <-- +S_L L1_Replacement 0 <-- +S_L Data_Shared 0 <-- +S_L Data_Owner 0 <-- +S_L Data_All_Tokens 0 <-- +S_L Ack 0 <-- +S_L Transient_GETX 0 <-- +S_L Transient_Local_GETX 0 <-- +S_L Transient_GETS 0 <-- +S_L Transient_Local_GETS 0 <-- +S_L Transient_GETS_Last_Token 0 <-- +S_L Transient_Local_GETS_Last_Token 0 <-- +S_L Persistent_GETX 0 <-- +S_L Persistent_GETS 0 <-- +S_L Own_Lock_or_Unlock 0 <-- + +IM_L Load 0 <-- +IM_L Ifetch 0 <-- +IM_L Store 0 <-- +IM_L L1_Replacement 0 <-- +IM_L Data_Shared 0 <-- +IM_L Data_Owner 0 <-- +IM_L Data_All_Tokens 0 <-- +IM_L Ack 0 <-- +IM_L Transient_GETX 0 <-- +IM_L Transient_Local_GETX 0 <-- +IM_L Transient_GETS 0 <-- +IM_L Transient_Local_GETS 0 <-- +IM_L Transient_GETS_Last_Token 0 <-- +IM_L Transient_Local_GETS_Last_Token 0 <-- +IM_L Persistent_GETX 0 <-- +IM_L Persistent_GETS 0 <-- +IM_L Own_Lock_or_Unlock 0 <-- +IM_L Request_Timeout 0 <-- + +SM_L Load 0 <-- +SM_L Ifetch 0 <-- +SM_L Store 0 <-- +SM_L L1_Replacement 0 <-- +SM_L Data_Shared 0 <-- +SM_L Data_Owner 0 <-- +SM_L Data_All_Tokens 0 <-- +SM_L Ack 0 <-- +SM_L Transient_GETX 0 <-- +SM_L Transient_Local_GETX 0 <-- +SM_L Transient_GETS 0 <-- +SM_L Transient_Local_GETS 0 <-- +SM_L Transient_GETS_Last_Token 0 <-- +SM_L Transient_Local_GETS_Last_Token 0 <-- +SM_L Persistent_GETX 0 <-- +SM_L Persistent_GETS 0 <-- +SM_L Own_Lock_or_Unlock 0 <-- +SM_L Request_Timeout 0 <-- + +IS_L Load 0 <-- +IS_L Ifetch 0 <-- +IS_L Store 0 <-- +IS_L L1_Replacement 0 <-- +IS_L Data_Shared 0 <-- +IS_L Data_Owner 0 <-- +IS_L Data_All_Tokens 0 <-- +IS_L Ack 0 <-- +IS_L Transient_GETX 0 <-- +IS_L Transient_Local_GETX 0 <-- +IS_L Transient_GETS 0 <-- +IS_L Transient_Local_GETS 0 <-- +IS_L Transient_GETS_Last_Token 0 <-- +IS_L Transient_Local_GETS_Last_Token 0 <-- +IS_L Persistent_GETX 0 <-- +IS_L Persistent_GETS 0 <-- +IS_L Own_Lock_or_Unlock 0 <-- +IS_L Request_Timeout 0 <-- + +Cache Stats: system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory + system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_misses: 0 + system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_demand_misses: 0 + system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_prefetches: 0 + system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_sw_prefetches: 0 + system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_hw_prefetches: 0 + system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_misses_per_transaction: nan + + system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + + --- L2Cache 0 --- + - Event Counts - +L1_GETS 1140 +L1_GETS_Last_Token 31 +L1_GETX 211 +L1_INV 0 +Transient_GETX 0 +Transient_GETS 0 +Transient_GETS_Last_Token 0 +L2_Replacement 1276 +Writeback_Tokens 82 +Writeback_Shared_Data 0 +Writeback_All_Tokens 1272 +Writeback_Owned 0 +Data_Shared 0 +Data_Owner 0 +Data_All_Tokens 0 +Ack 0 +Ack_All_Tokens 0 +Persistent_GETX 0 +Persistent_GETS 0 +Own_Lock_or_Unlock 0 + + - Transitions - +NP L1_GETS 986 +NP L1_GETX 138 +NP L1_INV 0 <-- +NP Transient_GETX 0 <-- +NP Transient_GETS 0 <-- +NP Writeback_Tokens 82 +NP Writeback_Shared_Data 0 <-- +NP Writeback_All_Tokens 1202 +NP Writeback_Owned 0 <-- +NP Data_Shared 0 <-- +NP Data_Owner 0 <-- +NP Data_All_Tokens 0 <-- +NP Ack 0 <-- +NP Persistent_GETX 0 <-- +NP Persistent_GETS 0 <-- +NP Own_Lock_or_Unlock 0 <-- + +I L1_GETS 0 <-- +I L1_GETS_Last_Token 31 +I L1_GETX 7 +I L1_INV 0 <-- +I Transient_GETX 0 <-- +I Transient_GETS 0 <-- +I Transient_GETS_Last_Token 0 <-- +I L2_Replacement 130 +I Writeback_Tokens 0 <-- +I Writeback_Shared_Data 0 <-- +I Writeback_All_Tokens 18 +I Writeback_Owned 0 <-- +I Data_Shared 0 <-- +I Data_Owner 0 <-- +I Data_All_Tokens 0 <-- +I Ack 0 <-- +I Persistent_GETX 0 <-- +I Persistent_GETS 0 <-- +I Own_Lock_or_Unlock 0 <-- + +S L1_GETS 0 <-- +S L1_GETS_Last_Token 0 <-- +S L1_GETX 0 <-- +S L1_INV 0 <-- +S Transient_GETX 0 <-- +S Transient_GETS 0 <-- +S Transient_GETS_Last_Token 0 <-- +S L2_Replacement 0 <-- +S Writeback_Tokens 0 <-- +S Writeback_Shared_Data 0 <-- +S Writeback_All_Tokens 0 <-- +S Writeback_Owned 0 <-- +S Data_Shared 0 <-- +S Data_Owner 0 <-- +S Data_All_Tokens 0 <-- +S Ack 0 <-- +S Persistent_GETX 0 <-- +S Persistent_GETS 0 <-- +S Own_Lock_or_Unlock 0 <-- + +O L1_GETS 0 <-- +O L1_GETS_Last_Token 0 <-- +O L1_GETX 18 +O L1_INV 0 <-- +O Transient_GETX 0 <-- +O Transient_GETS 0 <-- +O Transient_GETS_Last_Token 0 <-- +O L2_Replacement 84 +O Writeback_Tokens 0 <-- +O Writeback_Shared_Data 0 <-- +O Writeback_All_Tokens 52 +O Data_Shared 0 <-- +O Data_All_Tokens 0 <-- +O Ack 0 <-- +O Ack_All_Tokens 0 <-- +O Persistent_GETX 0 <-- +O Persistent_GETS 0 <-- +O Own_Lock_or_Unlock 0 <-- + +M L1_GETS 154 +M L1_GETX 48 +M L1_INV 0 <-- +M Transient_GETX 0 <-- +M Transient_GETS 0 <-- +M L2_Replacement 1062 +M Persistent_GETX 0 <-- +M Persistent_GETS 0 <-- +M Own_Lock_or_Unlock 0 <-- + +I_L L1_GETS 0 <-- +I_L L1_GETX 0 <-- +I_L L1_INV 0 <-- +I_L Transient_GETX 0 <-- +I_L Transient_GETS 0 <-- +I_L Transient_GETS_Last_Token 0 <-- +I_L L2_Replacement 0 <-- +I_L Writeback_Tokens 0 <-- +I_L Writeback_Shared_Data 0 <-- +I_L Writeback_All_Tokens 0 <-- +I_L Writeback_Owned 0 <-- +I_L Data_Shared 0 <-- +I_L Data_Owner 0 <-- +I_L Data_All_Tokens 0 <-- +I_L Ack 0 <-- +I_L Persistent_GETX 0 <-- +I_L Persistent_GETS 0 <-- +I_L Own_Lock_or_Unlock 0 <-- + +S_L L1_GETS 0 <-- +S_L L1_GETS_Last_Token 0 <-- +S_L L1_GETX 0 <-- +S_L L1_INV 0 <-- +S_L Transient_GETX 0 <-- +S_L Transient_GETS 0 <-- +S_L Transient_GETS_Last_Token 0 <-- +S_L L2_Replacement 0 <-- +S_L Writeback_Tokens 0 <-- +S_L Writeback_Shared_Data 0 <-- +S_L Writeback_All_Tokens 0 <-- +S_L Writeback_Owned 0 <-- +S_L Data_Shared 0 <-- +S_L Data_Owner 0 <-- +S_L Data_All_Tokens 0 <-- +S_L Ack 0 <-- +S_L Persistent_GETX 0 <-- +S_L Persistent_GETS 0 <-- +S_L Own_Lock_or_Unlock 0 <-- + +Memory controller: system.ruby.network.topology.ext_links2.ext_node.memBuffer: + memory_total_requests: 1369 + memory_reads: 1162 + memory_writes: 207 + memory_refreshes: 493 + memory_total_request_delays: 529 + memory_delays_per_request: 0.386413 + memory_delays_in_input_queue: 185 + memory_delays_behind_head_of_bank_queue: 0 + memory_delays_stalled_at_head_of_bank_queue: 344 + memory_stalls_for_bank_busy: 101 + memory_stalls_for_random_busy: 0 + memory_stalls_for_anti_starvation: 0 + memory_stalls_for_arbitration: 19 + memory_stalls_for_bus: 222 + memory_stalls_for_tfaw: 0 + memory_stalls_for_read_write_turnaround: 2 + memory_stalls_for_read_read_turnaround: 0 + accesses_per_bank: 75 17 45 46 54 108 37 16 19 22 32 34 52 49 39 31 39 21 21 21 28 38 61 27 30 22 32 72 90 124 14 53 + + --- Directory 0 --- + - Event Counts - +GETX 163 +GETS 1017 +Lockdown 0 +Unlockdown 0 +Own_Lock_or_Unlock 0 +Data_Owner 19 +Data_All_Tokens 188 +Ack_Owner 65 +Ack_Owner_All_Tokens 874 +Tokens 0 +Ack_All_Tokens 44 +Request_Timeout 0 +Memory_Data 1162 +Memory_Ack 207 +DMA_READ 0 +DMA_WRITE 0 +DMA_WRITE_All_Tokens 0 + + - Transitions - +O GETX 145 +O GETS 1017 +O Lockdown 0 <-- +O Own_Lock_or_Unlock 0 <-- +O Data_Owner 0 <-- +O Data_All_Tokens 0 <-- +O Tokens 0 <-- +O Ack_All_Tokens 44 +O DMA_READ 0 <-- +O DMA_WRITE 0 <-- +O DMA_WRITE_All_Tokens 0 <-- + +NO GETX 18 +NO GETS 0 <-- +NO Lockdown 0 <-- +NO Own_Lock_or_Unlock 0 <-- +NO Data_Owner 19 +NO Data_All_Tokens 188 +NO Ack_Owner 65 +NO Ack_Owner_All_Tokens 874 +NO Tokens 0 <-- +NO DMA_READ 0 <-- +NO DMA_WRITE 0 <-- + +L GETX 0 <-- +L GETS 0 <-- +L Lockdown 0 <-- +L Unlockdown 0 <-- +L Own_Lock_or_Unlock 0 <-- +L Data_Owner 0 <-- +L Data_All_Tokens 0 <-- +L Ack_Owner 0 <-- +L Ack_Owner_All_Tokens 0 <-- +L Tokens 0 <-- +L DMA_READ 0 <-- +L DMA_WRITE 0 <-- + +O_W GETX 0 <-- +O_W GETS 0 <-- +O_W Lockdown 0 <-- +O_W Unlockdown 0 <-- +O_W Own_Lock_or_Unlock 0 <-- +O_W Data_Owner 0 <-- +O_W Ack_Owner 0 <-- +O_W Tokens 0 <-- +O_W Ack_All_Tokens 0 <-- +O_W Memory_Data 0 <-- +O_W Memory_Ack 207 +O_W DMA_READ 0 <-- +O_W DMA_WRITE 0 <-- + +L_O_W GETX 0 <-- +L_O_W GETS 0 <-- +L_O_W Lockdown 0 <-- +L_O_W Unlockdown 0 <-- +L_O_W Own_Lock_or_Unlock 0 <-- +L_O_W Data_Owner 0 <-- +L_O_W Ack_Owner 0 <-- +L_O_W Tokens 0 <-- +L_O_W Ack_All_Tokens 0 <-- +L_O_W Memory_Data 0 <-- +L_O_W Memory_Ack 0 <-- +L_O_W DMA_READ 0 <-- +L_O_W DMA_WRITE 0 <-- + +L_NO_W GETX 0 <-- +L_NO_W GETS 0 <-- +L_NO_W Lockdown 0 <-- +L_NO_W Unlockdown 0 <-- +L_NO_W Own_Lock_or_Unlock 0 <-- +L_NO_W Data_Owner 0 <-- +L_NO_W Ack_Owner 0 <-- +L_NO_W Tokens 0 <-- +L_NO_W Ack_All_Tokens 0 <-- +L_NO_W Memory_Data 0 <-- +L_NO_W DMA_READ 0 <-- +L_NO_W DMA_WRITE 0 <-- + +DR_L_W GETX 0 <-- +DR_L_W GETS 0 <-- +DR_L_W Lockdown 0 <-- +DR_L_W Unlockdown 0 <-- +DR_L_W Own_Lock_or_Unlock 0 <-- +DR_L_W Data_Owner 0 <-- +DR_L_W Ack_Owner 0 <-- +DR_L_W Tokens 0 <-- +DR_L_W Ack_All_Tokens 0 <-- +DR_L_W Request_Timeout 0 <-- +DR_L_W Memory_Data 0 <-- +DR_L_W DMA_READ 0 <-- +DR_L_W DMA_WRITE 0 <-- + +NO_W GETX 0 <-- +NO_W GETS 0 <-- +NO_W Lockdown 0 <-- +NO_W Unlockdown 0 <-- +NO_W Own_Lock_or_Unlock 0 <-- +NO_W Data_Owner 0 <-- +NO_W Ack_Owner 0 <-- +NO_W Tokens 0 <-- +NO_W Ack_All_Tokens 0 <-- +NO_W Memory_Data 1162 +NO_W DMA_READ 0 <-- +NO_W DMA_WRITE 0 <-- + +O_DW_W GETX 0 <-- +O_DW_W GETS 0 <-- +O_DW_W Data_Owner 0 <-- +O_DW_W Ack_Owner 0 <-- +O_DW_W Tokens 0 <-- +O_DW_W Ack_All_Tokens 0 <-- +O_DW_W Memory_Ack 0 <-- +O_DW_W DMA_READ 0 <-- +O_DW_W DMA_WRITE 0 <-- + +O_DR_W GETX 0 <-- +O_DR_W GETS 0 <-- +O_DR_W Lockdown 0 <-- +O_DR_W Unlockdown 0 <-- +O_DR_W Own_Lock_or_Unlock 0 <-- +O_DR_W Data_Owner 0 <-- +O_DR_W Ack_Owner 0 <-- +O_DR_W Tokens 0 <-- +O_DR_W Ack_All_Tokens 0 <-- +O_DR_W Memory_Data 0 <-- +O_DR_W DMA_READ 0 <-- +O_DR_W DMA_WRITE 0 <-- + +O_DW GETX 0 <-- +O_DW GETS 0 <-- +O_DW Lockdown 0 <-- +O_DW Own_Lock_or_Unlock 0 <-- +O_DW Data_Owner 0 <-- +O_DW Data_All_Tokens 0 <-- +O_DW Ack_Owner 0 <-- +O_DW Ack_Owner_All_Tokens 0 <-- +O_DW Tokens 0 <-- +O_DW Ack_All_Tokens 0 <-- +O_DW DMA_READ 0 <-- +O_DW DMA_WRITE 0 <-- + +NO_DW GETX 0 <-- +NO_DW GETS 0 <-- +NO_DW Lockdown 0 <-- +NO_DW Own_Lock_or_Unlock 0 <-- +NO_DW Data_Owner 0 <-- +NO_DW Data_All_Tokens 0 <-- +NO_DW Tokens 0 <-- +NO_DW Request_Timeout 0 <-- +NO_DW DMA_READ 0 <-- +NO_DW DMA_WRITE 0 <-- + +NO_DR GETX 0 <-- +NO_DR GETS 0 <-- +NO_DR Lockdown 0 <-- +NO_DR Own_Lock_or_Unlock 0 <-- +NO_DR Data_Owner 0 <-- +NO_DR Data_All_Tokens 0 <-- +NO_DR Tokens 0 <-- +NO_DR Request_Timeout 0 <-- +NO_DR DMA_READ 0 <-- +NO_DR DMA_WRITE 0 <-- + +DW_L GETX 0 <-- +DW_L GETS 0 <-- +DW_L Lockdown 0 <-- +DW_L Unlockdown 0 <-- +DW_L Own_Lock_or_Unlock 0 <-- +DW_L Data_Owner 0 <-- +DW_L Data_All_Tokens 0 <-- +DW_L Ack_Owner 0 <-- +DW_L Ack_Owner_All_Tokens 0 <-- +DW_L Tokens 0 <-- +DW_L Request_Timeout 0 <-- +DW_L DMA_READ 0 <-- +DW_L DMA_WRITE 0 <-- + +DR_L GETX 0 <-- +DR_L GETS 0 <-- +DR_L Lockdown 0 <-- +DR_L Unlockdown 0 <-- +DR_L Own_Lock_or_Unlock 0 <-- +DR_L Data_Owner 0 <-- +DR_L Data_All_Tokens 0 <-- +DR_L Ack_Owner 0 <-- +DR_L Ack_Owner_All_Tokens 0 <-- +DR_L Tokens 0 <-- +DR_L Request_Timeout 0 <-- +DR_L DMA_READ 0 <-- +DR_L DMA_WRITE 0 <-- + diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simerr b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simerr new file mode 100755 index 000000000..eabe42249 --- /dev/null +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simerr @@ -0,0 +1,3 @@ +warn: Sockets disabled, not accepting gdb connections +For more information see: http://www.m5sim.org/warn/d946bea6 +hack: be nice to actually delete the event here diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simout b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simout new file mode 100755 index 000000000..9f63d9c39 --- /dev/null +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simout @@ -0,0 +1,17 @@ +M5 Simulator System + +Copyright (c) 2001-2008 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Jan 28 2010 15:54:34 +M5 revision 6068d4fc30d3+ 6931+ default qtip tip brad/rubycfg_regress_udpate +M5 started Jan 28 2010 15:55:45 +M5 executing on svvint04 +command line: build/ALPHA_SE_MOESI_CMP_token/m5.fast -d build/ALPHA_SE_MOESI_CMP_token/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_token -re tests/run.py build/ALPHA_SE_MOESI_CMP_token/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_token +Global frequency set at 1000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. +Hello world! +Exiting @ tick 236654 because target called exit() diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/stats.txt b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/stats.txt new file mode 100644 index 000000000..717c91c49 --- /dev/null +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/stats.txt @@ -0,0 +1,50 @@ + +---------- Begin Simulation Statistics ---------- +host_inst_rate 35577 # Simulator instruction rate (inst/s) +host_mem_usage 215884 # Number of bytes of host memory used +host_seconds 0.18 # Real time elapsed on the host +host_tick_rate 1314701 # Simulator tick rate (ticks/s) +sim_freq 1000000000 # Frequency of simulated ticks +sim_insts 6404 # Number of instructions simulated +sim_seconds 0.000237 # Number of seconds simulated +sim_ticks 236654 # Number of ticks simulated +system.cpu.dtb.data_accesses 2060 # DTB accesses +system.cpu.dtb.data_acv 0 # DTB access violations +system.cpu.dtb.data_hits 2050 # DTB hits +system.cpu.dtb.data_misses 10 # DTB misses +system.cpu.dtb.fetch_accesses 0 # ITB accesses +system.cpu.dtb.fetch_acv 0 # ITB acv +system.cpu.dtb.fetch_hits 0 # ITB hits +system.cpu.dtb.fetch_misses 0 # ITB misses +system.cpu.dtb.read_accesses 1192 # DTB read accesses +system.cpu.dtb.read_acv 0 # DTB read access violations +system.cpu.dtb.read_hits 1185 # DTB read hits +system.cpu.dtb.read_misses 7 # DTB read misses +system.cpu.dtb.write_accesses 868 # DTB write accesses +system.cpu.dtb.write_acv 0 # DTB write access violations +system.cpu.dtb.write_hits 865 # DTB write hits +system.cpu.dtb.write_misses 3 # DTB write misses +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.itb.data_accesses 0 # DTB accesses +system.cpu.itb.data_acv 0 # DTB access violations +system.cpu.itb.data_hits 0 # DTB hits +system.cpu.itb.data_misses 0 # DTB misses +system.cpu.itb.fetch_accesses 6432 # ITB accesses +system.cpu.itb.fetch_acv 0 # ITB acv +system.cpu.itb.fetch_hits 6415 # ITB hits +system.cpu.itb.fetch_misses 17 # ITB misses +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.read_acv 0 # DTB read access violations +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.write_acv 0 # DTB write access violations +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.numCycles 236654 # number of cpu cycles simulated +system.cpu.num_insts 6404 # Number of instructions executed +system.cpu.num_refs 2060 # Number of memory references +system.cpu.workload.PROG:num_syscalls 17 # Number of system calls + +---------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/config.ini b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/config.ini new file mode 100644 index 000000000..2f4078396 --- /dev/null +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/config.ini @@ -0,0 +1,249 @@ +[root] +type=Root +children=system +dummy=0 + +[system] +type=System +children=cpu physmem ruby +mem_mode=timing +physmem=system.physmem + +[system.cpu] +type=TimingSimpleCPU +children=dtb itb tracer workload +checker=Null +clock=1 +cpu_id=0 +defer_registration=false +do_checkpoint_insts=true +do_statistics_insts=true +dtb=system.cpu.dtb +function_trace=false +function_trace_start=0 +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +phase=0 +progress_interval=0 +system=system +tracer=system.cpu.tracer +workload=system.cpu.workload +dcache_port=system.ruby.network.topology.ext_links0.ext_node.sequencer.port[1] +icache_port=system.ruby.network.topology.ext_links0.ext_node.sequencer.port[0] + +[system.cpu.dtb] +type=AlphaTLB +size=64 + +[system.cpu.itb] +type=AlphaTLB +size=48 + +[system.cpu.tracer] +type=ExeTracer + +[system.cpu.workload] +type=LiveProcess +cmd=hello +cwd= +egid=100 +env= +errout=cerr +euid=100 +executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/alpha/linux/hello +gid=100 +input=cin +max_stack_size=67108864 +output=cout +pid=100 +ppid=99 +simpoint=0 +system=system +uid=100 + +[system.physmem] +type=PhysicalMemory +file= +latency=30 +latency_var=0 +null=false +range=0:134217727 +zero=false +port=system.ruby.network.topology.ext_links0.ext_node.sequencer.physMemPort + +[system.ruby] +type=RubySystem +children=debug network profiler tracer +block_size_bytes=64 +clock=1 +debug=system.ruby.debug +mem_size=134217728 +network=system.ruby.network +profiler=system.ruby.profiler +random_seed=1234 +randomization=false +stats_filename=ruby.stats +tracer=system.ruby.tracer + +[system.ruby.debug] +type=RubyDebug +filter_string=none +output_filename=none +protocol_trace=false +start_time=1 +verbosity_string=none + +[system.ruby.network] +type=SimpleNetwork +children=topology +adaptive_routing=true +buffer_size=0 +control_msg_size=8 +endpoint_bandwidth=10000 +link_latency=1 +number_of_virtual_networks=10 +topology=system.ruby.network.topology + +[system.ruby.network.topology] +type=Topology +children=ext_links0 ext_links1 int_links0 int_links1 +ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1 +int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1 +num_int_nodes=3 +print_config=false + +[system.ruby.network.topology.ext_links0] +type=ExtLink +children=ext_node +bw_multiplier=64 +ext_node=system.ruby.network.topology.ext_links0.ext_node +int_node=0 +latency=1 +weight=1 + +[system.ruby.network.topology.ext_links0.ext_node] +type=L1Cache_Controller +children=L2cacheMemory sequencer +L1DcacheMemory=system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache +L1IcacheMemory=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache +L2cacheMemory=system.ruby.network.topology.ext_links0.ext_node.L2cacheMemory +buffer_size=0 +cache_response_latency=12 +issue_latency=2 +number_of_TBEs=256 +recycle_latency=10 +sequencer=system.ruby.network.topology.ext_links0.ext_node.sequencer +transitions_per_cycle=32 +version=0 + +[system.ruby.network.topology.ext_links0.ext_node.L2cacheMemory] +type=RubyCache +assoc=2 +latency=15 +replacement_policy=PSEUDO_LRU +size=512 + +[system.ruby.network.topology.ext_links0.ext_node.sequencer] +type=RubySequencer +children=dcache icache +dcache=system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache +deadlock_threshold=500000 +icache=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache +max_outstanding_requests=16 +physmem=system.physmem +using_ruby_tester=false +version=0 +physMemPort=system.physmem.port[0] +port=system.cpu.icache_port system.cpu.dcache_port + +[system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache] +type=RubyCache +assoc=2 +latency=3 +replacement_policy=PSEUDO_LRU +size=256 + +[system.ruby.network.topology.ext_links0.ext_node.sequencer.icache] +type=RubyCache +assoc=2 +latency=3 +replacement_policy=PSEUDO_LRU +size=256 + +[system.ruby.network.topology.ext_links1] +type=ExtLink +children=ext_node +bw_multiplier=64 +ext_node=system.ruby.network.topology.ext_links1.ext_node +int_node=1 +latency=1 +weight=1 + +[system.ruby.network.topology.ext_links1.ext_node] +type=Directory_Controller +children=directory memBuffer +buffer_size=0 +directory=system.ruby.network.topology.ext_links1.ext_node.directory +memBuffer=system.ruby.network.topology.ext_links1.ext_node.memBuffer +memory_controller_latency=12 +number_of_TBEs=256 +recycle_latency=10 +transitions_per_cycle=32 +version=0 + +[system.ruby.network.topology.ext_links1.ext_node.directory] +type=RubyDirectoryMemory +size=134217728 +version=0 + +[system.ruby.network.topology.ext_links1.ext_node.memBuffer] +type=RubyMemoryControl +bank_bit_0=8 +bank_busy_time=11 +bank_queue_size=12 +banks_per_rank=8 +basic_bus_busy_time=2 +dimm_bit_0=12 +dimms_per_channel=2 +mem_bus_cycle_multiplier=10 +mem_ctl_latency=12 +mem_fixed_delay=0 +mem_random_arbitrate=0 +rank_bit_0=11 +rank_rank_delay=1 +ranks_per_dimm=2 +read_write_delay=2 +refresh_period=1560 +tFaw=0 +version=0 + +[system.ruby.network.topology.int_links0] +type=IntLink +bw_multiplier=16 +latency=1 +node_a=0 +node_b=2 +weight=1 + +[system.ruby.network.topology.int_links1] +type=IntLink +bw_multiplier=16 +latency=1 +node_a=1 +node_b=2 +weight=1 + +[system.ruby.profiler] +type=RubyProfiler +all_instructions=false +hot_lines=false +num_of_sequencers=1 + +[system.ruby.tracer] +type=RubyTracer +warmup_length=100000 + diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/ruby.stats b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/ruby.stats new file mode 100644 index 000000000..b64bafefe --- /dev/null +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/ruby.stats @@ -0,0 +1,576 @@ + +================ Begin RubySystem Configuration Print ================ + +RubySystem config: + random_seed: 1234 + randomization: 0 + cycle_period: 1 + block_size_bytes: 64 + block_size_bits: 6 + memory_size_bytes: 134217728 + memory_size_bits: 27 + +Network Configuration +--------------------- +network: SIMPLE_NETWORK +topology: + +virtual_net_0: active, unordered +virtual_net_1: active, unordered +virtual_net_2: active, unordered +virtual_net_3: active, unordered +virtual_net_4: active, ordered +virtual_net_5: active, ordered +virtual_net_6: inactive +virtual_net_7: inactive +virtual_net_8: inactive +virtual_net_9: inactive + + +Profiler Configuration +---------------------- +periodic_stats_period: 1000000 + +================ End RubySystem Configuration Print ================ + + +Real time: Jan/28/2010 11:55:11 + +Profiler Stats +-------------- +Elapsed_time_in_seconds: 0 +Elapsed_time_in_minutes: 0 +Elapsed_time_in_hours: 0 +Elapsed_time_in_days: 0 + +Virtual_time_in_seconds: 0.39 +Virtual_time_in_minutes: 0.0065 +Virtual_time_in_hours: 0.000108333 +Virtual_time_in_days: 4.51389e-06 + +Ruby_current_time: 215528 +Ruby_start_time: 0 +Ruby_cycles: 215528 + +mbytes_resident: 33.1406 +mbytes_total: 33.1484 +resident_ratio: 1 + +Total_misses: 0 +total_misses: 0 [ 0 ] +user_misses: 0 [ 0 ] +supervisor_misses: 0 [ 0 ] + +ruby_cycles_executed: 215529 [ 215529 ] + +transactions_started: 0 [ 0 ] +transactions_ended: 0 [ 0 ] +cycles_per_transaction: 0 [ 0 ] +misses_per_transaction: 0 [ 0 ] + + +Busy Controller Counts: +L1Cache-0:0 +Directory-0:0 + + +Busy Bank Count:0 + +sequencer_requests_outstanding: [binsize: 1 max: 1 count: 8465 average: 1 | standard deviation: 0 | 0 8465 ] + +All Non-Zero Cycle Demand Cache Accesses +---------------------------------------- +miss_latency: [binsize: 2 max: 377 count: 8464 average: 24.4641 | standard deviation: 54.9689 | 0 7305 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 199 174 167 309 200 14 3 4 1 4 0 15 1 5 2 1 0 0 0 1 3 4 4 7 1 1 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 1 0 2 0 0 0 0 1 0 1 0 2 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 15 4 1 1 0 2 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 ] +miss_latency_1: [binsize: 2 max: 261 count: 6414 average: 16.7424 | standard deviation: 43.645 | 0 5833 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 111 113 72 159 92 10 2 2 1 2 0 0 0 1 0 0 0 0 0 1 3 1 4 3 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_2: [binsize: 2 max: 333 count: 1185 average: 57.908 | standard deviation: 75.2483 | 0 765 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 80 52 60 116 72 4 1 0 0 1 0 12 1 2 2 1 0 0 0 0 0 2 0 3 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 1 0 2 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_3: [binsize: 2 max: 377 count: 865 average: 35.904 | standard deviation: 74.7708 | 0 707 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8 9 35 34 36 0 0 2 0 1 0 3 0 2 0 0 0 0 0 0 0 1 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 14 3 1 0 0 2 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 ] + +All Non-Zero Cycle SW Prefetch Requests +------------------------------------ +prefetch_latency: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +prefetch_latency_L2Miss:[binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +Request vs. RubySystem State Profile +-------------------------------- + + +filter_action: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + +Message Delayed Cycles +---------------------- +Total_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +Total_nonPF_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + virtual_network_0_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + virtual_network_1_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + virtual_network_2_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + virtual_network_3_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + virtual_network_4_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + virtual_network_5_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + virtual_network_6_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + virtual_network_7_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + virtual_network_8_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + virtual_network_9_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + +Resource Usage +-------------- +page_size: 4096 +user_time: 0 +system_time: 0 +page_reclaims: 7120 +page_faults: 2128 +swaps: 0 +block_inputs: 0 +block_outputs: 0 + +Network Stats +------------- + +switch_0_inlinks: 2 +switch_0_outlinks: 2 +links_utilized_percent_switch_0: 0.107382 + links_utilized_percent_switch_0_link_0: 0.0671258 bw: 640000 base_latency: 1 + links_utilized_percent_switch_0_link_1: 0.147637 bw: 160000 base_latency: 1 + + outgoing_messages_switch_0_link_0_Response_Data: 1159 83448 [ 0 1159 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_0_Writeback_Control: 1143 9144 [ 0 0 1143 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Request_Control: 1159 9272 [ 0 0 0 1159 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Writeback_Data: 220 15840 [ 220 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Writeback_Control: 2066 16528 [ 923 0 0 1143 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Unblock_Control: 1159 9272 [ 1159 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + +switch_1_inlinks: 2 +switch_1_outlinks: 2 +links_utilized_percent_switch_1: 0.152706 + links_utilized_percent_switch_1_link_0: 0.0369094 bw: 640000 base_latency: 1 + links_utilized_percent_switch_1_link_1: 0.268503 bw: 160000 base_latency: 1 + + outgoing_messages_switch_1_link_0_Request_Control: 1159 9272 [ 0 0 0 1159 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_Writeback_Data: 220 15840 [ 220 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_Writeback_Control: 2066 16528 [ 923 0 0 1143 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_Unblock_Control: 1159 9272 [ 1159 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Response_Data: 1159 83448 [ 0 1159 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Writeback_Control: 1143 9144 [ 0 0 1143 0 0 0 0 0 0 0 ] base_latency: 1 + +switch_2_inlinks: 2 +switch_2_outlinks: 2 +links_utilized_percent_switch_2: 0.20807 + links_utilized_percent_switch_2_link_0: 0.268503 bw: 160000 base_latency: 1 + links_utilized_percent_switch_2_link_1: 0.147637 bw: 160000 base_latency: 1 + + outgoing_messages_switch_2_link_0_Response_Data: 1159 83448 [ 0 1159 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_0_Writeback_Control: 1143 9144 [ 0 0 1143 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Request_Control: 1159 9272 [ 0 0 0 1159 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Writeback_Data: 220 15840 [ 220 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Writeback_Control: 2066 16528 [ 923 0 0 1143 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Unblock_Control: 1159 9272 [ 1159 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + +Cache Stats: system.ruby.network.topology.ext_links0.ext_node.sequencer.icache + system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_misses: 581 + system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_demand_misses: 581 + system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_prefetches: 0 + system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_sw_prefetches: 0 + system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_hw_prefetches: 0 + system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_misses_per_transaction: inf + + system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_type_IFETCH: 100% + + system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_access_mode_type_SupervisorMode: 581 100% + system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_size: [binsize: 1 max: 4 count: 581 average: 4 | standard deviation: 0 | 0 0 0 0 581 ] + +Cache Stats: system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache + system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_misses: 578 + system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_demand_misses: 578 + system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_prefetches: 0 + system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_sw_prefetches: 0 + system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_hw_prefetches: 0 + system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_misses_per_transaction: inf + + system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_request_type_LD: 72.6644% + system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_request_type_ST: 27.3356% + + system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_access_mode_type_SupervisorMode: 578 100% + system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_request_size: [binsize: 1 max: 8 count: 578 average: 7.5917 | standard deviation: 1.2123 | 0 0 0 0 59 0 0 0 519 ] + +Cache Stats: system.ruby.network.topology.ext_links0.ext_node.L2cacheMemory + system.ruby.network.topology.ext_links0.ext_node.L2cacheMemory_total_misses: 0 + system.ruby.network.topology.ext_links0.ext_node.L2cacheMemory_total_demand_misses: 0 + system.ruby.network.topology.ext_links0.ext_node.L2cacheMemory_total_prefetches: 0 + system.ruby.network.topology.ext_links0.ext_node.L2cacheMemory_total_sw_prefetches: 0 + system.ruby.network.topology.ext_links0.ext_node.L2cacheMemory_total_hw_prefetches: 0 + system.ruby.network.topology.ext_links0.ext_node.L2cacheMemory_misses_per_transaction: nan + + system.ruby.network.topology.ext_links0.ext_node.L2cacheMemory_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + + --- L1Cache 0 --- + - Event Counts - +Load 1209 +Ifetch 6447 +Store 946 +L2_Replacement 1143 +L1_to_L2 1354 +L2_to_L1D 138 +L2_to_L1I 65 +Other_GETX 0 +Other_GETS 0 +Ack 0 +Shared_Ack 0 +Data 0 +Shared_Data 0 +Exclusive_Data 1159 +Writeback_Ack 1143 +Writeback_Nack 0 +All_acks 0 +All_acks_no_sharers 1159 + + - Transitions - +I Load 420 +I Ifetch 581 +I Store 158 +I L2_Replacement 0 <-- +I L1_to_L2 0 <-- +I L2_to_L1D 0 <-- +I L2_to_L1I 0 <-- +I Other_GETX 0 <-- +I Other_GETS 0 <-- + +S Load 0 <-- +S Ifetch 0 <-- +S Store 0 <-- +S L2_Replacement 0 <-- +S L1_to_L2 0 <-- +S L2_to_L1D 0 <-- +S L2_to_L1I 0 <-- +S Other_GETX 0 <-- +S Other_GETS 0 <-- + +O Load 0 <-- +O Ifetch 0 <-- +O Store 0 <-- +O L2_Replacement 0 <-- +O L1_to_L2 0 <-- +O L2_to_L1D 0 <-- +O L2_to_L1I 0 <-- +O Other_GETX 0 <-- +O Other_GETS 0 <-- + +M Load 368 +M Ifetch 5833 +M Store 66 +M L2_Replacement 923 +M L1_to_L2 1061 +M L2_to_L1D 68 +M L2_to_L1I 65 +M Other_GETX 0 <-- +M Other_GETS 0 <-- + +MM Load 397 +MM Ifetch 0 <-- +MM Store 641 +MM L2_Replacement 220 +MM L1_to_L2 293 +MM L2_to_L1D 70 +MM L2_to_L1I 0 <-- +MM Other_GETX 0 <-- +MM Other_GETS 0 <-- + +IM Load 0 <-- +IM Ifetch 0 <-- +IM Store 0 <-- +IM L2_Replacement 0 <-- +IM L1_to_L2 0 <-- +IM Other_GETX 0 <-- +IM Other_GETS 0 <-- +IM Ack 0 <-- +IM Data 0 <-- +IM Exclusive_Data 158 + +SM Load 0 <-- +SM Ifetch 0 <-- +SM Store 0 <-- +SM L2_Replacement 0 <-- +SM L1_to_L2 0 <-- +SM Other_GETX 0 <-- +SM Other_GETS 0 <-- +SM Ack 0 <-- +SM Data 0 <-- + +OM Load 0 <-- +OM Ifetch 0 <-- +OM Store 0 <-- +OM L2_Replacement 0 <-- +OM L1_to_L2 0 <-- +OM Other_GETX 0 <-- +OM Other_GETS 0 <-- +OM Ack 0 <-- +OM All_acks 0 <-- +OM All_acks_no_sharers 0 <-- + +ISM Load 0 <-- +ISM Ifetch 0 <-- +ISM Store 0 <-- +ISM L2_Replacement 0 <-- +ISM L1_to_L2 0 <-- +ISM Ack 0 <-- +ISM All_acks_no_sharers 0 <-- + +M_W Load 0 <-- +M_W Ifetch 0 <-- +M_W Store 0 <-- +M_W L2_Replacement 0 <-- +M_W L1_to_L2 0 <-- +M_W Ack 0 <-- +M_W All_acks_no_sharers 1001 + +MM_W Load 0 <-- +MM_W Ifetch 0 <-- +MM_W Store 0 <-- +MM_W L2_Replacement 0 <-- +MM_W L1_to_L2 0 <-- +MM_W Ack 0 <-- +MM_W All_acks_no_sharers 158 + +IS Load 0 <-- +IS Ifetch 0 <-- +IS Store 0 <-- +IS L2_Replacement 0 <-- +IS L1_to_L2 0 <-- +IS Other_GETX 0 <-- +IS Other_GETS 0 <-- +IS Ack 0 <-- +IS Shared_Ack 0 <-- +IS Data 0 <-- +IS Shared_Data 0 <-- +IS Exclusive_Data 1001 + +SS Load 0 <-- +SS Ifetch 0 <-- +SS Store 0 <-- +SS L2_Replacement 0 <-- +SS L1_to_L2 0 <-- +SS Ack 0 <-- +SS Shared_Ack 0 <-- +SS All_acks 0 <-- +SS All_acks_no_sharers 0 <-- + +OI Load 0 <-- +OI Ifetch 0 <-- +OI Store 0 <-- +OI L2_Replacement 0 <-- +OI L1_to_L2 0 <-- +OI Other_GETX 0 <-- +OI Other_GETS 0 <-- +OI Writeback_Ack 0 <-- + +MI Load 24 +MI Ifetch 33 +MI Store 81 +MI L2_Replacement 0 <-- +MI L1_to_L2 0 <-- +MI Other_GETX 0 <-- +MI Other_GETS 0 <-- +MI Writeback_Ack 1143 + +II Load 0 <-- +II Ifetch 0 <-- +II Store 0 <-- +II L2_Replacement 0 <-- +II L1_to_L2 0 <-- +II Other_GETX 0 <-- +II Other_GETS 0 <-- +II Writeback_Ack 0 <-- +II Writeback_Nack 0 <-- + +Memory controller: system.ruby.network.topology.ext_links1.ext_node.memBuffer: + memory_total_requests: 1379 + memory_reads: 1159 + memory_writes: 220 + memory_refreshes: 449 + memory_total_request_delays: 342 + memory_delays_per_request: 0.248006 + memory_delays_in_input_queue: 1 + memory_delays_behind_head_of_bank_queue: 0 + memory_delays_stalled_at_head_of_bank_queue: 341 + memory_stalls_for_bank_busy: 167 + memory_stalls_for_random_busy: 0 + memory_stalls_for_anti_starvation: 0 + memory_stalls_for_arbitration: 19 + memory_stalls_for_bus: 57 + memory_stalls_for_tfaw: 0 + memory_stalls_for_read_write_turnaround: 98 + memory_stalls_for_read_read_turnaround: 0 + accesses_per_bank: 75 17 45 40 54 101 33 16 20 22 32 34 53 50 39 31 39 22 21 27 28 38 81 22 31 23 32 72 89 126 14 52 + + --- Directory 0 --- + - Event Counts - +GETX 519 +GETS 1114 +PUT 1143 +Unblock 1159 +Writeback_Clean 0 +Writeback_Dirty 0 +Writeback_Exclusive_Clean 923 +Writeback_Exclusive_Dirty 220 +DMA_READ 0 +DMA_WRITE 0 +Memory_Data 1159 +Memory_Ack 220 +Ack 0 +Shared_Ack 0 +Shared_Data 0 +Exclusive_Data 0 +All_acks_and_data 0 +All_acks_and_data_no_sharers 0 + + - Transitions - +NO GETX 0 <-- +NO GETS 0 <-- +NO PUT 1143 +NO DMA_READ 0 <-- +NO DMA_WRITE 0 <-- + +O GETX 0 <-- +O GETS 0 <-- +O PUT 0 <-- +O DMA_READ 0 <-- +O DMA_WRITE 0 <-- + +E GETX 158 +E GETS 1001 +E PUT 0 <-- +E DMA_READ 0 <-- +E DMA_WRITE 0 <-- + +NO_B GETX 0 <-- +NO_B GETS 0 <-- +NO_B PUT 0 <-- +NO_B Unblock 1159 +NO_B DMA_READ 0 <-- +NO_B DMA_WRITE 0 <-- + +O_B GETX 0 <-- +O_B GETS 0 <-- +O_B PUT 0 <-- +O_B Unblock 0 <-- +O_B DMA_READ 0 <-- +O_B DMA_WRITE 0 <-- + +NO_B_W GETX 0 <-- +NO_B_W GETS 0 <-- +NO_B_W PUT 0 <-- +NO_B_W Unblock 0 <-- +NO_B_W DMA_READ 0 <-- +NO_B_W DMA_WRITE 0 <-- +NO_B_W Memory_Data 1159 + +O_B_W GETX 0 <-- +O_B_W GETS 0 <-- +O_B_W PUT 0 <-- +O_B_W Unblock 0 <-- +O_B_W DMA_READ 0 <-- +O_B_W DMA_WRITE 0 <-- +O_B_W Memory_Data 0 <-- + +NO_W GETX 0 <-- +NO_W GETS 0 <-- +NO_W PUT 0 <-- +NO_W DMA_READ 0 <-- +NO_W DMA_WRITE 0 <-- +NO_W Memory_Data 0 <-- + +O_W GETX 0 <-- +O_W GETS 0 <-- +O_W PUT 0 <-- +O_W DMA_READ 0 <-- +O_W DMA_WRITE 0 <-- +O_W Memory_Data 0 <-- + +NO_DW_B_W GETX 0 <-- +NO_DW_B_W GETS 0 <-- +NO_DW_B_W PUT 0 <-- +NO_DW_B_W DMA_READ 0 <-- +NO_DW_B_W DMA_WRITE 0 <-- +NO_DW_B_W Ack 0 <-- +NO_DW_B_W Exclusive_Data 0 <-- +NO_DW_B_W All_acks_and_data_no_sharers 0 <-- + +NO_DR_B_W GETX 0 <-- +NO_DR_B_W GETS 0 <-- +NO_DR_B_W PUT 0 <-- +NO_DR_B_W DMA_READ 0 <-- +NO_DR_B_W DMA_WRITE 0 <-- +NO_DR_B_W Memory_Data 0 <-- +NO_DR_B_W Ack 0 <-- +NO_DR_B_W Shared_Ack 0 <-- +NO_DR_B_W Shared_Data 0 <-- +NO_DR_B_W Exclusive_Data 0 <-- + +NO_DR_B_D GETX 0 <-- +NO_DR_B_D GETS 0 <-- +NO_DR_B_D PUT 0 <-- +NO_DR_B_D DMA_READ 0 <-- +NO_DR_B_D DMA_WRITE 0 <-- +NO_DR_B_D Ack 0 <-- +NO_DR_B_D Shared_Ack 0 <-- +NO_DR_B_D Shared_Data 0 <-- +NO_DR_B_D Exclusive_Data 0 <-- +NO_DR_B_D All_acks_and_data 0 <-- +NO_DR_B_D All_acks_and_data_no_sharers 0 <-- + +NO_DR_B GETX 0 <-- +NO_DR_B GETS 0 <-- +NO_DR_B PUT 0 <-- +NO_DR_B DMA_READ 0 <-- +NO_DR_B DMA_WRITE 0 <-- +NO_DR_B Ack 0 <-- +NO_DR_B Shared_Ack 0 <-- +NO_DR_B Shared_Data 0 <-- +NO_DR_B Exclusive_Data 0 <-- +NO_DR_B All_acks_and_data 0 <-- +NO_DR_B All_acks_and_data_no_sharers 0 <-- + +NO_DW_W GETX 0 <-- +NO_DW_W GETS 0 <-- +NO_DW_W PUT 0 <-- +NO_DW_W DMA_READ 0 <-- +NO_DW_W DMA_WRITE 0 <-- +NO_DW_W Memory_Ack 0 <-- + +O_DR_B_W GETX 0 <-- +O_DR_B_W GETS 0 <-- +O_DR_B_W PUT 0 <-- +O_DR_B_W DMA_READ 0 <-- +O_DR_B_W DMA_WRITE 0 <-- +O_DR_B_W Memory_Data 0 <-- + +O_DR_B GETX 0 <-- +O_DR_B GETS 0 <-- +O_DR_B PUT 0 <-- +O_DR_B DMA_READ 0 <-- +O_DR_B DMA_WRITE 0 <-- +O_DR_B Ack 0 <-- +O_DR_B All_acks_and_data_no_sharers 0 <-- + +WB GETX 27 +WB GETS 20 +WB PUT 0 <-- +WB Unblock 0 <-- +WB Writeback_Clean 0 <-- +WB Writeback_Dirty 0 <-- +WB Writeback_Exclusive_Clean 923 +WB Writeback_Exclusive_Dirty 220 +WB DMA_READ 0 <-- +WB DMA_WRITE 0 <-- + +WB_O_W GETX 0 <-- +WB_O_W GETS 0 <-- +WB_O_W PUT 0 <-- +WB_O_W DMA_READ 0 <-- +WB_O_W DMA_WRITE 0 <-- +WB_O_W Memory_Ack 0 <-- + +WB_E_W GETX 334 +WB_E_W GETS 93 +WB_E_W PUT 0 <-- +WB_E_W DMA_READ 0 <-- +WB_E_W DMA_WRITE 0 <-- +WB_E_W Memory_Ack 220 + diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simerr b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simerr new file mode 100755 index 000000000..eabe42249 --- /dev/null +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simerr @@ -0,0 +1,3 @@ +warn: Sockets disabled, not accepting gdb connections +For more information see: http://www.m5sim.org/warn/d946bea6 +hack: be nice to actually delete the event here diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simout b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simout new file mode 100755 index 000000000..8dfe8bf7b --- /dev/null +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simout @@ -0,0 +1,17 @@ +M5 Simulator System + +Copyright (c) 2001-2008 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Jan 28 2010 11:30:01 +M5 revision 6068d4fc30d3+ 6931+ default qtip tip brad/rubycfg_regress_udpate +M5 started Jan 28 2010 11:55:11 +M5 executing on svvint06 +command line: build/ALPHA_SE_MOESI_hammer/m5.fast -d build/ALPHA_SE_MOESI_hammer/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby-MOESI_hammer -re tests/run.py build/ALPHA_SE_MOESI_hammer/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby-MOESI_hammer +Global frequency set at 1000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. +Hello world! +Exiting @ tick 215528 because target called exit() diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt new file mode 100644 index 000000000..67cd72f19 --- /dev/null +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt @@ -0,0 +1,50 @@ + +---------- Begin Simulation Statistics ---------- +host_inst_rate 45742 # Simulator instruction rate (inst/s) +host_mem_usage 213100 # Number of bytes of host memory used +host_seconds 0.14 # Real time elapsed on the host +host_tick_rate 1539442 # Simulator tick rate (ticks/s) +sim_freq 1000000000 # Frequency of simulated ticks +sim_insts 6404 # Number of instructions simulated +sim_seconds 0.000216 # Number of seconds simulated +sim_ticks 215528 # Number of ticks simulated +system.cpu.dtb.data_accesses 2060 # DTB accesses +system.cpu.dtb.data_acv 0 # DTB access violations +system.cpu.dtb.data_hits 2050 # DTB hits +system.cpu.dtb.data_misses 10 # DTB misses +system.cpu.dtb.fetch_accesses 0 # ITB accesses +system.cpu.dtb.fetch_acv 0 # ITB acv +system.cpu.dtb.fetch_hits 0 # ITB hits +system.cpu.dtb.fetch_misses 0 # ITB misses +system.cpu.dtb.read_accesses 1192 # DTB read accesses +system.cpu.dtb.read_acv 0 # DTB read access violations +system.cpu.dtb.read_hits 1185 # DTB read hits +system.cpu.dtb.read_misses 7 # DTB read misses +system.cpu.dtb.write_accesses 868 # DTB write accesses +system.cpu.dtb.write_acv 0 # DTB write access violations +system.cpu.dtb.write_hits 865 # DTB write hits +system.cpu.dtb.write_misses 3 # DTB write misses +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.itb.data_accesses 0 # DTB accesses +system.cpu.itb.data_acv 0 # DTB access violations +system.cpu.itb.data_hits 0 # DTB hits +system.cpu.itb.data_misses 0 # DTB misses +system.cpu.itb.fetch_accesses 6432 # ITB accesses +system.cpu.itb.fetch_acv 0 # ITB acv +system.cpu.itb.fetch_hits 6415 # ITB hits +system.cpu.itb.fetch_misses 17 # ITB misses +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.read_acv 0 # DTB read access violations +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.write_acv 0 # DTB write access violations +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.numCycles 215528 # number of cpu cycles simulated +system.cpu.num_insts 6404 # Number of instructions executed +system.cpu.num_refs 2060 # Number of memory references +system.cpu.workload.PROG:num_syscalls 17 # Number of system calls + +---------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/config.ini b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/config.ini index 8fd31875c..3438ec60f 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/config.ini +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/config.ini @@ -5,15 +5,15 @@ dummy=0 [system] type=System -children=cpu membus physmem -mem_mode=atomic +children=cpu physmem ruby +mem_mode=timing physmem=system.physmem [system.cpu] type=TimingSimpleCPU children=dtb itb tracer workload checker=Null -clock=500 +clock=1 cpu_id=0 defer_registration=false do_checkpoint_insts=true @@ -32,8 +32,8 @@ progress_interval=0 system=system tracer=system.cpu.tracer workload=system.cpu.workload -dcache_port=system.membus.port[2] -icache_port=system.membus.port[1] +dcache_port=system.ruby.network.topology.ext_links0.ext_node.sequencer.port[1] +icache_port=system.ruby.network.topology.ext_links0.ext_node.sequencer.port[0] [system.cpu.dtb] type=AlphaTLB @@ -54,7 +54,7 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello +executable=tests/test-progs/hello/bin/alpha/linux/hello gid=100 input=cin max_stack_size=67108864 @@ -65,30 +65,169 @@ simpoint=0 system=system uid=100 -[system.membus] -type=Bus -block_size=64 -bus_id=0 -clock=1000 -header_cycles=1 -responder_set=false -width=64 -port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port - [system.physmem] -type=RubyMemory -clock=1 -config_file=build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby/ruby.config -debug=false -debug_file=ruby.debug +type=PhysicalMemory file= -latency=30000 +latency=30 latency_var=0 null=false -num_cpus=1 -phase=0 range=0:134217727 -stats_file=ruby.stats zero=false -port=system.membus.port[0] +port=system.ruby.network.topology.ext_links0.ext_node.sequencer.physMemPort + +[system.ruby] +type=RubySystem +children=debug network profiler tracer +block_size_bytes=64 +clock=1 +debug=system.ruby.debug +mem_size=134217728 +network=system.ruby.network +profiler=system.ruby.profiler +random_seed=1234 +randomization=false +stats_filename=ruby.stats +tracer=system.ruby.tracer + +[system.ruby.debug] +type=RubyDebug +filter_string=none +output_filename=none +protocol_trace=false +start_time=1 +verbosity_string=none + +[system.ruby.network] +type=SimpleNetwork +children=topology +adaptive_routing=true +buffer_size=0 +control_msg_size=8 +endpoint_bandwidth=10000 +link_latency=1 +number_of_virtual_networks=10 +topology=system.ruby.network.topology + +[system.ruby.network.topology] +type=Topology +children=ext_links0 ext_links1 int_links0 int_links1 +ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1 +int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1 +num_int_nodes=3 +print_config=false + +[system.ruby.network.topology.ext_links0] +type=ExtLink +children=ext_node +bw_multiplier=64 +ext_node=system.ruby.network.topology.ext_links0.ext_node +int_node=0 +latency=1 +weight=1 + +[system.ruby.network.topology.ext_links0.ext_node] +type=L1Cache_Controller +children=sequencer +buffer_size=0 +cacheMemory=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache +cache_response_latency=12 +issue_latency=2 +number_of_TBEs=256 +recycle_latency=10 +sequencer=system.ruby.network.topology.ext_links0.ext_node.sequencer +transitions_per_cycle=32 +version=0 + +[system.ruby.network.topology.ext_links0.ext_node.sequencer] +type=RubySequencer +children=icache +dcache=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache +deadlock_threshold=500000 +icache=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache +max_outstanding_requests=16 +physmem=system.physmem +using_ruby_tester=false +version=0 +physMemPort=system.physmem.port[0] +port=system.cpu.icache_port system.cpu.dcache_port + +[system.ruby.network.topology.ext_links0.ext_node.sequencer.icache] +type=RubyCache +assoc=2 +latency=3 +replacement_policy=PSEUDO_LRU +size=256 + +[system.ruby.network.topology.ext_links1] +type=ExtLink +children=ext_node +bw_multiplier=64 +ext_node=system.ruby.network.topology.ext_links1.ext_node +int_node=1 +latency=1 +weight=1 + +[system.ruby.network.topology.ext_links1.ext_node] +type=Directory_Controller +children=directory memBuffer +buffer_size=0 +directory=system.ruby.network.topology.ext_links1.ext_node.directory +directory_latency=12 +memBuffer=system.ruby.network.topology.ext_links1.ext_node.memBuffer +number_of_TBEs=256 +recycle_latency=10 +transitions_per_cycle=32 +version=0 + +[system.ruby.network.topology.ext_links1.ext_node.directory] +type=RubyDirectoryMemory +size=134217728 +version=0 + +[system.ruby.network.topology.ext_links1.ext_node.memBuffer] +type=RubyMemoryControl +bank_bit_0=8 +bank_busy_time=11 +bank_queue_size=12 +banks_per_rank=8 +basic_bus_busy_time=2 +dimm_bit_0=12 +dimms_per_channel=2 +mem_bus_cycle_multiplier=10 +mem_ctl_latency=12 +mem_fixed_delay=0 +mem_random_arbitrate=0 +rank_bit_0=11 +rank_rank_delay=1 +ranks_per_dimm=2 +read_write_delay=2 +refresh_period=1560 +tFaw=0 +version=0 + +[system.ruby.network.topology.int_links0] +type=IntLink +bw_multiplier=16 +latency=1 +node_a=0 +node_b=2 +weight=1 + +[system.ruby.network.topology.int_links1] +type=IntLink +bw_multiplier=16 +latency=1 +node_a=1 +node_b=2 +weight=1 + +[system.ruby.profiler] +type=RubyProfiler +all_instructions=false +hot_lines=false +num_of_sequencers=1 + +[system.ruby.tracer] +type=RubyTracer +warmup_length=100000 diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/ruby.stats b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/ruby.stats index 612fc3cdf..d9b6ae533 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/ruby.stats +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/ruby.stats @@ -2,73 +2,18 @@ ================ Begin RubySystem Configuration Print ================ RubySystem config: - random_seed: 380268 + random_seed: 1234 randomization: 0 - tech_nm: 45 - freq_mhz: 3000 + cycle_period: 1 block_size_bytes: 64 block_size_bits: 6 - memory_size_bytes: 1073741824 - memory_size_bits: 30 -DMA_Controller config: DMAController_0 - version: 0 - buffer_size: 32 - dma_sequencer: DMASequencer_0 - number_of_TBEs: 128 - transitions_per_cycle: 32 -Directory_Controller config: DirectoryController_0 - version: 0 - buffer_size: 32 - directory_latency: 6 - directory_name: DirectoryMemory_0 - memory_controller_name: MemoryControl_0 - memory_latency: 158 - number_of_TBEs: 128 - recycle_latency: 10 - to_mem_ctrl_latency: 1 - transitions_per_cycle: 32 -L1Cache_Controller config: L1CacheController_0 - version: 0 - buffer_size: 32 - cache: l1u_0 - cache_response_latency: 12 - issue_latency: 2 - number_of_TBEs: 128 - sequencer: Sequencer_0 - transitions_per_cycle: 32 -Cache config: l1u_0 - controller: L1CacheController_0 - cache_associativity: 8 - num_cache_sets_bits: 2 - num_cache_sets: 4 - cache_set_size_bytes: 256 - cache_set_size_Kbytes: 0.25 - cache_set_size_Mbytes: 0.000244141 - cache_size_bytes: 2048 - cache_size_Kbytes: 2 - cache_size_Mbytes: 0.00195312 -DirectoryMemory Global Config: - number of directory memories: 1 - total memory size bytes: 1073741824 - total memory size bits: 30 -DirectoryMemory module config: DirectoryMemory_0 - controller: DirectoryController_0 - version: 0 - memory_bits: 30 - memory_size_bytes: 1073741824 - memory_size_Kbytes: 1.04858e+06 - memory_size_Mbytes: 1024 - memory_size_Gbytes: 1 -Seqeuncer config: Sequencer_0 - controller: L1CacheController_0 - version: 0 - max_outstanding_requests: 16 - deadlock_threshold: 500000 + memory_size_bytes: 134217728 + memory_size_bits: 27 Network Configuration --------------------- network: SIMPLE_NETWORK -topology: theTopology +topology: virtual_net_0: active, ordered virtual_net_1: active, ordered @@ -76,25 +21,11 @@ virtual_net_2: active, ordered virtual_net_3: inactive virtual_net_4: active, ordered virtual_net_5: active, ordered +virtual_net_6: inactive +virtual_net_7: inactive +virtual_net_8: inactive +virtual_net_9: inactive ---- Begin Topology Print --- - -Topology print ONLY indicates the _NETWORK_ latency between two machines -It does NOT include the latency within the machines - -L1Cache-0 Network Latencies - L1Cache-0 -> Directory-0 net_lat: 7 - L1Cache-0 -> DMA-0 net_lat: 7 - -Directory-0 Network Latencies - Directory-0 -> L1Cache-0 net_lat: 7 - Directory-0 -> DMA-0 net_lat: 7 - -DMA-0 Network Latencies - DMA-0 -> L1Cache-0 net_lat: 7 - DMA-0 -> Directory-0 net_lat: 7 - ---- End Topology Print --- Profiler Configuration ---------------------- @@ -103,7 +34,7 @@ periodic_stats_period: 1000000 ================ End RubySystem Configuration Print ================ -Real time: Jul/06/2009 11:11:08 +Real time: Jan/28/2010 10:15:29 Profiler Stats -------------- @@ -112,123 +43,52 @@ Elapsed_time_in_minutes: 0.0166667 Elapsed_time_in_hours: 0.000277778 Elapsed_time_in_days: 1.15741e-05 -Virtual_time_in_seconds: 0.84 -Virtual_time_in_minutes: 0.014 -Virtual_time_in_hours: 0.000233333 -Virtual_time_in_days: 0.000233333 +Virtual_time_in_seconds: 0.5 +Virtual_time_in_minutes: 0.00833333 +Virtual_time_in_hours: 0.000138889 +Virtual_time_in_days: 5.78704e-06 -Ruby_current_time: 25390001 -Ruby_start_time: 1 -Ruby_cycles: 25390000 +Ruby_current_time: 342698 +Ruby_start_time: 0 +Ruby_cycles: 342698 -mbytes_resident: 145.145 -mbytes_total: 1329.68 -resident_ratio: 0.109161 +mbytes_resident: 34.2148 +mbytes_total: 34.2227 +resident_ratio: 1 Total_misses: 0 total_misses: 0 [ 0 ] user_misses: 0 [ 0 ] supervisor_misses: 0 [ 0 ] -instruction_executed: 1 [ 1 ] -ruby_cycles_executed: 25390001 [ 25390001 ] -cycles_per_instruction: 2.539e+07 [ 2.539e+07 ] -misses_per_thousand_instructions: 0 [ 0 ] +ruby_cycles_executed: 342699 [ 342699 ] transactions_started: 0 [ 0 ] transactions_ended: 0 [ 0 ] -instructions_per_transaction: 0 [ 0 ] cycles_per_transaction: 0 [ 0 ] misses_per_transaction: 0 [ 0 ] -L1D_cache cache stats: - L1D_cache_total_misses: 0 - L1D_cache_total_demand_misses: 0 - L1D_cache_total_prefetches: 0 - L1D_cache_total_sw_prefetches: 0 - L1D_cache_total_hw_prefetches: 0 - L1D_cache_misses_per_transaction: 0 - L1D_cache_misses_per_instruction: 0 - L1D_cache_instructions_per_misses: NaN - - L1D_cache_request_size: [binsize: log2 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - -L1I_cache cache stats: - L1I_cache_total_misses: 0 - L1I_cache_total_demand_misses: 0 - L1I_cache_total_prefetches: 0 - L1I_cache_total_sw_prefetches: 0 - L1I_cache_total_hw_prefetches: 0 - L1I_cache_misses_per_transaction: 0 - L1I_cache_misses_per_instruction: 0 - L1I_cache_instructions_per_misses: NaN - - L1I_cache_request_size: [binsize: log2 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - -L2_cache cache stats: - L2_cache_total_misses: 0 - L2_cache_total_demand_misses: 0 - L2_cache_total_prefetches: 0 - L2_cache_total_sw_prefetches: 0 - L2_cache_total_hw_prefetches: 0 - L2_cache_misses_per_transaction: 0 - L2_cache_misses_per_instruction: 0 - L2_cache_instructions_per_misses: NaN - - L2_cache_request_size: [binsize: log2 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - - -Memory control: - memory_total_requests: 1554 - memory_reads: 793 - memory_writes: 761 - memory_refreshes: 14035 - memory_total_request_delays: 1878 - memory_delays_per_request: 1.20849 - memory_delays_in_input_queue: 761 - memory_delays_behind_head_of_bank_queue: 0 - memory_delays_stalled_at_head_of_bank_queue: 1117 - memory_stalls_for_bank_busy: 223 - memory_stalls_for_random_busy: 0 - memory_stalls_for_anti_starvation: 0 - memory_stalls_for_arbitration: 62 - memory_stalls_for_bus: 804 - memory_stalls_for_tfaw: 0 - memory_stalls_for_read_write_turnaround: 28 - memory_stalls_for_read_read_turnaround: 0 - accesses_per_bank: 58 26 38 28 28 95 36 22 26 30 48 48 82 65 56 48 61 37 36 30 52 58 52 34 45 35 40 98 78 83 22 59 Busy Controller Counts: L1Cache-0:0 Directory-0:0 -DMA-0:0 + Busy Bank Count:0 -L1TBE_usage: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] -L2TBE_usage: [binsize: 1 max: 1 count: 1554 average: 0.489704 | standard deviation: 0.500483 | 793 761 ] -StopTable_usage: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] -sequencer_requests_outstanding: [binsize: 1 max: 1 count: 8464 average: 1 | standard deviation: 0 | 0 8464 ] -store_buffer_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] -unique_blocks_in_store_buffer: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +sequencer_requests_outstanding: [binsize: 1 max: 1 count: 8465 average: 1 | standard deviation: 0 | 0 8465 ] All Non-Zero Cycle Demand Cache Accesses ---------------------------------------- -miss_latency: [binsize: 2 max: 279 count: 8464 average: 17.852 | standard deviation: 49.5344 | 0 7671 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 30 0 0 0 0 15 0 0 0 0 687 0 0 0 0 16 0 0 0 0 24 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 0 0 0 0 1 0 0 0 0 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_1: [binsize: 2 max: 269 count: 6414 average: 12.6723 | standard deviation: 41.1839 | 0 6008 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8 0 0 0 0 11 0 0 0 0 362 0 0 0 0 8 0 0 0 0 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_2: [binsize: 2 max: 279 count: 1185 average: 42.865 | standard deviation: 73.1137 | 0 900 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 14 0 0 0 0 1 0 0 0 0 241 0 0 0 0 7 0 0 0 0 12 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_3: [binsize: 2 max: 279 count: 865 average: 21.9931 | standard deviation: 55.1781 | 0 763 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8 0 0 0 0 3 0 0 0 0 84 0 0 0 0 1 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_L2Miss: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency: [binsize: 2 max: 377 count: 8464 average: 39.4889 | standard deviation: 72.9776 | 0 6734 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 6 1 3 6 0 334 211 182 529 243 4 4 0 5 2 15 9 4 14 10 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 30 18 15 24 37 2 3 0 0 2 2 1 1 3 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 ] +miss_latency_1: [binsize: 2 max: 285 count: 6414 average: 23.2806 | standard deviation: 57.2661 | 0 5684 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 3 1 2 4 0 155 91 77 220 92 2 3 0 1 2 2 6 1 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 20 9 5 10 12 2 1 0 0 1 2 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_2: [binsize: 2 max: 375 count: 1185 average: 110.608 | standard deviation: 87.0282 | 0 458 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 3 0 1 2 0 147 90 74 255 81 2 1 0 3 0 12 3 1 9 6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9 4 2 11 4 0 2 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_3: [binsize: 2 max: 377 count: 865 average: 62.2439 | standard deviation: 89.6671 | 0 592 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 32 30 31 54 70 0 0 0 1 0 1 0 2 2 4 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 5 8 3 21 0 0 0 0 0 0 0 1 2 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 ] All Non-Zero Cycle SW Prefetch Requests ------------------------------------ prefetch_latency: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] prefetch_latency_L2Miss:[binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] -multicast_retries: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] -gets_mask_prediction_count: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] -getx_mask_prediction_count: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] -explicit_training_mask: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - Request vs. RubySystem State Profile -------------------------------- @@ -237,104 +97,159 @@ filter_action: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN Message Delayed Cycles ---------------------- -Total_delay_cycles: [binsize: 1 max: 0 count: 1554 average: 0 | standard deviation: 0 | 1554 ] -Total_nonPF_delay_cycles: [binsize: 1 max: 0 count: 1554 average: 0 | standard deviation: 0 | 1554 ] +Total_delay_cycles: [binsize: 1 max: 0 count: 3456 average: 0 | standard deviation: 0 | 3456 ] +Total_nonPF_delay_cycles: [binsize: 1 max: 0 count: 3456 average: 0 | standard deviation: 0 | 3456 ] virtual_network_0_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - virtual_network_1_delay_cycles: [binsize: 1 max: 0 count: 793 average: 0 | standard deviation: 0 | 793 ] - virtual_network_2_delay_cycles: [binsize: 1 max: 0 count: 761 average: 0 | standard deviation: 0 | 761 ] + virtual_network_1_delay_cycles: [binsize: 1 max: 0 count: 1730 average: 0 | standard deviation: 0 | 1730 ] + virtual_network_2_delay_cycles: [binsize: 1 max: 0 count: 1726 average: 0 | standard deviation: 0 | 1726 ] virtual_network_3_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] virtual_network_4_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] virtual_network_5_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + virtual_network_6_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + virtual_network_7_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + virtual_network_8_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + virtual_network_9_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] Resource Usage -------------- page_size: 4096 user_time: 0 system_time: 0 -page_reclaims: 37916 -page_faults: 0 +page_reclaims: 7357 +page_faults: 2195 swaps: 0 block_inputs: 0 -block_outputs: 48 +block_outputs: 0 Network Stats ------------- switch_0_inlinks: 2 switch_0_outlinks: 2 -links_utilized_percent_switch_0: 0.000191266 - links_utilized_percent_switch_0_link_0: 7.65065e-05 bw: 640000 base_latency: 1 - links_utilized_percent_switch_0_link_1: 0.000306026 bw: 160000 base_latency: 1 +links_utilized_percent_switch_0: 0.157486 + links_utilized_percent_switch_0_link_0: 0.0630876 bw: 640000 base_latency: 1 + links_utilized_percent_switch_0_link_1: 0.251884 bw: 160000 base_latency: 1 - outgoing_messages_switch_0_link_0_Response_Data: 793 6344 [ 0 793 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_0_Writeback_Control: 761 6088 [ 0 0 761 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Control: 793 6344 [ 793 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Data: 761 6088 [ 761 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_0_Response_Data: 1730 124560 [ 0 1730 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_0_Writeback_Control: 1726 13808 [ 0 0 1726 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Control: 1730 13840 [ 1730 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Data: 1726 124272 [ 1726 0 0 0 0 0 0 0 0 0 ] base_latency: 1 switch_1_inlinks: 2 switch_1_outlinks: 2 -links_utilized_percent_switch_1: 0.000191266 - links_utilized_percent_switch_1_link_0: 7.65065e-05 bw: 640000 base_latency: 1 - links_utilized_percent_switch_1_link_1: 0.000306026 bw: 160000 base_latency: 1 +links_utilized_percent_switch_1: 0.157661 + links_utilized_percent_switch_1_link_0: 0.0629709 bw: 640000 base_latency: 1 + links_utilized_percent_switch_1_link_1: 0.25235 bw: 160000 base_latency: 1 - outgoing_messages_switch_1_link_0_Control: 793 6344 [ 793 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_0_Data: 761 6088 [ 761 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_Response_Data: 793 6344 [ 0 793 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_Writeback_Control: 761 6088 [ 0 0 761 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_Control: 1730 13840 [ 1730 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_Data: 1726 124272 [ 1726 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Response_Data: 1730 124560 [ 0 1730 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Writeback_Control: 1726 13808 [ 0 0 1726 0 0 0 0 0 0 0 ] base_latency: 1 switch_2_inlinks: 2 switch_2_outlinks: 2 -links_utilized_percent_switch_2: 0 - links_utilized_percent_switch_2_link_0: 0 bw: 640000 base_latency: 1 - links_utilized_percent_switch_2_link_1: 0 bw: 160000 base_latency: 1 - - -switch_3_inlinks: 3 -switch_3_outlinks: 3 -links_utilized_percent_switch_3: 0.000204017 - links_utilized_percent_switch_3_link_0: 0.000306026 bw: 160000 base_latency: 1 - links_utilized_percent_switch_3_link_1: 0.000306026 bw: 160000 base_latency: 1 - links_utilized_percent_switch_3_link_2: 0 bw: 160000 base_latency: 1 - - outgoing_messages_switch_3_link_0_Response_Data: 793 6344 [ 0 793 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_0_Writeback_Control: 761 6088 [ 0 0 761 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_1_Control: 793 6344 [ 793 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_1_Data: 761 6088 [ 761 0 0 0 0 0 ] base_latency: 1 - - --- DMA --- +links_utilized_percent_switch_2: 0.252117 + links_utilized_percent_switch_2_link_0: 0.25235 bw: 160000 base_latency: 1 + links_utilized_percent_switch_2_link_1: 0.251884 bw: 160000 base_latency: 1 + + outgoing_messages_switch_2_link_0_Response_Data: 1730 124560 [ 0 1730 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_0_Writeback_Control: 1726 13808 [ 0 0 1726 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Control: 1730 13840 [ 1730 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Data: 1726 124272 [ 1726 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + +Cache Stats: system.ruby.network.topology.ext_links0.ext_node.sequencer.icache + system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_misses: 1730 + system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_demand_misses: 1730 + system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_prefetches: 0 + system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_sw_prefetches: 0 + system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_hw_prefetches: 0 + system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_misses_per_transaction: inf + + system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_type_LD: 42.0231% + system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_type_ST: 15.7803% + system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_type_IFETCH: 42.1965% + + system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_access_mode_type_SupervisorMode: 1730 100% + system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_size: [binsize: 1 max: 8 count: 1730 average: 6.00925 | standard deviation: 2.00058 | 0 0 0 0 861 0 0 0 869 ] + + --- L1Cache 0 --- - Event Counts - -ReadRequest 0 -WriteRequest 0 -Data 0 -Ack 0 +Load 1185 +Ifetch 6414 +Store 865 +Data 1730 +Fwd_GETX 0 +Inv 0 +Replacement 1726 +Writeback_Ack 1726 +Writeback_Nack 0 - Transitions - -READY ReadRequest 0 <-- -READY WriteRequest 0 <-- +I Load 727 +I Ifetch 730 +I Store 273 +I Inv 0 <-- +I Replacement 0 <-- -BUSY_RD Data 0 <-- +II Writeback_Nack 0 <-- -BUSY_WR Ack 0 <-- +M Load 458 +M Ifetch 5684 +M Store 592 +M Fwd_GETX 0 <-- +M Inv 0 <-- +M Replacement 1726 + +MI Fwd_GETX 0 <-- +MI Inv 0 <-- +MI Writeback_Ack 1726 +MI Writeback_Nack 0 <-- + +MII Fwd_GETX 0 <-- + +IS Data 1457 + +IM Data 273 + +Memory controller: system.ruby.network.topology.ext_links1.ext_node.memBuffer: + memory_total_requests: 3456 + memory_reads: 1730 + memory_writes: 1726 + memory_refreshes: 714 + memory_total_request_delays: 5050 + memory_delays_per_request: 1.46123 + memory_delays_in_input_queue: 1722 + memory_delays_behind_head_of_bank_queue: 8 + memory_delays_stalled_at_head_of_bank_queue: 3320 + memory_stalls_for_bank_busy: 1509 + memory_stalls_for_random_busy: 0 + memory_stalls_for_anti_starvation: 0 + memory_stalls_for_arbitration: 99 + memory_stalls_for_bus: 1677 + memory_stalls_for_tfaw: 0 + memory_stalls_for_read_write_turnaround: 35 + memory_stalls_for_read_read_turnaround: 0 + accesses_per_bank: 162 36 92 110 106 362 98 36 32 34 83 92 110 104 84 86 83 53 50 58 64 124 212 72 66 50 122 190 220 325 42 98 - --- Directory --- + --- Directory 0 --- - Event Counts - -GETX 793 +GETX 1730 GETS 0 -PUTX 761 +PUTX 1726 PUTX_NotOwner 0 DMA_READ 0 DMA_WRITE 0 -Memory_Data 793 -Memory_Ack 761 +Memory_Data 1730 +Memory_Ack 1726 - Transitions - -I GETX 793 +I GETX 1730 I PUTX_NotOwner 0 <-- I DMA_READ 0 <-- I DMA_WRITE 0 <-- M GETX 0 <-- -M PUTX 761 +M PUTX 1726 M PUTX_NotOwner 0 <-- M DMA_READ 0 <-- M DMA_WRITE 0 <-- @@ -345,15 +260,19 @@ M_DRD PUTX 0 <-- M_DWR GETX 0 <-- M_DWR PUTX 0 <-- +M_DWRI GETX 0 <-- M_DWRI Memory_Ack 0 <-- +M_DRDI GETX 0 <-- +M_DRDI Memory_Ack 0 <-- + IM GETX 0 <-- IM GETS 0 <-- IM PUTX 0 <-- IM PUTX_NotOwner 0 <-- IM DMA_READ 0 <-- IM DMA_WRITE 0 <-- -IM Memory_Data 793 +IM Memory_Data 1730 MI GETX 0 <-- MI GETS 0 <-- @@ -361,7 +280,7 @@ MI PUTX 0 <-- MI PUTX_NotOwner 0 <-- MI DMA_READ 0 <-- MI DMA_WRITE 0 <-- -MI Memory_Ack 761 +MI Memory_Ack 1726 ID GETX 0 <-- ID GETS 0 <-- @@ -379,39 +298,3 @@ ID_W DMA_READ 0 <-- ID_W DMA_WRITE 0 <-- ID_W Memory_Ack 0 <-- - --- L1Cache --- - - Event Counts - -Load 1185 -Ifetch 6414 -Store 865 -Data 793 -Fwd_GETX 0 -Inv 0 -Replacement 761 -Writeback_Ack 761 -Writeback_Nack 0 - - - Transitions - -I Load 285 -I Ifetch 406 -I Store 102 -I Inv 0 <-- -I Replacement 0 <-- - -II Writeback_Nack 0 <-- - -M Load 900 -M Ifetch 6008 -M Store 763 -M Fwd_GETX 0 <-- -M Inv 0 <-- -M Replacement 761 - -MI Fwd_GETX 0 <-- -MI Inv 0 <-- -MI Writeback_Ack 761 - -IS Data 691 - -IM Data 102 - diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/simerr b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/simerr index 187d1a0ac..eabe42249 100755 --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/simerr +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/simerr @@ -1,23 +1,3 @@ -["-r", "tests/configs/../../src/mem/ruby/config/MI_example-homogeneous.rb", "-p", "1", "-m", "1", "-s", "1024"] -print config: 1 -Creating new MessageBuffer for 0 0 -Creating new MessageBuffer for 0 1 -Creating new MessageBuffer for 0 2 -Creating new MessageBuffer for 0 3 -Creating new MessageBuffer for 0 4 -Creating new MessageBuffer for 0 5 -Creating new MessageBuffer for 1 0 -Creating new MessageBuffer for 1 1 -Creating new MessageBuffer for 1 2 -Creating new MessageBuffer for 1 3 -Creating new MessageBuffer for 1 4 -Creating new MessageBuffer for 1 5 -Creating new MessageBuffer for 2 0 -Creating new MessageBuffer for 2 1 -Creating new MessageBuffer for 2 2 -Creating new MessageBuffer for 2 3 -Creating new MessageBuffer for 2 4 -Creating new MessageBuffer for 2 5 warn: Sockets disabled, not accepting gdb connections For more information see: http://www.m5sim.org/warn/d946bea6 hack: be nice to actually delete the event here diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/simout b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/simout index acf0a3d41..b8009485a 100755 --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/simout +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/simout @@ -5,14 +5,13 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jul 6 2009 11:03:45 -M5 revision d3635cac686a 6289 default ruby_refs.diff qtip tip -M5 started Jul 6 2009 11:11:07 -M5 executing on maize +M5 compiled Jan 27 2010 22:23:20 +M5 revision 6068d4fc30d3+ 6931+ default qtip tip brad/rubycfg_regress_udpate +M5 started Jan 28 2010 10:15:28 +M5 executing on svvint07 command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby -re tests/run.py build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby -Global frequency set at 1000000000000 ticks per second - Debug: Adding to filter: 'q' (Queue) +Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello world! -Exiting @ tick 25390000 because target called exit() +Exiting @ tick 342698 because target called exit() diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt index 27fddd18d..d59a173b9 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 8064 # Simulator instruction rate (inst/s) -host_mem_usage 1361592 # Number of bytes of host memory used -host_seconds 0.79 # Real time elapsed on the host -host_tick_rate 31966299 # Simulator tick rate (ticks/s) -sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 19405 # Simulator instruction rate (inst/s) +host_mem_usage 215700 # Number of bytes of host memory used +host_seconds 0.33 # Real time elapsed on the host +host_tick_rate 1038428 # Simulator tick rate (ticks/s) +sim_freq 1000000000 # Frequency of simulated ticks sim_insts 6404 # Number of instructions simulated -sim_seconds 0.000025 # Number of seconds simulated -sim_ticks 25390000 # Number of ticks simulated +sim_seconds 0.000343 # Number of seconds simulated +sim_ticks 342698 # Number of ticks simulated system.cpu.dtb.data_accesses 2060 # DTB accesses system.cpu.dtb.data_acv 0 # DTB access violations system.cpu.dtb.data_hits 2050 # DTB hits @@ -42,7 +42,7 @@ system.cpu.itb.write_acv 0 # DT system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 50780 # number of cpu cycles simulated +system.cpu.numCycles 342698 # number of cpu cycles simulated system.cpu.num_insts 6404 # Number of instructions executed system.cpu.num_refs 2060 # Number of memory references system.cpu.workload.PROG:num_syscalls 17 # Number of system calls |