diff options
Diffstat (limited to 'tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt')
| -rw-r--r-- | tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt | 240 |
1 files changed, 120 insertions, 120 deletions
diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt index 886aae88f..d7cfe3b16 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt @@ -3,10 +3,10 @@ sim_seconds 0.000007 # Number of seconds simulated sim_ticks 6833000 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 36521 # Simulator instruction rate (inst/s) -host_tick_rate 104491306 # Simulator tick rate (ticks/s) -host_mem_usage 242860 # Number of bytes of host memory used -host_seconds 0.07 # Real time elapsed on the host +host_inst_rate 39761 # Simulator instruction rate (inst/s) +host_tick_rate 113766137 # Simulator tick rate (ticks/s) +host_mem_usage 203344 # Number of bytes of host memory used +host_seconds 0.06 # Real time elapsed on the host sim_insts 2387 # Number of instructions simulated system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses @@ -24,10 +24,10 @@ system.cpu.dtb.data_hits 1035 # DT system.cpu.dtb.data_misses 44 # DTB misses system.cpu.dtb.data_acv 1 # DTB access violations system.cpu.dtb.data_accesses 1079 # DTB accesses -system.cpu.itb.fetch_hits 945 # ITB hits +system.cpu.itb.fetch_hits 941 # ITB hits system.cpu.itb.fetch_misses 30 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 975 # ITB accesses +system.cpu.itb.fetch_accesses 971 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -44,87 +44,87 @@ system.cpu.workload.num_syscalls 4 # Nu system.cpu.numCycles 13667 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 1041 # Number of BP lookups +system.cpu.BPredUnit.lookups 1038 # Number of BP lookups system.cpu.BPredUnit.condPredicted 518 # Number of conditional branches predicted system.cpu.BPredUnit.condIncorrect 226 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 733 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 220 # Number of BTB hits +system.cpu.BPredUnit.BTBLookups 732 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 219 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 210 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.usedRAS 208 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 34 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 3751 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 6413 # Number of instructions fetch has processed -system.cpu.fetch.Branches 1041 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 430 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 1115 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 754 # Number of cycles fetch has spent squashing +system.cpu.fetch.icacheStallCycles 3757 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 6399 # Number of instructions fetch has processed +system.cpu.fetch.Branches 1038 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 427 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 1112 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 750 # Number of cycles fetch has spent squashing system.cpu.fetch.BlockedCycles 212 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 17 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 785 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 945 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 157 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.CacheLines 941 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 156 # Number of outstanding Icache misses that were squashed system.cpu.fetch.rateDist::samples 6383 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.004700 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.420463 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.002507 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.418848 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 5268 82.53% 82.53% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 60 0.94% 83.47% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 118 1.85% 85.32% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 94 1.47% 86.79% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 140 2.19% 88.99% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 58 0.91% 89.90% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 55 0.86% 90.76% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 65 1.02% 91.78% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 5271 82.58% 82.58% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 60 0.94% 83.52% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 117 1.83% 85.35% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 94 1.47% 86.82% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 140 2.19% 89.02% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 57 0.89% 89.91% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 55 0.86% 90.77% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 64 1.00% 91.78% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::8 525 8.22% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::total 6383 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.076169 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.469232 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 4642 # Number of cycles decode is idle +system.cpu.fetch.branchRate 0.075949 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.468208 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 4647 # Number of cycles decode is idle system.cpu.decode.BlockedCycles 226 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 1083 # Number of cycles decode is running +system.cpu.decode.RunCycles 1081 # Number of cycles decode is running system.cpu.decode.UnblockCycles 6 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 426 # Number of cycles decode is squashing +system.cpu.decode.SquashCycles 423 # Number of cycles decode is squashing system.cpu.decode.BranchResolved 158 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 80 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 5734 # Number of instructions handled by decode +system.cpu.decode.DecodedInsts 5725 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 284 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 426 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 4737 # Number of cycles rename is idle +system.cpu.rename.SquashCycles 423 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 4742 # Number of cycles rename is idle system.cpu.rename.BlockCycles 57 # Number of cycles rename is blocking system.cpu.rename.serializeStallCycles 147 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 997 # Number of cycles rename is running +system.cpu.rename.RunCycles 995 # Number of cycles rename is running system.cpu.rename.UnblockCycles 19 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 5480 # Number of instructions processed by rename +system.cpu.rename.RenamedInsts 5471 # Number of instructions processed by rename system.cpu.rename.LSQFullEvents 14 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 3945 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 6160 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 6148 # Number of integer rename lookups +system.cpu.rename.RenamedOperands 3940 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 6152 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 6140 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 12 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1768 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 2177 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 2172 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 8 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 6 # count of temporary serializing insts renamed system.cpu.rename.skidInsts 107 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 882 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedLoads 881 # Number of loads inserted to the mem dependence unit. system.cpu.memDep0.insertedStores 453 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 3 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 3 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 4659 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsAdded 4657 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 6 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 3882 # Number of instructions issued +system.cpu.iq.iqInstsIssued 3881 # Number of instructions issued system.cpu.iq.iqSquashedInstsIssued 49 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 2129 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 1179 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedInstsExamined 2074 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 1177 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed system.cpu.iq.issued_per_cycle::samples 6383 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.608178 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.298400 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.608021 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.298413 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 4812 75.39% 75.39% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 543 8.51% 83.89% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 4813 75.40% 75.40% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 542 8.49% 83.89% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::2 388 6.08% 89.97% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::3 264 4.14% 94.11% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::4 199 3.12% 97.23% # Number of insts issued each cycle @@ -171,79 +171,79 @@ system.cpu.iq.fu_full::MemWrite 23 56.10% 100.00% # at system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 2767 71.28% 71.28% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 1 0.03% 71.30% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 71.30% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 71.30% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 71.30% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 71.30% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 71.30% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 71.30% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 71.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 71.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 71.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 71.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 71.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 71.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 71.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 71.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 71.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 71.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 71.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 71.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 71.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 71.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 71.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 71.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 71.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 71.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 71.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 71.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 71.30% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 734 18.91% 90.21% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 2767 71.30% 71.30% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 1 0.03% 71.32% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 71.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 71.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 71.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 71.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 71.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 71.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 71.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 71.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 71.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 71.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 71.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 71.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 71.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 71.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 71.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 71.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 71.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 71.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 71.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 71.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 71.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 71.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 71.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 71.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 71.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 71.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 71.32% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 733 18.89% 90.21% # Type of FU issued system.cpu.iq.FU_type_0::MemWrite 380 9.79% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 3882 # Type of FU issued -system.cpu.iq.rate 0.284042 # Inst issue rate +system.cpu.iq.FU_type_0::total 3881 # Type of FU issued +system.cpu.iq.rate 0.283969 # Inst issue rate system.cpu.iq.fu_busy_cnt 41 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.010562 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 14224 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 6793 # Number of integer instruction queue writes +system.cpu.iq.fu_busy_rate 0.010564 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 14222 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 6735 # Number of integer instruction queue writes system.cpu.iq.int_inst_queue_wakeup_accesses 3573 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 13 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 6 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 6 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 3916 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 3915 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 7 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 35 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 467 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 466 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 6 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.memOrderViolation 5 # Number of memory ordering violations system.cpu.iew.lsq.thread0.squashedStores 159 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 426 # Number of cycles IEW is squashing +system.cpu.iew.iewSquashCycles 423 # Number of cycles IEW is squashing system.cpu.iew.iewBlockCycles 44 # Number of cycles IEW is blocking system.cpu.iew.iewUnblockCycles 6 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 5003 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispatchedInsts 5001 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 64 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 882 # Number of dispatched load instructions +system.cpu.iew.iewDispLoadInsts 881 # Number of dispatched load instructions system.cpu.iew.iewDispStoreInsts 453 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 6 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 3 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 6 # Number of memory order violations +system.cpu.iew.memOrderViolationEvents 5 # Number of memory order violations system.cpu.iew.predictedTakenIncorrect 54 # Number of branches that were predicted taken incorrectly system.cpu.iew.predictedNotTakenIncorrect 121 # Number of branches that were predicted not taken incorrectly system.cpu.iew.branchMispredicts 175 # Number of branch mispredicts detected at execute system.cpu.iew.iewExecutedInsts 3749 # Number of executed instructions system.cpu.iew.iewExecLoadInsts 706 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 133 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecSquashedInsts 132 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 338 # number of nop insts executed system.cpu.iew.exec_refs 1080 # number of memory reference insts executed @@ -259,18 +259,18 @@ system.cpu.iew.wb_rate 0.261872 # in system.cpu.iew.wb_fanout 0.786143 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 2576 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 2418 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 2416 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 4 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 149 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 5957 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.432432 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.291215 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::samples 5960 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.432215 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.290536 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 5066 85.04% 85.04% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 221 3.71% 88.75% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 314 5.27% 94.02% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 118 1.98% 96.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 71 1.19% 97.20% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 5068 85.03% 85.03% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 222 3.72% 88.76% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 314 5.27% 94.03% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 119 2.00% 96.02% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 70 1.17% 97.20% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::5 53 0.89% 98.09% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::6 34 0.57% 98.66% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::7 20 0.34% 98.99% # Number of insts commited each cycle @@ -278,7 +278,7 @@ system.cpu.commit.committed_per_cycle::8 60 1.01% 100.00% # Nu system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 5957 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 5960 # Number of insts commited each cycle system.cpu.commit.count 2576 # Number of instructions committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.commit.refs 709 # Number of memory references committed @@ -290,8 +290,8 @@ system.cpu.commit.int_insts 2367 # Nu system.cpu.commit.function_calls 71 # Number of function calls committed. system.cpu.commit.bw_lim_events 60 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 10644 # The number of ROB reads -system.cpu.rob.rob_writes 10417 # The number of ROB writes +system.cpu.rob.rob_reads 10645 # The number of ROB reads +system.cpu.rob.rob_writes 10410 # The number of ROB writes system.cpu.timesIdled 139 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.idleCycles 7284 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 2387 # Number of Instructions Simulated @@ -307,27 +307,27 @@ system.cpu.misc_regfile_reads 1 # nu system.cpu.misc_regfile_writes 1 # number of misc regfile writes system.cpu.icache.replacements 0 # number of replacements system.cpu.icache.tagsinuse 91.574139 # Cycle average of tags in use -system.cpu.icache.total_refs 704 # Total number of references to valid blocks. +system.cpu.icache.total_refs 700 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 185 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 3.805405 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 3.783784 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.occ_blocks::0 91.574139 # Average occupied blocks per context system.cpu.icache.occ_percent::0 0.044714 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 704 # number of ReadReq hits -system.cpu.icache.demand_hits 704 # number of demand (read+write) hits -system.cpu.icache.overall_hits 704 # number of overall hits +system.cpu.icache.ReadReq_hits 700 # number of ReadReq hits +system.cpu.icache.demand_hits 700 # number of demand (read+write) hits +system.cpu.icache.overall_hits 700 # number of overall hits system.cpu.icache.ReadReq_misses 241 # number of ReadReq misses system.cpu.icache.demand_misses 241 # number of demand (read+write) misses system.cpu.icache.overall_misses 241 # number of overall misses system.cpu.icache.ReadReq_miss_latency 8777500 # number of ReadReq miss cycles system.cpu.icache.demand_miss_latency 8777500 # number of demand (read+write) miss cycles system.cpu.icache.overall_miss_latency 8777500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 945 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 945 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 945 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.255026 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.255026 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.255026 # miss rate for overall accesses +system.cpu.icache.ReadReq_accesses 941 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 941 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 941 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate 0.256111 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate 0.256111 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate 0.256111 # miss rate for overall accesses system.cpu.icache.ReadReq_avg_miss_latency 36421.161826 # average ReadReq miss latency system.cpu.icache.demand_avg_miss_latency 36421.161826 # average overall miss latency system.cpu.icache.overall_avg_miss_latency 36421.161826 # average overall miss latency @@ -351,9 +351,9 @@ system.cpu.icache.ReadReq_mshr_miss_latency 6554500 # system.cpu.icache.demand_mshr_miss_latency 6554500 # number of demand (read+write) MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency 6554500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.195767 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.195767 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.195767 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_mshr_miss_rate 0.196599 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate 0.196599 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate 0.196599 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency 35429.729730 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency 35429.729730 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency 35429.729730 # average overall mshr miss latency |