diff options
Diffstat (limited to 'tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt')
| -rw-r--r-- | tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt | 332 |
1 files changed, 166 insertions, 166 deletions
diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt index 3fca93af7..e80a12bfa 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 58135 # Simulator instruction rate (inst/s) -host_mem_usage 204672 # Number of bytes of host memory used -host_seconds 0.04 # Real time elapsed on the host -host_tick_rate 176416397 # Simulator tick rate (ticks/s) +host_inst_rate 106844 # Simulator instruction rate (inst/s) +host_mem_usage 202600 # Number of bytes of host memory used +host_seconds 0.02 # Real time elapsed on the host +host_tick_rate 323591910 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 2387 # Number of instructions simulated sim_seconds 0.000007 # Number of seconds simulated @@ -16,38 +16,38 @@ system.cpu.BPredUnit.condIncorrect 223 # Nu system.cpu.BPredUnit.condPredicted 485 # Number of conditional branches predicted system.cpu.BPredUnit.lookups 931 # Number of BP lookups system.cpu.BPredUnit.usedRAS 174 # Number of times the RAS was used to get a target. -system.cpu.commit.COM:branches 396 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 41 # number cycles where commit BW limit reached -system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle::samples 6308 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::mean 0.408370 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::stdev 1.199072 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::0 5350 84.81% 84.81% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::1 259 4.11% 88.92% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::2 343 5.44% 94.36% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::3 133 2.11% 96.46% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::4 72 1.14% 97.61% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::5 64 1.01% 98.62% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::6 26 0.41% 99.03% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::7 20 0.32% 99.35% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::8 41 0.65% 100.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::total 6308 # Number of insts commited each cycle -system.cpu.commit.COM:count 2576 # Number of instructions committed -system.cpu.commit.COM:fp_insts 6 # Number of committed floating point instructions. -system.cpu.commit.COM:function_calls 71 # Number of function calls committed. -system.cpu.commit.COM:int_insts 2367 # Number of committed integer instructions. -system.cpu.commit.COM:loads 415 # Number of loads committed -system.cpu.commit.COM:membars 0 # Number of memory barriers committed -system.cpu.commit.COM:refs 709 # Number of memory references committed -system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed system.cpu.commit.branchMispredicts 146 # The number of times a branch was mispredicted +system.cpu.commit.branches 396 # Number of branches committed +system.cpu.commit.bw_lim_events 41 # number cycles where commit BW limit reached +system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits system.cpu.commit.commitCommittedInsts 2576 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 4 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.commitSquashedInsts 1995 # The number of squashed insts skipped by commit +system.cpu.commit.committed_per_cycle::samples 6308 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.408370 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.199072 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 5350 84.81% 84.81% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 259 4.11% 88.92% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 343 5.44% 94.36% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 133 2.11% 96.46% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 72 1.14% 97.61% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 64 1.01% 98.62% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 26 0.41% 99.03% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 20 0.32% 99.35% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 41 0.65% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 6308 # Number of insts commited each cycle +system.cpu.commit.count 2576 # Number of instructions committed +system.cpu.commit.fp_insts 6 # Number of committed floating point instructions. +system.cpu.commit.function_calls 71 # Number of function calls committed. +system.cpu.commit.int_insts 2367 # Number of committed integer instructions. +system.cpu.commit.loads 415 # Number of loads committed +system.cpu.commit.membars 0 # Number of memory barriers committed +system.cpu.commit.refs 709 # Number of memory references committed +system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.committedInsts 2387 # Number of Instructions Simulated system.cpu.committedInsts_total 2387 # Number of Instructions Simulated system.cpu.cpi 6.107667 # CPI: Cycles Per Instruction @@ -96,8 +96,8 @@ system.cpu.dcache.demand_mshr_misses 85 # nu system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.011366 # Average percentage of cache occupancy system.cpu.dcache.occ_blocks::0 46.556735 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.011366 # Average percentage of cache occupancy system.cpu.dcache.overall_accesses 883 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 35891.666667 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 35829.411765 # average overall mshr miss latency @@ -119,15 +119,15 @@ system.cpu.dcache.tagsinuse 46.556735 # Cy system.cpu.dcache.total_refs 703 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 217 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 79 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 136 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 5047 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 5111 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 977 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 374 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 284 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 3 # Number of cycles decode is unblocking +system.cpu.decode.BlockedCycles 217 # Number of cycles decode is blocked +system.cpu.decode.BranchMispred 79 # Number of times decode detected a branch misprediction +system.cpu.decode.BranchResolved 136 # Number of times decode resolved a branch +system.cpu.decode.DecodedInsts 5047 # Number of instructions handled by decode +system.cpu.decode.IdleCycles 5111 # Number of cycles decode is idle +system.cpu.decode.RunCycles 977 # Number of cycles decode is running +system.cpu.decode.SquashCycles 374 # Number of cycles decode is squashing +system.cpu.decode.SquashedInsts 284 # Number of squashed instructions handled by decode +system.cpu.decode.UnblockCycles 3 # Number of cycles decode is unblocking system.cpu.dtb.data_accesses 1010 # DTB accesses system.cpu.dtb.data_acv 1 # DTB access violations system.cpu.dtb.data_hits 964 # DTB hits @@ -206,8 +206,8 @@ system.cpu.icache.demand_mshr_misses 181 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.044195 # Average percentage of cache occupancy system.cpu.icache.occ_blocks::0 90.511194 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.044195 # Average percentage of cache occupancy system.cpu.icache.overall_accesses 777 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 36200.431034 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 35306.629834 # average overall mshr miss latency @@ -230,21 +230,13 @@ system.cpu.icache.total_refs 545 # To system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idleCycles 7897 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 600 # Number of branches executed -system.cpu.iew.EXEC:nop 311 # number of nop insts executed -system.cpu.iew.EXEC:rate 0.241855 # Inst execution rate -system.cpu.iew.EXEC:refs 1011 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 366 # Number of stores executed -system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 1995 # num instructions consuming a value -system.cpu.iew.WB:count 3404 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.790977 # average fanout of values written-back -system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 1578 # num instructions producing a value -system.cpu.iew.WB:rate 0.233487 # insts written-back per cycle -system.cpu.iew.WB:sent 3463 # cumulative count of insts sent to commit system.cpu.iew.branchMispredicts 171 # Number of branch mispredicts detected at execute +system.cpu.iew.exec_branches 600 # Number of branches executed +system.cpu.iew.exec_nop 311 # number of nop insts executed +system.cpu.iew.exec_rate 0.241855 # Inst execution rate +system.cpu.iew.exec_refs 1011 # number of memory reference insts executed +system.cpu.iew.exec_stores 366 # Number of stores executed +system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.iewBlockCycles 48 # Number of cycles IEW is blocking system.cpu.iew.iewDispLoadInsts 779 # Number of dispatched load instructions system.cpu.iew.iewDispNonSpecInsts 6 # Number of dispatched non-speculative instructions @@ -272,103 +264,93 @@ system.cpu.iew.lsq.thread.0.squashedStores 134 # system.cpu.iew.memOrderViolationEvents 4 # Number of memory order violations system.cpu.iew.predictedNotTakenIncorrect 118 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedTakenIncorrect 53 # Number of branches that were predicted taken incorrectly +system.cpu.iew.wb_consumers 1995 # num instructions consuming a value +system.cpu.iew.wb_count 3404 # cumulative count of insts written-back +system.cpu.iew.wb_fanout 0.790977 # average fanout of values written-back +system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ +system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ +system.cpu.iew.wb_producers 1578 # num instructions producing a value +system.cpu.iew.wb_rate 0.233487 # insts written-back per cycle +system.cpu.iew.wb_sent 3463 # cumulative count of insts sent to commit system.cpu.int_regfile_reads 4291 # number of integer regfile reads system.cpu.int_regfile_writes 2610 # number of integer regfile writes system.cpu.ipc 0.163729 # IPC: Instructions Per Cycle system.cpu.ipc_total 0.163729 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntAlu 2594 71.36% 71.36% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntMult 1 0.03% 71.39% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 71.39% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 71.39% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 71.39% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 71.39% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 71.39% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 71.39% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 71.39% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 71.39% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 71.39% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 71.39% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 71.39% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 71.39% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 71.39% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 71.39% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 71.39% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 71.39% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 71.39% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 71.39% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 71.39% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 71.39% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 71.39% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 71.39% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 71.39% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 71.39% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 71.39% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 71.39% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 71.39% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemRead 669 18.40% 89.79% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemWrite 371 10.21% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::total 3635 # Type of FU issued -system.cpu.iq.ISSUE:fu_busy_cnt 32 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.008803 # FU busy rate (busy events/executed inst) -system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntAlu 1 3.12% 3.12% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 3.12% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 3.12% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 3.12% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 3.12% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 3.12% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 3.12% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 3.12% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 3.12% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 3.12% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 3.12% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 3.12% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 3.12% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 3.12% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 3.12% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 3.12% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 3.12% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 3.12% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 3.12% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 3.12% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 3.12% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 3.12% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 3.12% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 3.12% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 3.12% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 3.12% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 3.12% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 3.12% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 3.12% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemRead 9 28.12% 31.25% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemWrite 22 68.75% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:issued_per_cycle::samples 6682 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::mean 0.543999 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.232060 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::0 5130 76.77% 76.77% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::1 639 9.56% 86.34% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::2 335 5.01% 91.35% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::3 242 3.62% 94.97% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::4 178 2.66% 97.64% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::5 94 1.41% 99.04% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::6 39 0.58% 99.63% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::7 16 0.24% 99.87% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::8 9 0.13% 100.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::total 6682 # Number of insts issued each cycle -system.cpu.iq.ISSUE:rate 0.249331 # Inst issue rate +system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 2594 71.36% 71.36% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 1 0.03% 71.39% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 71.39% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 71.39% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 71.39% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 71.39% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 71.39% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 71.39% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 71.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 71.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 71.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 71.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 71.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 71.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 71.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 71.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 71.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 71.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 71.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 71.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 71.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 71.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 71.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 71.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 71.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 71.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 71.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 71.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 71.39% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 669 18.40% 89.79% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 371 10.21% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::total 3635 # Type of FU issued system.cpu.iq.fp_alu_accesses 7 # Number of floating point alu accesses system.cpu.iq.fp_inst_queue_reads 13 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_wakeup_accesses 6 # Number of floating instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_writes 6 # Number of floating instruction queue writes +system.cpu.iq.fu_busy_cnt 32 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.008803 # FU busy rate (busy events/executed inst) +system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 1 3.12% 3.12% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 3.12% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 3.12% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.12% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.12% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.12% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 3.12% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.12% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 3.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 3.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.12% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 9 28.12% 31.25% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 22 68.75% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.int_alu_accesses 3660 # Number of integer alu accesses system.cpu.iq.int_inst_queue_reads 14000 # Number of integer instruction queue reads system.cpu.iq.int_inst_queue_wakeup_accesses 3398 # Number of integer instruction queue wakeup accesses @@ -380,6 +362,24 @@ system.cpu.iq.iqSquashedInstsExamined 1704 # Nu system.cpu.iq.iqSquashedInstsIssued 29 # Number of squashed instructions issued system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed system.cpu.iq.iqSquashedOperandsExamined 959 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.issued_per_cycle::samples 6682 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.543999 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.232060 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 5130 76.77% 76.77% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 639 9.56% 86.34% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 335 5.01% 91.35% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 242 3.62% 94.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 178 2.66% 97.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 94 1.41% 99.04% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 39 0.58% 99.63% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 16 0.24% 99.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 9 0.13% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 6682 # Number of insts issued each cycle +system.cpu.iq.rate 0.249331 # Inst issue rate system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_hits 0 # DTB hits @@ -436,8 +436,8 @@ system.cpu.l2cache.demand_mshr_misses 266 # nu system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.003658 # Average percentage of cache occupancy system.cpu.l2cache.occ_blocks::0 119.871330 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.003658 # Average percentage of cache occupancy system.cpu.l2cache.overall_accesses 266 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 34351.503759 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 31176.691729 # average overall mshr miss latency @@ -468,27 +468,27 @@ system.cpu.misc_regfile_writes 1 # nu system.cpu.numCycles 14579 # number of cpu cycles simulated system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.rename.RENAME:BlockCycles 55 # Number of cycles rename is blocking -system.cpu.rename.RENAME:CommittedMaps 1768 # Number of HB maps that are committed -system.cpu.rename.RENAME:IQFullEvents 6 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 5189 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 2 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:RenameLookups 5515 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 4879 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 3490 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 901 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 374 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 17 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 1722 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:fp_rename_lookups 12 # Number of floating rename lookups -system.cpu.rename.RENAME:int_rename_lookups 5503 # Number of integer rename lookups -system.cpu.rename.RENAME:serializeStallCycles 146 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 8 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 74 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 6 # count of temporary serializing insts renamed +system.cpu.rename.BlockCycles 55 # Number of cycles rename is blocking +system.cpu.rename.CommittedMaps 1768 # Number of HB maps that are committed +system.cpu.rename.IQFullEvents 6 # Number of times rename has blocked due to IQ full +system.cpu.rename.IdleCycles 5189 # Number of cycles rename is idle +system.cpu.rename.LSQFullEvents 2 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenameLookups 5515 # Number of register rename lookups that rename has made +system.cpu.rename.RenamedInsts 4879 # Number of instructions processed by rename +system.cpu.rename.RenamedOperands 3490 # Number of destination operands rename has renamed +system.cpu.rename.RunCycles 901 # Number of cycles rename is running +system.cpu.rename.SquashCycles 374 # Number of cycles rename is squashing +system.cpu.rename.UnblockCycles 17 # Number of cycles rename is unblocking +system.cpu.rename.UndoneMaps 1722 # Number of HB maps that are undone due to squashing +system.cpu.rename.fp_rename_lookups 12 # Number of floating rename lookups +system.cpu.rename.int_rename_lookups 5503 # Number of integer rename lookups +system.cpu.rename.serializeStallCycles 146 # count of cycles rename stalled for serializing inst +system.cpu.rename.serializingInsts 8 # count of serializing insts renamed +system.cpu.rename.skidInsts 74 # count of insts added to the skid buffer +system.cpu.rename.tempSerializingInsts 6 # count of temporary serializing insts renamed system.cpu.rob.rob_reads 10591 # The number of ROB reads system.cpu.rob.rob_writes 9519 # The number of ROB writes system.cpu.timesIdled 151 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.workload.PROG:num_syscalls 4 # Number of system calls +system.cpu.workload.num_syscalls 4 # Number of system calls ---------- End Simulation Statistics ---------- |