diff options
Diffstat (limited to 'tests/quick/00.hello/ref/alpha/tru64/simple-atomic-ruby')
5 files changed, 0 insertions, 572 deletions
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic-ruby/config.ini b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic-ruby/config.ini deleted file mode 100644 index 63ec97980..000000000 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic-ruby/config.ini +++ /dev/null @@ -1,97 +0,0 @@ -[root] -type=Root -children=system -dummy=0 - -[system] -type=System -children=cpu membus physmem -mem_mode=atomic -physmem=system.physmem - -[system.cpu] -type=AtomicSimpleCPU -children=dtb itb tracer workload -checker=Null -clock=500 -cpu_id=0 -defer_registration=false -do_checkpoint_insts=true -do_statistics_insts=true -dtb=system.cpu.dtb -function_trace=false -function_trace_start=0 -itb=system.cpu.itb -max_insts_all_threads=0 -max_insts_any_thread=0 -max_loads_all_threads=0 -max_loads_any_thread=0 -numThreads=1 -phase=0 -progress_interval=0 -simulate_data_stalls=false -simulate_inst_stalls=false -system=system -tracer=system.cpu.tracer -width=1 -workload=system.cpu.workload -dcache_port=system.membus.port[2] -icache_port=system.membus.port[1] - -[system.cpu.dtb] -type=AlphaTLB -size=64 - -[system.cpu.itb] -type=AlphaTLB -size=48 - -[system.cpu.tracer] -type=ExeTracer - -[system.cpu.workload] -type=LiveProcess -cmd=hello -cwd= -egid=100 -env= -errout=cerr -euid=100 -executable=/dist/m5/regression/test-progs/hello/bin/alpha/tru64/hello -gid=100 -input=cin -max_stack_size=67108864 -output=cout -pid=100 -ppid=99 -simpoint=0 -system=system -uid=100 - -[system.membus] -type=Bus -block_size=64 -bus_id=0 -clock=1000 -header_cycles=1 -responder_set=false -width=64 -port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port - -[system.physmem] -type=RubyMemory -clock=1 -config_file=build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-atomic-ruby/ruby.config -debug=false -debug_file=ruby.debug -file= -latency=30000 -latency_var=0 -null=false -num_cpus=1 -phase=0 -range=0:134217727 -stats_file=ruby.stats -zero=false -port=system.membus.port[0] - diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic-ruby/ruby.stats b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic-ruby/ruby.stats deleted file mode 100644 index 823052d23..000000000 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic-ruby/ruby.stats +++ /dev/null @@ -1,382 +0,0 @@ - -================ Begin RubySystem Configuration Print ================ - -RubySystem config: - random_seed: 613394 - randomization: 0 - tech_nm: 45 - freq_mhz: 3000 - block_size_bytes: 64 - block_size_bits: 6 - memory_size_bytes: 1073741824 - memory_size_bits: 30 -DMA_Controller config: DMAController_0 - version: 0 - buffer_size: 32 - dma_sequencer: DMASequencer_0 - number_of_TBEs: 128 - transitions_per_cycle: 32 -Directory_Controller config: DirectoryController_0 - version: 0 - buffer_size: 32 - directory_latency: 6 - directory_name: DirectoryMemory_0 - memory_controller_name: MemoryControl_0 - memory_latency: 158 - number_of_TBEs: 128 - recycle_latency: 10 - to_mem_ctrl_latency: 1 - transitions_per_cycle: 32 -L1Cache_Controller config: L1CacheController_0 - version: 0 - buffer_size: 32 - cache: l1u_0 - cache_response_latency: 12 - issue_latency: 2 - number_of_TBEs: 128 - sequencer: Sequencer_0 - transitions_per_cycle: 32 -Cache config: l1u_0 - controller: L1CacheController_0 - cache_associativity: 8 - num_cache_sets_bits: 2 - num_cache_sets: 4 - cache_set_size_bytes: 256 - cache_set_size_Kbytes: 0.25 - cache_set_size_Mbytes: 0.000244141 - cache_size_bytes: 2048 - cache_size_Kbytes: 2 - cache_size_Mbytes: 0.00195312 -DirectoryMemory Global Config: - number of directory memories: 1 - total memory size bytes: 1073741824 - total memory size bits: 30 -DirectoryMemory module config: DirectoryMemory_0 - controller: DirectoryController_0 - version: 0 - memory_bits: 30 - memory_size_bytes: 1073741824 - memory_size_Kbytes: 1.04858e+06 - memory_size_Mbytes: 1024 - memory_size_Gbytes: 1 -Seqeuncer config: Sequencer_0 - controller: L1CacheController_0 - version: 0 - max_outstanding_requests: 16 - deadlock_threshold: 500000 - -Network Configuration ---------------------- -network: SIMPLE_NETWORK -topology: theTopology - -virtual_net_0: active, ordered -virtual_net_1: active, ordered -virtual_net_2: active, ordered -virtual_net_3: inactive -virtual_net_4: active, ordered -virtual_net_5: active, ordered - ---- Begin Topology Print --- - -Topology print ONLY indicates the _NETWORK_ latency between two machines -It does NOT include the latency within the machines - -L1Cache-0 Network Latencies - L1Cache-0 -> Directory-0 net_lat: 7 - L1Cache-0 -> DMA-0 net_lat: 7 - -Directory-0 Network Latencies - Directory-0 -> L1Cache-0 net_lat: 7 - Directory-0 -> DMA-0 net_lat: 7 - -DMA-0 Network Latencies - DMA-0 -> L1Cache-0 net_lat: 7 - DMA-0 -> Directory-0 net_lat: 7 - ---- End Topology Print --- - -Profiler Configuration ----------------------- -periodic_stats_period: 1000000 - -================ End RubySystem Configuration Print ================ - - -Real time: Jul/06/2009 11:11:05 - -Profiler Stats --------------- -Elapsed_time_in_seconds: 0 -Elapsed_time_in_minutes: 0 -Elapsed_time_in_hours: 0 -Elapsed_time_in_days: 0 - -Virtual_time_in_seconds: 0.21 -Virtual_time_in_minutes: 0.0035 -Virtual_time_in_hours: 5.83333e-05 -Virtual_time_in_days: 5.83333e-05 - -Ruby_current_time: 1297501 -Ruby_start_time: 1 -Ruby_cycles: 1297500 - -mbytes_resident: 143.516 -mbytes_total: 1328.64 -resident_ratio: 0.10802 - -Total_misses: 0 -total_misses: 0 [ 0 ] -user_misses: 0 [ 0 ] -supervisor_misses: 0 [ 0 ] - -instruction_executed: 1 [ 1 ] -ruby_cycles_executed: 1297501 [ 1297501 ] -cycles_per_instruction: 1.2975e+06 [ 1.2975e+06 ] -misses_per_thousand_instructions: 0 [ 0 ] - -transactions_started: 0 [ 0 ] -transactions_ended: 0 [ 0 ] -instructions_per_transaction: 0 [ 0 ] -cycles_per_transaction: 0 [ 0 ] -misses_per_transaction: 0 [ 0 ] - -L1D_cache cache stats: - L1D_cache_total_misses: 0 - L1D_cache_total_demand_misses: 0 - L1D_cache_total_prefetches: 0 - L1D_cache_total_sw_prefetches: 0 - L1D_cache_total_hw_prefetches: 0 - L1D_cache_misses_per_transaction: 0 - L1D_cache_misses_per_instruction: 0 - L1D_cache_instructions_per_misses: NaN - - L1D_cache_request_size: [binsize: log2 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - -L1I_cache cache stats: - L1I_cache_total_misses: 0 - L1I_cache_total_demand_misses: 0 - L1I_cache_total_prefetches: 0 - L1I_cache_total_sw_prefetches: 0 - L1I_cache_total_hw_prefetches: 0 - L1I_cache_misses_per_transaction: 0 - L1I_cache_misses_per_instruction: 0 - L1I_cache_instructions_per_misses: NaN - - L1I_cache_request_size: [binsize: log2 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - -L2_cache cache stats: - L2_cache_total_misses: 0 - L2_cache_total_demand_misses: 0 - L2_cache_total_prefetches: 0 - L2_cache_total_sw_prefetches: 0 - L2_cache_total_hw_prefetches: 0 - L2_cache_misses_per_transaction: 0 - L2_cache_misses_per_instruction: 0 - L2_cache_instructions_per_misses: NaN - - L2_cache_request_size: [binsize: log2 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - - -Busy Controller Counts: -L1Cache-0:0 -Directory-0:0 -DMA-0:0 - -Busy Bank Count:0 - -L1TBE_usage: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] -L2TBE_usage: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] -StopTable_usage: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] -sequencer_requests_outstanding: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] -store_buffer_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] -unique_blocks_in_store_buffer: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - -All Non-Zero Cycle Demand Cache Accesses ----------------------------------------- -miss_latency: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] -miss_latency_L2Miss: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - -All Non-Zero Cycle SW Prefetch Requests ------------------------------------- -prefetch_latency: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] -prefetch_latency_L2Miss:[binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] -multicast_retries: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] -gets_mask_prediction_count: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] -getx_mask_prediction_count: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] -explicit_training_mask: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - -Request vs. RubySystem State Profile --------------------------------- - - -filter_action: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - -Message Delayed Cycles ----------------------- -Total_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] -Total_nonPF_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - virtual_network_0_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - virtual_network_1_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - virtual_network_2_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - virtual_network_3_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - virtual_network_4_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - virtual_network_5_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - -Resource Usage --------------- -page_size: 4096 -user_time: 0 -system_time: 0 -page_reclaims: 37503 -page_faults: 0 -swaps: 0 -block_inputs: 24 -block_outputs: 48 - -Network Stats -------------- - -switch_0_inlinks: 2 -switch_0_outlinks: 2 -links_utilized_percent_switch_0: 0 - links_utilized_percent_switch_0_link_0: 0 bw: 640000 base_latency: 1 - links_utilized_percent_switch_0_link_1: 0 bw: 160000 base_latency: 1 - - -switch_1_inlinks: 2 -switch_1_outlinks: 2 -links_utilized_percent_switch_1: 0 - links_utilized_percent_switch_1_link_0: 0 bw: 640000 base_latency: 1 - links_utilized_percent_switch_1_link_1: 0 bw: 160000 base_latency: 1 - - -switch_2_inlinks: 2 -switch_2_outlinks: 2 -links_utilized_percent_switch_2: 0 - links_utilized_percent_switch_2_link_0: 0 bw: 640000 base_latency: 1 - links_utilized_percent_switch_2_link_1: 0 bw: 160000 base_latency: 1 - - -switch_3_inlinks: 3 -switch_3_outlinks: 3 -links_utilized_percent_switch_3: 0 - links_utilized_percent_switch_3_link_0: 0 bw: 160000 base_latency: 1 - links_utilized_percent_switch_3_link_1: 0 bw: 160000 base_latency: 1 - links_utilized_percent_switch_3_link_2: 0 bw: 160000 base_latency: 1 - - - --- DMA --- - - Event Counts - -ReadRequest 0 -WriteRequest 0 -Data 0 -Ack 0 - - - Transitions - -READY ReadRequest 0 <-- -READY WriteRequest 0 <-- - -BUSY_RD Data 0 <-- - -BUSY_WR Ack 0 <-- - - --- Directory --- - - Event Counts - -GETX 0 -GETS 0 -PUTX 0 -PUTX_NotOwner 0 -DMA_READ 0 -DMA_WRITE 0 -Memory_Data 0 -Memory_Ack 0 - - - Transitions - -I GETX 0 <-- -I PUTX_NotOwner 0 <-- -I DMA_READ 0 <-- -I DMA_WRITE 0 <-- - -M GETX 0 <-- -M PUTX 0 <-- -M PUTX_NotOwner 0 <-- -M DMA_READ 0 <-- -M DMA_WRITE 0 <-- - -M_DRD GETX 0 <-- -M_DRD PUTX 0 <-- - -M_DWR GETX 0 <-- -M_DWR PUTX 0 <-- - -M_DWRI Memory_Ack 0 <-- - -IM GETX 0 <-- -IM GETS 0 <-- -IM PUTX 0 <-- -IM PUTX_NotOwner 0 <-- -IM DMA_READ 0 <-- -IM DMA_WRITE 0 <-- -IM Memory_Data 0 <-- - -MI GETX 0 <-- -MI GETS 0 <-- -MI PUTX 0 <-- -MI PUTX_NotOwner 0 <-- -MI DMA_READ 0 <-- -MI DMA_WRITE 0 <-- -MI Memory_Ack 0 <-- - -ID GETX 0 <-- -ID GETS 0 <-- -ID PUTX 0 <-- -ID PUTX_NotOwner 0 <-- -ID DMA_READ 0 <-- -ID DMA_WRITE 0 <-- -ID Memory_Data 0 <-- - -ID_W GETX 0 <-- -ID_W GETS 0 <-- -ID_W PUTX 0 <-- -ID_W PUTX_NotOwner 0 <-- -ID_W DMA_READ 0 <-- -ID_W DMA_WRITE 0 <-- -ID_W Memory_Ack 0 <-- - - --- L1Cache --- - - Event Counts - -Load 0 -Ifetch 0 -Store 0 -Data 0 -Fwd_GETX 0 -Inv 0 -Replacement 0 -Writeback_Ack 0 -Writeback_Nack 0 - - - Transitions - -I Load 0 <-- -I Ifetch 0 <-- -I Store 0 <-- -I Inv 0 <-- -I Replacement 0 <-- - -II Writeback_Nack 0 <-- - -M Load 0 <-- -M Ifetch 0 <-- -M Store 0 <-- -M Fwd_GETX 0 <-- -M Inv 0 <-- -M Replacement 0 <-- - -MI Fwd_GETX 0 <-- -MI Inv 0 <-- -MI Writeback_Ack 0 <-- - -IS Data 0 <-- - -IM Data 0 <-- - diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic-ruby/simerr b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic-ruby/simerr deleted file mode 100755 index 7c60b79b0..000000000 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic-ruby/simerr +++ /dev/null @@ -1,25 +0,0 @@ -["-r", "tests/configs/../../src/mem/ruby/config/MI_example-homogeneous.rb", "-p", "1", "-m", "1", "-s", "1024"] -print config: 1 -Creating new MessageBuffer for 0 0 -Creating new MessageBuffer for 0 1 -Creating new MessageBuffer for 0 2 -Creating new MessageBuffer for 0 3 -Creating new MessageBuffer for 0 4 -Creating new MessageBuffer for 0 5 -Creating new MessageBuffer for 1 0 -Creating new MessageBuffer for 1 1 -Creating new MessageBuffer for 1 2 -Creating new MessageBuffer for 1 3 -Creating new MessageBuffer for 1 4 -Creating new MessageBuffer for 1 5 -Creating new MessageBuffer for 2 0 -Creating new MessageBuffer for 2 1 -Creating new MessageBuffer for 2 2 -Creating new MessageBuffer for 2 3 -Creating new MessageBuffer for 2 4 -Creating new MessageBuffer for 2 5 -warn: Sockets disabled, not accepting gdb connections -For more information see: http://www.m5sim.org/warn/d946bea6 -warn: ignoring syscall sigprocmask(1, 18446744073709547831, ...) -For more information see: http://www.m5sim.org/warn/5c5b547f -hack: be nice to actually delete the event here diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic-ruby/simout b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic-ruby/simout deleted file mode 100755 index 966c37603..000000000 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic-ruby/simout +++ /dev/null @@ -1,18 +0,0 @@ -M5 Simulator System - -Copyright (c) 2001-2008 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled Jul 6 2009 11:03:45 -M5 revision d3635cac686a 6289 default ruby_refs.diff qtip tip -M5 started Jul 6 2009 11:11:05 -M5 executing on maize -command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-atomic-ruby -re tests/run.py build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-atomic-ruby -Global frequency set at 1000000000000 ticks per second - Debug: Adding to filter: 'q' (Queue) -info: Entering event queue @ 0. Starting simulation... -info: Increasing stack size by one page. -Hello world! -Exiting @ tick 1297500 because target called exit() diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic-ruby/stats.txt b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic-ruby/stats.txt deleted file mode 100644 index 73b2bbb37..000000000 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic-ruby/stats.txt +++ /dev/null @@ -1,50 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -host_inst_rate 10832 # Simulator instruction rate (inst/s) -host_mem_usage 1360528 # Number of bytes of host memory used -host_seconds 0.24 # Real time elapsed on the host -host_tick_rate 5450330 # Simulator tick rate (ticks/s) -sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 2577 # Number of instructions simulated -sim_seconds 0.000001 # Number of seconds simulated -sim_ticks 1297500 # Number of ticks simulated -system.cpu.dtb.data_accesses 717 # DTB accesses -system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_hits 709 # DTB hits -system.cpu.dtb.data_misses 8 # DTB misses -system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.fetch_acv 0 # ITB acv -system.cpu.dtb.fetch_hits 0 # ITB hits -system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.read_accesses 419 # DTB read accesses -system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_hits 415 # DTB read hits -system.cpu.dtb.read_misses 4 # DTB read misses -system.cpu.dtb.write_accesses 298 # DTB write accesses -system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_hits 294 # DTB write hits -system.cpu.dtb.write_misses 4 # DTB write misses -system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.itb.data_acv 0 # DTB access violations -system.cpu.itb.data_hits 0 # DTB hits -system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.fetch_accesses 2596 # ITB accesses -system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_hits 2585 # ITB hits -system.cpu.itb.fetch_misses 11 # ITB misses -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.read_acv 0 # DTB read access violations -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.write_acv 0 # DTB write access violations -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 2596 # number of cpu cycles simulated -system.cpu.num_insts 2577 # Number of instructions executed -system.cpu.num_refs 717 # Number of memory references -system.cpu.workload.PROG:num_syscalls 4 # Number of system calls - ----------- End Simulation Statistics ---------- |