diff options
Diffstat (limited to 'tests/quick/00.hello/ref/alpha/tru64/simple-atomic')
4 files changed, 63 insertions, 55 deletions
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.ini b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.ini index 43e841230..fad1e21b6 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.ini +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.ini @@ -9,6 +9,8 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem mem_mode=atomic +memories=system.physmem +num_work_ids=16 physmem=system.physmem work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 @@ -17,6 +19,7 @@ work_cpus_ckpt_count=0 work_end_ckpt_count=0 work_end_exit_count=0 work_item_id=-1 +system_port=system.membus.port[0] [system.cpu] type=AtomicSimpleCPU @@ -44,8 +47,8 @@ system=system tracer=system.cpu.tracer width=1 workload=system.cpu.workload -dcache_port=system.membus.port[2] -icache_port=system.membus.port[1] +dcache_port=system.membus.port[3] +icache_port=system.membus.port[2] [system.cpu.dtb] type=AlphaTLB @@ -85,7 +88,7 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port +port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port [system.physmem] type=PhysicalMemory @@ -95,5 +98,5 @@ latency_var=0 null=false range=0:134217727 zero=false -port=system.membus.port[0] +port=system.membus.port[1] diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/simerr b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/simerr index 67f69f09d..31ae36f2e 100755 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/simerr +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/simerr @@ -1,5 +1,3 @@ warn: Sockets disabled, not accepting gdb connections -For more information see: http://www.m5sim.org/warn/d946bea6 warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...) -For more information see: http://www.m5sim.org/warn/5c5b547f hack: be nice to actually delete the event here diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/simout b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/simout index 534040190..fdc12b275 100755 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/simout +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/simout @@ -1,14 +1,10 @@ -M5 Simulator System +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. -Copyright (c) 2001-2008 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled Apr 19 2011 11:52:53 -M5 started Apr 19 2011 12:00:19 -M5 executing on maize -command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-atomic +gem5 compiled Jan 23 2012 04:48:33 +gem5 started Jan 23 2012 04:59:27 +gem5 executing on zizzer +command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA_SE/tests/opt/quick/00.hello/alpha/tru64/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stats.txt b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stats.txt index 50ec4667d..23e50fd7f 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stats.txt +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stats.txt @@ -1,66 +1,77 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 343171 # Simulator instruction rate (inst/s) -host_mem_usage 194176 # Number of bytes of host memory used -host_seconds 0.01 # Real time elapsed on the host -host_tick_rate 169102503 # Simulator tick rate (ticks/s) -sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 2577 # Number of instructions simulated sim_seconds 0.000001 # Number of seconds simulated sim_ticks 1297500 # Number of ticks simulated -system.cpu.dtb.data_accesses 717 # DTB accesses -system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_hits 709 # DTB hits -system.cpu.dtb.data_misses 8 # DTB misses -system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.fetch_acv 0 # ITB acv +final_tick 1297500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 182014 # Simulator instruction rate (inst/s) +host_tick_rate 91451888 # Simulator tick rate (ticks/s) +host_mem_usage 197324 # Number of bytes of host memory used +host_seconds 0.01 # Real time elapsed on the host +sim_insts 2577 # Number of instructions simulated +system.physmem.bytes_read 13356 # Number of bytes read from this memory +system.physmem.bytes_inst_read 10340 # Number of instructions bytes read from this memory +system.physmem.bytes_written 2058 # Number of bytes written to this memory +system.physmem.num_reads 3000 # Number of read requests responded to by this memory +system.physmem.num_writes 294 # Number of write requests responded to by this memory +system.physmem.num_other 0 # Number of other requests responded to by this memory +system.physmem.bw_read 10293641618 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 7969171484 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write 1586127168 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total 11879768786 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.read_accesses 419 # DTB read accesses -system.cpu.dtb.read_acv 0 # DTB read access violations +system.cpu.dtb.fetch_acv 0 # ITB acv +system.cpu.dtb.fetch_accesses 0 # ITB accesses system.cpu.dtb.read_hits 415 # DTB read hits system.cpu.dtb.read_misses 4 # DTB read misses -system.cpu.dtb.write_accesses 298 # DTB write accesses -system.cpu.dtb.write_acv 0 # DTB write access violations +system.cpu.dtb.read_acv 0 # DTB read access violations +system.cpu.dtb.read_accesses 419 # DTB read accesses system.cpu.dtb.write_hits 294 # DTB write hits system.cpu.dtb.write_misses 4 # DTB write misses -system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.itb.data_acv 0 # DTB access violations -system.cpu.itb.data_hits 0 # DTB hits -system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.fetch_accesses 2596 # ITB accesses -system.cpu.itb.fetch_acv 0 # ITB acv +system.cpu.dtb.write_acv 0 # DTB write access violations +system.cpu.dtb.write_accesses 298 # DTB write accesses +system.cpu.dtb.data_hits 709 # DTB hits +system.cpu.dtb.data_misses 8 # DTB misses +system.cpu.dtb.data_acv 0 # DTB access violations +system.cpu.dtb.data_accesses 717 # DTB accesses system.cpu.itb.fetch_hits 2585 # ITB hits system.cpu.itb.fetch_misses 11 # ITB misses -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.read_acv 0 # DTB read access violations +system.cpu.itb.fetch_acv 0 # ITB acv +system.cpu.itb.fetch_accesses 2596 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.write_acv 0 # DTB write access violations +system.cpu.itb.read_acv 0 # DTB read access violations +system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.itb.write_acv 0 # DTB write access violations +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.data_hits 0 # DTB hits +system.cpu.itb.data_misses 0 # DTB misses +system.cpu.itb.data_acv 0 # DTB access violations +system.cpu.itb.data_accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 4 # Number of system calls system.cpu.numCycles 2596 # number of cpu cycles simulated -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.num_busy_cycles 2596 # Number of busy cycles -system.cpu.num_conditional_control_insts 238 # number of instructions that are conditional controls -system.cpu.num_fp_alu_accesses 6 # Number of float alu accesses -system.cpu.num_fp_insts 6 # number of float instructions -system.cpu.num_fp_register_reads 6 # number of times the floating registers were read -system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_func_calls 140 # number of times a function call or return occured -system.cpu.num_idle_cycles 0 # Number of idle cycles +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.num_insts 2577 # Number of instructions executed system.cpu.num_int_alu_accesses 2375 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 6 # Number of float alu accesses +system.cpu.num_func_calls 140 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 238 # number of instructions that are conditional controls system.cpu.num_int_insts 2375 # number of integer instructions +system.cpu.num_fp_insts 6 # number of float instructions system.cpu.num_int_register_reads 2998 # number of times the integer registers were read system.cpu.num_int_register_writes 1768 # number of times the integer registers were written -system.cpu.num_load_insts 419 # Number of load instructions +system.cpu.num_fp_register_reads 6 # number of times the floating registers were read +system.cpu.num_fp_register_writes 0 # number of times the floating registers were written system.cpu.num_mem_refs 717 # number of memory refs +system.cpu.num_load_insts 419 # Number of load instructions system.cpu.num_store_insts 298 # Number of store instructions -system.cpu.workload.num_syscalls 4 # Number of system calls +system.cpu.num_idle_cycles 0 # Number of idle cycles +system.cpu.num_busy_cycles 2596 # Number of busy cycles +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.idle_fraction 0 # Percentage of idle cycles ---------- End Simulation Statistics ---------- |