diff options
Diffstat (limited to 'tests/quick/00.hello/ref/alpha/tru64/simple-timing/stats.txt')
| -rw-r--r-- | tests/quick/00.hello/ref/alpha/tru64/simple-timing/stats.txt | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stats.txt b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stats.txt index aa9ef9160..a8a5eaa16 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 236465 # Simulator instruction rate (inst/s) -host_mem_usage 222144 # Number of bytes of host memory used +host_inst_rate 195987 # Simulator instruction rate (inst/s) +host_mem_usage 201848 # Number of bytes of host memory used host_seconds 0.01 # Real time elapsed on the host -host_tick_rate 1500776387 # Simulator tick rate (ticks/s) +host_tick_rate 1258278911 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 2577 # Number of instructions simulated sim_seconds 0.000017 # Number of seconds simulated @@ -50,8 +50,8 @@ system.cpu.dcache.demand_mshr_misses 82 # nu system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.011577 # Average percentage of cache occupancy system.cpu.dcache.occ_blocks::0 47.418751 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.011577 # Average percentage of cache occupancy system.cpu.dcache.overall_accesses 709 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 56000 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency @@ -121,8 +121,8 @@ system.cpu.icache.demand_mshr_misses 163 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.039064 # Average percentage of cache occupancy system.cpu.icache.occ_blocks::0 80.003762 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.039064 # Average percentage of cache occupancy system.cpu.icache.overall_accesses 2586 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency @@ -201,8 +201,8 @@ system.cpu.l2cache.demand_mshr_misses 245 # nu system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.003268 # Average percentage of cache occupancy system.cpu.l2cache.occ_blocks::0 107.101205 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.003268 # Average percentage of cache occupancy system.cpu.l2cache.overall_accesses 245 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency @@ -244,6 +244,6 @@ system.cpu.num_int_register_writes 1768 # nu system.cpu.num_load_insts 419 # Number of load instructions system.cpu.num_mem_refs 717 # number of memory refs system.cpu.num_store_insts 298 # Number of store instructions -system.cpu.workload.PROG:num_syscalls 4 # Number of system calls +system.cpu.workload.num_syscalls 4 # Number of system calls ---------- End Simulation Statistics ---------- |