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Diffstat (limited to 'tests/quick/00.hello/ref/alpha/tru64/simple-timing')
-rw-r--r--tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini2
-rwxr-xr-xtests/quick/00.hello/ref/alpha/tru64/simple-timing/simout14
-rw-r--r--tests/quick/00.hello/ref/alpha/tru64/simple-timing/stats.txt83
3 files changed, 46 insertions, 53 deletions
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini
index ab47c5c67..c142fa659 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini
@@ -157,7 +157,7 @@ egid=100
env=
errout=cerr
euid=100
-executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/alpha/tru64/hello
+executable=/dist/m5/regression/test-progs/hello/bin/alpha/tru64/hello
gid=100
input=cin
max_stack_size=67108864
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/simout b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/simout
index 2135491a6..6dd6e994b 100755
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/simout
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/simout
@@ -1,3 +1,5 @@
+Redirecting stdout to build/ALPHA_SE/tests/opt/quick/00.hello/alpha/tru64/simple-timing/simout
+Redirecting stderr to build/ALPHA_SE/tests/opt/quick/00.hello/alpha/tru64/simple-timing/simerr
M5 Simulator System
Copyright (c) 2001-2008
@@ -5,13 +7,13 @@ The Regents of The University of Michigan
All Rights Reserved
-M5 compiled Feb 24 2010 23:12:40
-M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip
-M5 started Feb 25 2010 03:11:06
-M5 executing on SC2B0619
-command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-timing
+M5 compiled Aug 26 2010 11:51:59
+M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix
+M5 started Aug 26 2010 11:52:05
+M5 executing on zizzer
+command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/opt/quick/00.hello/alpha/tru64/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
Hello world!
-Exiting @ tick 17374000 because target called exit()
+Exiting @ tick 16769000 because target called exit()
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stats.txt b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stats.txt
index 3c63125e0..f08ca087e 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stats.txt
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stats.txt
@@ -1,13 +1,13 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 400715 # Simulator instruction rate (inst/s)
-host_mem_usage 189300 # Number of bytes of host memory used
-host_seconds 0.01 # Real time elapsed on the host
-host_tick_rate 2582342449 # Simulator tick rate (ticks/s)
+host_inst_rate 97740 # Simulator instruction rate (inst/s)
+host_mem_usage 203308 # Number of bytes of host memory used
+host_seconds 0.03 # Real time elapsed on the host
+host_tick_rate 629585132 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 2577 # Number of instructions simulated
sim_seconds 0.000017 # Number of seconds simulated
-sim_ticks 17374000 # Number of ticks simulated
+sim_ticks 16769000 # Number of ticks simulated
system.cpu.dcache.ReadReq_accesses 415 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency
@@ -21,13 +21,13 @@ system.cpu.dcache.ReadReq_mshr_misses 55 # nu
system.cpu.dcache.WriteReq_accesses 294 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits 256 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 2128000 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate 0.129252 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses 38 # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_miss_latency 2014000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate 0.129252 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses 38 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_hits 267 # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency 1512000 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate 0.091837 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses 27 # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_miss_latency 1431000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate 0.091837 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_misses 27 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_refs 7.646341 # Average number of references to valid blocks.
@@ -39,37 +39,37 @@ system.cpu.dcache.cache_copies 0 # nu
system.cpu.dcache.demand_accesses 709 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 56000 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency
-system.cpu.dcache.demand_hits 616 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 5208000 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate 0.131171 # miss rate for demand accesses
-system.cpu.dcache.demand_misses 93 # number of demand (read+write) misses
+system.cpu.dcache.demand_hits 627 # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency 4592000 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate 0.115656 # miss rate for demand accesses
+system.cpu.dcache.demand_misses 82 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 4929000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate 0.131171 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses 93 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_miss_latency 4346000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate 0.115656 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses 82 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.occ_%::0 0.011615 # Average percentage of cache occupancy
-system.cpu.dcache.occ_blocks::0 47.575114 # Average occupied blocks per context
+system.cpu.dcache.occ_%::0 0.011577 # Average percentage of cache occupancy
+system.cpu.dcache.occ_blocks::0 47.418751 # Average occupied blocks per context
system.cpu.dcache.overall_accesses 709 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 56000 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits 616 # number of overall hits
-system.cpu.dcache.overall_miss_latency 5208000 # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate 0.131171 # miss rate for overall accesses
-system.cpu.dcache.overall_misses 93 # number of overall misses
+system.cpu.dcache.overall_hits 627 # number of overall hits
+system.cpu.dcache.overall_miss_latency 4592000 # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate 0.115656 # miss rate for overall accesses
+system.cpu.dcache.overall_misses 82 # number of overall misses
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 4929000 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate 0.131171 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses 93 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_miss_latency 4346000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate 0.115656 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses 82 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.replacements 0 # number of replacements
system.cpu.dcache.sampled_refs 82 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 47.575114 # Cycle average of tags in use
+system.cpu.dcache.tagsinuse 47.418751 # Cycle average of tags in use
system.cpu.dcache.total_refs 627 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 0 # number of writebacks
@@ -121,8 +121,8 @@ system.cpu.icache.demand_mshr_misses 163 # nu
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.occ_%::0 0.039276 # Average percentage of cache occupancy
-system.cpu.icache.occ_blocks::0 80.437325 # Average occupied blocks per context
+system.cpu.icache.occ_%::0 0.039064 # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::0 80.003762 # Average occupied blocks per context
system.cpu.icache.overall_accesses 2586 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency
@@ -140,7 +140,7 @@ system.cpu.icache.overall_mshr_uncacheable_misses 0
system.cpu.icache.replacements 0 # number of replacements
system.cpu.icache.sampled_refs 163 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 80.437325 # Cycle average of tags in use
+system.cpu.icache.tagsinuse 80.003762 # Cycle average of tags in use
system.cpu.icache.total_refs 2423 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
@@ -179,15 +179,6 @@ system.cpu.l2cache.ReadReq_misses 218 # nu
system.cpu.l2cache.ReadReq_mshr_miss_latency 8720000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 218 # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_accesses 11 # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_avg_miss_latency 52000 # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_miss_latency 572000 # number of UpgradeReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_misses 11 # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency 440000 # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_misses 11 # number of UpgradeReq MSHR misses
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.l2cache.avg_refs 0 # Average number of references to valid blocks.
@@ -210,8 +201,8 @@ system.cpu.l2cache.demand_mshr_misses 245 # nu
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.occ_%::0 0.003139 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_blocks::0 102.857609 # Average occupied blocks per context
+system.cpu.l2cache.occ_%::0 0.003268 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::0 107.101205 # Average occupied blocks per context
system.cpu.l2cache.overall_accesses 245 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
@@ -227,14 +218,14 @@ system.cpu.l2cache.overall_mshr_misses 245 # nu
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.replacements 0 # number of replacements
-system.cpu.l2cache.sampled_refs 207 # Sample count of references to valid blocks.
+system.cpu.l2cache.sampled_refs 218 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 102.857609 # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse 107.101205 # Cycle average of tags in use
system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 0 # number of writebacks
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.numCycles 34748 # number of cpu cycles simulated
+system.cpu.numCycles 33538 # number of cpu cycles simulated
system.cpu.num_insts 2577 # Number of instructions executed
system.cpu.num_refs 717 # Number of memory references
system.cpu.workload.PROG:num_syscalls 4 # Number of system calls