diff options
Diffstat (limited to 'tests/quick/00.hello/ref/alpha/tru64/simple-timing')
4 files changed, 57 insertions, 53 deletions
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini index 48fcc2b94..4f7ec60f2 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini @@ -152,6 +152,7 @@ type=Bus block_size=64 bus_id=0 clock=1000 +header_cycles=1 responder_set=false width=64 port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side @@ -169,6 +170,7 @@ euid=100 executable=/dist/m5/regression/test-progs/hello/bin/alpha/tru64/hello gid=100 input=cin +max_stack_size=67108864 output=cout pid=100 ppid=99 @@ -180,6 +182,7 @@ type=Bus block_size=64 bus_id=0 clock=1000 +header_cycles=1 responder_set=false width=64 port=system.physmem.port[0] system.cpu.l2cache.mem_side diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/m5stats.txt b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/m5stats.txt index 60bfb7de8..c93b1f19c 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/m5stats.txt +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/m5stats.txt @@ -1,31 +1,31 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 178240 # Simulator instruction rate (inst/s) -host_mem_usage 195696 # Number of bytes of host memory used -host_seconds 0.01 # Real time elapsed on the host -host_tick_rate 641473527 # Simulator tick rate (ticks/s) +host_inst_rate 99969 # Simulator instruction rate (inst/s) +host_mem_usage 193012 # Number of bytes of host memory used +host_seconds 0.03 # Real time elapsed on the host +host_tick_rate 383001655 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 2577 # Number of instructions simulated -sim_seconds 0.000009 # Number of seconds simulated -sim_ticks 9438000 # Number of ticks simulated +sim_seconds 0.000010 # Number of seconds simulated +sim_ticks 9950000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 415 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 25000 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 23000 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_miss_latency 27000 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 24000 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_hits 360 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 1375000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency 1485000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.132530 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 55 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 1265000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 1320000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.132530 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 55 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 294 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 25000 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 23000 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 27000 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 24000 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_hits 256 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 950000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 1026000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.129252 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses 38 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 874000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 912000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.129252 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 38 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked @@ -37,29 +37,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 709 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 25000 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 23000 # average overall mshr miss latency +system.cpu.dcache.demand_avg_miss_latency 27000 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 24000 # average overall mshr miss latency system.cpu.dcache.demand_hits 616 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 2325000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency 2511000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.131171 # miss rate for demand accesses system.cpu.dcache.demand_misses 93 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 2139000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 2232000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.131171 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 93 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.overall_accesses 709 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 25000 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 23000 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 27000 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 24000 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 616 # number of overall hits -system.cpu.dcache.overall_miss_latency 2325000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency 2511000 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.131171 # miss rate for overall accesses system.cpu.dcache.overall_misses 93 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 2139000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 2232000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.131171 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 93 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -76,7 +76,7 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.sampled_refs 82 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 48.838317 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 48.703722 # Cycle average of tags in use system.cpu.dcache.total_refs 627 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks @@ -93,13 +93,13 @@ system.cpu.dtb.write_acv 0 # DT system.cpu.dtb.write_hits 294 # DTB write hits system.cpu.dtb.write_misses 4 # DTB write misses system.cpu.icache.ReadReq_accesses 2586 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 25000 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 23000 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_miss_latency 27000 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 24000 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_hits 2423 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 4075000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency 4401000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.063032 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 163 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 3749000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 3912000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.063032 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 163 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked @@ -111,29 +111,29 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.demand_accesses 2586 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 25000 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 23000 # average overall mshr miss latency +system.cpu.icache.demand_avg_miss_latency 27000 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 24000 # average overall mshr miss latency system.cpu.icache.demand_hits 2423 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 4075000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency 4401000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.063032 # miss rate for demand accesses system.cpu.icache.demand_misses 163 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 3749000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 3912000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.063032 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 163 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.overall_accesses 2586 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 25000 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 23000 # average overall mshr miss latency +system.cpu.icache.overall_avg_miss_latency 27000 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 24000 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.icache.overall_hits 2423 # number of overall hits -system.cpu.icache.overall_miss_latency 4075000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency 4401000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.063032 # miss rate for overall accesses system.cpu.icache.overall_misses 163 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 3749000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 3912000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.063032 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 163 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -150,7 +150,7 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.icache.replacements 0 # number of replacements system.cpu.icache.sampled_refs 163 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 83.395749 # Cycle average of tags in use +system.cpu.icache.tagsinuse 83.077797 # Cycle average of tags in use system.cpu.icache.total_refs 2423 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks @@ -160,27 +160,27 @@ system.cpu.itb.acv 0 # IT system.cpu.itb.hits 2586 # ITB hits system.cpu.itb.misses 11 # ITB misses system.cpu.l2cache.ReadExReq_accesses 27 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 22000 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 23000 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 11000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 594000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 621000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_misses 27 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_mshr_miss_latency 297000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_misses 27 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadReq_accesses 218 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 22000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency 23000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 11000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_miss_latency 4796000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency 5014000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_misses 218 # number of ReadReq misses system.cpu.l2cache.ReadReq_mshr_miss_latency 2398000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 218 # number of ReadReq MSHR misses system.cpu.l2cache.UpgradeReq_accesses 11 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 22000 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency 23000 # average UpgradeReq miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 11000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 242000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency 253000 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_misses 11 # number of UpgradeReq misses system.cpu.l2cache.UpgradeReq_mshr_miss_latency 121000 # number of UpgradeReq MSHR miss cycles @@ -195,10 +195,10 @@ system.cpu.l2cache.blocked_cycles_no_mshrs 0 # system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 245 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 22000 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency 23000 # average overall miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency 11000 # average overall mshr miss latency system.cpu.l2cache.demand_hits 0 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 5390000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency 5635000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate 1 # miss rate for demand accesses system.cpu.l2cache.demand_misses 245 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits @@ -209,11 +209,11 @@ system.cpu.l2cache.fast_writes 0 # nu system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.overall_accesses 245 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 22000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 23000 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 11000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 0 # number of overall hits -system.cpu.l2cache.overall_miss_latency 5390000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency 5635000 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 1 # miss rate for overall accesses system.cpu.l2cache.overall_misses 245 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits @@ -234,12 +234,12 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.sampled_refs 207 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 106.559981 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 106.181819 # Cycle average of tags in use system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 18876 # number of cpu cycles simulated +system.cpu.numCycles 19900 # number of cpu cycles simulated system.cpu.num_insts 2577 # Number of instructions executed system.cpu.num_refs 717 # Number of memory references system.cpu.workload.PROG:num_syscalls 4 # Number of system calls diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stderr b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stderr index 9f8e7c2e9..f26dcb93f 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stderr +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stderr @@ -1,3 +1,4 @@ +0: system.remote_gdb.listener: listening for remote gdb on port 7003 warn: Entering event queue @ 0. Starting simulation... warn: Increasing stack size by one page. warn: ignoring syscall sigprocmask(1, 18446744073709547831, ...) diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stdout b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stdout index 8d08b94be..c25792a5f 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stdout +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stdout @@ -1,14 +1,14 @@ Hello world! M5 Simulator System -Copyright (c) 2001-2006 +Copyright (c) 2001-2008 The Regents of The University of Michigan All Rights Reserved -M5 compiled Aug 14 2007 17:58:14 -M5 started Tue Aug 14 17:59:08 2007 -M5 executing on nacho +M5 compiled Feb 24 2008 12:58:20 +M5 started Sun Feb 24 12:58:25 2008 +M5 executing on tater command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-timing tests/run.py quick/00.hello/alpha/tru64/simple-timing Global frequency set at 1000000000000 ticks per second -Exiting @ tick 9438000 because target called exit() +Exiting @ tick 9950000 because target called exit() |