diff options
Diffstat (limited to 'tests/quick/00.hello/ref/alpha/tru64')
29 files changed, 783 insertions, 577 deletions
diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini index 2ddfc3365..2b9fce4f2 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini @@ -1,13 +1,22 @@ [root] type=Root children=system -dummy=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem mem_mode=atomic physmem=system.physmem +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 [system.cpu] type=DerivO3CPU @@ -484,7 +493,7 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/regression/test-progs/hello/bin/alpha/tru64/hello +executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/alpha/tru64/hello gid=100 input=cin max_stack_size=67108864 diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/simout b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/simout index fe2af5e09..e774ba11e 100755 --- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/simout +++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jan 17 2011 16:24:53 -M5 revision f72d94f8c275 7839 default qtip tip outgoing.patch qbase -M5 started Jan 17 2011 16:48:46 -M5 executing on zizzer +M5 compiled Feb 6 2011 20:42:22 +M5 revision b885adc82ab4+ 7924+ default tip qtip brad/regress_updates +M5 started Feb 6 2011 20:42:36 +M5 executing on SC2B0617 command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt index 2363f1511..311a86bd4 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 61982 # Simulator instruction rate (inst/s) -host_mem_usage 202420 # Number of bytes of host memory used -host_seconds 0.04 # Real time elapsed on the host -host_tick_rate 188319059 # Simulator tick rate (ticks/s) +host_inst_rate 78818 # Simulator instruction rate (inst/s) +host_mem_usage 204536 # Number of bytes of host memory used +host_seconds 0.03 # Real time elapsed on the host +host_tick_rate 238897798 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 2387 # Number of instructions simulated sim_seconds 0.000007 # Number of seconds simulated @@ -37,6 +37,9 @@ system.cpu.commit.COM:committed_per_cycle::min_value 0 system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::total 6328 # Number of insts commited each cycle system.cpu.commit.COM:count 2576 # Number of instructions committed +system.cpu.commit.COM:fp_insts 6 # Number of committed floating point instructions. +system.cpu.commit.COM:function_calls 71 # Number of function calls committed. +system.cpu.commit.COM:int_insts 2367 # Number of committed integer instructions. system.cpu.commit.COM:loads 415 # Number of loads committed system.cpu.commit.COM:membars 0 # Number of memory barriers committed system.cpu.commit.COM:refs 709 # Number of memory references committed @@ -169,6 +172,7 @@ system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Nu system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::total 6701 # Number of instructions fetched each cycle (Total) +system.cpu.fp_regfile_reads 6 # number of floating regfile reads system.cpu.icache.ReadReq_accesses 782 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_avg_miss_latency 36074.786325 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 35303.867403 # average ReadReq mshr miss latency @@ -268,6 +272,8 @@ system.cpu.iew.lsq.thread.0.squashedStores 141 # system.cpu.iew.memOrderViolationEvents 13 # Number of memory order violations system.cpu.iew.predictedNotTakenIncorrect 109 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedTakenIncorrect 55 # Number of branches that were predicted taken incorrectly +system.cpu.int_regfile_reads 4283 # number of integer regfile reads +system.cpu.int_regfile_writes 2601 # number of integer regfile writes system.cpu.ipc 0.163482 # IPC: Instructions Per Cycle system.cpu.ipc_total 0.163482 # IPC: Total IPC of All Threads system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued @@ -359,6 +365,14 @@ system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::total 6701 # Number of insts issued each cycle system.cpu.iq.ISSUE:rate 0.248682 # Inst issue rate +system.cpu.iq.fp_alu_accesses 7 # Number of floating point alu accesses +system.cpu.iq.fp_inst_queue_reads 13 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_wakeup_accesses 6 # Number of floating instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_writes 6 # Number of floating instruction queue writes +system.cpu.iq.int_alu_accesses 3659 # Number of integer alu accesses +system.cpu.iq.int_inst_queue_reads 14008 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_wakeup_accesses 3396 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_writes 5997 # Number of integer instruction queue writes system.cpu.iq.iqInstsAdded 4276 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqInstsIssued 3631 # Number of instructions issued system.cpu.iq.iqNonSpecInstsAdded 6 # Number of non-speculative instructions added to the IQ @@ -449,7 +463,11 @@ system.cpu.memDep0.conflictingLoads 16 # Nu system.cpu.memDep0.conflictingStores 16 # Number of conflicting stores. system.cpu.memDep0.insertedLoads 793 # Number of loads inserted to the mem dependence unit. system.cpu.memDep0.insertedStores 435 # Number of stores inserted to the mem dependence unit. +system.cpu.misc_regfile_reads 1 # number of misc regfile reads +system.cpu.misc_regfile_writes 1 # number of misc regfile writes system.cpu.numCycles 14601 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.rename.RENAME:BlockCycles 63 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 1768 # Number of HB maps that are committed system.cpu.rename.RENAME:IQFullEvents 3 # Number of times rename has blocked due to IQ full @@ -462,10 +480,14 @@ system.cpu.rename.RENAME:RunCycles 901 # Nu system.cpu.rename.RENAME:SquashCycles 373 # Number of cycles rename is squashing system.cpu.rename.RENAME:UnblockCycles 15 # Number of cycles rename is unblocking system.cpu.rename.RENAME:UndoneMaps 1713 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:fp_rename_lookups 12 # Number of floating rename lookups +system.cpu.rename.RENAME:int_rename_lookups 5502 # Number of integer rename lookups system.cpu.rename.RENAME:serializeStallCycles 146 # count of cycles rename stalled for serializing inst system.cpu.rename.RENAME:serializingInsts 8 # count of serializing insts renamed system.cpu.rename.RENAME:skidInsts 78 # count of insts added to the skid buffer system.cpu.rename.RENAME:tempSerializingInsts 6 # count of temporary serializing insts renamed +system.cpu.rob.rob_reads 10620 # The number of ROB reads +system.cpu.rob.rob_writes 9524 # The number of ROB writes system.cpu.timesIdled 152 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 4 # Number of system calls diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.ini b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.ini index ac9cc91a1..6bac111b6 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.ini +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.ini @@ -1,13 +1,22 @@ [root] type=Root children=system -dummy=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem mem_mode=atomic physmem=system.physmem +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 [system.cpu] type=AtomicSimpleCPU @@ -57,7 +66,7 @@ egid=100 env= errout=cerr euid=100 -executable=/chips/pd/randd/dist/test-progs/hello/bin/alpha/tru64/hello +executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/alpha/tru64/hello gid=100 input=cin max_stack_size=67108864 diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/simout b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/simout index 532375cf9..7d6e98afc 100755 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/simout +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/simout @@ -1,5 +1,3 @@ -Redirecting stdout to build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-atomic/simout -Redirecting stderr to build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-atomic/simerr M5 Simulator System Copyright (c) 2001-2008 @@ -7,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Nov 2 2010 21:30:55 -M5 revision 0af3760102ec+ 7713+ default qtip ext/alpha_prefetch.patch tip -M5 started Nov 2 2010 21:32:40 -M5 executing on aus-bc2-b15 +M5 compiled Feb 6 2011 20:42:22 +M5 revision b885adc82ab4+ 7924+ default tip qtip brad/regress_updates +M5 started Feb 6 2011 20:42:47 +M5 executing on SC2B0617 command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stats.txt b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stats.txt index d0028e484..3874b2441 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stats.txt +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 759729 # Simulator instruction rate (inst/s) -host_mem_usage 228516 # Number of bytes of host memory used +host_inst_rate 849934 # Simulator instruction rate (inst/s) +host_mem_usage 196124 # Number of bytes of host memory used host_seconds 0.00 # Real time elapsed on the host -host_tick_rate 362937063 # Simulator tick rate (ticks/s) +host_tick_rate 396667686 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 2577 # Number of instructions simulated sim_seconds 0.000001 # Number of seconds simulated @@ -43,8 +43,24 @@ system.cpu.itb.write_hits 0 # DT system.cpu.itb.write_misses 0 # DTB write misses system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.numCycles 2596 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.num_busy_cycles 2596 # Number of busy cycles +system.cpu.num_conditional_control_insts 238 # number of instructions that are conditional controls +system.cpu.num_fp_alu_accesses 6 # Number of float alu accesses +system.cpu.num_fp_insts 6 # number of float instructions +system.cpu.num_fp_register_reads 6 # number of times the floating registers were read +system.cpu.num_fp_register_writes 0 # number of times the floating registers were written +system.cpu.num_func_calls 140 # number of times a function call or return occured +system.cpu.num_idle_cycles 0 # Number of idle cycles system.cpu.num_insts 2577 # Number of instructions executed -system.cpu.num_refs 717 # Number of memory references +system.cpu.num_int_alu_accesses 2375 # Number of integer alu accesses +system.cpu.num_int_insts 2375 # number of integer instructions +system.cpu.num_int_register_reads 2998 # number of times the integer registers were read +system.cpu.num_int_register_writes 1768 # number of times the integer registers were written +system.cpu.num_load_insts 419 # Number of load instructions +system.cpu.num_mem_refs 717 # number of memory refs +system.cpu.num_store_insts 298 # Number of store instructions system.cpu.workload.PROG:num_syscalls 4 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/config.ini b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/config.ini index a4ed53868..b7bfb0aae 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/config.ini +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/config.ini @@ -1,13 +1,22 @@ [root] type=Root children=system -dummy=0 +time_sync_enable=false +time_sync_period=100000000 +time_sync_spin_threshold=100000 [system] type=System children=cpu dir_cntrl0 l1_cntrl0 l2_cntrl0 physmem ruby mem_mode=timing physmem=system.physmem +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 [system.cpu] type=TimingSimpleCPU @@ -54,7 +63,7 @@ egid=100 env= errout=cerr euid=100 -executable=tests/test-progs/hello/bin/alpha/tru64/hello +executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/alpha/tru64/hello gid=100 input=cin max_stack_size=67108864 @@ -186,6 +195,7 @@ tracer=system.ruby.tracer [system.ruby.cpu_ruby_ports] type=RubySequencer +access_phys_mem=true dcache=system.l1_cntrl0.L1DcacheMemory deadlock_threshold=500000 icache=system.l1_cntrl0.L1IcacheMemory diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/ruby.stats b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/ruby.stats index 4efa8de79..027313a2c 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/ruby.stats +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/ruby.stats @@ -34,27 +34,27 @@ periodic_stats_period: 1000000 ================ End RubySystem Configuration Print ================ -Real time: Jan/13/2011 22:36:30 +Real time: Feb/06/2011 20:42:15 Profiler Stats -------------- -Elapsed_time_in_seconds: 2 -Elapsed_time_in_minutes: 0.0333333 -Elapsed_time_in_hours: 0.000555556 -Elapsed_time_in_days: 2.31481e-05 +Elapsed_time_in_seconds: 0 +Elapsed_time_in_minutes: 0 +Elapsed_time_in_hours: 0 +Elapsed_time_in_days: 0 -Virtual_time_in_seconds: 0.79 -Virtual_time_in_minutes: 0.0131667 -Virtual_time_in_hours: 0.000219444 -Virtual_time_in_days: 9.14352e-06 +Virtual_time_in_seconds: 0.37 +Virtual_time_in_minutes: 0.00616667 +Virtual_time_in_hours: 0.000102778 +Virtual_time_in_days: 4.28241e-06 Ruby_current_time: 103637 Ruby_start_time: 0 Ruby_cycles: 103637 -mbytes_resident: 20.9219 -mbytes_total: 156.062 -resident_ratio: 0.134111 +mbytes_resident: 35.7305 +mbytes_total: 209.473 +resident_ratio: 0.170611 ruby_cycles_executed: [ 103638 ] @@ -119,7 +119,7 @@ Resource Usage page_size: 4096 user_time: 0 system_time: 0 -page_reclaims: 6028 +page_reclaims: 10361 page_faults: 0 swaps: 0 block_inputs: 0 diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/simout b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/simout index 5c8b35b72..be2d10449 100755 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/simout +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jan 13 2011 22:36:25 -M5 revision 81b32f1a8f29 7836 default MESI_CMP_update_ref.patch qtip tip -M5 started Jan 13 2011 22:36:28 -M5 executing on scamorza.cs.wisc.edu +M5 compiled Feb 6 2011 15:12:58 +M5 revision b885adc82ab4+ 7924+ default tip qtip brad/regress_updates +M5 started Feb 6 2011 20:42:15 +M5 executing on SC2B0617 command line: build/ALPHA_SE_MESI_CMP_directory/m5.fast -d build/ALPHA_SE_MESI_CMP_directory/tests/fast/quick/00.hello/alpha/tru64/simple-timing-ruby-MESI_CMP_directory -re tests/run.py build/ALPHA_SE_MESI_CMP_directory/tests/fast/quick/00.hello/alpha/tru64/simple-timing-ruby-MESI_CMP_directory Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/stats.txt b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/stats.txt index 5b40ee1fb..25c8ba580 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/stats.txt +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 2534 # Simulator instruction rate (inst/s) -host_mem_usage 159812 # Number of bytes of host memory used -host_seconds 1.02 # Real time elapsed on the host -host_tick_rate 101843 # Simulator tick rate (ticks/s) +host_inst_rate 29262 # Simulator instruction rate (inst/s) +host_mem_usage 214504 # Number of bytes of host memory used +host_seconds 0.09 # Real time elapsed on the host +host_tick_rate 1174597 # Simulator tick rate (ticks/s) sim_freq 1000000000 # Frequency of simulated ticks sim_insts 2577 # Number of instructions simulated sim_seconds 0.000104 # Number of seconds simulated @@ -43,8 +43,24 @@ system.cpu.itb.write_hits 0 # DT system.cpu.itb.write_misses 0 # DTB write misses system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.numCycles 103637 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.num_busy_cycles 103637 # Number of busy cycles +system.cpu.num_conditional_control_insts 238 # number of instructions that are conditional controls +system.cpu.num_fp_alu_accesses 6 # Number of float alu accesses +system.cpu.num_fp_insts 6 # number of float instructions +system.cpu.num_fp_register_reads 6 # number of times the floating registers were read +system.cpu.num_fp_register_writes 0 # number of times the floating registers were written +system.cpu.num_func_calls 140 # number of times a function call or return occured +system.cpu.num_idle_cycles 0 # Number of idle cycles system.cpu.num_insts 2577 # Number of instructions executed -system.cpu.num_refs 717 # Number of memory references +system.cpu.num_int_alu_accesses 2375 # Number of integer alu accesses +system.cpu.num_int_insts 2375 # number of integer instructions +system.cpu.num_int_register_reads 2998 # number of times the integer registers were read +system.cpu.num_int_register_writes 1768 # number of times the integer registers were written +system.cpu.num_load_insts 419 # Number of load instructions +system.cpu.num_mem_refs 717 # number of memory refs +system.cpu.num_store_insts 298 # Number of store instructions system.cpu.workload.PROG:num_syscalls 4 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/config.ini b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/config.ini index 59f975e1e..dae855509 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/config.ini +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/config.ini @@ -1,13 +1,22 @@ [root] type=Root children=system -dummy=0 +time_sync_enable=false +time_sync_period=100000000 +time_sync_spin_threshold=100000 [system] type=System children=cpu dir_cntrl0 l1_cntrl0 l2_cntrl0 physmem ruby mem_mode=timing physmem=system.physmem +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 [system.cpu] type=TimingSimpleCPU @@ -32,8 +41,8 @@ progress_interval=0 system=system tracer=system.cpu.tracer workload=system.cpu.workload -dcache_port=system.l1_cntrl0.sequencer.port[1] -icache_port=system.l1_cntrl0.sequencer.port[0] +dcache_port=system.ruby.cpu_ruby_ports.port[1] +icache_port=system.ruby.cpu_ruby_ports.port[0] [system.cpu.dtb] type=AlphaTLB @@ -54,7 +63,7 @@ egid=100 env= errout=cerr euid=100 -executable=tests/test-progs/hello/bin/alpha/tru64/hello +executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/alpha/tru64/hello gid=100 input=cin max_stack_size=67108864 @@ -108,32 +117,19 @@ version=0 [system.l1_cntrl0] type=L1Cache_Controller -children=sequencer -L1DcacheMemory=system.l1_cntrl0.sequencer.dcache -L1IcacheMemory=system.l1_cntrl0.sequencer.icache +children=L1DcacheMemory L1IcacheMemory +L1DcacheMemory=system.l1_cntrl0.L1DcacheMemory +L1IcacheMemory=system.l1_cntrl0.L1IcacheMemory buffer_size=0 l2_select_num_bits=0 number_of_TBEs=256 recycle_latency=10 request_latency=2 -sequencer=system.l1_cntrl0.sequencer +sequencer=system.ruby.cpu_ruby_ports transitions_per_cycle=32 version=0 -[system.l1_cntrl0.sequencer] -type=RubySequencer -children=dcache icache -dcache=system.l1_cntrl0.sequencer.dcache -deadlock_threshold=500000 -icache=system.l1_cntrl0.sequencer.icache -max_outstanding_requests=16 -physmem=system.physmem -using_ruby_tester=false -version=0 -physMemPort=system.physmem.port[0] -port=system.cpu.icache_port system.cpu.dcache_port - -[system.l1_cntrl0.sequencer.dcache] +[system.l1_cntrl0.L1DcacheMemory] type=RubyCache assoc=2 latency=3 @@ -141,7 +137,7 @@ replacement_policy=PSEUDO_LRU size=256 start_index_bit=6 -[system.l1_cntrl0.sequencer.icache] +[system.l1_cntrl0.L1IcacheMemory] type=RubyCache assoc=2 latency=3 @@ -177,14 +173,13 @@ latency_var=0 null=false range=0:134217727 zero=false -port=system.l1_cntrl0.sequencer.physMemPort +port=system.ruby.cpu_ruby_ports.physMemPort [system.ruby] type=RubySystem -children=debug network profiler tracer +children=cpu_ruby_ports network profiler tracer block_size_bytes=64 clock=1 -debug=system.ruby.debug mem_size=134217728 network=system.ruby.network no_mem_vec=false @@ -194,13 +189,18 @@ randomization=false stats_filename=ruby.stats tracer=system.ruby.tracer -[system.ruby.debug] -type=RubyDebug -filter_string=none -output_filename=none -protocol_trace=false -start_time=1 -verbosity_string=none +[system.ruby.cpu_ruby_ports] +type=RubySequencer +access_phys_mem=true +dcache=system.l1_cntrl0.L1DcacheMemory +deadlock_threshold=500000 +icache=system.l1_cntrl0.L1IcacheMemory +max_outstanding_requests=16 +physmem=system.physmem +using_ruby_tester=false +version=0 +physMemPort=system.physmem.port[0] +port=system.cpu.icache_port system.cpu.dcache_port [system.ruby.network] type=SimpleNetwork @@ -216,9 +216,9 @@ topology=system.ruby.network.topology [system.ruby.network.topology] type=Topology children=ext_links0 ext_links1 ext_links2 int_links0 int_links1 int_links2 +description=Crossbar ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1 system.ruby.network.topology.ext_links2 int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1 system.ruby.network.topology.int_links2 -name=Crossbar num_int_nodes=4 print_config=false diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/ruby.stats b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/ruby.stats index 86aa94fb6..494e34e3f 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/ruby.stats +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/ruby.stats @@ -13,7 +13,7 @@ RubySystem config: Network Configuration --------------------- network: SIMPLE_NETWORK -topology: Crossbar +topology: virtual_net_0: active, unordered virtual_net_1: active, unordered @@ -34,7 +34,7 @@ periodic_stats_period: 1000000 ================ End RubySystem Configuration Print ================ -Real time: Aug/05/2010 10:37:10 +Real time: Feb/06/2011 20:43:54 Profiler Stats -------------- @@ -43,18 +43,18 @@ Elapsed_time_in_minutes: 0 Elapsed_time_in_hours: 0 Elapsed_time_in_days: 0 -Virtual_time_in_seconds: 0.41 -Virtual_time_in_minutes: 0.00683333 -Virtual_time_in_hours: 0.000113889 -Virtual_time_in_days: 4.74537e-06 +Virtual_time_in_seconds: 0.34 +Virtual_time_in_minutes: 0.00566667 +Virtual_time_in_hours: 9.44444e-05 +Virtual_time_in_days: 3.93519e-06 Ruby_current_time: 85988 Ruby_start_time: 0 Ruby_cycles: 85988 -mbytes_resident: 33.6484 -mbytes_total: 33.6562 -resident_ratio: 1 +mbytes_resident: 35.8281 +mbytes_total: 209.613 +resident_ratio: 0.170962 ruby_cycles_executed: [ 85989 ] @@ -119,8 +119,8 @@ Resource Usage page_size: 4096 user_time: 0 system_time: 0 -page_reclaims: 7386 -page_faults: 2090 +page_reclaims: 10369 +page_faults: 0 swaps: 0 block_inputs: 0 block_outputs: 0 @@ -201,20 +201,20 @@ links_utilized_percent_switch_3: 0.342645 outgoing_messages_switch_3_link_2_Writeback_Control: 745 5960 [ 0 411 334 0 0 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_3_link_2_Unblock_Control: 427 3416 [ 0 0 427 0 0 0 0 0 0 0 ] base_latency: 1 -Cache Stats: system.l1_cntrl0.sequencer.icache - system.l1_cntrl0.sequencer.icache_total_misses: 0 - system.l1_cntrl0.sequencer.icache_total_demand_misses: 0 - system.l1_cntrl0.sequencer.icache_total_prefetches: 0 - system.l1_cntrl0.sequencer.icache_total_sw_prefetches: 0 - system.l1_cntrl0.sequencer.icache_total_hw_prefetches: 0 +Cache Stats: system.l1_cntrl0.L1IcacheMemory + system.l1_cntrl0.L1IcacheMemory_total_misses: 0 + system.l1_cntrl0.L1IcacheMemory_total_demand_misses: 0 + system.l1_cntrl0.L1IcacheMemory_total_prefetches: 0 + system.l1_cntrl0.L1IcacheMemory_total_sw_prefetches: 0 + system.l1_cntrl0.L1IcacheMemory_total_hw_prefetches: 0 -Cache Stats: system.l1_cntrl0.sequencer.dcache - system.l1_cntrl0.sequencer.dcache_total_misses: 0 - system.l1_cntrl0.sequencer.dcache_total_demand_misses: 0 - system.l1_cntrl0.sequencer.dcache_total_prefetches: 0 - system.l1_cntrl0.sequencer.dcache_total_sw_prefetches: 0 - system.l1_cntrl0.sequencer.dcache_total_hw_prefetches: 0 +Cache Stats: system.l1_cntrl0.L1DcacheMemory + system.l1_cntrl0.L1DcacheMemory_total_misses: 0 + system.l1_cntrl0.L1DcacheMemory_total_demand_misses: 0 + system.l1_cntrl0.L1DcacheMemory_total_prefetches: 0 + system.l1_cntrl0.L1DcacheMemory_total_sw_prefetches: 0 + system.l1_cntrl0.L1DcacheMemory_total_hw_prefetches: 0 --- L1Cache --- diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simout b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simout index c8e6b0646..b4ee3d335 100755 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simout +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Aug 5 2010 10:34:54 -M5 revision 1cd2a169499f+ 7535+ default brad/hammer_merge_gets qtip tip -M5 started Aug 5 2010 10:37:10 -M5 executing on svvint09 +M5 compiled Feb 6 2011 20:43:45 +M5 revision b885adc82ab4+ 7924+ default tip qtip brad/regress_updates +M5 started Feb 6 2011 20:43:54 +M5 executing on SC2B0617 command line: build/ALPHA_SE_MOESI_CMP_directory/m5.fast -d build/ALPHA_SE_MOESI_CMP_directory/tests/fast/quick/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory -re tests/run.py build/ALPHA_SE_MOESI_CMP_directory/tests/fast/quick/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt index bc9801bf7..9e38951ad 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 19822 # Simulator instruction rate (inst/s) -host_mem_usage 211548 # Number of bytes of host memory used -host_seconds 0.13 # Real time elapsed on the host -host_tick_rate 661411 # Simulator tick rate (ticks/s) +host_inst_rate 22051 # Simulator instruction rate (inst/s) +host_mem_usage 214648 # Number of bytes of host memory used +host_seconds 0.12 # Real time elapsed on the host +host_tick_rate 734783 # Simulator tick rate (ticks/s) sim_freq 1000000000 # Frequency of simulated ticks sim_insts 2577 # Number of instructions simulated sim_seconds 0.000086 # Number of seconds simulated @@ -43,8 +43,24 @@ system.cpu.itb.write_hits 0 # DT system.cpu.itb.write_misses 0 # DTB write misses system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.numCycles 85988 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.num_busy_cycles 85988 # Number of busy cycles +system.cpu.num_conditional_control_insts 238 # number of instructions that are conditional controls +system.cpu.num_fp_alu_accesses 6 # Number of float alu accesses +system.cpu.num_fp_insts 6 # number of float instructions +system.cpu.num_fp_register_reads 6 # number of times the floating registers were read +system.cpu.num_fp_register_writes 0 # number of times the floating registers were written +system.cpu.num_func_calls 140 # number of times a function call or return occured +system.cpu.num_idle_cycles 0 # Number of idle cycles system.cpu.num_insts 2577 # Number of instructions executed -system.cpu.num_refs 717 # Number of memory references +system.cpu.num_int_alu_accesses 2375 # Number of integer alu accesses +system.cpu.num_int_insts 2375 # number of integer instructions +system.cpu.num_int_register_reads 2998 # number of times the integer registers were read +system.cpu.num_int_register_writes 1768 # number of times the integer registers were written +system.cpu.num_load_insts 419 # Number of load instructions +system.cpu.num_mem_refs 717 # number of memory refs +system.cpu.num_store_insts 298 # Number of store instructions system.cpu.workload.PROG:num_syscalls 4 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/config.ini b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/config.ini index 1971d2a44..537819260 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/config.ini +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/config.ini @@ -1,13 +1,22 @@ [root] type=Root children=system -dummy=0 +time_sync_enable=false +time_sync_period=100000000 +time_sync_spin_threshold=100000 [system] type=System children=cpu dir_cntrl0 l1_cntrl0 l2_cntrl0 physmem ruby mem_mode=timing physmem=system.physmem +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 [system.cpu] type=TimingSimpleCPU @@ -32,8 +41,8 @@ progress_interval=0 system=system tracer=system.cpu.tracer workload=system.cpu.workload -dcache_port=system.l1_cntrl0.sequencer.port[1] -icache_port=system.l1_cntrl0.sequencer.port[0] +dcache_port=system.ruby.cpu_ruby_ports.port[1] +icache_port=system.ruby.cpu_ruby_ports.port[0] [system.cpu.dtb] type=AlphaTLB @@ -54,7 +63,7 @@ egid=100 env= errout=cerr euid=100 -executable=tests/test-progs/hello/bin/alpha/tru64/hello +executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/alpha/tru64/hello gid=100 input=cin max_stack_size=67108864 @@ -111,9 +120,9 @@ version=0 [system.l1_cntrl0] type=L1Cache_Controller -children=sequencer -L1DcacheMemory=system.l1_cntrl0.sequencer.dcache -L1IcacheMemory=system.l1_cntrl0.sequencer.icache +children=L1DcacheMemory L1IcacheMemory +L1DcacheMemory=system.l1_cntrl0.L1DcacheMemory +L1IcacheMemory=system.l1_cntrl0.L1IcacheMemory N_tokens=2 buffer_size=0 dynamic_timeout_enabled=true @@ -125,24 +134,11 @@ no_mig_atomic=true number_of_TBEs=256 recycle_latency=10 retry_threshold=1 -sequencer=system.l1_cntrl0.sequencer +sequencer=system.ruby.cpu_ruby_ports transitions_per_cycle=32 version=0 -[system.l1_cntrl0.sequencer] -type=RubySequencer -children=dcache icache -dcache=system.l1_cntrl0.sequencer.dcache -deadlock_threshold=500000 -icache=system.l1_cntrl0.sequencer.icache -max_outstanding_requests=16 -physmem=system.physmem -using_ruby_tester=false -version=0 -physMemPort=system.physmem.port[0] -port=system.cpu.icache_port system.cpu.dcache_port - -[system.l1_cntrl0.sequencer.dcache] +[system.l1_cntrl0.L1DcacheMemory] type=RubyCache assoc=2 latency=2 @@ -150,7 +146,7 @@ replacement_policy=PSEUDO_LRU size=256 start_index_bit=6 -[system.l1_cntrl0.sequencer.icache] +[system.l1_cntrl0.L1IcacheMemory] type=RubyCache assoc=2 latency=2 @@ -188,14 +184,13 @@ latency_var=0 null=false range=0:134217727 zero=false -port=system.l1_cntrl0.sequencer.physMemPort +port=system.ruby.cpu_ruby_ports.physMemPort [system.ruby] type=RubySystem -children=debug network profiler tracer +children=cpu_ruby_ports network profiler tracer block_size_bytes=64 clock=1 -debug=system.ruby.debug mem_size=134217728 network=system.ruby.network no_mem_vec=false @@ -205,13 +200,18 @@ randomization=false stats_filename=ruby.stats tracer=system.ruby.tracer -[system.ruby.debug] -type=RubyDebug -filter_string=none -output_filename=none -protocol_trace=false -start_time=1 -verbosity_string=none +[system.ruby.cpu_ruby_ports] +type=RubySequencer +access_phys_mem=true +dcache=system.l1_cntrl0.L1DcacheMemory +deadlock_threshold=500000 +icache=system.l1_cntrl0.L1IcacheMemory +max_outstanding_requests=16 +physmem=system.physmem +using_ruby_tester=false +version=0 +physMemPort=system.physmem.port[0] +port=system.cpu.icache_port system.cpu.dcache_port [system.ruby.network] type=SimpleNetwork @@ -227,9 +227,9 @@ topology=system.ruby.network.topology [system.ruby.network.topology] type=Topology children=ext_links0 ext_links1 ext_links2 int_links0 int_links1 int_links2 +description=Crossbar ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1 system.ruby.network.topology.ext_links2 int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1 system.ruby.network.topology.int_links2 -name=Crossbar num_int_nodes=4 print_config=false diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/ruby.stats b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/ruby.stats index dbdcc6601..9d8b157dc 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/ruby.stats +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/ruby.stats @@ -13,7 +13,7 @@ RubySystem config: Network Configuration --------------------- network: SIMPLE_NETWORK -topology: Crossbar +topology: virtual_net_0: active, ordered virtual_net_1: active, unordered @@ -34,7 +34,7 @@ periodic_stats_period: 1000000 ================ End RubySystem Configuration Print ================ -Real time: Aug/05/2010 10:43:25 +Real time: Feb/06/2011 20:27:50 Profiler Stats -------------- @@ -43,18 +43,18 @@ Elapsed_time_in_minutes: 0 Elapsed_time_in_hours: 0 Elapsed_time_in_days: 0 -Virtual_time_in_seconds: 0.25 -Virtual_time_in_minutes: 0.00416667 -Virtual_time_in_hours: 6.94444e-05 -Virtual_time_in_days: 2.89352e-06 +Virtual_time_in_seconds: 0.33 +Virtual_time_in_minutes: 0.0055 +Virtual_time_in_hours: 9.16667e-05 +Virtual_time_in_days: 3.81944e-06 Ruby_current_time: 92099 Ruby_start_time: 0 Ruby_cycles: 92099 -mbytes_resident: 33.5859 -mbytes_total: 33.5938 -resident_ratio: 1 +mbytes_resident: 35.7734 +mbytes_total: 209.453 +resident_ratio: 0.170832 ruby_cycles_executed: [ 92100 ] @@ -127,10 +127,10 @@ Resource Usage page_size: 4096 user_time: 0 system_time: 0 -page_reclaims: 7341 -page_faults: 2084 +page_reclaims: 10358 +page_faults: 0 swaps: 0 -block_inputs: 0 +block_inputs: 16 block_outputs: 0 Network Stats @@ -193,28 +193,28 @@ links_utilized_percent_switch_3: 0.205739 outgoing_messages_switch_3_link_2_Writeback_Data: 92 6624 [ 0 0 0 0 92 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_3_link_2_Writeback_Control: 402 3216 [ 0 0 0 0 402 0 0 0 0 0 ] base_latency: 1 -Cache Stats: system.l1_cntrl0.sequencer.icache - system.l1_cntrl0.sequencer.icache_total_misses: 270 - system.l1_cntrl0.sequencer.icache_total_demand_misses: 270 - system.l1_cntrl0.sequencer.icache_total_prefetches: 0 - system.l1_cntrl0.sequencer.icache_total_sw_prefetches: 0 - system.l1_cntrl0.sequencer.icache_total_hw_prefetches: 0 +Cache Stats: system.l1_cntrl0.L1IcacheMemory + system.l1_cntrl0.L1IcacheMemory_total_misses: 270 + system.l1_cntrl0.L1IcacheMemory_total_demand_misses: 270 + system.l1_cntrl0.L1IcacheMemory_total_prefetches: 0 + system.l1_cntrl0.L1IcacheMemory_total_sw_prefetches: 0 + system.l1_cntrl0.L1IcacheMemory_total_hw_prefetches: 0 - system.l1_cntrl0.sequencer.icache_request_type_IFETCH: 100% + system.l1_cntrl0.L1IcacheMemory_request_type_IFETCH: 100% - system.l1_cntrl0.sequencer.icache_access_mode_type_SupervisorMode: 270 100% + system.l1_cntrl0.L1IcacheMemory_access_mode_type_SupervisorMode: 270 100% -Cache Stats: system.l1_cntrl0.sequencer.dcache - system.l1_cntrl0.sequencer.dcache_total_misses: 243 - system.l1_cntrl0.sequencer.dcache_total_demand_misses: 243 - system.l1_cntrl0.sequencer.dcache_total_prefetches: 0 - system.l1_cntrl0.sequencer.dcache_total_sw_prefetches: 0 - system.l1_cntrl0.sequencer.dcache_total_hw_prefetches: 0 +Cache Stats: system.l1_cntrl0.L1DcacheMemory + system.l1_cntrl0.L1DcacheMemory_total_misses: 243 + system.l1_cntrl0.L1DcacheMemory_total_demand_misses: 243 + system.l1_cntrl0.L1DcacheMemory_total_prefetches: 0 + system.l1_cntrl0.L1DcacheMemory_total_sw_prefetches: 0 + system.l1_cntrl0.L1DcacheMemory_total_hw_prefetches: 0 - system.l1_cntrl0.sequencer.dcache_request_type_LD: 74.8971% - system.l1_cntrl0.sequencer.dcache_request_type_ST: 25.1029% + system.l1_cntrl0.L1DcacheMemory_request_type_LD: 74.8971% + system.l1_cntrl0.L1DcacheMemory_request_type_ST: 25.1029% - system.l1_cntrl0.sequencer.dcache_access_mode_type_SupervisorMode: 243 100% + system.l1_cntrl0.L1DcacheMemory_access_mode_type_SupervisorMode: 243 100% --- L1Cache --- - Event Counts - @@ -222,7 +222,7 @@ Load [415 ] 415 Ifetch [2585 ] 2585 Store [294 ] 294 Atomic [0 ] 0 -L1_Replacement [506 ] 506 +L1_Replacement [503 ] 503 Data_Shared [18 ] 18 Data_Owner [0 ] 0 Data_All_Tokens [495 ] 495 @@ -352,7 +352,7 @@ M_W Load [47 ] 47 M_W Ifetch [1038 ] 1038 M_W Store [6 ] 6 M_W Atomic [0 ] 0 -M_W L1_Replacement [4 ] 4 +M_W L1_Replacement [1 ] 1 M_W Transient_GETX [0 ] 0 M_W Transient_Local_GETX [0 ] 0 M_W Transient_GETS [0 ] 0 diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simout b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simout index 9cf458143..aa7eff126 100755 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simout +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Aug 5 2010 10:41:36 -M5 revision 1cd2a169499f+ 7535+ default brad/hammer_merge_gets qtip tip -M5 started Aug 5 2010 10:43:25 -M5 executing on svvint09 +M5 compiled Feb 6 2011 20:27:42 +M5 revision b885adc82ab4+ 7924+ default tip qtip brad/regress_updates +M5 started Feb 6 2011 20:27:50 +M5 executing on SC2B0617 command line: build/ALPHA_SE_MOESI_CMP_token/m5.fast -d build/ALPHA_SE_MOESI_CMP_token/tests/fast/quick/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_token -re tests/run.py build/ALPHA_SE_MOESI_CMP_token/tests/fast/quick/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_token Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt index e8b218502..e986a3c8f 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 42948 # Simulator instruction rate (inst/s) -host_mem_usage 211392 # Number of bytes of host memory used +host_inst_rate 45706 # Simulator instruction rate (inst/s) +host_mem_usage 214484 # Number of bytes of host memory used host_seconds 0.06 # Real time elapsed on the host -host_tick_rate 1534907 # Simulator tick rate (ticks/s) +host_tick_rate 1628169 # Simulator tick rate (ticks/s) sim_freq 1000000000 # Frequency of simulated ticks sim_insts 2577 # Number of instructions simulated sim_seconds 0.000092 # Number of seconds simulated @@ -43,8 +43,24 @@ system.cpu.itb.write_hits 0 # DT system.cpu.itb.write_misses 0 # DTB write misses system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.numCycles 92099 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.num_busy_cycles 92099 # Number of busy cycles +system.cpu.num_conditional_control_insts 238 # number of instructions that are conditional controls +system.cpu.num_fp_alu_accesses 6 # Number of float alu accesses +system.cpu.num_fp_insts 6 # number of float instructions +system.cpu.num_fp_register_reads 6 # number of times the floating registers were read +system.cpu.num_fp_register_writes 0 # number of times the floating registers were written +system.cpu.num_func_calls 140 # number of times a function call or return occured +system.cpu.num_idle_cycles 0 # Number of idle cycles system.cpu.num_insts 2577 # Number of instructions executed -system.cpu.num_refs 717 # Number of memory references +system.cpu.num_int_alu_accesses 2375 # Number of integer alu accesses +system.cpu.num_int_insts 2375 # number of integer instructions +system.cpu.num_int_register_reads 2998 # number of times the integer registers were read +system.cpu.num_int_register_writes 1768 # number of times the integer registers were written +system.cpu.num_load_insts 419 # Number of load instructions +system.cpu.num_mem_refs 717 # number of memory refs +system.cpu.num_store_insts 298 # Number of store instructions system.cpu.workload.PROG:num_syscalls 4 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/config.ini b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/config.ini index 4d36728d7..08f882272 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/config.ini +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/config.ini @@ -1,13 +1,22 @@ [root] type=Root children=system -dummy=0 +time_sync_enable=false +time_sync_period=100000000 +time_sync_spin_threshold=100000 [system] type=System children=cpu dir_cntrl0 l1_cntrl0 physmem ruby mem_mode=timing physmem=system.physmem +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 [system.cpu] type=TimingSimpleCPU @@ -32,8 +41,8 @@ progress_interval=0 system=system tracer=system.cpu.tracer workload=system.cpu.workload -dcache_port=system.l1_cntrl0.sequencer.port[1] -icache_port=system.l1_cntrl0.sequencer.port[0] +dcache_port=system.ruby.cpu_ruby_ports.port[1] +icache_port=system.ruby.cpu_ruby_ports.port[0] [system.cpu.dtb] type=AlphaTLB @@ -54,7 +63,7 @@ egid=100 env= errout=cerr euid=100 -executable=tests/test-progs/hello/bin/alpha/tru64/hello +executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/alpha/tru64/hello gid=100 input=cin max_stack_size=67108864 @@ -70,6 +79,7 @@ type=Directory_Controller children=directory memBuffer probeFilter buffer_size=0 directory=system.dir_cntrl0.directory +full_bit_dir_enabled=false memBuffer=system.dir_cntrl0.memBuffer memory_controller_latency=2 number_of_TBEs=256 @@ -118,17 +128,18 @@ start_index_bit=6 [system.l1_cntrl0] type=L1Cache_Controller -children=L2cacheMemory sequencer -L1DcacheMemory=system.l1_cntrl0.sequencer.dcache -L1IcacheMemory=system.l1_cntrl0.sequencer.icache +children=L2cacheMemory +L1DcacheMemory=system.ruby.cpu_ruby_ports.dcache +L1IcacheMemory=system.ruby.cpu_ruby_ports.icache L2cacheMemory=system.l1_cntrl0.L2cacheMemory buffer_size=0 cache_response_latency=10 issue_latency=2 +l2_cache_hit_latency=10 no_mig_atomic=true number_of_TBEs=256 recycle_latency=10 -sequencer=system.l1_cntrl0.sequencer +sequencer=system.ruby.cpu_ruby_ports transitions_per_cycle=32 version=0 @@ -140,12 +151,37 @@ replacement_policy=PSEUDO_LRU size=512 start_index_bit=6 -[system.l1_cntrl0.sequencer] +[system.physmem] +type=PhysicalMemory +file= +latency=30 +latency_var=0 +null=false +range=0:134217727 +zero=false +port=system.ruby.cpu_ruby_ports.physMemPort + +[system.ruby] +type=RubySystem +children=cpu_ruby_ports network profiler tracer +block_size_bytes=64 +clock=1 +mem_size=134217728 +network=system.ruby.network +no_mem_vec=false +profiler=system.ruby.profiler +random_seed=1234 +randomization=false +stats_filename=ruby.stats +tracer=system.ruby.tracer + +[system.ruby.cpu_ruby_ports] type=RubySequencer children=dcache icache -dcache=system.l1_cntrl0.sequencer.dcache +access_phys_mem=true +dcache=system.ruby.cpu_ruby_ports.dcache deadlock_threshold=500000 -icache=system.l1_cntrl0.sequencer.icache +icache=system.ruby.cpu_ruby_ports.icache max_outstanding_requests=16 physmem=system.physmem using_ruby_tester=false @@ -153,7 +189,7 @@ version=0 physMemPort=system.physmem.port[0] port=system.cpu.icache_port system.cpu.dcache_port -[system.l1_cntrl0.sequencer.dcache] +[system.ruby.cpu_ruby_ports.dcache] type=RubyCache assoc=2 latency=2 @@ -161,7 +197,7 @@ replacement_policy=PSEUDO_LRU size=256 start_index_bit=6 -[system.l1_cntrl0.sequencer.icache] +[system.ruby.cpu_ruby_ports.icache] type=RubyCache assoc=2 latency=2 @@ -169,39 +205,6 @@ replacement_policy=PSEUDO_LRU size=256 start_index_bit=6 -[system.physmem] -type=PhysicalMemory -file= -latency=30 -latency_var=0 -null=false -range=0:134217727 -zero=false -port=system.l1_cntrl0.sequencer.physMemPort - -[system.ruby] -type=RubySystem -children=debug network profiler tracer -block_size_bytes=64 -clock=1 -debug=system.ruby.debug -mem_size=134217728 -network=system.ruby.network -no_mem_vec=false -profiler=system.ruby.profiler -random_seed=1234 -randomization=false -stats_filename=ruby.stats -tracer=system.ruby.tracer - -[system.ruby.debug] -type=RubyDebug -filter_string=none -output_filename=none -protocol_trace=false -start_time=1 -verbosity_string=none - [system.ruby.network] type=SimpleNetwork children=topology @@ -216,9 +219,9 @@ topology=system.ruby.network.topology [system.ruby.network.topology] type=Topology children=ext_links0 ext_links1 int_links0 int_links1 +description=Crossbar ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1 int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1 -name=Crossbar num_int_nodes=3 print_config=false diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/ruby.stats b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/ruby.stats index 6e53a933a..7f9bbf1b9 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/ruby.stats +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/ruby.stats @@ -13,7 +13,7 @@ RubySystem config: Network Configuration --------------------- network: SIMPLE_NETWORK -topology: Crossbar +topology: virtual_net_0: active, ordered virtual_net_1: active, ordered @@ -34,7 +34,7 @@ periodic_stats_period: 1000000 ================ End RubySystem Configuration Print ================ -Real time: Aug/05/2010 14:44:19 +Real time: Feb/06/2011 20:42:21 Profiler Stats -------------- @@ -43,20 +43,20 @@ Elapsed_time_in_minutes: 0 Elapsed_time_in_hours: 0 Elapsed_time_in_days: 0 -Virtual_time_in_seconds: 0.21 -Virtual_time_in_minutes: 0.0035 -Virtual_time_in_hours: 5.83333e-05 -Virtual_time_in_days: 2.43056e-06 +Virtual_time_in_seconds: 0.31 +Virtual_time_in_minutes: 0.00516667 +Virtual_time_in_hours: 8.61111e-05 +Virtual_time_in_days: 3.58796e-06 -Ruby_current_time: 78408 +Ruby_current_time: 78448 Ruby_start_time: 0 -Ruby_cycles: 78408 +Ruby_cycles: 78448 -mbytes_resident: 33.3242 -mbytes_total: 33.332 -resident_ratio: 1 +mbytes_resident: 35.418 +mbytes_total: 208.91 +resident_ratio: 0.169593 -ruby_cycles_executed: [ 78409 ] +ruby_cycles_executed: [ 78449 ] Busy Controller Counts: L1Cache-0:0 @@ -69,13 +69,13 @@ sequencer_requests_outstanding: [binsize: 1 max: 1 count: 3295 average: 1 | All Non-Zero Cycle Demand Cache Accesses ---------------------------------------- -miss_latency: [binsize: 2 max: 320 count: 3294 average: 22.8033 | standard deviation: 52.924 | 0 2784 0 0 0 0 69 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 35 77 96 65 60 75 2 0 2 1 4 0 1 2 4 4 1 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 3 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_IFETCH: [binsize: 1 max: 181 count: 2585 average: 16.5544 | standard deviation: 44.4412 | 0 0 2315 0 0 0 0 0 0 0 0 0 22 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 17 19 16 48 18 11 31 24 15 37 0 1 0 0 0 0 0 0 0 3 0 0 0 0 0 0 1 1 0 0 2 0 1 1 2 ] -miss_latency_LD: [binsize: 2 max: 319 count: 415 average: 57.4602 | standard deviation: 75.1127 | 0 233 0 0 0 0 36 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 34 23 16 17 26 1 0 2 0 1 0 0 1 3 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_ST: [binsize: 2 max: 320 count: 294 average: 28.8265 | standard deviation: 63.3064 | 0 236 0 0 0 0 11 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 8 7 7 4 12 0 0 0 1 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 2 0 1 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency: [binsize: 2 max: 320 count: 3294 average: 22.8154 | standard deviation: 52.8821 | 0 2784 0 0 0 0 69 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 35 77 95 66 57 76 2 2 1 4 2 0 1 2 2 5 1 4 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 3 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_IFETCH: [binsize: 1 max: 181 count: 2585 average: 16.5636 | standard deviation: 44.4401 | 0 0 2315 0 0 0 0 0 0 0 0 0 0 22 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 47 18 11 32 22 14 39 1 1 1 1 0 0 0 2 1 0 0 0 0 0 0 0 1 0 0 0 2 1 0 2 1 ] +miss_latency_LD: [binsize: 2 max: 319 count: 415 average: 57.3952 | standard deviation: 74.7751 | 0 233 0 0 0 0 36 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 35 24 16 16 26 0 1 1 0 1 0 0 1 2 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_ST: [binsize: 2 max: 320 count: 294 average: 28.9728 | standard deviation: 63.5282 | 0 236 0 0 0 0 11 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3 7 6 7 5 10 0 0 0 1 1 0 1 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 2 0 1 0 0 0 0 0 0 0 0 0 0 ] miss_latency_L1Cache: [binsize: 1 max: 2 count: 2784 average: 2 | standard deviation: 0 | 0 0 2784 ] -miss_latency_L2Cache: [binsize: 1 max: 12 count: 69 average: 12 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 69 ] -miss_latency_Directory: [binsize: 2 max: 320 count: 441 average: 155.823 | standard deviation: 21.7136 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 35 77 96 65 60 75 2 0 2 1 4 0 1 2 4 4 1 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 3 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_L2Cache: [binsize: 1 max: 13 count: 69 average: 13 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 69 ] +miss_latency_Directory: [binsize: 2 max: 320 count: 441 average: 155.757 | standard deviation: 21.4255 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 35 77 95 66 57 76 2 2 1 4 2 0 1 2 2 5 1 4 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 3 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] @@ -87,14 +87,14 @@ miss_latency_dir_forward_to_first_response: [binsize: 1 max: 158 count: 1 averag miss_latency_dir_first_response_to_completion: [binsize: 1 max: 0 count: 1 average: 0 | standard deviation: 0 | 1 ] imcomplete_dir_Times: 440 miss_latency_IFETCH_L1Cache: [binsize: 1 max: 2 count: 2315 average: 2 | standard deviation: 0 | 0 0 2315 ] -miss_latency_IFETCH_L2Cache: [binsize: 1 max: 12 count: 22 average: 12 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 22 ] -miss_latency_IFETCH_Directory: [binsize: 1 max: 181 count: 248 average: 152.819 | standard deviation: 5.60689 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 17 19 16 48 18 11 31 24 15 37 0 1 0 0 0 0 0 0 0 3 0 0 0 0 0 0 1 1 0 0 2 0 1 1 2 ] +miss_latency_IFETCH_L2Cache: [binsize: 1 max: 13 count: 22 average: 13 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 22 ] +miss_latency_IFETCH_Directory: [binsize: 1 max: 181 count: 248 average: 152.827 | standard deviation: 5.37952 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 47 18 11 32 22 14 39 1 1 1 1 0 0 0 2 1 0 0 0 0 0 0 0 1 0 0 0 2 1 0 2 1 ] miss_latency_LD_L1Cache: [binsize: 1 max: 2 count: 233 average: 2 | standard deviation: 0 | 0 0 233 ] -miss_latency_LD_L2Cache: [binsize: 1 max: 12 count: 36 average: 12 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 36 ] -miss_latency_LD_Directory: [binsize: 2 max: 319 count: 146 average: 157.178 | standard deviation: 25.3138 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 34 23 16 17 26 1 0 2 0 1 0 0 1 3 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_LD_L2Cache: [binsize: 1 max: 13 count: 36 average: 13 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 36 ] +miss_latency_LD_Directory: [binsize: 2 max: 319 count: 146 average: 156.747 | standard deviation: 24.5989 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 35 24 16 16 26 0 1 1 0 1 0 0 1 2 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] miss_latency_ST_L1Cache: [binsize: 1 max: 2 count: 236 average: 2 | standard deviation: 0 | 0 0 236 ] -miss_latency_ST_L2Cache: [binsize: 1 max: 12 count: 11 average: 12 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 11 ] -miss_latency_ST_Directory: [binsize: 2 max: 320 count: 47 average: 167.468 | standard deviation: 46.1312 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 8 7 7 4 12 0 0 0 1 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 2 0 1 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_ST_L2Cache: [binsize: 1 max: 13 count: 11 average: 13 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 11 ] +miss_latency_ST_Directory: [binsize: 2 max: 320 count: 47 average: 168.149 | standard deviation: 46.0633 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3 7 6 7 5 10 0 0 0 1 1 0 1 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 2 0 1 0 0 0 0 0 0 0 0 0 0 ] All Non-Zero Cycle SW Prefetch Requests ------------------------------------ @@ -126,8 +126,8 @@ Resource Usage page_size: 4096 user_time: 0 system_time: 0 -page_reclaims: 7298 -page_faults: 2071 +page_reclaims: 10333 +page_faults: 0 swaps: 0 block_inputs: 0 block_outputs: 0 @@ -144,9 +144,9 @@ total_msgs: 7791 total_bytes: 162552 switch_0_inlinks: 2 switch_0_outlinks: 2 -links_utilized_percent_switch_0: 0.110878 - links_utilized_percent_switch_0_link_0: 0.0700502 bw: 640000 base_latency: 1 - links_utilized_percent_switch_0_link_1: 0.151706 bw: 160000 base_latency: 1 +links_utilized_percent_switch_0: 0.110822 + links_utilized_percent_switch_0_link_0: 0.0700145 bw: 640000 base_latency: 1 + links_utilized_percent_switch_0_link_1: 0.151629 bw: 160000 base_latency: 1 outgoing_messages_switch_0_link_0_Response_Data: 441 31752 [ 0 0 0 0 441 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_0_link_0_Writeback_Control: 425 3400 [ 0 0 0 425 0 0 0 0 0 0 ] base_latency: 1 @@ -157,9 +157,9 @@ links_utilized_percent_switch_0: 0.110878 switch_1_inlinks: 2 switch_1_outlinks: 2 -links_utilized_percent_switch_1: 0.159064 - links_utilized_percent_switch_1_link_0: 0.0379266 bw: 640000 base_latency: 1 - links_utilized_percent_switch_1_link_1: 0.280201 bw: 160000 base_latency: 1 +links_utilized_percent_switch_1: 0.158983 + links_utilized_percent_switch_1_link_0: 0.0379073 bw: 640000 base_latency: 1 + links_utilized_percent_switch_1_link_1: 0.280058 bw: 160000 base_latency: 1 outgoing_messages_switch_1_link_0_Request_Control: 441 3528 [ 0 0 441 0 0 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_1_link_0_Writeback_Data: 81 5832 [ 0 0 0 0 0 81 0 0 0 0 ] base_latency: 1 @@ -170,9 +170,9 @@ links_utilized_percent_switch_1: 0.159064 switch_2_inlinks: 2 switch_2_outlinks: 2 -links_utilized_percent_switch_2: 0.215954 - links_utilized_percent_switch_2_link_0: 0.280201 bw: 160000 base_latency: 1 - links_utilized_percent_switch_2_link_1: 0.151706 bw: 160000 base_latency: 1 +links_utilized_percent_switch_2: 0.215844 + links_utilized_percent_switch_2_link_0: 0.280058 bw: 160000 base_latency: 1 + links_utilized_percent_switch_2_link_1: 0.151629 bw: 160000 base_latency: 1 outgoing_messages_switch_2_link_0_Response_Data: 441 31752 [ 0 0 0 0 441 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_2_link_0_Writeback_Control: 425 3400 [ 0 0 0 425 0 0 0 0 0 0 ] base_latency: 1 @@ -181,47 +181,47 @@ links_utilized_percent_switch_2: 0.215954 outgoing_messages_switch_2_link_1_Writeback_Control: 769 6152 [ 0 0 425 0 0 344 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_2_link_1_Unblock_Control: 440 3520 [ 0 0 0 0 0 440 0 0 0 0 ] base_latency: 1 -Cache Stats: system.l1_cntrl0.sequencer.icache - system.l1_cntrl0.sequencer.icache_total_misses: 270 - system.l1_cntrl0.sequencer.icache_total_demand_misses: 270 - system.l1_cntrl0.sequencer.icache_total_prefetches: 0 - system.l1_cntrl0.sequencer.icache_total_sw_prefetches: 0 - system.l1_cntrl0.sequencer.icache_total_hw_prefetches: 0 +Cache Stats: system.ruby.cpu_ruby_ports.icache + system.ruby.cpu_ruby_ports.icache_total_misses: 270 + system.ruby.cpu_ruby_ports.icache_total_demand_misses: 270 + system.ruby.cpu_ruby_ports.icache_total_prefetches: 0 + system.ruby.cpu_ruby_ports.icache_total_sw_prefetches: 0 + system.ruby.cpu_ruby_ports.icache_total_hw_prefetches: 0 - system.l1_cntrl0.sequencer.icache_request_type_IFETCH: 100% + system.ruby.cpu_ruby_ports.icache_request_type_IFETCH: 100% - system.l1_cntrl0.sequencer.icache_access_mode_type_SupervisorMode: 270 100% + system.ruby.cpu_ruby_ports.icache_access_mode_type_SupervisorMode: 270 100% -Cache Stats: system.l1_cntrl0.sequencer.dcache - system.l1_cntrl0.sequencer.dcache_total_misses: 240 - system.l1_cntrl0.sequencer.dcache_total_demand_misses: 240 - system.l1_cntrl0.sequencer.dcache_total_prefetches: 0 - system.l1_cntrl0.sequencer.dcache_total_sw_prefetches: 0 - system.l1_cntrl0.sequencer.dcache_total_hw_prefetches: 0 +Cache Stats: system.ruby.cpu_ruby_ports.dcache + system.ruby.cpu_ruby_ports.dcache_total_misses: 240 + system.ruby.cpu_ruby_ports.dcache_total_demand_misses: 240 + system.ruby.cpu_ruby_ports.dcache_total_prefetches: 0 + system.ruby.cpu_ruby_ports.dcache_total_sw_prefetches: 0 + system.ruby.cpu_ruby_ports.dcache_total_hw_prefetches: 0 - system.l1_cntrl0.sequencer.dcache_request_type_LD: 75.8333% - system.l1_cntrl0.sequencer.dcache_request_type_ST: 24.1667% + system.ruby.cpu_ruby_ports.dcache_request_type_LD: 75.8333% + system.ruby.cpu_ruby_ports.dcache_request_type_ST: 24.1667% - system.l1_cntrl0.sequencer.dcache_access_mode_type_SupervisorMode: 240 100% + system.ruby.cpu_ruby_ports.dcache_access_mode_type_SupervisorMode: 240 100% Cache Stats: system.l1_cntrl0.L2cacheMemory - system.l1_cntrl0.L2cacheMemory_total_misses: 441 - system.l1_cntrl0.L2cacheMemory_total_demand_misses: 441 + system.l1_cntrl0.L2cacheMemory_total_misses: 510 + system.l1_cntrl0.L2cacheMemory_total_demand_misses: 510 system.l1_cntrl0.L2cacheMemory_total_prefetches: 0 system.l1_cntrl0.L2cacheMemory_total_sw_prefetches: 0 system.l1_cntrl0.L2cacheMemory_total_hw_prefetches: 0 - system.l1_cntrl0.L2cacheMemory_request_type_LD: 33.1066% - system.l1_cntrl0.L2cacheMemory_request_type_ST: 10.6576% - system.l1_cntrl0.L2cacheMemory_request_type_IFETCH: 56.2358% + system.l1_cntrl0.L2cacheMemory_request_type_LD: 35.6863% + system.l1_cntrl0.L2cacheMemory_request_type_ST: 11.3725% + system.l1_cntrl0.L2cacheMemory_request_type_IFETCH: 52.9412% - system.l1_cntrl0.L2cacheMemory_access_mode_type_SupervisorMode: 441 100% + system.l1_cntrl0.L2cacheMemory_access_mode_type_SupervisorMode: 510 100% --- L1Cache --- - Event Counts - -Load [428 ] 428 -Ifetch [2597 ] 2597 -Store [302 ] 302 +Load [422 ] 422 +Ifetch [2591 ] 2591 +Store [298 ] 298 L2_Replacement [425 ] 425 L1_to_L2 [502 ] 502 Trigger_L2_to_L1D [47 ] 47 @@ -231,6 +231,7 @@ Other_GETX [0 ] 0 Other_GETS [0 ] 0 Merged_GETS [0 ] 0 Other_GETS_No_Mig [0 ] 0 +NC_DMA_GETS [0 ] 0 Invalidate [0 ] 0 Ack [0 ] 0 Shared_Ack [0 ] 0 @@ -253,6 +254,7 @@ I Trigger_L2_to_L1I [0 ] 0 I Other_GETX [0 ] 0 I Other_GETS [0 ] 0 I Other_GETS_No_Mig [0 ] 0 +I NC_DMA_GETS [0 ] 0 I Invalidate [0 ] 0 S Load [0 ] 0 @@ -265,6 +267,7 @@ S Trigger_L2_to_L1I [0 ] 0 S Other_GETX [0 ] 0 S Other_GETS [0 ] 0 S Other_GETS_No_Mig [0 ] 0 +S NC_DMA_GETS [0 ] 0 S Invalidate [0 ] 0 O Load [0 ] 0 @@ -278,6 +281,7 @@ O Other_GETX [0 ] 0 O Other_GETS [0 ] 0 O Merged_GETS [0 ] 0 O Other_GETS_No_Mig [0 ] 0 +O NC_DMA_GETS [0 ] 0 O Invalidate [0 ] 0 M Load [131 ] 131 @@ -291,6 +295,7 @@ M Other_GETX [0 ] 0 M Other_GETS [0 ] 0 M Merged_GETS [0 ] 0 M Other_GETS_No_Mig [0 ] 0 +M NC_DMA_GETS [0 ] 0 M Invalidate [0 ] 0 MM Load [138 ] 138 @@ -304,6 +309,7 @@ MM Other_GETX [0 ] 0 MM Other_GETS [0 ] 0 MM Merged_GETS [0 ] 0 MM Other_GETS_No_Mig [0 ] 0 +MM NC_DMA_GETS [0 ] 0 MM Invalidate [0 ] 0 IM Load [0 ] 0 @@ -314,6 +320,7 @@ IM L1_to_L2 [0 ] 0 IM Other_GETX [0 ] 0 IM Other_GETS [0 ] 0 IM Other_GETS_No_Mig [0 ] 0 +IM NC_DMA_GETS [0 ] 0 IM Invalidate [0 ] 0 IM Ack [0 ] 0 IM Data [0 ] 0 @@ -327,9 +334,11 @@ SM L1_to_L2 [0 ] 0 SM Other_GETX [0 ] 0 SM Other_GETS [0 ] 0 SM Other_GETS_No_Mig [0 ] 0 +SM NC_DMA_GETS [0 ] 0 SM Invalidate [0 ] 0 SM Ack [0 ] 0 SM Data [0 ] 0 +SM Exclusive_Data [0 ] 0 OM Load [0 ] 0 OM Ifetch [0 ] 0 @@ -340,6 +349,7 @@ OM Other_GETX [0 ] 0 OM Other_GETS [0 ] 0 OM Merged_GETS [0 ] 0 OM Other_GETS_No_Mig [0 ] 0 +OM NC_DMA_GETS [0 ] 0 OM Invalidate [0 ] 0 OM Ack [0 ] 0 OM All_acks [0 ] 0 @@ -377,6 +387,7 @@ IS L1_to_L2 [0 ] 0 IS Other_GETX [0 ] 0 IS Other_GETS [0 ] 0 IS Other_GETS_No_Mig [0 ] 0 +IS NC_DMA_GETS [0 ] 0 IS Invalidate [0 ] 0 IS Ack [0 ] 0 IS Shared_Ack [0 ] 0 @@ -403,18 +414,20 @@ OI Other_GETX [0 ] 0 OI Other_GETS [0 ] 0 OI Merged_GETS [0 ] 0 OI Other_GETS_No_Mig [0 ] 0 +OI NC_DMA_GETS [0 ] 0 OI Invalidate [0 ] 0 OI Writeback_Ack [0 ] 0 -MI Load [13 ] 13 -MI Ifetch [12 ] 12 -MI Store [8 ] 8 +MI Load [7 ] 7 +MI Ifetch [6 ] 6 +MI Store [4 ] 4 MI L2_Replacement [0 ] 0 MI L1_to_L2 [0 ] 0 MI Other_GETX [0 ] 0 MI Other_GETS [0 ] 0 MI Merged_GETS [0 ] 0 MI Other_GETS_No_Mig [0 ] 0 +MI NC_DMA_GETS [0 ] 0 MI Invalidate [0 ] 0 MI Writeback_Ack [425 ] 425 @@ -426,6 +439,7 @@ II L1_to_L2 [0 ] 0 II Other_GETX [0 ] 0 II Other_GETS [0 ] 0 II Other_GETS_No_Mig [0 ] 0 +II NC_DMA_GETS [0 ] 0 II Invalidate [0 ] 0 II Writeback_Ack [0 ] 0 II Writeback_Nack [0 ] 0 @@ -440,6 +454,7 @@ IT Other_GETX [0 ] 0 IT Other_GETS [0 ] 0 IT Merged_GETS [0 ] 0 IT Other_GETS_No_Mig [0 ] 0 +IT NC_DMA_GETS [0 ] 0 IT Invalidate [0 ] 0 ST Load [0 ] 0 @@ -452,6 +467,7 @@ ST Other_GETX [0 ] 0 ST Other_GETS [0 ] 0 ST Merged_GETS [0 ] 0 ST Other_GETS_No_Mig [0 ] 0 +ST NC_DMA_GETS [0 ] 0 ST Invalidate [0 ] 0 OT Load [0 ] 0 @@ -464,6 +480,7 @@ OT Other_GETX [0 ] 0 OT Other_GETS [0 ] 0 OT Merged_GETS [0 ] 0 OT Other_GETS_No_Mig [0 ] 0 +OT NC_DMA_GETS [0 ] 0 OT Invalidate [0 ] 0 MT Load [0 ] 0 @@ -476,6 +493,7 @@ MT Other_GETX [0 ] 0 MT Other_GETS [0 ] 0 MT Merged_GETS [0 ] 0 MT Other_GETS_No_Mig [0 ] 0 +MT NC_DMA_GETS [0 ] 0 MT Invalidate [0 ] 0 MMT Load [0 ] 0 @@ -488,6 +506,7 @@ MMT Other_GETX [0 ] 0 MMT Other_GETS [0 ] 0 MMT Merged_GETS [0 ] 0 MMT Other_GETS_No_Mig [0 ] 0 +MMT NC_DMA_GETS [0 ] 0 MMT Invalidate [0 ] 0 Cache Stats: system.dir_cntrl0.probeFilter @@ -503,18 +522,18 @@ Memory controller: system.dir_cntrl0.memBuffer: memory_reads: 441 memory_writes: 81 memory_refreshes: 164 - memory_total_request_delays: 147 - memory_delays_per_request: 0.281609 + memory_total_request_delays: 151 + memory_delays_per_request: 0.289272 memory_delays_in_input_queue: 2 memory_delays_behind_head_of_bank_queue: 0 - memory_delays_stalled_at_head_of_bank_queue: 145 - memory_stalls_for_bank_busy: 27 + memory_delays_stalled_at_head_of_bank_queue: 149 + memory_stalls_for_bank_busy: 22 memory_stalls_for_random_busy: 0 memory_stalls_for_anti_starvation: 0 - memory_stalls_for_arbitration: 6 - memory_stalls_for_bus: 23 + memory_stalls_for_arbitration: 7 + memory_stalls_for_bus: 26 memory_stalls_for_tfaw: 0 - memory_stalls_for_read_write_turnaround: 89 + memory_stalls_for_read_write_turnaround: 94 memory_stalls_for_read_read_turnaround: 0 accesses_per_bank: 18 10 0 36 20 19 31 22 5 4 7 4 22 41 22 3 4 6 7 13 10 18 14 41 16 5 5 12 13 18 14 62 @@ -625,6 +644,8 @@ NO_B_X PUT [0 ] 0 NO_B_X UnblockS [0 ] 0 NO_B_X UnblockM [0 ] 0 NO_B_X Pf_Replacement [0 ] 0 +NO_B_X DMA_READ [0 ] 0 +NO_B_X DMA_WRITE [0 ] 0 NO_B_S GETX [0 ] 0 NO_B_S GETS [0 ] 0 @@ -648,6 +669,7 @@ O_B GETX [0 ] 0 O_B GETS [0 ] 0 O_B PUT [0 ] 0 O_B UnblockS [0 ] 0 +O_B UnblockM [0 ] 0 O_B Pf_Replacement [0 ] 0 O_B DMA_READ [0 ] 0 O_B DMA_WRITE [0 ] 0 diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simout b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simout index 76a97a409..aaa603cbd 100755 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simout +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simout @@ -5,13 +5,13 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Aug 5 2010 14:43:33 -M5 revision c5f5b5533e96+ 7536+ default qtip tip brad/regress_updates -M5 started Aug 5 2010 14:44:19 -M5 executing on svvint09 +M5 compiled Feb 6 2011 15:12:45 +M5 revision b885adc82ab4+ 7924+ default tip qtip brad/regress_updates +M5 started Feb 6 2011 20:42:21 +M5 executing on SC2B0617 command line: build/ALPHA_SE_MOESI_hammer/m5.fast -d build/ALPHA_SE_MOESI_hammer/tests/fast/quick/00.hello/alpha/tru64/simple-timing-ruby-MOESI_hammer -re tests/run.py build/ALPHA_SE_MOESI_hammer/tests/fast/quick/00.hello/alpha/tru64/simple-timing-ruby-MOESI_hammer Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello world! -Exiting @ tick 78408 because target called exit() +Exiting @ tick 78448 because target called exit() diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt index 58de899ed..e005e2d30 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 42947 # Simulator instruction rate (inst/s) -host_mem_usage 211060 # Number of bytes of host memory used -host_seconds 0.06 # Real time elapsed on the host -host_tick_rate 1306713 # Simulator tick rate (ticks/s) +host_inst_rate 52381 # Simulator instruction rate (inst/s) +host_mem_usage 213928 # Number of bytes of host memory used +host_seconds 0.05 # Real time elapsed on the host +host_tick_rate 1589078 # Simulator tick rate (ticks/s) sim_freq 1000000000 # Frequency of simulated ticks sim_insts 2577 # Number of instructions simulated sim_seconds 0.000078 # Number of seconds simulated -sim_ticks 78408 # Number of ticks simulated +sim_ticks 78448 # Number of ticks simulated system.cpu.dtb.data_accesses 717 # DTB accesses system.cpu.dtb.data_acv 0 # DTB access violations system.cpu.dtb.data_hits 709 # DTB hits @@ -42,9 +42,25 @@ system.cpu.itb.write_acv 0 # DT system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 78408 # number of cpu cycles simulated +system.cpu.numCycles 78448 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.num_busy_cycles 78448 # Number of busy cycles +system.cpu.num_conditional_control_insts 238 # number of instructions that are conditional controls +system.cpu.num_fp_alu_accesses 6 # Number of float alu accesses +system.cpu.num_fp_insts 6 # number of float instructions +system.cpu.num_fp_register_reads 6 # number of times the floating registers were read +system.cpu.num_fp_register_writes 0 # number of times the floating registers were written +system.cpu.num_func_calls 140 # number of times a function call or return occured +system.cpu.num_idle_cycles 0 # Number of idle cycles system.cpu.num_insts 2577 # Number of instructions executed -system.cpu.num_refs 717 # Number of memory references +system.cpu.num_int_alu_accesses 2375 # Number of integer alu accesses +system.cpu.num_int_insts 2375 # number of integer instructions +system.cpu.num_int_register_reads 2998 # number of times the integer registers were read +system.cpu.num_int_register_writes 1768 # number of times the integer registers were written +system.cpu.num_load_insts 419 # Number of load instructions +system.cpu.num_mem_refs 717 # number of memory refs +system.cpu.num_store_insts 298 # Number of store instructions system.cpu.workload.PROG:num_syscalls 4 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/config.ini b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/config.ini index 4c150fde0..69aa148c6 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/config.ini +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/config.ini @@ -1,13 +1,22 @@ [root] type=Root children=system -dummy=0 +time_sync_enable=false +time_sync_period=100000000 +time_sync_spin_threshold=100000 [system] type=System -children=cpu physmem ruby +children=cpu dir_cntrl0 l1_cntrl0 physmem ruby mem_mode=timing physmem=system.physmem +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 [system.cpu] type=TimingSimpleCPU @@ -32,8 +41,8 @@ progress_interval=0 system=system tracer=system.cpu.tracer workload=system.cpu.workload -dcache_port=system.ruby.network.topology.ext_links0.ext_node.sequencer.port[1] -icache_port=system.ruby.network.topology.ext_links0.ext_node.sequencer.port[0] +dcache_port=system.ruby.cpu_ruby_ports.port[1] +icache_port=system.ruby.cpu_ruby_ports.port[0] [system.cpu.dtb] type=AlphaTLB @@ -54,7 +63,7 @@ egid=100 env= errout=cerr euid=100 -executable=tests/test-progs/hello/bin/alpha/tru64/hello +executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/alpha/tru64/hello gid=100 input=cin max_stack_size=67108864 @@ -65,6 +74,59 @@ simpoint=0 system=system uid=100 +[system.dir_cntrl0] +type=Directory_Controller +children=directory memBuffer +buffer_size=0 +directory=system.dir_cntrl0.directory +directory_latency=12 +memBuffer=system.dir_cntrl0.memBuffer +number_of_TBEs=256 +recycle_latency=10 +transitions_per_cycle=32 +version=0 + +[system.dir_cntrl0.directory] +type=RubyDirectoryMemory +map_levels=4 +numa_high_bit=6 +size=134217728 +use_map=false +version=0 + +[system.dir_cntrl0.memBuffer] +type=RubyMemoryControl +bank_bit_0=8 +bank_busy_time=11 +bank_queue_size=12 +banks_per_rank=8 +basic_bus_busy_time=2 +dimm_bit_0=12 +dimms_per_channel=2 +mem_bus_cycle_multiplier=10 +mem_ctl_latency=12 +mem_fixed_delay=0 +mem_random_arbitrate=0 +rank_bit_0=11 +rank_rank_delay=1 +ranks_per_dimm=2 +read_write_delay=2 +refresh_period=1560 +tFaw=0 +version=0 + +[system.l1_cntrl0] +type=L1Cache_Controller +buffer_size=0 +cacheMemory=system.ruby.cpu_ruby_ports.dcache +cache_response_latency=12 +issue_latency=2 +number_of_TBEs=256 +recycle_latency=10 +sequencer=system.ruby.cpu_ruby_ports +transitions_per_cycle=32 +version=0 + [system.physmem] type=PhysicalMemory file= @@ -73,34 +135,48 @@ latency_var=0 null=false range=0:134217727 zero=false -port=system.ruby.network.topology.ext_links0.ext_node.sequencer.physMemPort +port=system.ruby.cpu_ruby_ports.physMemPort [system.ruby] type=RubySystem -children=debug network profiler tracer +children=cpu_ruby_ports network profiler tracer block_size_bytes=64 clock=1 -debug=system.ruby.debug mem_size=134217728 network=system.ruby.network +no_mem_vec=false profiler=system.ruby.profiler random_seed=1234 randomization=false stats_filename=ruby.stats tracer=system.ruby.tracer -[system.ruby.debug] -type=RubyDebug -filter_string=none -output_filename=none -protocol_trace=false -start_time=1 -verbosity_string=none +[system.ruby.cpu_ruby_ports] +type=RubySequencer +children=dcache +access_phys_mem=true +dcache=system.ruby.cpu_ruby_ports.dcache +deadlock_threshold=500000 +icache=system.ruby.cpu_ruby_ports.dcache +max_outstanding_requests=16 +physmem=system.physmem +using_ruby_tester=false +version=0 +physMemPort=system.physmem.port[0] +port=system.cpu.icache_port system.cpu.dcache_port + +[system.ruby.cpu_ruby_ports.dcache] +type=RubyCache +assoc=2 +latency=3 +replacement_policy=PSEUDO_LRU +size=256 +start_index_bit=6 [system.ruby.network] type=SimpleNetwork children=topology -adaptive_routing=true +adaptive_routing=false buffer_size=0 control_msg_size=8 endpoint_bandwidth=10000 @@ -111,6 +187,7 @@ topology=system.ruby.network.topology [system.ruby.network.topology] type=Topology children=ext_links0 ext_links1 int_links0 int_links1 +description=Crossbar ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1 int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1 num_int_nodes=3 @@ -118,93 +195,20 @@ print_config=false [system.ruby.network.topology.ext_links0] type=ExtLink -children=ext_node bw_multiplier=64 -ext_node=system.ruby.network.topology.ext_links0.ext_node +ext_node=system.l1_cntrl0 int_node=0 latency=1 weight=1 -[system.ruby.network.topology.ext_links0.ext_node] -type=L1Cache_Controller -children=sequencer -buffer_size=0 -cacheMemory=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache -cache_response_latency=12 -issue_latency=2 -number_of_TBEs=256 -recycle_latency=10 -sequencer=system.ruby.network.topology.ext_links0.ext_node.sequencer -transitions_per_cycle=32 -version=0 - -[system.ruby.network.topology.ext_links0.ext_node.sequencer] -type=RubySequencer -children=icache -dcache=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache -deadlock_threshold=500000 -icache=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache -max_outstanding_requests=16 -physmem=system.physmem -using_ruby_tester=false -version=0 -physMemPort=system.physmem.port[0] -port=system.cpu.icache_port system.cpu.dcache_port - -[system.ruby.network.topology.ext_links0.ext_node.sequencer.icache] -type=RubyCache -assoc=2 -latency=3 -replacement_policy=PSEUDO_LRU -size=256 - [system.ruby.network.topology.ext_links1] type=ExtLink -children=ext_node bw_multiplier=64 -ext_node=system.ruby.network.topology.ext_links1.ext_node +ext_node=system.dir_cntrl0 int_node=1 latency=1 weight=1 -[system.ruby.network.topology.ext_links1.ext_node] -type=Directory_Controller -children=directory memBuffer -buffer_size=0 -directory=system.ruby.network.topology.ext_links1.ext_node.directory -directory_latency=12 -memBuffer=system.ruby.network.topology.ext_links1.ext_node.memBuffer -number_of_TBEs=256 -recycle_latency=10 -transitions_per_cycle=32 -version=0 - -[system.ruby.network.topology.ext_links1.ext_node.directory] -type=RubyDirectoryMemory -size=134217728 -version=0 - -[system.ruby.network.topology.ext_links1.ext_node.memBuffer] -type=RubyMemoryControl -bank_bit_0=8 -bank_busy_time=11 -bank_queue_size=12 -banks_per_rank=8 -basic_bus_busy_time=2 -dimm_bit_0=12 -dimms_per_channel=2 -mem_bus_cycle_multiplier=10 -mem_ctl_latency=12 -mem_fixed_delay=0 -mem_random_arbitrate=0 -rank_bit_0=11 -rank_rank_delay=1 -ranks_per_dimm=2 -read_write_delay=2 -refresh_period=1560 -tFaw=0 -version=0 - [system.ruby.network.topology.int_links0] type=IntLink bw_multiplier=16 diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/ruby.stats b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/ruby.stats index edd5bdfcc..b4aefc92b 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/ruby.stats +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/ruby.stats @@ -18,9 +18,9 @@ topology: virtual_net_0: active, ordered virtual_net_1: active, ordered virtual_net_2: active, ordered -virtual_net_3: inactive +virtual_net_3: active, ordered virtual_net_4: active, ordered -virtual_net_5: active, ordered +virtual_net_5: inactive virtual_net_6: inactive virtual_net_7: inactive virtual_net_8: inactive @@ -34,40 +34,29 @@ periodic_stats_period: 1000000 ================ End RubySystem Configuration Print ================ -Real time: Jan/28/2010 10:26:06 +Real time: Feb/06/2011 20:42:40 Profiler Stats -------------- -Elapsed_time_in_seconds: 0 -Elapsed_time_in_minutes: 0 -Elapsed_time_in_hours: 0 -Elapsed_time_in_days: 0 +Elapsed_time_in_seconds: 1 +Elapsed_time_in_minutes: 0.0166667 +Elapsed_time_in_hours: 0.000277778 +Elapsed_time_in_days: 1.15741e-05 -Virtual_time_in_seconds: 0.25 -Virtual_time_in_minutes: 0.00416667 -Virtual_time_in_hours: 6.94444e-05 -Virtual_time_in_days: 2.89352e-06 +Virtual_time_in_seconds: 0.32 +Virtual_time_in_minutes: 0.00533333 +Virtual_time_in_hours: 8.88889e-05 +Virtual_time_in_days: 3.7037e-06 Ruby_current_time: 123378 Ruby_start_time: 0 Ruby_cycles: 123378 -mbytes_resident: 32.8828 -mbytes_total: 32.8906 -resident_ratio: 1 - -Total_misses: 0 -total_misses: 0 [ 0 ] -user_misses: 0 [ 0 ] -supervisor_misses: 0 [ 0 ] - -ruby_cycles_executed: 123379 [ 123379 ] - -transactions_started: 0 [ 0 ] -transactions_ended: 0 [ 0 ] -cycles_per_transaction: 0 [ 0 ] -misses_per_transaction: 0 [ 0 ] +mbytes_resident: 35.3594 +mbytes_total: 208.918 +resident_ratio: 0.169287 +ruby_cycles_executed: [ 123379 ] Busy Controller Counts: L1Cache-0:0 @@ -81,9 +70,27 @@ sequencer_requests_outstanding: [binsize: 1 max: 1 count: 3295 average: 1 | All Non-Zero Cycle Demand Cache Accesses ---------------------------------------- miss_latency: [binsize: 2 max: 375 count: 3294 average: 36.4554 | standard deviation: 69.7725 | 0 2668 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 2 0 0 0 3 1 1 4 2 101 88 63 177 126 0 1 1 8 0 2 1 1 4 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7 4 5 13 2 0 0 0 1 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 ] -miss_latency_1: [binsize: 2 max: 375 count: 2585 average: 23.1702 | standard deviation: 56.4841 | 0 2288 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 2 0 0 2 2 31 53 29 71 82 0 1 0 5 0 1 1 1 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 2 1 3 2 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ] -miss_latency_2: [binsize: 2 max: 281 count: 415 average: 107.304 | standard deviation: 88.8453 | 0 170 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 1 0 2 0 56 24 27 75 32 0 0 1 3 0 1 0 0 2 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5 0 4 7 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_3: [binsize: 2 max: 265 count: 294 average: 53.2585 | standard deviation: 80.456 | 0 210 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 14 11 7 31 12 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_IFETCH: [binsize: 2 max: 375 count: 2585 average: 23.1702 | standard deviation: 56.4841 | 0 2288 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 2 0 0 2 2 31 53 29 71 82 0 1 0 5 0 1 1 1 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 2 1 3 2 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ] +miss_latency_LD: [binsize: 2 max: 281 count: 415 average: 107.304 | standard deviation: 88.8453 | 0 170 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 1 0 2 0 56 24 27 75 32 0 0 1 3 0 1 0 0 2 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5 0 4 7 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_ST: [binsize: 2 max: 265 count: 294 average: 53.2585 | standard deviation: 80.456 | 0 210 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 14 11 7 31 12 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_L1Cache: [binsize: 1 max: 3 count: 2668 average: 3 | standard deviation: 0 | 0 0 0 2668 ] +miss_latency_Directory: [binsize: 2 max: 375 count: 626 average: 179.042 | standard deviation: 22.5462 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 2 0 0 0 3 1 1 4 2 101 88 63 177 126 0 1 1 8 0 2 1 1 4 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7 4 5 13 2 0 0 0 1 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 ] +miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_wCC_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +imcomplete_wCC_Times: 0 +miss_latency_dir_issue_to_initial_request: [binsize: 1 max: 0 count: 1 average: 0 | standard deviation: 0 | 1 ] +miss_latency_dir_initial_forward_request: [binsize: 1 max: 0 count: 1 average: 0 | standard deviation: 0 | 1 ] +miss_latency_dir_forward_to_first_response: [binsize: 1 max: 0 count: 1 average: 0 | standard deviation: 0 | 1 ] +miss_latency_dir_first_response_to_completion: [binsize: 1 max: 159 count: 1 average: 159 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ] +imcomplete_dir_Times: 625 +miss_latency_IFETCH_L1Cache: [binsize: 1 max: 3 count: 2288 average: 3 | standard deviation: 0 | 0 0 0 2288 ] +miss_latency_IFETCH_Directory: [binsize: 2 max: 375 count: 297 average: 178.556 | standard deviation: 21.9279 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 2 0 0 2 2 31 53 29 71 82 0 1 0 5 0 1 1 1 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 2 1 3 2 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ] +miss_latency_LD_L1Cache: [binsize: 1 max: 3 count: 170 average: 3 | standard deviation: 0 | 0 0 0 170 ] +miss_latency_LD_Directory: [binsize: 2 max: 281 count: 245 average: 179.678 | standard deviation: 23.5327 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 1 0 2 0 56 24 27 75 32 0 0 1 3 0 1 0 0 2 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5 0 4 7 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_ST_L1Cache: [binsize: 1 max: 3 count: 210 average: 3 | standard deviation: 0 | 0 0 0 210 ] +miss_latency_ST_Directory: [binsize: 2 max: 265 count: 84 average: 178.905 | standard deviation: 21.977 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 14 11 7 31 12 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] All Non-Zero Cycle SW Prefetch Requests ------------------------------------ @@ -115,8 +122,8 @@ Resource Usage page_size: 4096 user_time: 0 system_time: 0 -page_reclaims: 7118 -page_faults: 2103 +page_reclaims: 10291 +page_faults: 0 swaps: 0 block_inputs: 0 block_outputs: 0 @@ -124,16 +131,22 @@ block_outputs: 0 Network Stats ------------- +total_msg_count_Control: 1878 15024 +total_msg_count_Data: 1866 134352 +total_msg_count_Response_Data: 1878 135216 +total_msg_count_Writeback_Control: 1866 14928 +total_msgs: 7488 total_bytes: 299520 + switch_0_inlinks: 2 switch_0_outlinks: 2 links_utilized_percent_switch_0: 0.157808 links_utilized_percent_switch_0_link_0: 0.0633825 bw: 640000 base_latency: 1 links_utilized_percent_switch_0_link_1: 0.252233 bw: 160000 base_latency: 1 - outgoing_messages_switch_0_link_0_Response_Data: 626 45072 [ 0 626 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_0_Writeback_Control: 622 4976 [ 0 0 622 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Control: 626 5008 [ 626 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Data: 622 44784 [ 622 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_0_Response_Data: 626 45072 [ 0 0 0 0 626 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_0_Writeback_Control: 622 4976 [ 0 0 0 622 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Control: 626 5008 [ 0 0 626 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Data: 622 44784 [ 0 0 622 0 0 0 0 0 0 0 ] base_latency: 1 switch_1_inlinks: 2 switch_1_outlinks: 2 @@ -141,10 +154,10 @@ links_utilized_percent_switch_1: 0.158294 links_utilized_percent_switch_1_link_0: 0.0630582 bw: 640000 base_latency: 1 links_utilized_percent_switch_1_link_1: 0.25353 bw: 160000 base_latency: 1 - outgoing_messages_switch_1_link_0_Control: 626 5008 [ 626 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_0_Data: 622 44784 [ 622 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_Response_Data: 626 45072 [ 0 626 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_Writeback_Control: 622 4976 [ 0 0 622 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_Control: 626 5008 [ 0 0 626 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_Data: 622 44784 [ 0 0 622 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Response_Data: 626 45072 [ 0 0 0 0 626 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Writeback_Control: 622 4976 [ 0 0 0 622 0 0 0 0 0 0 ] base_latency: 1 switch_2_inlinks: 2 switch_2_outlinks: 2 @@ -152,66 +165,64 @@ links_utilized_percent_switch_2: 0.252881 links_utilized_percent_switch_2_link_0: 0.25353 bw: 160000 base_latency: 1 links_utilized_percent_switch_2_link_1: 0.252233 bw: 160000 base_latency: 1 - outgoing_messages_switch_2_link_0_Response_Data: 626 45072 [ 0 626 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_0_Writeback_Control: 622 4976 [ 0 0 622 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_1_Control: 626 5008 [ 626 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_1_Data: 622 44784 [ 622 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_0_Response_Data: 626 45072 [ 0 0 0 0 626 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_0_Writeback_Control: 622 4976 [ 0 0 0 622 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Control: 626 5008 [ 0 0 626 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Data: 622 44784 [ 0 0 622 0 0 0 0 0 0 0 ] base_latency: 1 -Cache Stats: system.ruby.network.topology.ext_links0.ext_node.sequencer.icache - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_misses: 626 - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_demand_misses: 626 - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_hw_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_misses_per_transaction: inf +Cache Stats: system.ruby.cpu_ruby_ports.dcache + system.ruby.cpu_ruby_ports.dcache_total_misses: 626 + system.ruby.cpu_ruby_ports.dcache_total_demand_misses: 626 + system.ruby.cpu_ruby_ports.dcache_total_prefetches: 0 + system.ruby.cpu_ruby_ports.dcache_total_sw_prefetches: 0 + system.ruby.cpu_ruby_ports.dcache_total_hw_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_type_LD: 39.1374% - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_type_ST: 13.4185% - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_type_IFETCH: 47.4441% + system.ruby.cpu_ruby_ports.dcache_request_type_LD: 39.1374% + system.ruby.cpu_ruby_ports.dcache_request_type_ST: 13.4185% + system.ruby.cpu_ruby_ports.dcache_request_type_IFETCH: 47.4441% - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_access_mode_type_SupervisorMode: 626 100% - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_size: [binsize: 1 max: 8 count: 626 average: 5.71885 | standard deviation: 1.98192 | 0 0 0 0 357 0 0 0 269 ] + system.ruby.cpu_ruby_ports.dcache_access_mode_type_SupervisorMode: 626 100% - --- L1Cache 0 --- + --- L1Cache --- - Event Counts - -Load 415 -Ifetch 2585 -Store 294 -Data 626 -Fwd_GETX 0 -Inv 0 -Replacement 622 -Writeback_Ack 622 -Writeback_Nack 0 +Load [415 ] 415 +Ifetch [2585 ] 2585 +Store [294 ] 294 +Data [626 ] 626 +Fwd_GETX [0 ] 0 +Inv [0 ] 0 +Replacement [622 ] 622 +Writeback_Ack [622 ] 622 +Writeback_Nack [0 ] 0 - Transitions - -I Load 245 -I Ifetch 297 -I Store 84 -I Inv 0 <-- -I Replacement 0 <-- +I Load [245 ] 245 +I Ifetch [297 ] 297 +I Store [84 ] 84 +I Inv [0 ] 0 +I Replacement [0 ] 0 -II Writeback_Nack 0 <-- +II Writeback_Nack [0 ] 0 -M Load 170 -M Ifetch 2288 -M Store 210 -M Fwd_GETX 0 <-- -M Inv 0 <-- -M Replacement 622 +M Load [170 ] 170 +M Ifetch [2288 ] 2288 +M Store [210 ] 210 +M Fwd_GETX [0 ] 0 +M Inv [0 ] 0 +M Replacement [622 ] 622 -MI Fwd_GETX 0 <-- -MI Inv 0 <-- -MI Writeback_Ack 622 -MI Writeback_Nack 0 <-- +MI Fwd_GETX [0 ] 0 +MI Inv [0 ] 0 +MI Writeback_Ack [622 ] 622 +MI Writeback_Nack [0 ] 0 -MII Fwd_GETX 0 <-- +MII Fwd_GETX [0 ] 0 -IS Data 542 +IS Data [542 ] 542 -IM Data 84 +IM Data [84 ] 84 -Memory controller: system.ruby.network.topology.ext_links1.ext_node.memBuffer: +Memory controller: system.dir_cntrl0.memBuffer: memory_total_requests: 1248 memory_reads: 626 memory_writes: 622 @@ -231,70 +242,69 @@ Memory controller: system.ruby.network.topology.ext_links1.ext_node.memBuffer: memory_stalls_for_read_read_turnaround: 0 accesses_per_bank: 55 40 0 100 42 42 88 45 14 10 14 10 46 82 38 6 22 14 14 48 20 52 26 92 34 10 12 24 28 44 38 138 - --- Directory 0 --- + --- Directory --- - Event Counts - -GETX 626 -GETS 0 -PUTX 622 -PUTX_NotOwner 0 -DMA_READ 0 -DMA_WRITE 0 -Memory_Data 626 -Memory_Ack 622 +GETX [626 ] 626 +GETS [0 ] 0 +PUTX [622 ] 622 +PUTX_NotOwner [0 ] 0 +DMA_READ [0 ] 0 +DMA_WRITE [0 ] 0 +Memory_Data [626 ] 626 +Memory_Ack [622 ] 622 - Transitions - -I GETX 626 -I PUTX_NotOwner 0 <-- -I DMA_READ 0 <-- -I DMA_WRITE 0 <-- - -M GETX 0 <-- -M PUTX 622 -M PUTX_NotOwner 0 <-- -M DMA_READ 0 <-- -M DMA_WRITE 0 <-- - -M_DRD GETX 0 <-- -M_DRD PUTX 0 <-- - -M_DWR GETX 0 <-- -M_DWR PUTX 0 <-- - -M_DWRI GETX 0 <-- -M_DWRI Memory_Ack 0 <-- - -M_DRDI GETX 0 <-- -M_DRDI Memory_Ack 0 <-- - -IM GETX 0 <-- -IM GETS 0 <-- -IM PUTX 0 <-- -IM PUTX_NotOwner 0 <-- -IM DMA_READ 0 <-- -IM DMA_WRITE 0 <-- -IM Memory_Data 626 - -MI GETX 0 <-- -MI GETS 0 <-- -MI PUTX 0 <-- -MI PUTX_NotOwner 0 <-- -MI DMA_READ 0 <-- -MI DMA_WRITE 0 <-- -MI Memory_Ack 622 - -ID GETX 0 <-- -ID GETS 0 <-- -ID PUTX 0 <-- -ID PUTX_NotOwner 0 <-- -ID DMA_READ 0 <-- -ID DMA_WRITE 0 <-- -ID Memory_Data 0 <-- - -ID_W GETX 0 <-- -ID_W GETS 0 <-- -ID_W PUTX 0 <-- -ID_W PUTX_NotOwner 0 <-- -ID_W DMA_READ 0 <-- -ID_W DMA_WRITE 0 <-- -ID_W Memory_Ack 0 <-- - +I GETX [626 ] 626 +I PUTX_NotOwner [0 ] 0 +I DMA_READ [0 ] 0 +I DMA_WRITE [0 ] 0 + +M GETX [0 ] 0 +M PUTX [622 ] 622 +M PUTX_NotOwner [0 ] 0 +M DMA_READ [0 ] 0 +M DMA_WRITE [0 ] 0 + +M_DRD GETX [0 ] 0 +M_DRD PUTX [0 ] 0 + +M_DWR GETX [0 ] 0 +M_DWR PUTX [0 ] 0 + +M_DWRI GETX [0 ] 0 +M_DWRI Memory_Ack [0 ] 0 + +M_DRDI GETX [0 ] 0 +M_DRDI Memory_Ack [0 ] 0 + +IM GETX [0 ] 0 +IM GETS [0 ] 0 +IM PUTX [0 ] 0 +IM PUTX_NotOwner [0 ] 0 +IM DMA_READ [0 ] 0 +IM DMA_WRITE [0 ] 0 +IM Memory_Data [626 ] 626 + +MI GETX [0 ] 0 +MI GETS [0 ] 0 +MI PUTX [0 ] 0 +MI PUTX_NotOwner [0 ] 0 +MI DMA_READ [0 ] 0 +MI DMA_WRITE [0 ] 0 +MI Memory_Ack [622 ] 622 + +ID GETX [0 ] 0 +ID GETS [0 ] 0 +ID PUTX [0 ] 0 +ID PUTX_NotOwner [0 ] 0 +ID DMA_READ [0 ] 0 +ID DMA_WRITE [0 ] 0 +ID Memory_Data [0 ] 0 + +ID_W GETX [0 ] 0 +ID_W GETS [0 ] 0 +ID_W PUTX [0 ] 0 +ID_W PUTX_NotOwner [0 ] 0 +ID_W DMA_READ [0 ] 0 +ID_W DMA_WRITE [0 ] 0 +ID_W Memory_Ack
\ No newline at end of file diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/simout b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/simout index 994f7ec2d..6eeddaa9f 100755 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/simout +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jan 27 2010 22:23:20 -M5 revision 6068d4fc30d3+ 6931+ default qtip tip brad/rubycfg_regress_udpate -M5 started Jan 28 2010 10:26:06 -M5 executing on svvint07 +M5 compiled Feb 6 2011 20:42:22 +M5 revision b885adc82ab4+ 7924+ default tip qtip brad/regress_updates +M5 started Feb 6 2011 20:42:39 +M5 executing on SC2B0617 command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-timing-ruby -re tests/run.py build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-timing-ruby Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt index dd60f4239..ef8e53c20 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 51538 # Simulator instruction rate (inst/s) -host_mem_usage 214632 # Number of bytes of host memory used +host_inst_rate 50430 # Simulator instruction rate (inst/s) +host_mem_usage 213936 # Number of bytes of host memory used host_seconds 0.05 # Real time elapsed on the host -host_tick_rate 2467461 # Simulator tick rate (ticks/s) +host_tick_rate 2406014 # Simulator tick rate (ticks/s) sim_freq 1000000000 # Frequency of simulated ticks sim_insts 2577 # Number of instructions simulated sim_seconds 0.000123 # Number of seconds simulated @@ -43,8 +43,24 @@ system.cpu.itb.write_hits 0 # DT system.cpu.itb.write_misses 0 # DTB write misses system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.numCycles 123378 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.num_busy_cycles 123378 # Number of busy cycles +system.cpu.num_conditional_control_insts 238 # number of instructions that are conditional controls +system.cpu.num_fp_alu_accesses 6 # Number of float alu accesses +system.cpu.num_fp_insts 6 # number of float instructions +system.cpu.num_fp_register_reads 6 # number of times the floating registers were read +system.cpu.num_fp_register_writes 0 # number of times the floating registers were written +system.cpu.num_func_calls 140 # number of times a function call or return occured +system.cpu.num_idle_cycles 0 # Number of idle cycles system.cpu.num_insts 2577 # Number of instructions executed -system.cpu.num_refs 717 # Number of memory references +system.cpu.num_int_alu_accesses 2375 # Number of integer alu accesses +system.cpu.num_int_insts 2375 # number of integer instructions +system.cpu.num_int_register_reads 2998 # number of times the integer registers were read +system.cpu.num_int_register_writes 1768 # number of times the integer registers were written +system.cpu.num_load_insts 419 # Number of load instructions +system.cpu.num_mem_refs 717 # number of memory refs +system.cpu.num_store_insts 298 # Number of store instructions system.cpu.workload.PROG:num_syscalls 4 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini index c142fa659..f6e43920a 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini @@ -1,13 +1,22 @@ [root] type=Root children=system -dummy=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem mem_mode=atomic physmem=system.physmem +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 [system.cpu] type=TimingSimpleCPU @@ -157,7 +166,7 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/regression/test-progs/hello/bin/alpha/tru64/hello +executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/alpha/tru64/hello gid=100 input=cin max_stack_size=67108864 diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/simout b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/simout index 6dd6e994b..c6d73c335 100755 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/simout +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/simout @@ -1,5 +1,3 @@ -Redirecting stdout to build/ALPHA_SE/tests/opt/quick/00.hello/alpha/tru64/simple-timing/simout -Redirecting stderr to build/ALPHA_SE/tests/opt/quick/00.hello/alpha/tru64/simple-timing/simerr M5 Simulator System Copyright (c) 2001-2008 @@ -7,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Aug 26 2010 11:51:59 -M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix -M5 started Aug 26 2010 11:52:05 -M5 executing on zizzer -command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/opt/quick/00.hello/alpha/tru64/simple-timing +M5 compiled Feb 6 2011 20:42:22 +M5 revision b885adc82ab4+ 7924+ default tip qtip brad/regress_updates +M5 started Feb 6 2011 20:43:01 +M5 executing on SC2B0617 +command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stats.txt b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stats.txt index f08ca087e..3dca8b0f4 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 97740 # Simulator instruction rate (inst/s) -host_mem_usage 203308 # Number of bytes of host memory used -host_seconds 0.03 # Real time elapsed on the host -host_tick_rate 629585132 # Simulator tick rate (ticks/s) +host_inst_rate 391701 # Simulator instruction rate (inst/s) +host_mem_usage 203856 # Number of bytes of host memory used +host_seconds 0.01 # Real time elapsed on the host +host_tick_rate 2449817385 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 2577 # Number of instructions simulated sim_seconds 0.000017 # Number of seconds simulated @@ -226,8 +226,24 @@ system.cpu.l2cache.warmup_cycle 0 # Cy system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.numCycles 33538 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.num_busy_cycles 33538 # Number of busy cycles +system.cpu.num_conditional_control_insts 238 # number of instructions that are conditional controls +system.cpu.num_fp_alu_accesses 6 # Number of float alu accesses +system.cpu.num_fp_insts 6 # number of float instructions +system.cpu.num_fp_register_reads 6 # number of times the floating registers were read +system.cpu.num_fp_register_writes 0 # number of times the floating registers were written +system.cpu.num_func_calls 140 # number of times a function call or return occured +system.cpu.num_idle_cycles 0 # Number of idle cycles system.cpu.num_insts 2577 # Number of instructions executed -system.cpu.num_refs 717 # Number of memory references +system.cpu.num_int_alu_accesses 2375 # Number of integer alu accesses +system.cpu.num_int_insts 2375 # number of integer instructions +system.cpu.num_int_register_reads 2998 # number of times the integer registers were read +system.cpu.num_int_register_writes 1768 # number of times the integer registers were written +system.cpu.num_load_insts 419 # Number of load instructions +system.cpu.num_mem_refs 717 # number of memory refs +system.cpu.num_store_insts 298 # Number of store instructions system.cpu.workload.PROG:num_syscalls 4 # Number of system calls ---------- End Simulation Statistics ---------- |