diff options
Diffstat (limited to 'tests/quick/00.hello/ref/alpha/tru64')
37 files changed, 0 insertions, 8174 deletions
diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini deleted file mode 100644 index f0e8b9ebf..000000000 --- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini +++ /dev/null @@ -1,535 +0,0 @@ -[root] -type=Root -children=system -time_sync_enable=false -time_sync_period=100000000000 -time_sync_spin_threshold=100000000 - -[system] -type=System -children=cpu membus physmem -mem_mode=atomic -memories=system.physmem -num_work_ids=16 -physmem=system.physmem -work_begin_ckpt_count=0 -work_begin_cpu_id_exit=-1 -work_begin_exit_count=0 -work_cpus_ckpt_count=0 -work_end_ckpt_count=0 -work_end_exit_count=0 -work_item_id=-1 -system_port=system.membus.port[0] - -[system.cpu] -type=DerivO3CPU -children=dcache dtb fuPool icache itb l2cache toL2Bus tracer workload -BTBEntries=4096 -BTBTagSize=16 -LFSTSize=1024 -LQEntries=32 -LSQCheckLoads=true -LSQDepCheckShift=4 -RASSize=16 -SQEntries=32 -SSITSize=1024 -activity=0 -backComSize=5 -cachePorts=200 -checker=Null -choiceCtrBits=2 -choicePredictorSize=8192 -clock=500 -commitToDecodeDelay=1 -commitToFetchDelay=1 -commitToIEWDelay=1 -commitToRenameDelay=1 -commitWidth=8 -cpu_id=0 -decodeToFetchDelay=1 -decodeToRenameDelay=1 -decodeWidth=8 -defer_registration=false -dispatchWidth=8 -do_checkpoint_insts=true -do_statistics_insts=true -dtb=system.cpu.dtb -fetchToDecodeDelay=1 -fetchTrapLatency=1 -fetchWidth=8 -forwardComSize=5 -fuPool=system.cpu.fuPool -function_trace=false -function_trace_start=0 -globalCtrBits=2 -globalHistoryBits=13 -globalPredictorSize=8192 -iewToCommitDelay=1 -iewToDecodeDelay=1 -iewToFetchDelay=1 -iewToRenameDelay=1 -instShiftAmt=2 -issueToExecuteDelay=1 -issueWidth=8 -itb=system.cpu.itb -localCtrBits=2 -localHistoryBits=11 -localHistoryTableSize=2048 -localPredictorSize=2048 -max_insts_all_threads=0 -max_insts_any_thread=0 -max_loads_all_threads=0 -max_loads_any_thread=0 -numIQEntries=64 -numPhysFloatRegs=256 -numPhysIntRegs=256 -numROBEntries=192 -numRobs=1 -numThreads=1 -phase=0 -predType=tournament -progress_interval=0 -renameToDecodeDelay=1 -renameToFetchDelay=1 -renameToIEWDelay=2 -renameToROBDelay=1 -renameWidth=8 -smtCommitPolicy=RoundRobin -smtFetchPolicy=SingleThread -smtIQPolicy=Partitioned -smtIQThreshold=100 -smtLSQPolicy=Partitioned -smtLSQThreshold=100 -smtNumFetchingThreads=1 -smtROBPolicy=Partitioned -smtROBThreshold=100 -squashWidth=8 -store_set_clear_period=250000 -system=system -tracer=system.cpu.tracer -trapLatency=13 -wbDepth=1 -wbWidth=8 -workload=system.cpu.workload -dcache_port=system.cpu.dcache.cpu_side -icache_port=system.cpu.icache.cpu_side - -[system.cpu.dcache] -type=BaseCache -addr_range=0:18446744073709551615 -assoc=2 -block_size=64 -forward_snoops=true -hash_delay=1 -is_top_level=true -latency=1000 -max_miss_count=0 -mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 -prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 -prioritizeRequests=false -repl=Null -size=262144 -subblock_size=0 -tgts_per_mshr=20 -trace_addr=0 -two_queue=false -write_buffers=8 -cpu_side=system.cpu.dcache_port -mem_side=system.cpu.toL2Bus.port[1] - -[system.cpu.dtb] -type=AlphaTLB -size=64 - -[system.cpu.fuPool] -type=FUPool -children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 -FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 - -[system.cpu.fuPool.FUList0] -type=FUDesc -children=opList -count=6 -opList=system.cpu.fuPool.FUList0.opList - -[system.cpu.fuPool.FUList0.opList] -type=OpDesc -issueLat=1 -opClass=IntAlu -opLat=1 - -[system.cpu.fuPool.FUList1] -type=FUDesc -children=opList0 opList1 -count=2 -opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 - -[system.cpu.fuPool.FUList1.opList0] -type=OpDesc -issueLat=1 -opClass=IntMult -opLat=3 - -[system.cpu.fuPool.FUList1.opList1] -type=OpDesc -issueLat=19 -opClass=IntDiv -opLat=20 - -[system.cpu.fuPool.FUList2] -type=FUDesc -children=opList0 opList1 opList2 -count=4 -opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 - -[system.cpu.fuPool.FUList2.opList0] -type=OpDesc -issueLat=1 -opClass=FloatAdd -opLat=2 - -[system.cpu.fuPool.FUList2.opList1] -type=OpDesc -issueLat=1 -opClass=FloatCmp -opLat=2 - -[system.cpu.fuPool.FUList2.opList2] -type=OpDesc -issueLat=1 -opClass=FloatCvt -opLat=2 - -[system.cpu.fuPool.FUList3] -type=FUDesc -children=opList0 opList1 opList2 -count=2 -opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 - -[system.cpu.fuPool.FUList3.opList0] -type=OpDesc -issueLat=1 -opClass=FloatMult -opLat=4 - -[system.cpu.fuPool.FUList3.opList1] -type=OpDesc -issueLat=12 -opClass=FloatDiv -opLat=12 - -[system.cpu.fuPool.FUList3.opList2] -type=OpDesc -issueLat=24 -opClass=FloatSqrt -opLat=24 - -[system.cpu.fuPool.FUList4] -type=FUDesc -children=opList -count=0 -opList=system.cpu.fuPool.FUList4.opList - -[system.cpu.fuPool.FUList4.opList] -type=OpDesc -issueLat=1 -opClass=MemRead -opLat=1 - -[system.cpu.fuPool.FUList5] -type=FUDesc -children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 -count=4 -opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 - -[system.cpu.fuPool.FUList5.opList00] -type=OpDesc -issueLat=1 -opClass=SimdAdd -opLat=1 - -[system.cpu.fuPool.FUList5.opList01] -type=OpDesc -issueLat=1 -opClass=SimdAddAcc -opLat=1 - -[system.cpu.fuPool.FUList5.opList02] -type=OpDesc -issueLat=1 -opClass=SimdAlu -opLat=1 - -[system.cpu.fuPool.FUList5.opList03] -type=OpDesc -issueLat=1 -opClass=SimdCmp -opLat=1 - -[system.cpu.fuPool.FUList5.opList04] -type=OpDesc -issueLat=1 -opClass=SimdCvt -opLat=1 - -[system.cpu.fuPool.FUList5.opList05] -type=OpDesc -issueLat=1 -opClass=SimdMisc -opLat=1 - -[system.cpu.fuPool.FUList5.opList06] -type=OpDesc -issueLat=1 -opClass=SimdMult -opLat=1 - -[system.cpu.fuPool.FUList5.opList07] -type=OpDesc -issueLat=1 -opClass=SimdMultAcc -opLat=1 - -[system.cpu.fuPool.FUList5.opList08] -type=OpDesc -issueLat=1 -opClass=SimdShift -opLat=1 - -[system.cpu.fuPool.FUList5.opList09] -type=OpDesc -issueLat=1 -opClass=SimdShiftAcc -opLat=1 - -[system.cpu.fuPool.FUList5.opList10] -type=OpDesc -issueLat=1 -opClass=SimdSqrt -opLat=1 - -[system.cpu.fuPool.FUList5.opList11] -type=OpDesc -issueLat=1 -opClass=SimdFloatAdd -opLat=1 - -[system.cpu.fuPool.FUList5.opList12] -type=OpDesc -issueLat=1 -opClass=SimdFloatAlu -opLat=1 - -[system.cpu.fuPool.FUList5.opList13] -type=OpDesc -issueLat=1 -opClass=SimdFloatCmp -opLat=1 - -[system.cpu.fuPool.FUList5.opList14] -type=OpDesc -issueLat=1 -opClass=SimdFloatCvt -opLat=1 - -[system.cpu.fuPool.FUList5.opList15] -type=OpDesc -issueLat=1 -opClass=SimdFloatDiv -opLat=1 - -[system.cpu.fuPool.FUList5.opList16] -type=OpDesc -issueLat=1 -opClass=SimdFloatMisc -opLat=1 - -[system.cpu.fuPool.FUList5.opList17] -type=OpDesc -issueLat=1 -opClass=SimdFloatMult -opLat=1 - -[system.cpu.fuPool.FUList5.opList18] -type=OpDesc -issueLat=1 -opClass=SimdFloatMultAcc -opLat=1 - -[system.cpu.fuPool.FUList5.opList19] -type=OpDesc -issueLat=1 -opClass=SimdFloatSqrt -opLat=1 - -[system.cpu.fuPool.FUList6] -type=FUDesc -children=opList -count=0 -opList=system.cpu.fuPool.FUList6.opList - -[system.cpu.fuPool.FUList6.opList] -type=OpDesc -issueLat=1 -opClass=MemWrite -opLat=1 - -[system.cpu.fuPool.FUList7] -type=FUDesc -children=opList0 opList1 -count=4 -opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 - -[system.cpu.fuPool.FUList7.opList0] -type=OpDesc -issueLat=1 -opClass=MemRead -opLat=1 - -[system.cpu.fuPool.FUList7.opList1] -type=OpDesc -issueLat=1 -opClass=MemWrite -opLat=1 - -[system.cpu.fuPool.FUList8] -type=FUDesc -children=opList -count=1 -opList=system.cpu.fuPool.FUList8.opList - -[system.cpu.fuPool.FUList8.opList] -type=OpDesc -issueLat=3 -opClass=IprAccess -opLat=3 - -[system.cpu.icache] -type=BaseCache -addr_range=0:18446744073709551615 -assoc=2 -block_size=64 -forward_snoops=true -hash_delay=1 -is_top_level=true -latency=1000 -max_miss_count=0 -mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 -prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 -prioritizeRequests=false -repl=Null -size=131072 -subblock_size=0 -tgts_per_mshr=20 -trace_addr=0 -two_queue=false -write_buffers=8 -cpu_side=system.cpu.icache_port -mem_side=system.cpu.toL2Bus.port[0] - -[system.cpu.itb] -type=AlphaTLB -size=48 - -[system.cpu.l2cache] -type=BaseCache -addr_range=0:18446744073709551615 -assoc=2 -block_size=64 -forward_snoops=true -hash_delay=1 -is_top_level=false -latency=1000 -max_miss_count=0 -mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 -prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 -prioritizeRequests=false -repl=Null -size=2097152 -subblock_size=0 -tgts_per_mshr=5 -trace_addr=0 -two_queue=false -write_buffers=8 -cpu_side=system.cpu.toL2Bus.port[2] -mem_side=system.membus.port[2] - -[system.cpu.toL2Bus] -type=Bus -block_size=64 -bus_id=0 -clock=1000 -header_cycles=1 -use_default_range=false -width=64 -port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side - -[system.cpu.tracer] -type=ExeTracer - -[system.cpu.workload] -type=LiveProcess -cmd=hello -cwd= -egid=100 -env= -errout=cerr -euid=100 -executable=/dist/m5/regression/test-progs/hello/bin/alpha/tru64/hello -gid=100 -input=cin -max_stack_size=67108864 -output=cout -pid=100 -ppid=99 -simpoint=0 -system=system -uid=100 - -[system.membus] -type=Bus -block_size=64 -bus_id=0 -clock=1000 -header_cycles=1 -use_default_range=false -width=64 -port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side - -[system.physmem] -type=PhysicalMemory -file= -latency=30000 -latency_var=0 -null=false -range=0:134217727 -zero=false -port=system.membus.port[1] - diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/simerr b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/simerr deleted file mode 100755 index 27f858d8f..000000000 --- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/simerr +++ /dev/null @@ -1,4 +0,0 @@ -warn: Sockets disabled, not accepting gdb connections -warn: Prefetch instructions in Alpha do not do anything -warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...) -hack: be nice to actually delete the event here diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/simout b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/simout deleted file mode 100755 index 2afd9a6f8..000000000 --- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/simout +++ /dev/null @@ -1,12 +0,0 @@ -gem5 Simulator System. http://gem5.org -gem5 is copyrighted software; use the --copyright option for details. - -gem5 compiled Jan 23 2012 04:48:33 -gem5 started Jan 23 2012 04:59:27 -gem5 executing on zizzer -command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/quick/00.hello/alpha/tru64/o3-timing -Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -info: Increasing stack size by one page. -Hello world! -Exiting @ tick 6833000 because target called exit() diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt deleted file mode 100644 index d94c5613d..000000000 --- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt +++ /dev/null @@ -1,505 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 0.000007 # Number of seconds simulated -sim_ticks 6833000 # Number of ticks simulated -final_tick 6833000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 46364 # Simulator instruction rate (inst/s) -host_tick_rate 132671945 # Simulator tick rate (ticks/s) -host_mem_usage 207164 # Number of bytes of host memory used -host_seconds 0.05 # Real time elapsed on the host -sim_insts 2387 # Number of instructions simulated -system.physmem.bytes_read 17280 # Number of bytes read from this memory -system.physmem.bytes_inst_read 11840 # Number of instructions bytes read from this memory -system.physmem.bytes_written 0 # Number of bytes written to this memory -system.physmem.num_reads 270 # Number of read requests responded to by this memory -system.physmem.num_writes 0 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 2528903849 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 1732767452 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total 2528903849 # Total bandwidth to/from this memory (bytes/s) -system.cpu.dtb.fetch_hits 0 # ITB hits -system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.fetch_acv 0 # ITB acv -system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 679 # DTB read hits -system.cpu.dtb.read_misses 26 # DTB read misses -system.cpu.dtb.read_acv 1 # DTB read access violations -system.cpu.dtb.read_accesses 705 # DTB read accesses -system.cpu.dtb.write_hits 356 # DTB write hits -system.cpu.dtb.write_misses 18 # DTB write misses -system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 374 # DTB write accesses -system.cpu.dtb.data_hits 1035 # DTB hits -system.cpu.dtb.data_misses 44 # DTB misses -system.cpu.dtb.data_acv 1 # DTB access violations -system.cpu.dtb.data_accesses 1079 # DTB accesses -system.cpu.itb.fetch_hits 941 # ITB hits -system.cpu.itb.fetch_misses 30 # ITB misses -system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 971 # ITB accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.read_acv 0 # DTB read access violations -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.write_acv 0 # DTB write access violations -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.data_hits 0 # DTB hits -system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.data_acv 0 # DTB access violations -system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.workload.num_syscalls 4 # Number of system calls -system.cpu.numCycles 13667 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 1038 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 518 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 226 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 732 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 219 # Number of BTB hits -system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 208 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 34 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 3757 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 6399 # Number of instructions fetch has processed -system.cpu.fetch.Branches 1038 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 427 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 1112 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 750 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 212 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 17 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 785 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 941 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 156 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 6383 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.002507 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.418848 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 5271 82.58% 82.58% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 60 0.94% 83.52% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 117 1.83% 85.35% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 94 1.47% 86.82% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 140 2.19% 89.02% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 57 0.89% 89.91% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 55 0.86% 90.77% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 64 1.00% 91.78% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 525 8.22% 100.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 6383 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.075949 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.468208 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 4647 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 226 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 1081 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 6 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 423 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 158 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 80 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 5725 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 284 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 423 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 4742 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 57 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 147 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 995 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 19 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 5471 # Number of instructions processed by rename -system.cpu.rename.LSQFullEvents 14 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 3940 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 6152 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 6140 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 12 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 1768 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 2172 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 8 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 6 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 107 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 881 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 453 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 3 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 3 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 4657 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 6 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 3881 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 49 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 2074 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 1177 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 6383 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.608021 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.298413 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 4813 75.40% 75.40% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 542 8.49% 83.89% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 388 6.08% 89.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 264 4.14% 94.11% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 199 3.12% 97.23% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 107 1.68% 98.90% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 55 0.86% 99.77% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 10 0.16% 99.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 5 0.08% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 6383 # Number of insts issued each cycle -system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 1 2.44% 2.44% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 2.44% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 2.44% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.44% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.44% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.44% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 2.44% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.44% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 2.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 2.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.44% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 17 41.46% 43.90% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 23 56.10% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 2767 71.30% 71.30% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 1 0.03% 71.32% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 71.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 71.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 71.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 71.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 71.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 71.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 71.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 71.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 71.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 71.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 71.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 71.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 71.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 71.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 71.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 71.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 71.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 71.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 71.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 71.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 71.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 71.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 71.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 71.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 71.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 71.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 71.32% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 733 18.89% 90.21% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 380 9.79% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 3881 # Type of FU issued -system.cpu.iq.rate 0.283969 # Inst issue rate -system.cpu.iq.fu_busy_cnt 41 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.010564 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 14222 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 6735 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 3573 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 13 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 6 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 6 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 3915 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 7 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 35 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 466 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 5 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 159 # Number of stores squashed -system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 423 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 44 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 6 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 5001 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 64 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 881 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 453 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 6 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 3 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 5 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 54 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 121 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 175 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 3749 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 706 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 132 # Number of squashed instructions skipped in execute -system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 338 # number of nop insts executed -system.cpu.iew.exec_refs 1080 # number of memory reference insts executed -system.cpu.iew.exec_branches 629 # Number of branches executed -system.cpu.iew.exec_stores 374 # Number of stores executed -system.cpu.iew.exec_rate 0.274310 # Inst execution rate -system.cpu.iew.wb_sent 3647 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 3579 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1702 # num instructions producing a value -system.cpu.iew.wb_consumers 2165 # num instructions consuming a value -system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.261872 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.786143 # average fanout of values written-back -system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 2576 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 2416 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 4 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 149 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 5960 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.432215 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.290536 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 5068 85.03% 85.03% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 222 3.72% 88.76% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 314 5.27% 94.03% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 119 2.00% 96.02% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 70 1.17% 97.20% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 53 0.89% 98.09% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 34 0.57% 98.66% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 20 0.34% 98.99% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 60 1.01% 100.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 5960 # Number of insts commited each cycle -system.cpu.commit.count 2576 # Number of instructions committed -system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 709 # Number of memory references committed -system.cpu.commit.loads 415 # Number of loads committed -system.cpu.commit.membars 0 # Number of memory barriers committed -system.cpu.commit.branches 396 # Number of branches committed -system.cpu.commit.fp_insts 6 # Number of committed floating point instructions. -system.cpu.commit.int_insts 2367 # Number of committed integer instructions. -system.cpu.commit.function_calls 71 # Number of function calls committed. -system.cpu.commit.bw_lim_events 60 # number cycles where commit BW limit reached -system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 10645 # The number of ROB reads -system.cpu.rob.rob_writes 10410 # The number of ROB writes -system.cpu.timesIdled 139 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 7284 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 2387 # Number of Instructions Simulated -system.cpu.committedInsts_total 2387 # Number of Instructions Simulated -system.cpu.cpi 5.725597 # CPI: Cycles Per Instruction -system.cpu.cpi_total 5.725597 # CPI: Total CPI of All Threads -system.cpu.ipc 0.174654 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.174654 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 4520 # number of integer regfile reads -system.cpu.int_regfile_writes 2768 # number of integer regfile writes -system.cpu.fp_regfile_reads 6 # number of floating regfile reads -system.cpu.misc_regfile_reads 1 # number of misc regfile reads -system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 91.574139 # Cycle average of tags in use -system.cpu.icache.total_refs 700 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 185 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 3.783784 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 91.574139 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.044714 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 700 # number of ReadReq hits -system.cpu.icache.demand_hits 700 # number of demand (read+write) hits -system.cpu.icache.overall_hits 700 # number of overall hits -system.cpu.icache.ReadReq_misses 241 # number of ReadReq misses -system.cpu.icache.demand_misses 241 # number of demand (read+write) misses -system.cpu.icache.overall_misses 241 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 8777500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 8777500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 8777500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 941 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 941 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 941 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.256111 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.256111 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.256111 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 36421.161826 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 36421.161826 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 36421.161826 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 56 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 56 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 56 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 185 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 185 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 185 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 6554500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 6554500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 6554500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.196599 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.196599 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.196599 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 35429.729730 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 35429.729730 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 35429.729730 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 45.439198 # Cycle average of tags in use -system.cpu.dcache.total_refs 765 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 85 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 9 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 45.439198 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.011094 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 543 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 222 # number of WriteReq hits -system.cpu.dcache.demand_hits 765 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 765 # number of overall hits -system.cpu.dcache.ReadReq_misses 101 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 72 # number of WriteReq misses -system.cpu.dcache.demand_misses 173 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 173 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 3605000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 2816500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency 6421500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 6421500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 644 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses 294 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 938 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 938 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.156832 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.244898 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate 0.184435 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.184435 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 35693.069307 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 39118.055556 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency 37118.497110 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 37118.497110 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 40 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 48 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits 88 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 88 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 61 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 24 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 85 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 85 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 2169000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 872000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 3041000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 3041000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.094720 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate 0.081633 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.090618 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.090618 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 35557.377049 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 36333.333333 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 35776.470588 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 35776.470588 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 120.203882 # Cycle average of tags in use -system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 246 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 120.203882 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.003668 # Average percentage of cache occupancy -system.cpu.l2cache.demand_hits 0 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 0 # number of overall hits -system.cpu.l2cache.ReadReq_misses 246 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses 24 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 270 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 270 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 8447500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 831000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 9278500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 9278500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 246 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 24 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 270 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 270 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 1 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 1 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 34339.430894 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 34625 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 34364.814815 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 34364.814815 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 246 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 24 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 270 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 270 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 7661500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 756000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 8417500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 8417500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31144.308943 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31500 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31175.925926 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31175.925926 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate - ----------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.ini b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.ini deleted file mode 100644 index fad1e21b6..000000000 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.ini +++ /dev/null @@ -1,102 +0,0 @@ -[root] -type=Root -children=system -time_sync_enable=false -time_sync_period=100000000000 -time_sync_spin_threshold=100000000 - -[system] -type=System -children=cpu membus physmem -mem_mode=atomic -memories=system.physmem -num_work_ids=16 -physmem=system.physmem -work_begin_ckpt_count=0 -work_begin_cpu_id_exit=-1 -work_begin_exit_count=0 -work_cpus_ckpt_count=0 -work_end_ckpt_count=0 -work_end_exit_count=0 -work_item_id=-1 -system_port=system.membus.port[0] - -[system.cpu] -type=AtomicSimpleCPU -children=dtb itb tracer workload -checker=Null -clock=500 -cpu_id=0 -defer_registration=false -do_checkpoint_insts=true -do_statistics_insts=true -dtb=system.cpu.dtb -function_trace=false -function_trace_start=0 -itb=system.cpu.itb -max_insts_all_threads=0 -max_insts_any_thread=0 -max_loads_all_threads=0 -max_loads_any_thread=0 -numThreads=1 -phase=0 -progress_interval=0 -simulate_data_stalls=false -simulate_inst_stalls=false -system=system -tracer=system.cpu.tracer -width=1 -workload=system.cpu.workload -dcache_port=system.membus.port[3] -icache_port=system.membus.port[2] - -[system.cpu.dtb] -type=AlphaTLB -size=64 - -[system.cpu.itb] -type=AlphaTLB -size=48 - -[system.cpu.tracer] -type=ExeTracer - -[system.cpu.workload] -type=LiveProcess -cmd=hello -cwd= -egid=100 -env= -errout=cerr -euid=100 -executable=/dist/m5/regression/test-progs/hello/bin/alpha/tru64/hello -gid=100 -input=cin -max_stack_size=67108864 -output=cout -pid=100 -ppid=99 -simpoint=0 -system=system -uid=100 - -[system.membus] -type=Bus -block_size=64 -bus_id=0 -clock=1000 -header_cycles=1 -use_default_range=false -width=64 -port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port - -[system.physmem] -type=PhysicalMemory -file= -latency=30000 -latency_var=0 -null=false -range=0:134217727 -zero=false -port=system.membus.port[1] - diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/simerr b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/simerr deleted file mode 100755 index 31ae36f2e..000000000 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/simerr +++ /dev/null @@ -1,3 +0,0 @@ -warn: Sockets disabled, not accepting gdb connections -warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...) -hack: be nice to actually delete the event here diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/simout b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/simout deleted file mode 100755 index fdc12b275..000000000 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/simout +++ /dev/null @@ -1,12 +0,0 @@ -gem5 Simulator System. http://gem5.org -gem5 is copyrighted software; use the --copyright option for details. - -gem5 compiled Jan 23 2012 04:48:33 -gem5 started Jan 23 2012 04:59:27 -gem5 executing on zizzer -command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA_SE/tests/opt/quick/00.hello/alpha/tru64/simple-atomic -Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -info: Increasing stack size by one page. -Hello world! -Exiting @ tick 1297500 because target called exit() diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stats.txt b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stats.txt deleted file mode 100644 index 23e50fd7f..000000000 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stats.txt +++ /dev/null @@ -1,77 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 0.000001 # Number of seconds simulated -sim_ticks 1297500 # Number of ticks simulated -final_tick 1297500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 182014 # Simulator instruction rate (inst/s) -host_tick_rate 91451888 # Simulator tick rate (ticks/s) -host_mem_usage 197324 # Number of bytes of host memory used -host_seconds 0.01 # Real time elapsed on the host -sim_insts 2577 # Number of instructions simulated -system.physmem.bytes_read 13356 # Number of bytes read from this memory -system.physmem.bytes_inst_read 10340 # Number of instructions bytes read from this memory -system.physmem.bytes_written 2058 # Number of bytes written to this memory -system.physmem.num_reads 3000 # Number of read requests responded to by this memory -system.physmem.num_writes 294 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 10293641618 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 7969171484 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 1586127168 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 11879768786 # Total bandwidth to/from this memory (bytes/s) -system.cpu.dtb.fetch_hits 0 # ITB hits -system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.fetch_acv 0 # ITB acv -system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 415 # DTB read hits -system.cpu.dtb.read_misses 4 # DTB read misses -system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 419 # DTB read accesses -system.cpu.dtb.write_hits 294 # DTB write hits -system.cpu.dtb.write_misses 4 # DTB write misses -system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 298 # DTB write accesses -system.cpu.dtb.data_hits 709 # DTB hits -system.cpu.dtb.data_misses 8 # DTB misses -system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 717 # DTB accesses -system.cpu.itb.fetch_hits 2585 # ITB hits -system.cpu.itb.fetch_misses 11 # ITB misses -system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 2596 # ITB accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.read_acv 0 # DTB read access violations -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.write_acv 0 # DTB write access violations -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.data_hits 0 # DTB hits -system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.data_acv 0 # DTB access violations -system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.workload.num_syscalls 4 # Number of system calls -system.cpu.numCycles 2596 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.num_insts 2577 # Number of instructions executed -system.cpu.num_int_alu_accesses 2375 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 6 # Number of float alu accesses -system.cpu.num_func_calls 140 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 238 # number of instructions that are conditional controls -system.cpu.num_int_insts 2375 # number of integer instructions -system.cpu.num_fp_insts 6 # number of float instructions -system.cpu.num_int_register_reads 2998 # number of times the integer registers were read -system.cpu.num_int_register_writes 1768 # number of times the integer registers were written -system.cpu.num_fp_register_reads 6 # number of times the floating registers were read -system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_mem_refs 717 # number of memory refs -system.cpu.num_load_insts 419 # Number of load instructions -system.cpu.num_store_insts 298 # Number of store instructions -system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 2596 # Number of busy cycles -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.idle_fraction 0 # Percentage of idle cycles - ----------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/config.ini b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/config.ini deleted file mode 100644 index 89c8aeac1..000000000 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/config.ini +++ /dev/null @@ -1,327 +0,0 @@ -[root] -type=Root -children=system -time_sync_enable=false -time_sync_period=100000000 -time_sync_spin_threshold=100000 - -[system] -type=System -children=cpu dir_cntrl0 l1_cntrl0 l2_cntrl0 physmem ruby sys_port_proxy -mem_mode=timing -memories=system.physmem -num_work_ids=16 -physmem=system.physmem -work_begin_ckpt_count=0 -work_begin_cpu_id_exit=-1 -work_begin_exit_count=0 -work_cpus_ckpt_count=0 -work_end_ckpt_count=0 -work_end_exit_count=0 -work_item_id=-1 -system_port=system.sys_port_proxy.port[0] - -[system.cpu] -type=TimingSimpleCPU -children=dtb itb tracer workload -checker=Null -clock=1 -cpu_id=0 -defer_registration=false -do_checkpoint_insts=true -do_statistics_insts=true -dtb=system.cpu.dtb -function_trace=false -function_trace_start=0 -itb=system.cpu.itb -max_insts_all_threads=0 -max_insts_any_thread=0 -max_loads_all_threads=0 -max_loads_any_thread=0 -numThreads=1 -phase=0 -progress_interval=0 -system=system -tracer=system.cpu.tracer -workload=system.cpu.workload -dcache_port=system.l1_cntrl0.sequencer.port[1] -icache_port=system.l1_cntrl0.sequencer.port[0] - -[system.cpu.dtb] -type=AlphaTLB -size=64 - -[system.cpu.itb] -type=AlphaTLB -size=48 - -[system.cpu.tracer] -type=ExeTracer - -[system.cpu.workload] -type=LiveProcess -cmd=hello -cwd= -egid=100 -env= -errout=cerr -euid=100 -executable=/dist/m5/regression/test-progs/hello/bin/alpha/tru64/hello -gid=100 -input=cin -max_stack_size=67108864 -output=cout -pid=100 -ppid=99 -simpoint=0 -system=system -uid=100 - -[system.dir_cntrl0] -type=Directory_Controller -children=directory memBuffer -buffer_size=0 -cntrl_id=2 -directory=system.dir_cntrl0.directory -directory_latency=6 -memBuffer=system.dir_cntrl0.memBuffer -number_of_TBEs=256 -recycle_latency=10 -ruby_system=system.ruby -to_mem_ctrl_latency=1 -transitions_per_cycle=32 -version=0 - -[system.dir_cntrl0.directory] -type=RubyDirectoryMemory -map_levels=4 -numa_high_bit=6 -size=134217728 -use_map=false -version=0 - -[system.dir_cntrl0.memBuffer] -type=RubyMemoryControl -bank_bit_0=8 -bank_busy_time=11 -bank_queue_size=12 -banks_per_rank=8 -basic_bus_busy_time=2 -dimm_bit_0=12 -dimms_per_channel=2 -mem_bus_cycle_multiplier=10 -mem_ctl_latency=12 -mem_fixed_delay=0 -mem_random_arbitrate=0 -rank_bit_0=11 -rank_rank_delay=1 -ranks_per_dimm=2 -read_write_delay=2 -refresh_period=1560 -tFaw=0 -version=0 - -[system.l1_cntrl0] -type=L1Cache_Controller -children=L1DcacheMemory L1IcacheMemory sequencer -L1DcacheMemory=system.l1_cntrl0.L1DcacheMemory -L1IcacheMemory=system.l1_cntrl0.L1IcacheMemory -buffer_size=0 -cntrl_id=0 -l1_request_latency=2 -l1_response_latency=2 -l2_select_num_bits=0 -number_of_TBEs=256 -recycle_latency=10 -ruby_system=system.ruby -sequencer=system.l1_cntrl0.sequencer -to_l2_latency=1 -transitions_per_cycle=32 -version=0 - -[system.l1_cntrl0.L1DcacheMemory] -type=RubyCache -assoc=2 -is_icache=false -latency=3 -replacement_policy=PSEUDO_LRU -size=256 -start_index_bit=6 - -[system.l1_cntrl0.L1IcacheMemory] -type=RubyCache -assoc=2 -is_icache=false -latency=3 -replacement_policy=PSEUDO_LRU -size=256 -start_index_bit=6 - -[system.l1_cntrl0.sequencer] -type=RubySequencer -access_phys_mem=true -dcache=system.l1_cntrl0.L1DcacheMemory -deadlock_threshold=500000 -icache=system.l1_cntrl0.L1IcacheMemory -max_outstanding_requests=16 -physmem=system.physmem -ruby_system=system.ruby -using_network_tester=false -using_ruby_tester=false -version=0 -physMemPort=system.physmem.port[0] -port=system.cpu.icache_port system.cpu.dcache_port - -[system.l2_cntrl0] -type=L2Cache_Controller -children=L2cacheMemory -L2cacheMemory=system.l2_cntrl0.L2cacheMemory -buffer_size=0 -cntrl_id=1 -l2_request_latency=2 -l2_response_latency=2 -number_of_TBEs=256 -recycle_latency=10 -ruby_system=system.ruby -to_l1_latency=1 -transitions_per_cycle=32 -version=0 - -[system.l2_cntrl0.L2cacheMemory] -type=RubyCache -assoc=2 -is_icache=false -latency=15 -replacement_policy=PSEUDO_LRU -size=512 -start_index_bit=6 - -[system.physmem] -type=PhysicalMemory -file= -latency=30 -latency_var=0 -null=false -range=0:134217727 -zero=false -port=system.l1_cntrl0.sequencer.physMemPort system.sys_port_proxy.physMemPort - -[system.ruby] -type=RubySystem -children=network profiler -block_size_bytes=64 -clock=1 -mem_size=134217728 -no_mem_vec=false -random_seed=1234 -randomization=false -stats_filename=ruby.stats - -[system.ruby.network] -type=SimpleNetwork -children=topology -adaptive_routing=false -buffer_size=0 -control_msg_size=8 -endpoint_bandwidth=1000 -number_of_virtual_networks=10 -ruby_system=system.ruby -topology=system.ruby.network.topology - -[system.ruby.network.topology] -type=Topology -children=ext_links0 ext_links1 ext_links2 int_links0 int_links1 int_links2 routers0 routers1 routers2 routers3 -description=Crossbar -ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1 system.ruby.network.topology.ext_links2 -int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1 system.ruby.network.topology.int_links2 -print_config=false -routers=system.ruby.network.topology.routers0 system.ruby.network.topology.routers1 system.ruby.network.topology.routers2 system.ruby.network.topology.routers3 - -[system.ruby.network.topology.ext_links0] -type=SimpleExtLink -bandwidth_factor=16 -ext_node=system.l1_cntrl0 -int_node=system.ruby.network.topology.routers0 -latency=1 -link_id=0 -weight=1 - -[system.ruby.network.topology.ext_links1] -type=SimpleExtLink -bandwidth_factor=16 -ext_node=system.l2_cntrl0 -int_node=system.ruby.network.topology.routers1 -latency=1 -link_id=1 -weight=1 - -[system.ruby.network.topology.ext_links2] -type=SimpleExtLink -bandwidth_factor=16 -ext_node=system.dir_cntrl0 -int_node=system.ruby.network.topology.routers2 -latency=1 -link_id=2 -weight=1 - -[system.ruby.network.topology.int_links0] -type=SimpleIntLink -bandwidth_factor=16 -latency=1 -link_id=3 -node_a=system.ruby.network.topology.routers0 -node_b=system.ruby.network.topology.routers3 -weight=1 - -[system.ruby.network.topology.int_links1] -type=SimpleIntLink -bandwidth_factor=16 -latency=1 -link_id=4 -node_a=system.ruby.network.topology.routers1 -node_b=system.ruby.network.topology.routers3 -weight=1 - -[system.ruby.network.topology.int_links2] -type=SimpleIntLink -bandwidth_factor=16 -latency=1 -link_id=5 -node_a=system.ruby.network.topology.routers2 -node_b=system.ruby.network.topology.routers3 -weight=1 - -[system.ruby.network.topology.routers0] -type=BasicRouter -router_id=0 - -[system.ruby.network.topology.routers1] -type=BasicRouter -router_id=1 - -[system.ruby.network.topology.routers2] -type=BasicRouter -router_id=2 - -[system.ruby.network.topology.routers3] -type=BasicRouter -router_id=3 - -[system.ruby.profiler] -type=RubyProfiler -all_instructions=false -hot_lines=false -num_of_sequencers=1 -ruby_system=system.ruby - -[system.sys_port_proxy] -type=RubyPortProxy -access_phys_mem=true -physmem=system.physmem -ruby_system=system.ruby -using_network_tester=false -using_ruby_tester=false -version=0 -physMemPort=system.physmem.port[1] -port=system.system_port - diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/ruby.stats b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/ruby.stats deleted file mode 100644 index 1c4da6ce4..000000000 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/ruby.stats +++ /dev/null @@ -1,641 +0,0 @@ - -================ Begin RubySystem Configuration Print ================ - -RubySystem config: - random_seed: 1234 - randomization: 0 - cycle_period: 1 - block_size_bytes: 64 - block_size_bits: 6 - memory_size_bytes: 134217728 - memory_size_bits: 27 - -Network Configuration ---------------------- -network: SIMPLE_NETWORK -topology: - -virtual_net_0: active, unordered -virtual_net_1: active, unordered -virtual_net_2: active, unordered -virtual_net_3: inactive -virtual_net_4: inactive -virtual_net_5: inactive -virtual_net_6: inactive -virtual_net_7: inactive -virtual_net_8: inactive -virtual_net_9: inactive - - -Profiler Configuration ----------------------- -periodic_stats_period: 1000000 - -================ End RubySystem Configuration Print ================ - - -Real time: Jan/23/2012 04:21:58 - -Profiler Stats --------------- -Elapsed_time_in_seconds: 2 -Elapsed_time_in_minutes: 0.0333333 -Elapsed_time_in_hours: 0.000555556 -Elapsed_time_in_days: 2.31481e-05 - -Virtual_time_in_seconds: 0.26 -Virtual_time_in_minutes: 0.00433333 -Virtual_time_in_hours: 7.22222e-05 -Virtual_time_in_days: 3.00926e-06 - -Ruby_current_time: 104867 -Ruby_start_time: 0 -Ruby_cycles: 104867 - -mbytes_resident: 43.0078 -mbytes_total: 212.113 -resident_ratio: 0.202759 - -ruby_cycles_executed: [ 104868 ] - -Busy Controller Counts: -L1Cache-0:0 -L2Cache-0:0 -Directory-0:0 - - -Busy Bank Count:0 - -sequencer_requests_outstanding: [binsize: 1 max: 1 count: 3295 average: 1 | standard deviation: 0 | 0 3295 ] - -All Non-Zero Cycle Demand Cache Accesses ----------------------------------------- -miss_latency: [binsize: 2 max: 275 count: 3294 average: 30.8358 | standard deviation: 62.2139 | 0 2722 0 0 0 0 0 0 0 23 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 62 131 87 117 74 6 17 4 2 2 1 11 10 5 4 3 5 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_LD: [binsize: 2 max: 235 count: 415 average: 80.7349 | standard deviation: 83.1868 | 0 211 0 0 0 0 0 0 0 11 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 24 46 24 49 14 4 7 4 1 1 0 5 0 4 0 3 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_ST: [binsize: 2 max: 275 count: 294 average: 39.8435 | standard deviation: 69.7713 | 0 226 0 0 0 0 0 0 0 3 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8 19 3 12 8 0 8 0 0 0 0 1 1 0 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_IFETCH: [binsize: 2 max: 267 count: 2585 average: 21.8004 | standard deviation: 52.7361 | 0 2285 0 0 0 0 0 0 0 9 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 30 66 60 56 52 2 2 0 1 1 1 5 9 1 1 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_NULL: [binsize: 2 max: 275 count: 3294 average: 30.8358 | standard deviation: 62.2139 | 0 2722 0 0 0 0 0 0 0 23 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 62 131 87 117 74 6 17 4 2 2 1 11 10 5 4 3 5 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] -miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] -miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] -miss_latency_wCC_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] -imcomplete_wCC_Times: 0 -miss_latency_dir_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] -miss_latency_dir_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] -miss_latency_dir_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] -miss_latency_dir_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] -imcomplete_dir_Times: 0 -miss_latency_LD_NULL: [binsize: 2 max: 235 count: 415 average: 80.7349 | standard deviation: 83.1868 | 0 211 0 0 0 0 0 0 0 11 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 24 46 24 49 14 4 7 4 1 1 0 5 0 4 0 3 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_ST_NULL: [binsize: 2 max: 275 count: 294 average: 39.8435 | standard deviation: 69.7713 | 0 226 0 0 0 0 0 0 0 3 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8 19 3 12 8 0 8 0 0 0 0 1 1 0 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_IFETCH_NULL: [binsize: 2 max: 267 count: 2585 average: 21.8004 | standard deviation: 52.7361 | 0 2285 0 0 0 0 0 0 0 9 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 30 66 60 56 52 2 2 0 1 1 1 5 9 1 1 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] - -All Non-Zero Cycle SW Prefetch Requests ------------------------------------- -prefetch_latency: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] -prefetch_latency_L2Miss:[binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] -Request vs. RubySystem State Profile --------------------------------- - - -filter_action: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - -Message Delayed Cycles ----------------------- -Total_delay_cycles: [binsize: 1 max: 20 count: 3612 average: 0.0636766 | standard deviation: 0.653474 | 3562 0 1 0 47 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 ] -Total_nonPF_delay_cycles: [binsize: 1 max: 2 count: 2644 average: 0.00075643 | standard deviation: 0.0389028 | 2643 0 1 ] - virtual_network_0_delay_cycles: [binsize: 1 max: 20 count: 968 average: 0.235537 | standard deviation: 1.24505 | 919 0 0 0 47 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 ] - virtual_network_1_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - virtual_network_2_delay_cycles: [binsize: 1 max: 0 count: 431 average: 0 | standard deviation: 0 | 431 ] - virtual_network_3_delay_cycles: [binsize: 1 max: 2 count: 2213 average: 0.000903751 | standard deviation: 0.0425243 | 2212 0 1 ] - virtual_network_4_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - virtual_network_5_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - virtual_network_6_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - virtual_network_7_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - virtual_network_8_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - virtual_network_9_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - -Resource Usage --------------- -page_size: 4096 -user_time: 0 -system_time: 0 -page_reclaims: 11317 -page_faults: 0 -swaps: 0 -block_inputs: 0 -block_outputs: 88 - -Network Stats -------------- - -total_msg_count_Control: 3357 26856 -total_msg_count_Request_Control: 1293 10344 -total_msg_count_Response_Data: 3666 263952 -total_msg_count_Response_Control: 5220 41760 -total_msg_count_Writeback_Data: 327 23544 -total_msg_count_Writeback_Control: 231 1848 -total_msgs: 14094 total_bytes: 368304 - -switch_0_inlinks: 2 -switch_0_outlinks: 2 -links_utilized_percent_switch_0: 1.90098 - links_utilized_percent_switch_0_link_0: 2.71916 bw: 16000 base_latency: 1 - links_utilized_percent_switch_0_link_1: 1.0828 bw: 16000 base_latency: 1 - - outgoing_messages_switch_0_link_0_Request_Control: 431 3448 [ 431 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_0_Response_Data: 572 41184 [ 0 572 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_0_Response_Control: 124 992 [ 0 124 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Control: 572 4576 [ 572 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Response_Control: 641 5128 [ 0 369 272 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Writeback_Data: 109 7848 [ 47 62 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Writeback_Control: 77 616 [ 77 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - -switch_1_inlinks: 2 -switch_1_outlinks: 2 -links_utilized_percent_switch_1: 3.65844 - links_utilized_percent_switch_1_link_0: 3.68705 bw: 16000 base_latency: 1 - links_utilized_percent_switch_1_link_1: 3.62984 bw: 16000 base_latency: 1 - - outgoing_messages_switch_1_link_0_Control: 572 4576 [ 572 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_0_Response_Data: 547 39384 [ 0 547 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_0_Response_Control: 1180 9440 [ 0 908 272 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_0_Writeback_Data: 109 7848 [ 47 62 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_0_Writeback_Control: 77 616 [ 77 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_Control: 547 4376 [ 547 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_Request_Control: 431 3448 [ 431 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_Response_Data: 675 48600 [ 0 675 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_Response_Control: 560 4480 [ 0 560 0 0 0 0 0 0 0 0 ] base_latency: 1 - -switch_2_inlinks: 2 -switch_2_outlinks: 2 -links_utilized_percent_switch_2: 1.75746 - links_utilized_percent_switch_2_link_0: 0.910677 bw: 16000 base_latency: 1 - links_utilized_percent_switch_2_link_1: 2.60425 bw: 16000 base_latency: 1 - - outgoing_messages_switch_2_link_0_Control: 547 4376 [ 547 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_0_Response_Data: 103 7416 [ 0 103 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_0_Response_Control: 436 3488 [ 0 436 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_1_Response_Data: 547 39384 [ 0 547 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_1_Response_Control: 539 4312 [ 0 539 0 0 0 0 0 0 0 0 ] base_latency: 1 - -switch_3_inlinks: 3 -switch_3_outlinks: 3 -links_utilized_percent_switch_3: 2.43896 - links_utilized_percent_switch_3_link_0: 2.71916 bw: 16000 base_latency: 1 - links_utilized_percent_switch_3_link_1: 3.68705 bw: 16000 base_latency: 1 - links_utilized_percent_switch_3_link_2: 0.910677 bw: 16000 base_latency: 1 - - outgoing_messages_switch_3_link_0_Request_Control: 431 3448 [ 431 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_0_Response_Data: 572 41184 [ 0 572 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_0_Response_Control: 124 992 [ 0 124 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_1_Control: 572 4576 [ 572 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_1_Response_Data: 547 39384 [ 0 547 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_1_Response_Control: 1180 9440 [ 0 908 272 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_1_Writeback_Data: 109 7848 [ 47 62 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_1_Writeback_Control: 77 616 [ 77 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_2_Control: 547 4376 [ 547 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_2_Response_Data: 103 7416 [ 0 103 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_2_Response_Control: 436 3488 [ 0 436 0 0 0 0 0 0 0 0 ] base_latency: 1 - -Cache Stats: system.l1_cntrl0.L1IcacheMemory - system.l1_cntrl0.L1IcacheMemory_total_misses: 300 - system.l1_cntrl0.L1IcacheMemory_total_demand_misses: 300 - system.l1_cntrl0.L1IcacheMemory_total_prefetches: 0 - system.l1_cntrl0.L1IcacheMemory_total_sw_prefetches: 0 - system.l1_cntrl0.L1IcacheMemory_total_hw_prefetches: 0 - - system.l1_cntrl0.L1IcacheMemory_request_type_IFETCH: 100% - - system.l1_cntrl0.L1IcacheMemory_access_mode_type_Supervisor: 300 100% - -Cache Stats: system.l1_cntrl0.L1DcacheMemory - system.l1_cntrl0.L1DcacheMemory_total_misses: 272 - system.l1_cntrl0.L1DcacheMemory_total_demand_misses: 272 - system.l1_cntrl0.L1DcacheMemory_total_prefetches: 0 - system.l1_cntrl0.L1DcacheMemory_total_sw_prefetches: 0 - system.l1_cntrl0.L1DcacheMemory_total_hw_prefetches: 0 - - system.l1_cntrl0.L1DcacheMemory_request_type_LD: 75% - system.l1_cntrl0.L1DcacheMemory_request_type_ST: 25% - - system.l1_cntrl0.L1DcacheMemory_access_mode_type_Supervisor: 272 100% - - --- L1Cache --- - - Event Counts - -Load [415 ] 415 -Ifetch [2585 ] 2585 -Store [294 ] 294 -Inv [431 ] 431 -L1_Replacement [502 ] 502 -Fwd_GETX [0 ] 0 -Fwd_GETS [0 ] 0 -Fwd_GET_INSTR [0 ] 0 -Data [0 ] 0 -Data_Exclusive [204 ] 204 -DataS_fromL1 [0 ] 0 -Data_all_Acks [368 ] 368 -Ack [0 ] 0 -Ack_all [0 ] 0 -WB_Ack [124 ] 124 - - - Transitions - -NP Load [182 ] 182 -NP Ifetch [270 ] 270 -NP Store [58 ] 58 -NP Inv [162 ] 162 -NP L1_Replacement [0 ] 0 - -I Load [22 ] 22 -I Ifetch [30 ] 30 -I Store [10 ] 10 -I Inv [0 ] 0 -I L1_Replacement [206 ] 206 - -S Load [0 ] 0 -S Ifetch [2285 ] 2285 -S Store [0 ] 0 -S Inv [124 ] 124 -S L1_Replacement [172 ] 172 - -E Load [140 ] 140 -E Ifetch [0 ] 0 -E Store [41 ] 41 -E Inv [83 ] 83 -E L1_Replacement [79 ] 79 -E Fwd_GETX [0 ] 0 -E Fwd_GETS [0 ] 0 -E Fwd_GET_INSTR [0 ] 0 - -M Load [71 ] 71 -M Ifetch [0 ] 0 -M Store [185 ] 185 -M Inv [62 ] 62 -M L1_Replacement [45 ] 45 -M Fwd_GETX [0 ] 0 -M Fwd_GETS [0 ] 0 -M Fwd_GET_INSTR [0 ] 0 - -IS Load [0 ] 0 -IS Ifetch [0 ] 0 -IS Store [0 ] 0 -IS Inv [0 ] 0 -IS L1_Replacement [0 ] 0 -IS Data_Exclusive [204 ] 204 -IS DataS_fromL1 [0 ] 0 -IS Data_all_Acks [300 ] 300 - -IM Load [0 ] 0 -IM Ifetch [0 ] 0 -IM Store [0 ] 0 -IM Inv [0 ] 0 -IM L1_Replacement [0 ] 0 -IM Data [0 ] 0 -IM Data_all_Acks [68 ] 68 -IM Ack [0 ] 0 - -SM Load [0 ] 0 -SM Ifetch [0 ] 0 -SM Store [0 ] 0 -SM Inv [0 ] 0 -SM L1_Replacement [0 ] 0 -SM Ack [0 ] 0 -SM Ack_all [0 ] 0 - -IS_I Load [0 ] 0 -IS_I Ifetch [0 ] 0 -IS_I Store [0 ] 0 -IS_I Inv [0 ] 0 -IS_I L1_Replacement [0 ] 0 -IS_I Data_Exclusive [0 ] 0 -IS_I DataS_fromL1 [0 ] 0 -IS_I Data_all_Acks [0 ] 0 - -M_I Load [0 ] 0 -M_I Ifetch [0 ] 0 -M_I Store [0 ] 0 -M_I Inv [0 ] 0 -M_I L1_Replacement [0 ] 0 -M_I Fwd_GETX [0 ] 0 -M_I Fwd_GETS [0 ] 0 -M_I Fwd_GET_INSTR [0 ] 0 -M_I WB_Ack [124 ] 124 - -E_I Load [0 ] 0 -E_I Ifetch [0 ] 0 -E_I Store [0 ] 0 -E_I L1_Replacement [0 ] 0 - -SINK_WB_ACK Load [0 ] 0 -SINK_WB_ACK Ifetch [0 ] 0 -SINK_WB_ACK Store [0 ] 0 -SINK_WB_ACK Inv [0 ] 0 -SINK_WB_ACK L1_Replacement [0 ] 0 -SINK_WB_ACK WB_Ack [0 ] 0 - -Cache Stats: system.l2_cntrl0.L2cacheMemory - system.l2_cntrl0.L2cacheMemory_total_misses: 547 - system.l2_cntrl0.L2cacheMemory_total_demand_misses: 547 - system.l2_cntrl0.L2cacheMemory_total_prefetches: 0 - system.l2_cntrl0.L2cacheMemory_total_sw_prefetches: 0 - system.l2_cntrl0.L2cacheMemory_total_hw_prefetches: 0 - - system.l2_cntrl0.L2cacheMemory_request_type_GETS: 35.1005% - system.l2_cntrl0.L2cacheMemory_request_type_GET_INSTR: 53.1993% - system.l2_cntrl0.L2cacheMemory_request_type_GETX: 11.7002% - - system.l2_cntrl0.L2cacheMemory_access_mode_type_Supervisor: 547 100% - - --- L2Cache --- - - Event Counts - -L1_GET_INSTR [300 ] 300 -L1_GETS [206 ] 206 -L1_GETX [70 ] 70 -L1_UPGRADE [0 ] 0 -L1_PUTX [124 ] 124 -L1_PUTX_old [0 ] 0 -Fwd_L1_GETX [0 ] 0 -Fwd_L1_GETS [0 ] 0 -Fwd_L1_GET_INSTR [0 ] 0 -L2_Replacement [43 ] 43 -L2_Replacement_clean [496 ] 496 -Mem_Data [547 ] 547 -Mem_Ack [539 ] 539 -WB_Data [62 ] 62 -WB_Data_clean [0 ] 0 -Ack [0 ] 0 -Ack_all [369 ] 369 -Unblock [0 ] 0 -Unblock_Cancel [0 ] 0 -Exclusive_Unblock [272 ] 272 -MEM_Inv [0 ] 0 - - - Transitions - -NP L1_GET_INSTR [291 ] 291 -NP L1_GETS [192 ] 192 -NP L1_GETX [64 ] 64 -NP L1_PUTX [0 ] 0 -NP L1_PUTX_old [0 ] 0 - -SS L1_GET_INSTR [9 ] 9 -SS L1_GETS [0 ] 0 -SS L1_GETX [0 ] 0 -SS L1_UPGRADE [0 ] 0 -SS L1_PUTX [0 ] 0 -SS L1_PUTX_old [0 ] 0 -SS L2_Replacement [0 ] 0 -SS L2_Replacement_clean [286 ] 286 -SS MEM_Inv [0 ] 0 - -M L1_GET_INSTR [0 ] 0 -M L1_GETS [12 ] 12 -M L1_GETX [4 ] 4 -M L1_PUTX [0 ] 0 -M L1_PUTX_old [0 ] 0 -M L2_Replacement [39 ] 39 -M L2_Replacement_clean [69 ] 69 -M MEM_Inv [0 ] 0 - -MT L1_GET_INSTR [0 ] 0 -MT L1_GETS [0 ] 0 -MT L1_GETX [0 ] 0 -MT L1_PUTX [124 ] 124 -MT L1_PUTX_old [0 ] 0 -MT L2_Replacement [4 ] 4 -MT L2_Replacement_clean [141 ] 141 -MT MEM_Inv [0 ] 0 - -M_I L1_GET_INSTR [0 ] 0 -M_I L1_GETS [2 ] 2 -M_I L1_GETX [2 ] 2 -M_I L1_UPGRADE [0 ] 0 -M_I L1_PUTX [0 ] 0 -M_I L1_PUTX_old [0 ] 0 -M_I Mem_Ack [539 ] 539 -M_I MEM_Inv [0 ] 0 - -MT_I L1_GET_INSTR [0 ] 0 -MT_I L1_GETS [0 ] 0 -MT_I L1_GETX [0 ] 0 -MT_I L1_UPGRADE [0 ] 0 -MT_I L1_PUTX [0 ] 0 -MT_I L1_PUTX_old [0 ] 0 -MT_I WB_Data [2 ] 2 -MT_I WB_Data_clean [0 ] 0 -MT_I Ack_all [2 ] 2 -MT_I MEM_Inv [0 ] 0 - -MCT_I L1_GET_INSTR [0 ] 0 -MCT_I L1_GETS [0 ] 0 -MCT_I L1_GETX [0 ] 0 -MCT_I L1_UPGRADE [0 ] 0 -MCT_I L1_PUTX [0 ] 0 -MCT_I L1_PUTX_old [0 ] 0 -MCT_I WB_Data [60 ] 60 -MCT_I WB_Data_clean [0 ] 0 -MCT_I Ack_all [81 ] 81 - -I_I L1_GET_INSTR [0 ] 0 -I_I L1_GETS [0 ] 0 -I_I L1_GETX [0 ] 0 -I_I L1_UPGRADE [0 ] 0 -I_I L1_PUTX [0 ] 0 -I_I L1_PUTX_old [0 ] 0 -I_I Ack [0 ] 0 -I_I Ack_all [286 ] 286 - -S_I L1_GET_INSTR [0 ] 0 -S_I L1_GETS [0 ] 0 -S_I L1_GETX [0 ] 0 -S_I L1_UPGRADE [0 ] 0 -S_I L1_PUTX [0 ] 0 -S_I L1_PUTX_old [0 ] 0 -S_I Ack [0 ] 0 -S_I Ack_all [0 ] 0 -S_I MEM_Inv [0 ] 0 - -ISS L1_GET_INSTR [0 ] 0 -ISS L1_GETS [0 ] 0 -ISS L1_GETX [0 ] 0 -ISS L1_PUTX [0 ] 0 -ISS L1_PUTX_old [0 ] 0 -ISS L2_Replacement [0 ] 0 -ISS L2_Replacement_clean [0 ] 0 -ISS Mem_Data [192 ] 192 -ISS MEM_Inv [0 ] 0 - -IS L1_GET_INSTR [0 ] 0 -IS L1_GETS [0 ] 0 -IS L1_GETX [0 ] 0 -IS L1_PUTX [0 ] 0 -IS L1_PUTX_old [0 ] 0 -IS L2_Replacement [0 ] 0 -IS L2_Replacement_clean [0 ] 0 -IS Mem_Data [291 ] 291 -IS MEM_Inv [0 ] 0 - -IM L1_GET_INSTR [0 ] 0 -IM L1_GETS [0 ] 0 -IM L1_GETX [0 ] 0 -IM L1_PUTX [0 ] 0 -IM L1_PUTX_old [0 ] 0 -IM L2_Replacement [0 ] 0 -IM L2_Replacement_clean [0 ] 0 -IM Mem_Data [64 ] 64 -IM MEM_Inv [0 ] 0 - -SS_MB L1_GET_INSTR [0 ] 0 -SS_MB L1_GETS [0 ] 0 -SS_MB L1_GETX [0 ] 0 -SS_MB L1_UPGRADE [0 ] 0 -SS_MB L1_PUTX [0 ] 0 -SS_MB L1_PUTX_old [0 ] 0 -SS_MB L2_Replacement [0 ] 0 -SS_MB L2_Replacement_clean [0 ] 0 -SS_MB Unblock_Cancel [0 ] 0 -SS_MB Exclusive_Unblock [0 ] 0 -SS_MB MEM_Inv [0 ] 0 - -MT_MB L1_GET_INSTR [0 ] 0 -MT_MB L1_GETS [0 ] 0 -MT_MB L1_GETX [0 ] 0 -MT_MB L1_UPGRADE [0 ] 0 -MT_MB L1_PUTX [0 ] 0 -MT_MB L1_PUTX_old [0 ] 0 -MT_MB L2_Replacement [0 ] 0 -MT_MB L2_Replacement_clean [0 ] 0 -MT_MB Unblock_Cancel [0 ] 0 -MT_MB Exclusive_Unblock [272 ] 272 -MT_MB MEM_Inv [0 ] 0 - -M_MB L1_GET_INSTR [0 ] 0 -M_MB L1_GETS [0 ] 0 -M_MB L1_GETX [0 ] 0 -M_MB L1_UPGRADE [0 ] 0 -M_MB L1_PUTX [0 ] 0 -M_MB L1_PUTX_old [0 ] 0 -M_MB L2_Replacement [0 ] 0 -M_MB L2_Replacement_clean [0 ] 0 -M_MB Exclusive_Unblock [0 ] 0 -M_MB MEM_Inv [0 ] 0 - -MT_IIB L1_GET_INSTR [0 ] 0 -MT_IIB L1_GETS [0 ] 0 -MT_IIB L1_GETX [0 ] 0 -MT_IIB L1_UPGRADE [0 ] 0 -MT_IIB L1_PUTX [0 ] 0 -MT_IIB L1_PUTX_old [0 ] 0 -MT_IIB L2_Replacement [0 ] 0 -MT_IIB L2_Replacement_clean [0 ] 0 -MT_IIB WB_Data [0 ] 0 -MT_IIB WB_Data_clean [0 ] 0 -MT_IIB Unblock [0 ] 0 -MT_IIB MEM_Inv [0 ] 0 - -MT_IB L1_GET_INSTR [0 ] 0 -MT_IB L1_GETS [0 ] 0 -MT_IB L1_GETX [0 ] 0 -MT_IB L1_UPGRADE [0 ] 0 -MT_IB L1_PUTX [0 ] 0 -MT_IB L1_PUTX_old [0 ] 0 -MT_IB L2_Replacement [0 ] 0 -MT_IB L2_Replacement_clean [0 ] 0 -MT_IB WB_Data [0 ] 0 -MT_IB WB_Data_clean [0 ] 0 -MT_IB Unblock_Cancel [0 ] 0 -MT_IB MEM_Inv [0 ] 0 - -MT_SB L1_GET_INSTR [0 ] 0 -MT_SB L1_GETS [0 ] 0 -MT_SB L1_GETX [0 ] 0 -MT_SB L1_UPGRADE [0 ] 0 -MT_SB L1_PUTX [0 ] 0 -MT_SB L1_PUTX_old [0 ] 0 -MT_SB L2_Replacement [0 ] 0 -MT_SB L2_Replacement_clean [0 ] 0 -MT_SB Unblock [0 ] 0 -MT_SB MEM_Inv [0 ] 0 - -Memory controller: system.dir_cntrl0.memBuffer: - memory_total_requests: 650 - memory_reads: 547 - memory_writes: 103 - memory_refreshes: 219 - memory_total_request_delays: 306 - memory_delays_per_request: 0.470769 - memory_delays_in_input_queue: 27 - memory_delays_behind_head_of_bank_queue: 0 - memory_delays_stalled_at_head_of_bank_queue: 279 - memory_stalls_for_bank_busy: 56 - memory_stalls_for_random_busy: 0 - memory_stalls_for_anti_starvation: 0 - memory_stalls_for_arbitration: 9 - memory_stalls_for_bus: 94 - memory_stalls_for_tfaw: 0 - memory_stalls_for_read_write_turnaround: 120 - memory_stalls_for_read_read_turnaround: 0 - accesses_per_bank: 26 14 0 49 21 21 42 25 6 4 7 4 24 42 26 3 5 7 7 18 10 29 15 50 19 5 6 16 14 24 19 92 - - --- Directory --- - - Event Counts - -Fetch [547 ] 547 -Data [103 ] 103 -Memory_Data [547 ] 547 -Memory_Ack [103 ] 103 -DMA_READ [0 ] 0 -DMA_WRITE [0 ] 0 -CleanReplacement [436 ] 436 - - - Transitions - -I Fetch [547 ] 547 -I DMA_READ [0 ] 0 -I DMA_WRITE [0 ] 0 - -ID Fetch [0 ] 0 -ID Data [0 ] 0 -ID Memory_Data [0 ] 0 -ID DMA_READ [0 ] 0 -ID DMA_WRITE [0 ] 0 - -ID_W Fetch [0 ] 0 -ID_W Data [0 ] 0 -ID_W Memory_Ack [0 ] 0 -ID_W DMA_READ [0 ] 0 -ID_W DMA_WRITE [0 ] 0 - -M Data [103 ] 103 -M DMA_READ [0 ] 0 -M DMA_WRITE [0 ] 0 -M CleanReplacement [436 ] 436 - -IM Fetch [0 ] 0 -IM Data [0 ] 0 -IM Memory_Data [547 ] 547 -IM DMA_READ [0 ] 0 -IM DMA_WRITE [0 ] 0 - -MI Fetch [0 ] 0 -MI Data [0 ] 0 -MI Memory_Ack [103 ] 103 -MI DMA_READ [0 ] 0 -MI DMA_WRITE [0 ] 0 - -M_DRD Data [0 ] 0 -M_DRD DMA_READ [0 ] 0 -M_DRD DMA_WRITE [0 ] 0 - -M_DRDI Fetch [0 ] 0 -M_DRDI Data [0 ] 0 -M_DRDI Memory_Ack [0 ] 0 -M_DRDI DMA_READ [0 ] 0 -M_DRDI DMA_WRITE [0 ] 0 - -M_DWR Data [0 ] 0 -M_DWR DMA_READ [0 ] 0 -M_DWR DMA_WRITE [0 ] 0 - -M_DWRI Fetch [0 ] 0 -M_DWRI Data [0 ] 0 -M_DWRI Memory_Ack [0 ] 0 -M_DWRI DMA_READ [0 ] 0 -M_DWRI DMA_WRITE [0 ] 0 - diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/simerr b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/simerr deleted file mode 100755 index 31ae36f2e..000000000 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/simerr +++ /dev/null @@ -1,3 +0,0 @@ -warn: Sockets disabled, not accepting gdb connections -warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...) -hack: be nice to actually delete the event here diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/simout b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/simout deleted file mode 100755 index dc0ba2922..000000000 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/simout +++ /dev/null @@ -1,12 +0,0 @@ -gem5 Simulator System. http://gem5.org -gem5 is copyrighted software; use the --copyright option for details. - -gem5 compiled Jan 23 2012 03:44:57 -gem5 started Jan 23 2012 04:21:56 -gem5 executing on zizzer -command line: build/ALPHA_SE_MESI_CMP_directory/gem5.opt -d build/ALPHA_SE_MESI_CMP_directory/tests/opt/quick/00.hello/alpha/tru64/simple-timing-ruby-MESI_CMP_directory -re tests/run.py build/ALPHA_SE_MESI_CMP_directory/tests/opt/quick/00.hello/alpha/tru64/simple-timing-ruby-MESI_CMP_directory -Global frequency set at 1000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -info: Increasing stack size by one page. -Hello world! -Exiting @ tick 104867 because target called exit() diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/stats.txt b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/stats.txt deleted file mode 100644 index ebac3fa83..000000000 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/stats.txt +++ /dev/null @@ -1,77 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 0.000105 # Number of seconds simulated -sim_ticks 104867 # Number of ticks simulated -final_tick 104867 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 1196 # Simulator instruction rate (inst/s) -host_tick_rate 48657 # Simulator tick rate (ticks/s) -host_mem_usage 217208 # Number of bytes of host memory used -host_seconds 2.16 # Real time elapsed on the host -sim_insts 2577 # Number of instructions simulated -system.physmem.bytes_read 13356 # Number of bytes read from this memory -system.physmem.bytes_inst_read 10340 # Number of instructions bytes read from this memory -system.physmem.bytes_written 2058 # Number of bytes written to this memory -system.physmem.num_reads 3000 # Number of read requests responded to by this memory -system.physmem.num_writes 294 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 127361324 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 98601085 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 19624858 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 146986182 # Total bandwidth to/from this memory (bytes/s) -system.cpu.dtb.fetch_hits 0 # ITB hits -system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.fetch_acv 0 # ITB acv -system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 415 # DTB read hits -system.cpu.dtb.read_misses 4 # DTB read misses -system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 419 # DTB read accesses -system.cpu.dtb.write_hits 294 # DTB write hits -system.cpu.dtb.write_misses 4 # DTB write misses -system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 298 # DTB write accesses -system.cpu.dtb.data_hits 709 # DTB hits -system.cpu.dtb.data_misses 8 # DTB misses -system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 717 # DTB accesses -system.cpu.itb.fetch_hits 2586 # ITB hits -system.cpu.itb.fetch_misses 11 # ITB misses -system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 2597 # ITB accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.read_acv 0 # DTB read access violations -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.write_acv 0 # DTB write access violations -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.data_hits 0 # DTB hits -system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.data_acv 0 # DTB access violations -system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.workload.num_syscalls 4 # Number of system calls -system.cpu.numCycles 104867 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.num_insts 2577 # Number of instructions executed -system.cpu.num_int_alu_accesses 2375 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 6 # Number of float alu accesses -system.cpu.num_func_calls 140 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 238 # number of instructions that are conditional controls -system.cpu.num_int_insts 2375 # number of integer instructions -system.cpu.num_fp_insts 6 # number of float instructions -system.cpu.num_int_register_reads 2998 # number of times the integer registers were read -system.cpu.num_int_register_writes 1768 # number of times the integer registers were written -system.cpu.num_fp_register_reads 6 # number of times the floating registers were read -system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_mem_refs 717 # number of memory refs -system.cpu.num_load_insts 419 # Number of load instructions -system.cpu.num_store_insts 298 # Number of store instructions -system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 104867 # Number of busy cycles -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.idle_fraction 0 # Percentage of idle cycles - ----------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/config.ini b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/config.ini deleted file mode 100644 index e5748fef4..000000000 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/config.ini +++ /dev/null @@ -1,323 +0,0 @@ -[root] -type=Root -children=system -time_sync_enable=false -time_sync_period=100000000 -time_sync_spin_threshold=100000 - -[system] -type=System -children=cpu dir_cntrl0 l1_cntrl0 l2_cntrl0 physmem ruby sys_port_proxy -mem_mode=timing -memories=system.physmem -num_work_ids=16 -physmem=system.physmem -work_begin_ckpt_count=0 -work_begin_cpu_id_exit=-1 -work_begin_exit_count=0 -work_cpus_ckpt_count=0 -work_end_ckpt_count=0 -work_end_exit_count=0 -work_item_id=-1 -system_port=system.sys_port_proxy.port[0] - -[system.cpu] -type=TimingSimpleCPU -children=dtb itb tracer workload -checker=Null -clock=1 -cpu_id=0 -defer_registration=false -do_checkpoint_insts=true -do_statistics_insts=true -dtb=system.cpu.dtb -function_trace=false -function_trace_start=0 -itb=system.cpu.itb -max_insts_all_threads=0 -max_insts_any_thread=0 -max_loads_all_threads=0 -max_loads_any_thread=0 -numThreads=1 -phase=0 -progress_interval=0 -system=system -tracer=system.cpu.tracer -workload=system.cpu.workload -dcache_port=system.l1_cntrl0.sequencer.port[1] -icache_port=system.l1_cntrl0.sequencer.port[0] - -[system.cpu.dtb] -type=AlphaTLB -size=64 - -[system.cpu.itb] -type=AlphaTLB -size=48 - -[system.cpu.tracer] -type=ExeTracer - -[system.cpu.workload] -type=LiveProcess -cmd=hello -cwd= -egid=100 -env= -errout=cerr -euid=100 -executable=/dist/m5/regression/test-progs/hello/bin/alpha/tru64/hello -gid=100 -input=cin -max_stack_size=67108864 -output=cout -pid=100 -ppid=99 -simpoint=0 -system=system -uid=100 - -[system.dir_cntrl0] -type=Directory_Controller -children=directory memBuffer -buffer_size=0 -cntrl_id=2 -directory=system.dir_cntrl0.directory -directory_latency=6 -memBuffer=system.dir_cntrl0.memBuffer -number_of_TBEs=256 -recycle_latency=10 -ruby_system=system.ruby -transitions_per_cycle=32 -version=0 - -[system.dir_cntrl0.directory] -type=RubyDirectoryMemory -map_levels=4 -numa_high_bit=6 -size=134217728 -use_map=false -version=0 - -[system.dir_cntrl0.memBuffer] -type=RubyMemoryControl -bank_bit_0=8 -bank_busy_time=11 -bank_queue_size=12 -banks_per_rank=8 -basic_bus_busy_time=2 -dimm_bit_0=12 -dimms_per_channel=2 -mem_bus_cycle_multiplier=10 -mem_ctl_latency=12 -mem_fixed_delay=0 -mem_random_arbitrate=0 -rank_bit_0=11 -rank_rank_delay=1 -ranks_per_dimm=2 -read_write_delay=2 -refresh_period=1560 -tFaw=0 -version=0 - -[system.l1_cntrl0] -type=L1Cache_Controller -children=L1DcacheMemory L1IcacheMemory sequencer -L1DcacheMemory=system.l1_cntrl0.L1DcacheMemory -L1IcacheMemory=system.l1_cntrl0.L1IcacheMemory -buffer_size=0 -cntrl_id=0 -l2_select_num_bits=0 -number_of_TBEs=256 -recycle_latency=10 -request_latency=2 -ruby_system=system.ruby -sequencer=system.l1_cntrl0.sequencer -transitions_per_cycle=32 -version=0 - -[system.l1_cntrl0.L1DcacheMemory] -type=RubyCache -assoc=2 -is_icache=false -latency=3 -replacement_policy=PSEUDO_LRU -size=256 -start_index_bit=6 - -[system.l1_cntrl0.L1IcacheMemory] -type=RubyCache -assoc=2 -is_icache=false -latency=3 -replacement_policy=PSEUDO_LRU -size=256 -start_index_bit=6 - -[system.l1_cntrl0.sequencer] -type=RubySequencer -access_phys_mem=true -dcache=system.l1_cntrl0.L1DcacheMemory -deadlock_threshold=500000 -icache=system.l1_cntrl0.L1IcacheMemory -max_outstanding_requests=16 -physmem=system.physmem -ruby_system=system.ruby -using_network_tester=false -using_ruby_tester=false -version=0 -physMemPort=system.physmem.port[0] -port=system.cpu.icache_port system.cpu.dcache_port - -[system.l2_cntrl0] -type=L2Cache_Controller -children=L2cacheMemory -L2cacheMemory=system.l2_cntrl0.L2cacheMemory -buffer_size=0 -cntrl_id=1 -number_of_TBEs=256 -recycle_latency=10 -request_latency=2 -response_latency=2 -ruby_system=system.ruby -transitions_per_cycle=32 -version=0 - -[system.l2_cntrl0.L2cacheMemory] -type=RubyCache -assoc=2 -is_icache=false -latency=15 -replacement_policy=PSEUDO_LRU -size=512 -start_index_bit=6 - -[system.physmem] -type=PhysicalMemory -file= -latency=30 -latency_var=0 -null=false -range=0:134217727 -zero=false -port=system.l1_cntrl0.sequencer.physMemPort system.sys_port_proxy.physMemPort - -[system.ruby] -type=RubySystem -children=network profiler -block_size_bytes=64 -clock=1 -mem_size=134217728 -no_mem_vec=false -random_seed=1234 -randomization=false -stats_filename=ruby.stats - -[system.ruby.network] -type=SimpleNetwork -children=topology -adaptive_routing=false -buffer_size=0 -control_msg_size=8 -endpoint_bandwidth=1000 -number_of_virtual_networks=10 -ruby_system=system.ruby -topology=system.ruby.network.topology - -[system.ruby.network.topology] -type=Topology -children=ext_links0 ext_links1 ext_links2 int_links0 int_links1 int_links2 routers0 routers1 routers2 routers3 -description=Crossbar -ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1 system.ruby.network.topology.ext_links2 -int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1 system.ruby.network.topology.int_links2 -print_config=false -routers=system.ruby.network.topology.routers0 system.ruby.network.topology.routers1 system.ruby.network.topology.routers2 system.ruby.network.topology.routers3 - -[system.ruby.network.topology.ext_links0] -type=SimpleExtLink -bandwidth_factor=16 -ext_node=system.l1_cntrl0 -int_node=system.ruby.network.topology.routers0 -latency=1 -link_id=0 -weight=1 - -[system.ruby.network.topology.ext_links1] -type=SimpleExtLink -bandwidth_factor=16 -ext_node=system.l2_cntrl0 -int_node=system.ruby.network.topology.routers1 -latency=1 -link_id=1 -weight=1 - -[system.ruby.network.topology.ext_links2] -type=SimpleExtLink -bandwidth_factor=16 -ext_node=system.dir_cntrl0 -int_node=system.ruby.network.topology.routers2 -latency=1 -link_id=2 -weight=1 - -[system.ruby.network.topology.int_links0] -type=SimpleIntLink -bandwidth_factor=16 -latency=1 -link_id=3 -node_a=system.ruby.network.topology.routers0 -node_b=system.ruby.network.topology.routers3 -weight=1 - -[system.ruby.network.topology.int_links1] -type=SimpleIntLink -bandwidth_factor=16 -latency=1 -link_id=4 -node_a=system.ruby.network.topology.routers1 -node_b=system.ruby.network.topology.routers3 -weight=1 - -[system.ruby.network.topology.int_links2] -type=SimpleIntLink -bandwidth_factor=16 -latency=1 -link_id=5 -node_a=system.ruby.network.topology.routers2 -node_b=system.ruby.network.topology.routers3 -weight=1 - -[system.ruby.network.topology.routers0] -type=BasicRouter -router_id=0 - -[system.ruby.network.topology.routers1] -type=BasicRouter -router_id=1 - -[system.ruby.network.topology.routers2] -type=BasicRouter -router_id=2 - -[system.ruby.network.topology.routers3] -type=BasicRouter -router_id=3 - -[system.ruby.profiler] -type=RubyProfiler -all_instructions=false -hot_lines=false -num_of_sequencers=1 -ruby_system=system.ruby - -[system.sys_port_proxy] -type=RubyPortProxy -access_phys_mem=true -physmem=system.physmem -ruby_system=system.ruby -using_network_tester=false -using_ruby_tester=false -version=0 -physMemPort=system.physmem.port[1] -port=system.system_port - diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/ruby.stats b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/ruby.stats deleted file mode 100644 index f2273438f..000000000 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/ruby.stats +++ /dev/null @@ -1,1470 +0,0 @@ - -================ Begin RubySystem Configuration Print ================ - -RubySystem config: - random_seed: 1234 - randomization: 0 - cycle_period: 1 - block_size_bytes: 64 - block_size_bits: 6 - memory_size_bytes: 134217728 - memory_size_bits: 27 - -Network Configuration ---------------------- -network: SIMPLE_NETWORK -topology: - -virtual_net_0: active, unordered -virtual_net_1: active, unordered -virtual_net_2: active, unordered -virtual_net_3: inactive -virtual_net_4: inactive -virtual_net_5: inactive -virtual_net_6: inactive -virtual_net_7: inactive -virtual_net_8: inactive -virtual_net_9: inactive - - -Profiler Configuration ----------------------- -periodic_stats_period: 1000000 - -================ End RubySystem Configuration Print ================ - - -Real time: Jan/23/2012 04:22:12 - -Profiler Stats --------------- -Elapsed_time_in_seconds: 0 -Elapsed_time_in_minutes: 0 -Elapsed_time_in_hours: 0 -Elapsed_time_in_days: 0 - -Virtual_time_in_seconds: 0.25 -Virtual_time_in_minutes: 0.00416667 -Virtual_time_in_hours: 6.94444e-05 -Virtual_time_in_days: 2.89352e-06 - -Ruby_current_time: 85418 -Ruby_start_time: 0 -Ruby_cycles: 85418 - -mbytes_resident: 42.9688 -mbytes_total: 212.301 -resident_ratio: 0.202396 - -ruby_cycles_executed: [ 85419 ] - -Busy Controller Counts: -L2Cache-0:0 -L1Cache-0:0 - -Directory-0:0 - -Busy Bank Count:0 - -sequencer_requests_outstanding: [binsize: 1 max: 1 count: 3295 average: 1 | standard deviation: 0 | 0 3295 ] - -All Non-Zero Cycle Demand Cache Accesses ----------------------------------------- -miss_latency: [binsize: 2 max: 281 count: 3294 average: 24.9314 | standard deviation: 56.0488 | 0 2784 0 0 0 0 0 0 0 67 20 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 80 91 84 78 63 5 2 2 1 3 3 0 2 2 1 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_LD: [binsize: 2 max: 277 count: 415 average: 60.9277 | standard deviation: 78.686 | 0 233 0 0 0 0 0 0 0 40 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 17 41 19 25 0 0 0 0 0 1 0 0 0 1 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_ST: [binsize: 2 max: 245 count: 294 average: 28.5238 | standard deviation: 59.597 | 0 236 0 0 0 0 0 0 0 0 15 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 17 3 12 7 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_IFETCH: [binsize: 2 max: 281 count: 2585 average: 18.7439 | standard deviation: 48.5885 | 0 2315 0 0 0 0 0 0 0 27 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 49 57 40 47 31 2 2 2 1 3 2 0 2 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_NULL: [binsize: 2 max: 281 count: 3294 average: 24.9314 | standard deviation: 56.0488 | 0 2784 0 0 0 0 0 0 0 67 20 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 80 91 84 78 63 5 2 2 1 3 3 0 2 2 1 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] -miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] -miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] -miss_latency_wCC_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] -imcomplete_wCC_Times: 0 -miss_latency_dir_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] -miss_latency_dir_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] -miss_latency_dir_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] -miss_latency_dir_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] -imcomplete_dir_Times: 0 -miss_latency_LD_NULL: [binsize: 2 max: 277 count: 415 average: 60.9277 | standard deviation: 78.686 | 0 233 0 0 0 0 0 0 0 40 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 17 41 19 25 0 0 0 0 0 1 0 0 0 1 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_ST_NULL: [binsize: 2 max: 245 count: 294 average: 28.5238 | standard deviation: 59.597 | 0 236 0 0 0 0 0 0 0 0 15 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 17 3 12 7 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_IFETCH_NULL: [binsize: 2 max: 281 count: 2585 average: 18.7439 | standard deviation: 48.5885 | 0 2315 0 0 0 0 0 0 0 27 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 49 57 40 47 31 2 2 2 1 3 2 0 2 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] - -All Non-Zero Cycle SW Prefetch Requests ------------------------------------- -prefetch_latency: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] -prefetch_latency_L2Miss:[binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] -Request vs. RubySystem State Profile --------------------------------- - - -filter_action: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - -Message Delayed Cycles ----------------------- -Total_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] -Total_nonPF_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - virtual_network_0_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - virtual_network_1_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - virtual_network_2_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - virtual_network_3_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - virtual_network_4_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - virtual_network_5_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - virtual_network_6_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - virtual_network_7_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - virtual_network_8_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - virtual_network_9_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - -Resource Usage --------------- -page_size: 4096 -user_time: 0 -system_time: 0 -page_reclaims: 11325 -page_faults: 11 -swaps: 0 -block_inputs: 1584 -block_outputs: 88 - -Network Stats -------------- - -total_msg_count_Request_Control: 2799 22392 -total_msg_count_Response_Data: 2538 182736 -total_msg_count_ResponseL2hit_Data: 261 18792 -total_msg_count_Writeback_Data: 1734 124848 -total_msg_count_Writeback_Control: 6447 51576 -total_msg_count_Unblock_Control: 2798 22384 -total_msgs: 16577 total_bytes: 422728 - -switch_0_inlinks: 2 -switch_0_outlinks: 2 -links_utilized_percent_switch_0: 5.15524 - links_utilized_percent_switch_0_link_0: 6.00225 bw: 16000 base_latency: 1 - links_utilized_percent_switch_0_link_1: 4.30823 bw: 16000 base_latency: 1 - - outgoing_messages_switch_0_link_0_Request_Control: 510 4080 [ 510 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_0_Response_Data: 423 30456 [ 0 0 423 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_0_Writeback_Data: 502 36144 [ 0 0 502 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_0_Writeback_Control: 909 7272 [ 502 407 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_0_Unblock_Control: 510 4080 [ 0 0 510 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Request_Control: 423 3384 [ 0 423 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Response_Data: 423 30456 [ 0 0 423 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_ResponseL2hit_Data: 87 6264 [ 0 0 87 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Writeback_Data: 76 5472 [ 0 0 76 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Writeback_Control: 1240 9920 [ 502 407 331 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Unblock_Control: 423 3384 [ 0 0 423 0 0 0 0 0 0 0 ] base_latency: 1 - -switch_1_inlinks: 2 -switch_1_outlinks: 2 -links_utilized_percent_switch_1: 3.2581 - links_utilized_percent_switch_1_link_0: 2.98064 bw: 16000 base_latency: 1 - links_utilized_percent_switch_1_link_1: 3.53555 bw: 16000 base_latency: 1 - - outgoing_messages_switch_1_link_0_Response_Data: 423 30456 [ 0 0 423 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_0_ResponseL2hit_Data: 87 6264 [ 0 0 87 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_0_Writeback_Control: 502 4016 [ 502 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_Request_Control: 510 4080 [ 510 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_Writeback_Data: 502 36144 [ 0 0 502 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_Writeback_Control: 502 4016 [ 502 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_Unblock_Control: 510 4080 [ 0 0 510 0 0 0 0 0 0 0 ] base_latency: 1 - -switch_2_inlinks: 2 -switch_2_outlinks: 2 -links_utilized_percent_switch_2: 1.89685 - links_utilized_percent_switch_2_link_0: 1.327 bw: 16000 base_latency: 1 - links_utilized_percent_switch_2_link_1: 2.46669 bw: 16000 base_latency: 1 - - outgoing_messages_switch_2_link_0_Request_Control: 423 3384 [ 0 423 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_0_Writeback_Data: 76 5472 [ 0 0 76 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_0_Writeback_Control: 738 5904 [ 0 407 331 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_0_Unblock_Control: 422 3376 [ 0 0 422 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_1_Response_Data: 423 30456 [ 0 0 423 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_1_Writeback_Control: 407 3256 [ 0 407 0 0 0 0 0 0 0 0 ] base_latency: 1 - -switch_3_inlinks: 3 -switch_3_outlinks: 3 -links_utilized_percent_switch_3: 3.43682 - links_utilized_percent_switch_3_link_0: 6.00225 bw: 16000 base_latency: 1 - links_utilized_percent_switch_3_link_1: 2.98064 bw: 16000 base_latency: 1 - links_utilized_percent_switch_3_link_2: 1.32759 bw: 16000 base_latency: 1 - - outgoing_messages_switch_3_link_0_Request_Control: 510 4080 [ 510 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_0_Response_Data: 423 30456 [ 0 0 423 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_0_Writeback_Data: 502 36144 [ 0 0 502 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_0_Writeback_Control: 909 7272 [ 502 407 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_0_Unblock_Control: 510 4080 [ 0 0 510 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_1_Response_Data: 423 30456 [ 0 0 423 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_1_ResponseL2hit_Data: 87 6264 [ 0 0 87 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_1_Writeback_Control: 502 4016 [ 502 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_2_Request_Control: 423 3384 [ 0 423 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_2_Writeback_Data: 76 5472 [ 0 0 76 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_2_Writeback_Control: 738 5904 [ 0 407 331 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_2_Unblock_Control: 423 3384 [ 0 0 423 0 0 0 0 0 0 0 ] base_latency: 1 - -Cache Stats: system.l1_cntrl0.L1IcacheMemory - system.l1_cntrl0.L1IcacheMemory_total_misses: 0 - system.l1_cntrl0.L1IcacheMemory_total_demand_misses: 0 - system.l1_cntrl0.L1IcacheMemory_total_prefetches: 0 - system.l1_cntrl0.L1IcacheMemory_total_sw_prefetches: 0 - system.l1_cntrl0.L1IcacheMemory_total_hw_prefetches: 0 - - -Cache Stats: system.l1_cntrl0.L1DcacheMemory - system.l1_cntrl0.L1DcacheMemory_total_misses: 0 - system.l1_cntrl0.L1DcacheMemory_total_demand_misses: 0 - system.l1_cntrl0.L1DcacheMemory_total_prefetches: 0 - system.l1_cntrl0.L1DcacheMemory_total_sw_prefetches: 0 - system.l1_cntrl0.L1DcacheMemory_total_hw_prefetches: 0 - - - --- L1Cache --- - - Event Counts - -Load [415 ] 415 -Ifetch [2585 ] 2585 -Store [294 ] 294 -L1_Replacement [506 ] 506 -Own_GETX [0 ] 0 -Fwd_GETX [0 ] 0 -Fwd_GETS [0 ] 0 -Fwd_DMA [0 ] 0 -Inv [0 ] 0 -Ack [0 ] 0 -Data [0 ] 0 -Exclusive_Data [510 ] 510 -Writeback_Ack [0 ] 0 -Writeback_Ack_Data [502 ] 502 -Writeback_Nack [0 ] 0 -All_acks [58 ] 58 -Use_Timeout [509 ] 509 - - - Transitions - -I Load [182 ] 182 -I Ifetch [270 ] 270 -I Store [58 ] 58 -I L1_Replacement [0 ] 0 -I Inv [0 ] 0 - -S Load [0 ] 0 -S Ifetch [0 ] 0 -S Store [0 ] 0 -S L1_Replacement [0 ] 0 -S Fwd_GETS [0 ] 0 -S Fwd_DMA [0 ] 0 -S Inv [0 ] 0 - -O Load [0 ] 0 -O Ifetch [0 ] 0 -O Store [0 ] 0 -O L1_Replacement [0 ] 0 -O Fwd_GETX [0 ] 0 -O Fwd_GETS [0 ] 0 -O Fwd_DMA [0 ] 0 - -M Load [82 ] 82 -M Ifetch [1220 ] 1220 -M Store [33 ] 33 -M L1_Replacement [406 ] 406 -M Fwd_GETX [0 ] 0 -M Fwd_GETS [0 ] 0 -M Fwd_DMA [0 ] 0 - -M_W Load [49 ] 49 -M_W Ifetch [1095 ] 1095 -M_W Store [7 ] 7 -M_W L1_Replacement [4 ] 4 -M_W Own_GETX [0 ] 0 -M_W Fwd_GETX [0 ] 0 -M_W Fwd_GETS [0 ] 0 -M_W Fwd_DMA [0 ] 0 -M_W Inv [0 ] 0 -M_W Use_Timeout [444 ] 444 - -MM Load [99 ] 99 -MM Ifetch [0 ] 0 -MM Store [114 ] 114 -MM L1_Replacement [96 ] 96 -MM Fwd_GETX [0 ] 0 -MM Fwd_GETS [0 ] 0 -MM Fwd_DMA [0 ] 0 - -MM_W Load [3 ] 3 -MM_W Ifetch [0 ] 0 -MM_W Store [82 ] 82 -MM_W L1_Replacement [0 ] 0 -MM_W Own_GETX [0 ] 0 -MM_W Fwd_GETX [0 ] 0 -MM_W Fwd_GETS [0 ] 0 -MM_W Fwd_DMA [0 ] 0 -MM_W Inv [0 ] 0 -MM_W Use_Timeout [65 ] 65 - -IM Load [0 ] 0 -IM Ifetch [0 ] 0 -IM Store [0 ] 0 -IM L1_Replacement [0 ] 0 -IM Inv [0 ] 0 -IM Ack [0 ] 0 -IM Data [0 ] 0 -IM Exclusive_Data [58 ] 58 - -SM Load [0 ] 0 -SM Ifetch [0 ] 0 -SM Store [0 ] 0 -SM L1_Replacement [0 ] 0 -SM Fwd_GETS [0 ] 0 -SM Fwd_DMA [0 ] 0 -SM Inv [0 ] 0 -SM Ack [0 ] 0 -SM Data [0 ] 0 -SM Exclusive_Data [0 ] 0 - -OM Load [0 ] 0 -OM Ifetch [0 ] 0 -OM Store [0 ] 0 -OM L1_Replacement [0 ] 0 -OM Own_GETX [0 ] 0 -OM Fwd_GETX [0 ] 0 -OM Fwd_GETS [0 ] 0 -OM Fwd_DMA [0 ] 0 -OM Ack [0 ] 0 -OM All_acks [58 ] 58 - -IS Load [0 ] 0 -IS Ifetch [0 ] 0 -IS Store [0 ] 0 -IS L1_Replacement [0 ] 0 -IS Inv [0 ] 0 -IS Data [0 ] 0 -IS Exclusive_Data [452 ] 452 - -SI Load [0 ] 0 -SI Ifetch [0 ] 0 -SI Store [0 ] 0 -SI L1_Replacement [0 ] 0 -SI Fwd_GETS [0 ] 0 -SI Fwd_DMA [0 ] 0 -SI Inv [0 ] 0 -SI Writeback_Ack [0 ] 0 -SI Writeback_Ack_Data [0 ] 0 -SI Writeback_Nack [0 ] 0 - -OI Load [0 ] 0 -OI Ifetch [0 ] 0 -OI Store [0 ] 0 -OI L1_Replacement [0 ] 0 -OI Fwd_GETX [0 ] 0 -OI Fwd_GETS [0 ] 0 -OI Fwd_DMA [0 ] 0 -OI Writeback_Ack [0 ] 0 -OI Writeback_Ack_Data [0 ] 0 -OI Writeback_Nack [0 ] 0 - -MI Load [0 ] 0 -MI Ifetch [0 ] 0 -MI Store [0 ] 0 -MI L1_Replacement [0 ] 0 -MI Fwd_GETX [0 ] 0 -MI Fwd_GETS [0 ] 0 -MI Fwd_DMA [0 ] 0 -MI Writeback_Ack [0 ] 0 -MI Writeback_Ack_Data [502 ] 502 -MI Writeback_Nack [0 ] 0 - -II Load [0 ] 0 -II Ifetch [0 ] 0 -II Store [0 ] 0 -II L1_Replacement [0 ] 0 -II Inv [0 ] 0 -II Writeback_Ack [0 ] 0 -II Writeback_Ack_Data [0 ] 0 -II Writeback_Nack [0 ] 0 - -Cache Stats: system.l2_cntrl0.L2cacheMemory - system.l2_cntrl0.L2cacheMemory_total_misses: 0 - system.l2_cntrl0.L2cacheMemory_total_demand_misses: 0 - system.l2_cntrl0.L2cacheMemory_total_prefetches: 0 - system.l2_cntrl0.L2cacheMemory_total_sw_prefetches: 0 - system.l2_cntrl0.L2cacheMemory_total_hw_prefetches: 0 - - - --- L2Cache --- - - Event Counts - -L1_GETS [454 ] 454 -L1_GETX [58 ] 58 -L1_PUTO [0 ] 0 -L1_PUTX [502 ] 502 -L1_PUTS_only [0 ] 0 -L1_PUTS [0 ] 0 -Fwd_GETX [0 ] 0 -Fwd_GETS [0 ] 0 -Fwd_DMA [0 ] 0 -Own_GETX [0 ] 0 -Inv [0 ] 0 -IntAck [0 ] 0 -ExtAck [0 ] 0 -All_Acks [43 ] 43 -Data [43 ] 43 -Data_Exclusive [380 ] 380 -L1_WBCLEANDATA [396 ] 396 -L1_WBDIRTYDATA [106 ] 106 -Writeback_Ack [407 ] 407 -Writeback_Nack [0 ] 0 -Unblock [0 ] 0 -Exclusive_Unblock [510 ] 510 -DmaAck [0 ] 0 -L2_Replacement [407 ] 407 - - - Transitions - -NP L1_GETS [380 ] 380 -NP L1_GETX [43 ] 43 -NP L1_PUTO [0 ] 0 -NP L1_PUTX [0 ] 0 -NP L1_PUTS [0 ] 0 -NP Inv [0 ] 0 - -I L1_GETS [0 ] 0 -I L1_GETX [0 ] 0 -I L1_PUTO [0 ] 0 -I L1_PUTX [0 ] 0 -I L1_PUTS [0 ] 0 -I Inv [0 ] 0 -I L2_Replacement [0 ] 0 - -ILS L1_GETS [0 ] 0 -ILS L1_GETX [0 ] 0 -ILS L1_PUTO [0 ] 0 -ILS L1_PUTX [0 ] 0 -ILS L1_PUTS_only [0 ] 0 -ILS L1_PUTS [0 ] 0 -ILS Inv [0 ] 0 -ILS L2_Replacement [0 ] 0 - -ILX L1_GETS [0 ] 0 -ILX L1_GETX [0 ] 0 -ILX L1_PUTO [0 ] 0 -ILX L1_PUTX [502 ] 502 -ILX L1_PUTS_only [0 ] 0 -ILX L1_PUTS [0 ] 0 -ILX Fwd_GETX [0 ] 0 -ILX Fwd_GETS [0 ] 0 -ILX Fwd_DMA [0 ] 0 -ILX Inv [0 ] 0 -ILX Data [0 ] 0 -ILX L2_Replacement [0 ] 0 - -ILO L1_GETS [0 ] 0 -ILO L1_GETX [0 ] 0 -ILO L1_PUTO [0 ] 0 -ILO L1_PUTX [0 ] 0 -ILO L1_PUTS [0 ] 0 -ILO Fwd_GETX [0 ] 0 -ILO Fwd_GETS [0 ] 0 -ILO Fwd_DMA [0 ] 0 -ILO Inv [0 ] 0 -ILO Data [0 ] 0 -ILO L2_Replacement [0 ] 0 - -ILOX L1_GETS [0 ] 0 -ILOX L1_GETX [0 ] 0 -ILOX L1_PUTO [0 ] 0 -ILOX L1_PUTX [0 ] 0 -ILOX L1_PUTS [0 ] 0 -ILOX Fwd_GETX [0 ] 0 -ILOX Fwd_GETS [0 ] 0 -ILOX Fwd_DMA [0 ] 0 -ILOX Data [0 ] 0 - -ILOS L1_GETS [0 ] 0 -ILOS L1_GETX [0 ] 0 -ILOS L1_PUTO [0 ] 0 -ILOS L1_PUTX [0 ] 0 -ILOS L1_PUTS_only [0 ] 0 -ILOS L1_PUTS [0 ] 0 -ILOS Fwd_GETX [0 ] 0 -ILOS Fwd_GETS [0 ] 0 -ILOS Fwd_DMA [0 ] 0 -ILOS Data [0 ] 0 -ILOS L2_Replacement [0 ] 0 - -ILOSX L1_GETS [0 ] 0 -ILOSX L1_GETX [0 ] 0 -ILOSX L1_PUTO [0 ] 0 -ILOSX L1_PUTX [0 ] 0 -ILOSX L1_PUTS_only [0 ] 0 -ILOSX L1_PUTS [0 ] 0 -ILOSX Fwd_GETX [0 ] 0 -ILOSX Fwd_GETS [0 ] 0 -ILOSX Fwd_DMA [0 ] 0 -ILOSX Data [0 ] 0 - -S L1_GETS [0 ] 0 -S L1_GETX [0 ] 0 -S L1_PUTX [0 ] 0 -S L1_PUTS [0 ] 0 -S Inv [0 ] 0 -S L2_Replacement [0 ] 0 - -O L1_GETS [0 ] 0 -O L1_GETX [0 ] 0 -O L1_PUTX [0 ] 0 -O Fwd_GETX [0 ] 0 -O Fwd_GETS [0 ] 0 -O Fwd_DMA [0 ] 0 -O L2_Replacement [0 ] 0 - -OLS L1_GETS [0 ] 0 -OLS L1_GETX [0 ] 0 -OLS L1_PUTX [0 ] 0 -OLS L1_PUTS_only [0 ] 0 -OLS L1_PUTS [0 ] 0 -OLS Fwd_GETX [0 ] 0 -OLS Fwd_GETS [0 ] 0 -OLS Fwd_DMA [0 ] 0 -OLS L2_Replacement [0 ] 0 - -OLSX L1_GETS [0 ] 0 -OLSX L1_GETX [0 ] 0 -OLSX L1_PUTO [0 ] 0 -OLSX L1_PUTX [0 ] 0 -OLSX L1_PUTS_only [0 ] 0 -OLSX L1_PUTS [0 ] 0 -OLSX Fwd_GETX [0 ] 0 -OLSX Fwd_GETS [0 ] 0 -OLSX Fwd_DMA [0 ] 0 -OLSX L2_Replacement [0 ] 0 - -SLS L1_GETS [0 ] 0 -SLS L1_GETX [0 ] 0 -SLS L1_PUTX [0 ] 0 -SLS L1_PUTS_only [0 ] 0 -SLS L1_PUTS [0 ] 0 -SLS Inv [0 ] 0 -SLS L2_Replacement [0 ] 0 - -M L1_GETS [72 ] 72 -M L1_GETX [15 ] 15 -M L1_PUTO [0 ] 0 -M L1_PUTX [0 ] 0 -M L1_PUTS [0 ] 0 -M Fwd_GETX [0 ] 0 -M Fwd_GETS [0 ] 0 -M Fwd_DMA [0 ] 0 -M L2_Replacement [407 ] 407 - -IFGX L1_GETS [0 ] 0 -IFGX L1_GETX [0 ] 0 -IFGX L1_PUTO [0 ] 0 -IFGX L1_PUTX [0 ] 0 -IFGX L1_PUTS_only [0 ] 0 -IFGX L1_PUTS [0 ] 0 -IFGX Fwd_GETX [0 ] 0 -IFGX Fwd_GETS [0 ] 0 -IFGX Fwd_DMA [0 ] 0 -IFGX Inv [0 ] 0 -IFGX Data [0 ] 0 -IFGX Data_Exclusive [0 ] 0 -IFGX L2_Replacement [0 ] 0 - -IFGS L1_GETS [0 ] 0 -IFGS L1_GETX [0 ] 0 -IFGS L1_PUTO [0 ] 0 -IFGS L1_PUTX [0 ] 0 -IFGS L1_PUTS_only [0 ] 0 -IFGS L1_PUTS [0 ] 0 -IFGS Fwd_GETX [0 ] 0 -IFGS Fwd_GETS [0 ] 0 -IFGS Fwd_DMA [0 ] 0 -IFGS Inv [0 ] 0 -IFGS Data [0 ] 0 -IFGS Data_Exclusive [0 ] 0 -IFGS L2_Replacement [0 ] 0 - -ISFGS L1_GETS [0 ] 0 -ISFGS L1_GETX [0 ] 0 -ISFGS L1_PUTO [0 ] 0 -ISFGS L1_PUTX [0 ] 0 -ISFGS L1_PUTS_only [0 ] 0 -ISFGS L1_PUTS [0 ] 0 -ISFGS Fwd_GETX [0 ] 0 -ISFGS Fwd_GETS [0 ] 0 -ISFGS Fwd_DMA [0 ] 0 -ISFGS Inv [0 ] 0 -ISFGS Data [0 ] 0 -ISFGS L2_Replacement [0 ] 0 - -IFGXX L1_GETS [0 ] 0 -IFGXX L1_GETX [0 ] 0 -IFGXX L1_PUTO [0 ] 0 -IFGXX L1_PUTX [0 ] 0 -IFGXX L1_PUTS_only [0 ] 0 -IFGXX L1_PUTS [0 ] 0 -IFGXX Fwd_GETX [0 ] 0 -IFGXX Fwd_GETS [0 ] 0 -IFGXX Fwd_DMA [0 ] 0 -IFGXX Inv [0 ] 0 -IFGXX IntAck [0 ] 0 -IFGXX All_Acks [0 ] 0 -IFGXX Data_Exclusive [0 ] 0 -IFGXX L2_Replacement [0 ] 0 - -OFGX L1_GETS [0 ] 0 -OFGX L1_GETX [0 ] 0 -OFGX L1_PUTO [0 ] 0 -OFGX L1_PUTX [0 ] 0 -OFGX L1_PUTS_only [0 ] 0 -OFGX L1_PUTS [0 ] 0 -OFGX Fwd_GETX [0 ] 0 -OFGX Fwd_GETS [0 ] 0 -OFGX Fwd_DMA [0 ] 0 -OFGX Inv [0 ] 0 -OFGX L2_Replacement [0 ] 0 - -OLSF L1_GETS [0 ] 0 -OLSF L1_GETX [0 ] 0 -OLSF L1_PUTO [0 ] 0 -OLSF L1_PUTX [0 ] 0 -OLSF L1_PUTS_only [0 ] 0 -OLSF L1_PUTS [0 ] 0 -OLSF Fwd_GETX [0 ] 0 -OLSF Fwd_GETS [0 ] 0 -OLSF Fwd_DMA [0 ] 0 -OLSF Inv [0 ] 0 -OLSF IntAck [0 ] 0 -OLSF All_Acks [0 ] 0 -OLSF L2_Replacement [0 ] 0 - -ILOW L1_GETS [0 ] 0 -ILOW L1_GETX [0 ] 0 -ILOW L1_PUTO [0 ] 0 -ILOW L1_PUTX [0 ] 0 -ILOW L1_PUTS_only [0 ] 0 -ILOW L1_PUTS [0 ] 0 -ILOW Fwd_GETX [0 ] 0 -ILOW Fwd_GETS [0 ] 0 -ILOW Fwd_DMA [0 ] 0 -ILOW Inv [0 ] 0 -ILOW L1_WBCLEANDATA [0 ] 0 -ILOW L1_WBDIRTYDATA [0 ] 0 -ILOW Unblock [0 ] 0 -ILOW L2_Replacement [0 ] 0 - -ILOXW L1_GETS [0 ] 0 -ILOXW L1_GETX [0 ] 0 -ILOXW L1_PUTO [0 ] 0 -ILOXW L1_PUTX [0 ] 0 -ILOXW L1_PUTS_only [0 ] 0 -ILOXW L1_PUTS [0 ] 0 -ILOXW Fwd_GETX [0 ] 0 -ILOXW Fwd_GETS [0 ] 0 -ILOXW Fwd_DMA [0 ] 0 -ILOXW Inv [0 ] 0 -ILOXW L1_WBCLEANDATA [0 ] 0 -ILOXW L1_WBDIRTYDATA [0 ] 0 -ILOXW Unblock [0 ] 0 -ILOXW L2_Replacement [0 ] 0 - -ILOSW L1_GETS [0 ] 0 -ILOSW L1_GETX [0 ] 0 -ILOSW L1_PUTO [0 ] 0 -ILOSW L1_PUTX [0 ] 0 -ILOSW L1_PUTS_only [0 ] 0 -ILOSW L1_PUTS [0 ] 0 -ILOSW Fwd_GETX [0 ] 0 -ILOSW Fwd_GETS [0 ] 0 -ILOSW Fwd_DMA [0 ] 0 -ILOSW Inv [0 ] 0 -ILOSW L1_WBCLEANDATA [0 ] 0 -ILOSW L1_WBDIRTYDATA [0 ] 0 -ILOSW Unblock [0 ] 0 -ILOSW L2_Replacement [0 ] 0 - -ILOSXW L1_GETS [0 ] 0 -ILOSXW L1_GETX [0 ] 0 -ILOSXW L1_PUTO [0 ] 0 -ILOSXW L1_PUTX [0 ] 0 -ILOSXW L1_PUTS_only [0 ] 0 -ILOSXW L1_PUTS [0 ] 0 -ILOSXW Fwd_GETX [0 ] 0 -ILOSXW Fwd_GETS [0 ] 0 -ILOSXW Fwd_DMA [0 ] 0 -ILOSXW Inv [0 ] 0 -ILOSXW L1_WBCLEANDATA [0 ] 0 -ILOSXW L1_WBDIRTYDATA [0 ] 0 -ILOSXW Unblock [0 ] 0 -ILOSXW L2_Replacement [0 ] 0 - -SLSW L1_GETS [0 ] 0 -SLSW L1_GETX [0 ] 0 -SLSW L1_PUTO [0 ] 0 -SLSW L1_PUTX [0 ] 0 -SLSW L1_PUTS_only [0 ] 0 -SLSW L1_PUTS [0 ] 0 -SLSW Fwd_GETX [0 ] 0 -SLSW Fwd_GETS [0 ] 0 -SLSW Fwd_DMA [0 ] 0 -SLSW Inv [0 ] 0 -SLSW Unblock [0 ] 0 -SLSW L2_Replacement [0 ] 0 - -OLSW L1_GETS [0 ] 0 -OLSW L1_GETX [0 ] 0 -OLSW L1_PUTO [0 ] 0 -OLSW L1_PUTX [0 ] 0 -OLSW L1_PUTS_only [0 ] 0 -OLSW L1_PUTS [0 ] 0 -OLSW Fwd_GETX [0 ] 0 -OLSW Fwd_GETS [0 ] 0 -OLSW Fwd_DMA [0 ] 0 -OLSW Inv [0 ] 0 -OLSW Unblock [0 ] 0 -OLSW L2_Replacement [0 ] 0 - -ILSW L1_GETS [0 ] 0 -ILSW L1_GETX [0 ] 0 -ILSW L1_PUTO [0 ] 0 -ILSW L1_PUTX [0 ] 0 -ILSW L1_PUTS_only [0 ] 0 -ILSW L1_PUTS [0 ] 0 -ILSW Fwd_GETX [0 ] 0 -ILSW Fwd_GETS [0 ] 0 -ILSW Fwd_DMA [0 ] 0 -ILSW Inv [0 ] 0 -ILSW L1_WBCLEANDATA [0 ] 0 -ILSW Unblock [0 ] 0 -ILSW L2_Replacement [0 ] 0 - -IW L1_GETS [0 ] 0 -IW L1_GETX [0 ] 0 -IW L1_PUTO [0 ] 0 -IW L1_PUTX [0 ] 0 -IW L1_PUTS_only [0 ] 0 -IW L1_PUTS [0 ] 0 -IW Fwd_GETX [0 ] 0 -IW Fwd_GETS [0 ] 0 -IW Fwd_DMA [0 ] 0 -IW Inv [0 ] 0 -IW L1_WBCLEANDATA [0 ] 0 -IW L2_Replacement [0 ] 0 - -OW L1_GETS [0 ] 0 -OW L1_GETX [0 ] 0 -OW L1_PUTO [0 ] 0 -OW L1_PUTX [0 ] 0 -OW L1_PUTS_only [0 ] 0 -OW L1_PUTS [0 ] 0 -OW Fwd_GETX [0 ] 0 -OW Fwd_GETS [0 ] 0 -OW Fwd_DMA [0 ] 0 -OW Inv [0 ] 0 -OW Unblock [0 ] 0 -OW L2_Replacement [0 ] 0 - -SW L1_GETS [0 ] 0 -SW L1_GETX [0 ] 0 -SW L1_PUTO [0 ] 0 -SW L1_PUTX [0 ] 0 -SW L1_PUTS_only [0 ] 0 -SW L1_PUTS [0 ] 0 -SW Fwd_GETX [0 ] 0 -SW Fwd_GETS [0 ] 0 -SW Fwd_DMA [0 ] 0 -SW Inv [0 ] 0 -SW Unblock [0 ] 0 -SW L2_Replacement [0 ] 0 - -OXW L1_GETS [0 ] 0 -OXW L1_GETX [0 ] 0 -OXW L1_PUTO [0 ] 0 -OXW L1_PUTX [0 ] 0 -OXW L1_PUTS_only [0 ] 0 -OXW L1_PUTS [0 ] 0 -OXW Fwd_GETX [0 ] 0 -OXW Fwd_GETS [0 ] 0 -OXW Fwd_DMA [0 ] 0 -OXW Inv [0 ] 0 -OXW Unblock [0 ] 0 -OXW L2_Replacement [0 ] 0 - -OLSXW L1_GETS [0 ] 0 -OLSXW L1_GETX [0 ] 0 -OLSXW L1_PUTO [0 ] 0 -OLSXW L1_PUTX [0 ] 0 -OLSXW L1_PUTS_only [0 ] 0 -OLSXW L1_PUTS [0 ] 0 -OLSXW Fwd_GETX [0 ] 0 -OLSXW Fwd_GETS [0 ] 0 -OLSXW Fwd_DMA [0 ] 0 -OLSXW Inv [0 ] 0 -OLSXW Unblock [0 ] 0 -OLSXW L2_Replacement [0 ] 0 - -ILXW L1_GETS [0 ] 0 -ILXW L1_GETX [0 ] 0 -ILXW L1_PUTO [0 ] 0 -ILXW L1_PUTX [0 ] 0 -ILXW L1_PUTS_only [0 ] 0 -ILXW L1_PUTS [0 ] 0 -ILXW Fwd_GETX [0 ] 0 -ILXW Fwd_GETS [0 ] 0 -ILXW Fwd_DMA [0 ] 0 -ILXW Inv [0 ] 0 -ILXW Data [0 ] 0 -ILXW L1_WBCLEANDATA [396 ] 396 -ILXW L1_WBDIRTYDATA [106 ] 106 -ILXW Unblock [0 ] 0 -ILXW L2_Replacement [0 ] 0 - -IFLS L1_GETS [0 ] 0 -IFLS L1_GETX [0 ] 0 -IFLS L1_PUTO [0 ] 0 -IFLS L1_PUTX [0 ] 0 -IFLS L1_PUTS_only [0 ] 0 -IFLS L1_PUTS [0 ] 0 -IFLS Fwd_GETX [0 ] 0 -IFLS Fwd_GETS [0 ] 0 -IFLS Fwd_DMA [0 ] 0 -IFLS Inv [0 ] 0 -IFLS Unblock [0 ] 0 -IFLS L2_Replacement [0 ] 0 - -IFLO L1_GETS [0 ] 0 -IFLO L1_GETX [0 ] 0 -IFLO L1_PUTO [0 ] 0 -IFLO L1_PUTX [0 ] 0 -IFLO L1_PUTS_only [0 ] 0 -IFLO L1_PUTS [0 ] 0 -IFLO Fwd_GETX [0 ] 0 -IFLO Fwd_GETS [0 ] 0 -IFLO Fwd_DMA [0 ] 0 -IFLO Inv [0 ] 0 -IFLO Unblock [0 ] 0 -IFLO L2_Replacement [0 ] 0 - -IFLOX L1_GETS [0 ] 0 -IFLOX L1_GETX [0 ] 0 -IFLOX L1_PUTO [0 ] 0 -IFLOX L1_PUTX [0 ] 0 -IFLOX L1_PUTS_only [0 ] 0 -IFLOX L1_PUTS [0 ] 0 -IFLOX Fwd_GETX [0 ] 0 -IFLOX Fwd_GETS [0 ] 0 -IFLOX Fwd_DMA [0 ] 0 -IFLOX Inv [0 ] 0 -IFLOX Unblock [0 ] 0 -IFLOX Exclusive_Unblock [0 ] 0 -IFLOX L2_Replacement [0 ] 0 - -IFLOXX L1_GETS [0 ] 0 -IFLOXX L1_GETX [0 ] 0 -IFLOXX L1_PUTO [0 ] 0 -IFLOXX L1_PUTX [0 ] 0 -IFLOXX L1_PUTS_only [0 ] 0 -IFLOXX L1_PUTS [0 ] 0 -IFLOXX Fwd_GETX [0 ] 0 -IFLOXX Fwd_GETS [0 ] 0 -IFLOXX Fwd_DMA [0 ] 0 -IFLOXX Inv [0 ] 0 -IFLOXX Unblock [0 ] 0 -IFLOXX Exclusive_Unblock [0 ] 0 -IFLOXX L2_Replacement [0 ] 0 - -IFLOSX L1_GETS [0 ] 0 -IFLOSX L1_GETX [0 ] 0 -IFLOSX L1_PUTO [0 ] 0 -IFLOSX L1_PUTX [0 ] 0 -IFLOSX L1_PUTS_only [0 ] 0 -IFLOSX L1_PUTS [0 ] 0 -IFLOSX Fwd_GETX [0 ] 0 -IFLOSX Fwd_GETS [0 ] 0 -IFLOSX Fwd_DMA [0 ] 0 -IFLOSX Inv [0 ] 0 -IFLOSX Unblock [0 ] 0 -IFLOSX Exclusive_Unblock [0 ] 0 -IFLOSX L2_Replacement [0 ] 0 - -IFLXO L1_GETS [0 ] 0 -IFLXO L1_GETX [0 ] 0 -IFLXO L1_PUTO [0 ] 0 -IFLXO L1_PUTX [0 ] 0 -IFLXO L1_PUTS_only [0 ] 0 -IFLXO L1_PUTS [0 ] 0 -IFLXO Fwd_GETX [0 ] 0 -IFLXO Fwd_GETS [0 ] 0 -IFLXO Fwd_DMA [0 ] 0 -IFLXO Inv [0 ] 0 -IFLXO Exclusive_Unblock [0 ] 0 -IFLXO L2_Replacement [0 ] 0 - -IGS L1_GETS [0 ] 0 -IGS L1_GETX [0 ] 0 -IGS L1_PUTO [0 ] 0 -IGS L1_PUTX [0 ] 0 -IGS L1_PUTS_only [0 ] 0 -IGS L1_PUTS [0 ] 0 -IGS Fwd_GETX [0 ] 0 -IGS Fwd_GETS [0 ] 0 -IGS Fwd_DMA [0 ] 0 -IGS Own_GETX [0 ] 0 -IGS Inv [0 ] 0 -IGS Data [0 ] 0 -IGS Data_Exclusive [380 ] 380 -IGS Unblock [0 ] 0 -IGS Exclusive_Unblock [380 ] 380 -IGS L2_Replacement [0 ] 0 - -IGM L1_GETS [0 ] 0 -IGM L1_GETX [0 ] 0 -IGM L1_PUTO [0 ] 0 -IGM L1_PUTX [0 ] 0 -IGM L1_PUTS_only [0 ] 0 -IGM L1_PUTS [0 ] 0 -IGM Fwd_GETX [0 ] 0 -IGM Fwd_GETS [0 ] 0 -IGM Fwd_DMA [0 ] 0 -IGM Own_GETX [0 ] 0 -IGM Inv [0 ] 0 -IGM ExtAck [0 ] 0 -IGM Data [43 ] 43 -IGM Data_Exclusive [0 ] 0 -IGM L2_Replacement [0 ] 0 - -IGMLS L1_GETS [0 ] 0 -IGMLS L1_GETX [0 ] 0 -IGMLS L1_PUTO [0 ] 0 -IGMLS L1_PUTX [0 ] 0 -IGMLS L1_PUTS_only [0 ] 0 -IGMLS L1_PUTS [0 ] 0 -IGMLS Inv [0 ] 0 -IGMLS IntAck [0 ] 0 -IGMLS ExtAck [0 ] 0 -IGMLS All_Acks [0 ] 0 -IGMLS Data [0 ] 0 -IGMLS Data_Exclusive [0 ] 0 -IGMLS L2_Replacement [0 ] 0 - -IGMO L1_GETS [0 ] 0 -IGMO L1_GETX [0 ] 0 -IGMO L1_PUTO [0 ] 0 -IGMO L1_PUTX [0 ] 0 -IGMO L1_PUTS_only [0 ] 0 -IGMO L1_PUTS [0 ] 0 -IGMO Fwd_GETX [0 ] 0 -IGMO Fwd_GETS [0 ] 0 -IGMO Fwd_DMA [0 ] 0 -IGMO Own_GETX [0 ] 0 -IGMO ExtAck [0 ] 0 -IGMO All_Acks [43 ] 43 -IGMO Exclusive_Unblock [43 ] 43 -IGMO L2_Replacement [0 ] 0 - -IGMIO L1_GETS [0 ] 0 -IGMIO L1_GETX [0 ] 0 -IGMIO L1_PUTO [0 ] 0 -IGMIO L1_PUTX [0 ] 0 -IGMIO L1_PUTS_only [0 ] 0 -IGMIO L1_PUTS [0 ] 0 -IGMIO Fwd_GETX [0 ] 0 -IGMIO Fwd_GETS [0 ] 0 -IGMIO Fwd_DMA [0 ] 0 -IGMIO Own_GETX [0 ] 0 -IGMIO ExtAck [0 ] 0 -IGMIO All_Acks [0 ] 0 - -OGMIO L1_GETS [0 ] 0 -OGMIO L1_GETX [0 ] 0 -OGMIO L1_PUTO [0 ] 0 -OGMIO L1_PUTX [0 ] 0 -OGMIO L1_PUTS_only [0 ] 0 -OGMIO L1_PUTS [0 ] 0 -OGMIO Fwd_GETX [0 ] 0 -OGMIO Fwd_GETS [0 ] 0 -OGMIO Fwd_DMA [0 ] 0 -OGMIO Own_GETX [0 ] 0 -OGMIO ExtAck [0 ] 0 -OGMIO All_Acks [0 ] 0 - -IGMIOF L1_GETS [0 ] 0 -IGMIOF L1_GETX [0 ] 0 -IGMIOF L1_PUTO [0 ] 0 -IGMIOF L1_PUTX [0 ] 0 -IGMIOF L1_PUTS_only [0 ] 0 -IGMIOF L1_PUTS [0 ] 0 -IGMIOF IntAck [0 ] 0 -IGMIOF All_Acks [0 ] 0 -IGMIOF Data_Exclusive [0 ] 0 - -IGMIOFS L1_GETS [0 ] 0 -IGMIOFS L1_GETX [0 ] 0 -IGMIOFS L1_PUTO [0 ] 0 -IGMIOFS L1_PUTX [0 ] 0 -IGMIOFS L1_PUTS_only [0 ] 0 -IGMIOFS L1_PUTS [0 ] 0 -IGMIOFS Fwd_GETX [0 ] 0 -IGMIOFS Fwd_GETS [0 ] 0 -IGMIOFS Fwd_DMA [0 ] 0 -IGMIOFS Inv [0 ] 0 -IGMIOFS Data [0 ] 0 -IGMIOFS L2_Replacement [0 ] 0 - -OGMIOF L1_GETS [0 ] 0 -OGMIOF L1_GETX [0 ] 0 -OGMIOF L1_PUTO [0 ] 0 -OGMIOF L1_PUTX [0 ] 0 -OGMIOF L1_PUTS_only [0 ] 0 -OGMIOF L1_PUTS [0 ] 0 -OGMIOF IntAck [0 ] 0 -OGMIOF All_Acks [0 ] 0 - -II L1_GETS [0 ] 0 -II L1_GETX [0 ] 0 -II L1_PUTO [0 ] 0 -II L1_PUTX [0 ] 0 -II L1_PUTS_only [0 ] 0 -II L1_PUTS [0 ] 0 -II IntAck [0 ] 0 -II All_Acks [0 ] 0 - -MM L1_GETS [0 ] 0 -MM L1_GETX [0 ] 0 -MM L1_PUTO [0 ] 0 -MM L1_PUTX [0 ] 0 -MM L1_PUTS_only [0 ] 0 -MM L1_PUTS [0 ] 0 -MM Fwd_GETX [0 ] 0 -MM Fwd_GETS [0 ] 0 -MM Fwd_DMA [0 ] 0 -MM Inv [0 ] 0 -MM Exclusive_Unblock [15 ] 15 -MM L2_Replacement [0 ] 0 - -SS L1_GETS [0 ] 0 -SS L1_GETX [0 ] 0 -SS L1_PUTO [0 ] 0 -SS L1_PUTX [0 ] 0 -SS L1_PUTS_only [0 ] 0 -SS L1_PUTS [0 ] 0 -SS Fwd_GETX [0 ] 0 -SS Fwd_GETS [0 ] 0 -SS Fwd_DMA [0 ] 0 -SS Inv [0 ] 0 -SS Unblock [0 ] 0 -SS L2_Replacement [0 ] 0 - -OO L1_GETS [0 ] 0 -OO L1_GETX [0 ] 0 -OO L1_PUTO [0 ] 0 -OO L1_PUTX [0 ] 0 -OO L1_PUTS_only [0 ] 0 -OO L1_PUTS [0 ] 0 -OO Fwd_GETX [0 ] 0 -OO Fwd_GETS [0 ] 0 -OO Fwd_DMA [0 ] 0 -OO Inv [0 ] 0 -OO Unblock [0 ] 0 -OO Exclusive_Unblock [72 ] 72 -OO L2_Replacement [0 ] 0 - -OLSS L1_GETS [0 ] 0 -OLSS L1_GETX [0 ] 0 -OLSS L1_PUTO [0 ] 0 -OLSS L1_PUTX [0 ] 0 -OLSS L1_PUTS_only [0 ] 0 -OLSS L1_PUTS [0 ] 0 -OLSS Fwd_GETX [0 ] 0 -OLSS Fwd_GETS [0 ] 0 -OLSS Fwd_DMA [0 ] 0 -OLSS Inv [0 ] 0 -OLSS Unblock [0 ] 0 -OLSS L2_Replacement [0 ] 0 - -OLSXS L1_GETS [0 ] 0 -OLSXS L1_GETX [0 ] 0 -OLSXS L1_PUTO [0 ] 0 -OLSXS L1_PUTX [0 ] 0 -OLSXS L1_PUTS_only [0 ] 0 -OLSXS L1_PUTS [0 ] 0 -OLSXS Fwd_GETX [0 ] 0 -OLSXS Fwd_GETS [0 ] 0 -OLSXS Fwd_DMA [0 ] 0 -OLSXS Inv [0 ] 0 -OLSXS Unblock [0 ] 0 -OLSXS L2_Replacement [0 ] 0 - -SLSS L1_GETS [0 ] 0 -SLSS L1_GETX [0 ] 0 -SLSS L1_PUTO [0 ] 0 -SLSS L1_PUTX [0 ] 0 -SLSS L1_PUTS_only [0 ] 0 -SLSS L1_PUTS [0 ] 0 -SLSS Fwd_GETX [0 ] 0 -SLSS Fwd_GETS [0 ] 0 -SLSS Fwd_DMA [0 ] 0 -SLSS Inv [0 ] 0 -SLSS Unblock [0 ] 0 -SLSS L2_Replacement [0 ] 0 - -OI L1_GETS [0 ] 0 -OI L1_GETX [0 ] 0 -OI L1_PUTO [0 ] 0 -OI L1_PUTX [0 ] 0 -OI L1_PUTS_only [0 ] 0 -OI L1_PUTS [0 ] 0 -OI Fwd_GETX [0 ] 0 -OI Fwd_GETS [0 ] 0 -OI Fwd_DMA [0 ] 0 -OI Writeback_Ack [0 ] 0 -OI Writeback_Nack [0 ] 0 -OI L2_Replacement [0 ] 0 - -MI L1_GETS [2 ] 2 -MI L1_GETX [0 ] 0 -MI L1_PUTO [0 ] 0 -MI L1_PUTX [0 ] 0 -MI L1_PUTS_only [0 ] 0 -MI L1_PUTS [0 ] 0 -MI Fwd_GETX [0 ] 0 -MI Fwd_GETS [0 ] 0 -MI Fwd_DMA [0 ] 0 -MI Writeback_Ack [407 ] 407 -MI L2_Replacement [0 ] 0 - -MII L1_GETS [0 ] 0 -MII L1_GETX [0 ] 0 -MII L1_PUTO [0 ] 0 -MII L1_PUTX [0 ] 0 -MII L1_PUTS_only [0 ] 0 -MII L1_PUTS [0 ] 0 -MII Writeback_Ack [0 ] 0 -MII Writeback_Nack [0 ] 0 -MII L2_Replacement [0 ] 0 - -OLSI L1_GETS [0 ] 0 -OLSI L1_GETX [0 ] 0 -OLSI L1_PUTO [0 ] 0 -OLSI L1_PUTX [0 ] 0 -OLSI L1_PUTS_only [0 ] 0 -OLSI L1_PUTS [0 ] 0 -OLSI Fwd_GETX [0 ] 0 -OLSI Fwd_GETS [0 ] 0 -OLSI Fwd_DMA [0 ] 0 -OLSI Writeback_Ack [0 ] 0 -OLSI L2_Replacement [0 ] 0 - -ILSI L1_GETS [0 ] 0 -ILSI L1_GETX [0 ] 0 -ILSI L1_PUTO [0 ] 0 -ILSI L1_PUTX [0 ] 0 -ILSI L1_PUTS_only [0 ] 0 -ILSI L1_PUTS [0 ] 0 -ILSI IntAck [0 ] 0 -ILSI All_Acks [0 ] 0 -ILSI Writeback_Ack [0 ] 0 -ILSI L2_Replacement [0 ] 0 - -ILOSD L1_GETS [0 ] 0 -ILOSD L1_GETX [0 ] 0 -ILOSD L1_PUTO [0 ] 0 -ILOSD L1_PUTX [0 ] 0 -ILOSD L1_PUTS_only [0 ] 0 -ILOSD L1_PUTS [0 ] 0 -ILOSD Fwd_GETX [0 ] 0 -ILOSD Fwd_GETS [0 ] 0 -ILOSD Fwd_DMA [0 ] 0 -ILOSD Own_GETX [0 ] 0 -ILOSD Inv [0 ] 0 -ILOSD DmaAck [0 ] 0 -ILOSD L2_Replacement [0 ] 0 - -ILOSXD L1_GETS [0 ] 0 -ILOSXD L1_GETX [0 ] 0 -ILOSXD L1_PUTO [0 ] 0 -ILOSXD L1_PUTX [0 ] 0 -ILOSXD L1_PUTS_only [0 ] 0 -ILOSXD L1_PUTS [0 ] 0 -ILOSXD Fwd_GETX [0 ] 0 -ILOSXD Fwd_GETS [0 ] 0 -ILOSXD Fwd_DMA [0 ] 0 -ILOSXD Own_GETX [0 ] 0 -ILOSXD Inv [0 ] 0 -ILOSXD DmaAck [0 ] 0 -ILOSXD L2_Replacement [0 ] 0 - -ILOD L1_GETS [0 ] 0 -ILOD L1_GETX [0 ] 0 -ILOD L1_PUTO [0 ] 0 -ILOD L1_PUTX [0 ] 0 -ILOD L1_PUTS_only [0 ] 0 -ILOD L1_PUTS [0 ] 0 -ILOD Fwd_GETX [0 ] 0 -ILOD Fwd_GETS [0 ] 0 -ILOD Fwd_DMA [0 ] 0 -ILOD Own_GETX [0 ] 0 -ILOD Inv [0 ] 0 -ILOD DmaAck [0 ] 0 -ILOD L2_Replacement [0 ] 0 - -ILXD L1_GETS [0 ] 0 -ILXD L1_GETX [0 ] 0 -ILXD L1_PUTO [0 ] 0 -ILXD L1_PUTX [0 ] 0 -ILXD L1_PUTS_only [0 ] 0 -ILXD L1_PUTS [0 ] 0 -ILXD Fwd_GETX [0 ] 0 -ILXD Fwd_GETS [0 ] 0 -ILXD Fwd_DMA [0 ] 0 -ILXD Own_GETX [0 ] 0 -ILXD Inv [0 ] 0 -ILXD DmaAck [0 ] 0 -ILXD L2_Replacement [0 ] 0 - -ILOXD L1_GETS [0 ] 0 -ILOXD L1_GETX [0 ] 0 -ILOXD L1_PUTO [0 ] 0 -ILOXD L1_PUTX [0 ] 0 -ILOXD L1_PUTS_only [0 ] 0 -ILOXD L1_PUTS [0 ] 0 -ILOXD Fwd_GETX [0 ] 0 -ILOXD Fwd_GETS [0 ] 0 -ILOXD Fwd_DMA [0 ] 0 -ILOXD Own_GETX [0 ] 0 -ILOXD Inv [0 ] 0 -ILOXD DmaAck [0 ] 0 -ILOXD L2_Replacement [0 ] 0 - -Memory controller: system.dir_cntrl0.memBuffer: - memory_total_requests: 499 - memory_reads: 423 - memory_writes: 76 - memory_refreshes: 178 - memory_total_request_delays: 116 - memory_delays_per_request: 0.232465 - memory_delays_in_input_queue: 2 - memory_delays_behind_head_of_bank_queue: 0 - memory_delays_stalled_at_head_of_bank_queue: 114 - memory_stalls_for_bank_busy: 56 - memory_stalls_for_random_busy: 0 - memory_stalls_for_anti_starvation: 0 - memory_stalls_for_arbitration: 10 - memory_stalls_for_bus: 25 - memory_stalls_for_tfaw: 0 - memory_stalls_for_read_write_turnaround: 23 - memory_stalls_for_read_read_turnaround: 0 - accesses_per_bank: 18 10 0 34 20 19 28 21 5 3 6 4 21 40 20 3 4 5 7 13 10 16 14 41 15 5 5 12 12 18 14 56 - - --- Directory --- - - Event Counts - -GETX [43 ] 43 -GETS [380 ] 380 -PUTX [407 ] 407 -PUTO [0 ] 0 -PUTO_SHARERS [0 ] 0 -Unblock [0 ] 0 -Last_Unblock [0 ] 0 -Exclusive_Unblock [422 ] 422 -Clean_Writeback [331 ] 331 -Dirty_Writeback [76 ] 76 -Memory_Data [423 ] 423 -Memory_Ack [76 ] 76 -DMA_READ [0 ] 0 -DMA_WRITE [0 ] 0 -DMA_ACK [0 ] 0 -Data [0 ] 0 - - - Transitions - -I GETX [43 ] 43 -I GETS [380 ] 380 -I PUTX [0 ] 0 -I PUTO [0 ] 0 -I Memory_Data [0 ] 0 -I Memory_Ack [74 ] 74 -I DMA_READ [0 ] 0 -I DMA_WRITE [0 ] 0 - -S GETX [0 ] 0 -S GETS [0 ] 0 -S PUTX [0 ] 0 -S PUTO [0 ] 0 -S Memory_Data [0 ] 0 -S Memory_Ack [0 ] 0 -S DMA_READ [0 ] 0 -S DMA_WRITE [0 ] 0 - -O GETX [0 ] 0 -O GETS [0 ] 0 -O PUTX [0 ] 0 -O PUTO [0 ] 0 -O PUTO_SHARERS [0 ] 0 -O Memory_Data [0 ] 0 -O Memory_Ack [0 ] 0 -O DMA_READ [0 ] 0 -O DMA_WRITE [0 ] 0 - -M GETX [0 ] 0 -M GETS [0 ] 0 -M PUTX [407 ] 407 -M PUTO [0 ] 0 -M PUTO_SHARERS [0 ] 0 -M Memory_Data [0 ] 0 -M Memory_Ack [0 ] 0 -M DMA_READ [0 ] 0 -M DMA_WRITE [0 ] 0 - -IS GETX [0 ] 0 -IS GETS [0 ] 0 -IS PUTX [0 ] 0 -IS PUTO [0 ] 0 -IS PUTO_SHARERS [0 ] 0 -IS Unblock [0 ] 0 -IS Exclusive_Unblock [379 ] 379 -IS Memory_Data [380 ] 380 -IS Memory_Ack [2 ] 2 -IS DMA_READ [0 ] 0 -IS DMA_WRITE [0 ] 0 - -SS GETX [0 ] 0 -SS GETS [0 ] 0 -SS PUTX [0 ] 0 -SS PUTO [0 ] 0 -SS PUTO_SHARERS [0 ] 0 -SS Unblock [0 ] 0 -SS Last_Unblock [0 ] 0 -SS Memory_Data [0 ] 0 -SS Memory_Ack [0 ] 0 -SS DMA_READ [0 ] 0 -SS DMA_WRITE [0 ] 0 - -OO GETX [0 ] 0 -OO GETS [0 ] 0 -OO PUTX [0 ] 0 -OO PUTO [0 ] 0 -OO PUTO_SHARERS [0 ] 0 -OO Unblock [0 ] 0 -OO Last_Unblock [0 ] 0 -OO Memory_Data [0 ] 0 -OO Memory_Ack [0 ] 0 -OO DMA_READ [0 ] 0 -OO DMA_WRITE [0 ] 0 - -MO GETX [0 ] 0 -MO GETS [0 ] 0 -MO PUTX [0 ] 0 -MO PUTO [0 ] 0 -MO PUTO_SHARERS [0 ] 0 -MO Unblock [0 ] 0 -MO Exclusive_Unblock [0 ] 0 -MO Memory_Data [0 ] 0 -MO Memory_Ack [0 ] 0 -MO DMA_READ [0 ] 0 -MO DMA_WRITE [0 ] 0 - -MM GETX [0 ] 0 -MM GETS [0 ] 0 -MM PUTX [0 ] 0 -MM PUTO [0 ] 0 -MM PUTO_SHARERS [0 ] 0 -MM Exclusive_Unblock [43 ] 43 -MM Memory_Data [43 ] 43 -MM Memory_Ack [0 ] 0 -MM DMA_READ [0 ] 0 -MM DMA_WRITE [0 ] 0 - - -MI GETX [0 ] 0 -MI GETS [0 ] 0 -MI PUTX [0 ] 0 -MI PUTO [0 ] 0 -MI PUTO_SHARERS [0 ] 0 -MI Unblock [0 ] 0 -MI Clean_Writeback [331 ] 331 -MI Dirty_Writeback [76 ] 76 -MI Memory_Data [0 ] 0 -MI Memory_Ack [0 ] 0 -MI DMA_READ [0 ] 0 -MI DMA_WRITE [0 ] 0 - -MIS GETX [0 ] 0 -MIS GETS [0 ] 0 -MIS PUTX [0 ] 0 -MIS PUTO [0 ] 0 -MIS PUTO_SHARERS [0 ] 0 -MIS Unblock [0 ] 0 -MIS Clean_Writeback [0 ] 0 -MIS Dirty_Writeback [0 ] 0 -MIS Memory_Data [0 ] 0 -MIS Memory_Ack [0 ] 0 -MIS DMA_READ [0 ] 0 -MIS DMA_WRITE [0 ] 0 - -OS GETX [0 ] 0 -OS GETS [0 ] 0 -OS PUTX [0 ] 0 -OS PUTO [0 ] 0 -OS PUTO_SHARERS [0 ] 0 -OS Unblock [0 ] 0 -OS Clean_Writeback [0 ] 0 -OS Dirty_Writeback [0 ] 0 -OS Memory_Data [0 ] 0 -OS Memory_Ack [0 ] 0 -OS DMA_READ [0 ] 0 -OS DMA_WRITE [0 ] 0 - -OSS GETX [0 ] 0 -OSS GETS [0 ] 0 -OSS PUTX [0 ] 0 -OSS PUTO [0 ] 0 -OSS PUTO_SHARERS [0 ] 0 -OSS Unblock [0 ] 0 -OSS Clean_Writeback [0 ] 0 -OSS Dirty_Writeback [0 ] 0 -OSS Memory_Data [0 ] 0 -OSS Memory_Ack [0 ] 0 -OSS DMA_READ [0 ] 0 -OSS DMA_WRITE [0 ] 0 - -XI_M GETX [0 ] 0 -XI_M GETS [0 ] 0 -XI_M PUTX [0 ] 0 -XI_M PUTO [0 ] 0 -XI_M PUTO_SHARERS [0 ] 0 -XI_M Memory_Data [0 ] 0 -XI_M Memory_Ack [0 ] 0 -XI_M DMA_READ [0 ] 0 -XI_M DMA_WRITE [0 ] 0 - -XI_U GETX [0 ] 0 -XI_U GETS [0 ] 0 -XI_U PUTX [0 ] 0 -XI_U PUTO [0 ] 0 -XI_U PUTO_SHARERS [0 ] 0 -XI_U Exclusive_Unblock [0 ] 0 -XI_U Memory_Ack [0 ] 0 -XI_U DMA_READ [0 ] 0 -XI_U DMA_WRITE [0 ] 0 - -OI_D GETX [0 ] 0 -OI_D GETS [0 ] 0 -OI_D PUTX [0 ] 0 -OI_D PUTO [0 ] 0 -OI_D PUTO_SHARERS [0 ] 0 -OI_D DMA_READ [0 ] 0 -OI_D DMA_WRITE [0 ] 0 -OI_D Data [0 ] 0 - -OD GETX [0 ] 0 -OD GETS [0 ] 0 -OD PUTX [0 ] 0 -OD PUTO [0 ] 0 -OD PUTO_SHARERS [0 ] 0 -OD DMA_READ [0 ] 0 -OD DMA_WRITE [0 ] 0 -OD DMA_ACK [0 ] 0 - -MD GETX [0 ] 0 -MD GETS [0 ] 0 -MD PUTX [0 ] 0 -MD PUTO [0 ] 0 -MD PUTO_SHARERS [0 ] 0 -MD DMA_READ [0 ] 0 -MD DMA_WRITE [0 ] 0 -MD DMA_ACK [0 ] 0 - diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simerr b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simerr deleted file mode 100755 index 31ae36f2e..000000000 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simerr +++ /dev/null @@ -1,3 +0,0 @@ -warn: Sockets disabled, not accepting gdb connections -warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...) -hack: be nice to actually delete the event here diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simout b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simout deleted file mode 100755 index 0529ad1d8..000000000 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simout +++ /dev/null @@ -1,12 +0,0 @@ -gem5 Simulator System. http://gem5.org -gem5 is copyrighted software; use the --copyright option for details. - -gem5 compiled Jan 23 2012 03:47:36 -gem5 started Jan 23 2012 04:22:12 -gem5 executing on zizzer -command line: build/ALPHA_SE_MOESI_CMP_directory/gem5.opt -d build/ALPHA_SE_MOESI_CMP_directory/tests/opt/quick/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory -re tests/run.py build/ALPHA_SE_MOESI_CMP_directory/tests/opt/quick/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory -Global frequency set at 1000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -info: Increasing stack size by one page. -Hello world! -Exiting @ tick 85418 because target called exit() diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt deleted file mode 100644 index 8d97fa8c6..000000000 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt +++ /dev/null @@ -1,77 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 0.000085 # Number of seconds simulated -sim_ticks 85418 # Number of ticks simulated -final_tick 85418 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 13096 # Simulator instruction rate (inst/s) -host_tick_rate 434048 # Simulator tick rate (ticks/s) -host_mem_usage 217400 # Number of bytes of host memory used -host_seconds 0.20 # Real time elapsed on the host -sim_insts 2577 # Number of instructions simulated -system.physmem.bytes_read 13356 # Number of bytes read from this memory -system.physmem.bytes_inst_read 10340 # Number of instructions bytes read from this memory -system.physmem.bytes_written 2058 # Number of bytes written to this memory -system.physmem.num_reads 3000 # Number of read requests responded to by this memory -system.physmem.num_writes 294 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 156360486 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 121051769 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 24093282 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 180453769 # Total bandwidth to/from this memory (bytes/s) -system.cpu.dtb.fetch_hits 0 # ITB hits -system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.fetch_acv 0 # ITB acv -system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 415 # DTB read hits -system.cpu.dtb.read_misses 4 # DTB read misses -system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 419 # DTB read accesses -system.cpu.dtb.write_hits 294 # DTB write hits -system.cpu.dtb.write_misses 4 # DTB write misses -system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 298 # DTB write accesses -system.cpu.dtb.data_hits 709 # DTB hits -system.cpu.dtb.data_misses 8 # DTB misses -system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 717 # DTB accesses -system.cpu.itb.fetch_hits 2586 # ITB hits -system.cpu.itb.fetch_misses 11 # ITB misses -system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 2597 # ITB accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.read_acv 0 # DTB read access violations -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.write_acv 0 # DTB write access violations -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.data_hits 0 # DTB hits -system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.data_acv 0 # DTB access violations -system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.workload.num_syscalls 4 # Number of system calls -system.cpu.numCycles 85418 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.num_insts 2577 # Number of instructions executed -system.cpu.num_int_alu_accesses 2375 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 6 # Number of float alu accesses -system.cpu.num_func_calls 140 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 238 # number of instructions that are conditional controls -system.cpu.num_int_insts 2375 # number of integer instructions -system.cpu.num_fp_insts 6 # number of float instructions -system.cpu.num_int_register_reads 2998 # number of times the integer registers were read -system.cpu.num_int_register_writes 1768 # number of times the integer registers were written -system.cpu.num_fp_register_reads 6 # number of times the floating registers were read -system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_mem_refs 717 # number of memory refs -system.cpu.num_load_insts 419 # Number of load instructions -system.cpu.num_store_insts 298 # Number of store instructions -system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 85418 # Number of busy cycles -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.idle_fraction 0 # Percentage of idle cycles - ----------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/config.ini b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/config.ini deleted file mode 100644 index 4c0569af0..000000000 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/config.ini +++ /dev/null @@ -1,334 +0,0 @@ -[root] -type=Root -children=system -time_sync_enable=false -time_sync_period=100000000 -time_sync_spin_threshold=100000 - -[system] -type=System -children=cpu dir_cntrl0 l1_cntrl0 l2_cntrl0 physmem ruby sys_port_proxy -mem_mode=timing -memories=system.physmem -num_work_ids=16 -physmem=system.physmem -work_begin_ckpt_count=0 -work_begin_cpu_id_exit=-1 -work_begin_exit_count=0 -work_cpus_ckpt_count=0 -work_end_ckpt_count=0 -work_end_exit_count=0 -work_item_id=-1 -system_port=system.sys_port_proxy.port[0] - -[system.cpu] -type=TimingSimpleCPU -children=dtb itb tracer workload -checker=Null -clock=1 -cpu_id=0 -defer_registration=false -do_checkpoint_insts=true -do_statistics_insts=true -dtb=system.cpu.dtb -function_trace=false -function_trace_start=0 -itb=system.cpu.itb -max_insts_all_threads=0 -max_insts_any_thread=0 -max_loads_all_threads=0 -max_loads_any_thread=0 -numThreads=1 -phase=0 -progress_interval=0 -system=system -tracer=system.cpu.tracer -workload=system.cpu.workload -dcache_port=system.l1_cntrl0.sequencer.port[1] -icache_port=system.l1_cntrl0.sequencer.port[0] - -[system.cpu.dtb] -type=AlphaTLB -size=64 - -[system.cpu.itb] -type=AlphaTLB -size=48 - -[system.cpu.tracer] -type=ExeTracer - -[system.cpu.workload] -type=LiveProcess -cmd=hello -cwd= -egid=100 -env= -errout=cerr -euid=100 -executable=/dist/m5/regression/test-progs/hello/bin/alpha/tru64/hello -gid=100 -input=cin -max_stack_size=67108864 -output=cout -pid=100 -ppid=99 -simpoint=0 -system=system -uid=100 - -[system.dir_cntrl0] -type=Directory_Controller -children=directory memBuffer -buffer_size=0 -cntrl_id=2 -directory=system.dir_cntrl0.directory -directory_latency=5 -distributed_persistent=true -fixed_timeout_latency=100 -l2_select_num_bits=0 -memBuffer=system.dir_cntrl0.memBuffer -number_of_TBEs=256 -recycle_latency=10 -ruby_system=system.ruby -transitions_per_cycle=32 -version=0 - -[system.dir_cntrl0.directory] -type=RubyDirectoryMemory -map_levels=4 -numa_high_bit=6 -size=134217728 -use_map=false -version=0 - -[system.dir_cntrl0.memBuffer] -type=RubyMemoryControl -bank_bit_0=8 -bank_busy_time=11 -bank_queue_size=12 -banks_per_rank=8 -basic_bus_busy_time=2 -dimm_bit_0=12 -dimms_per_channel=2 -mem_bus_cycle_multiplier=10 -mem_ctl_latency=12 -mem_fixed_delay=0 -mem_random_arbitrate=0 -rank_bit_0=11 -rank_rank_delay=1 -ranks_per_dimm=2 -read_write_delay=2 -refresh_period=1560 -tFaw=0 -version=0 - -[system.l1_cntrl0] -type=L1Cache_Controller -children=L1DcacheMemory L1IcacheMemory sequencer -L1DcacheMemory=system.l1_cntrl0.L1DcacheMemory -L1IcacheMemory=system.l1_cntrl0.L1IcacheMemory -N_tokens=2 -buffer_size=0 -cntrl_id=0 -dynamic_timeout_enabled=true -fixed_timeout_latency=300 -l1_request_latency=2 -l1_response_latency=2 -l2_select_num_bits=0 -no_mig_atomic=true -number_of_TBEs=256 -recycle_latency=10 -retry_threshold=1 -ruby_system=system.ruby -sequencer=system.l1_cntrl0.sequencer -transitions_per_cycle=32 -version=0 - -[system.l1_cntrl0.L1DcacheMemory] -type=RubyCache -assoc=2 -is_icache=false -latency=2 -replacement_policy=PSEUDO_LRU -size=256 -start_index_bit=6 - -[system.l1_cntrl0.L1IcacheMemory] -type=RubyCache -assoc=2 -is_icache=false -latency=2 -replacement_policy=PSEUDO_LRU -size=256 -start_index_bit=6 - -[system.l1_cntrl0.sequencer] -type=RubySequencer -access_phys_mem=true -dcache=system.l1_cntrl0.L1DcacheMemory -deadlock_threshold=500000 -icache=system.l1_cntrl0.L1IcacheMemory -max_outstanding_requests=16 -physmem=system.physmem -ruby_system=system.ruby -using_network_tester=false -using_ruby_tester=false -version=0 -physMemPort=system.physmem.port[0] -port=system.cpu.icache_port system.cpu.dcache_port - -[system.l2_cntrl0] -type=L2Cache_Controller -children=L2cacheMemory -L2cacheMemory=system.l2_cntrl0.L2cacheMemory -N_tokens=2 -buffer_size=0 -cntrl_id=1 -filtering_enabled=true -l2_request_latency=5 -l2_response_latency=5 -number_of_TBEs=256 -recycle_latency=10 -ruby_system=system.ruby -transitions_per_cycle=32 -version=0 - -[system.l2_cntrl0.L2cacheMemory] -type=RubyCache -assoc=2 -is_icache=false -latency=10 -replacement_policy=PSEUDO_LRU -size=512 -start_index_bit=6 - -[system.physmem] -type=PhysicalMemory -file= -latency=30 -latency_var=0 -null=false -range=0:134217727 -zero=false -port=system.l1_cntrl0.sequencer.physMemPort system.sys_port_proxy.physMemPort - -[system.ruby] -type=RubySystem -children=network profiler -block_size_bytes=64 -clock=1 -mem_size=134217728 -no_mem_vec=false -random_seed=1234 -randomization=false -stats_filename=ruby.stats - -[system.ruby.network] -type=SimpleNetwork -children=topology -adaptive_routing=false -buffer_size=0 -control_msg_size=8 -endpoint_bandwidth=1000 -number_of_virtual_networks=10 -ruby_system=system.ruby -topology=system.ruby.network.topology - -[system.ruby.network.topology] -type=Topology -children=ext_links0 ext_links1 ext_links2 int_links0 int_links1 int_links2 routers0 routers1 routers2 routers3 -description=Crossbar -ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1 system.ruby.network.topology.ext_links2 -int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1 system.ruby.network.topology.int_links2 -print_config=false -routers=system.ruby.network.topology.routers0 system.ruby.network.topology.routers1 system.ruby.network.topology.routers2 system.ruby.network.topology.routers3 - -[system.ruby.network.topology.ext_links0] -type=SimpleExtLink -bandwidth_factor=16 -ext_node=system.l1_cntrl0 -int_node=system.ruby.network.topology.routers0 -latency=1 -link_id=0 -weight=1 - -[system.ruby.network.topology.ext_links1] -type=SimpleExtLink -bandwidth_factor=16 -ext_node=system.l2_cntrl0 -int_node=system.ruby.network.topology.routers1 -latency=1 -link_id=1 -weight=1 - -[system.ruby.network.topology.ext_links2] -type=SimpleExtLink -bandwidth_factor=16 -ext_node=system.dir_cntrl0 -int_node=system.ruby.network.topology.routers2 -latency=1 -link_id=2 -weight=1 - -[system.ruby.network.topology.int_links0] -type=SimpleIntLink -bandwidth_factor=16 -latency=1 -link_id=3 -node_a=system.ruby.network.topology.routers0 -node_b=system.ruby.network.topology.routers3 -weight=1 - -[system.ruby.network.topology.int_links1] -type=SimpleIntLink -bandwidth_factor=16 -latency=1 -link_id=4 -node_a=system.ruby.network.topology.routers1 -node_b=system.ruby.network.topology.routers3 -weight=1 - -[system.ruby.network.topology.int_links2] -type=SimpleIntLink -bandwidth_factor=16 -latency=1 -link_id=5 -node_a=system.ruby.network.topology.routers2 -node_b=system.ruby.network.topology.routers3 -weight=1 - -[system.ruby.network.topology.routers0] -type=BasicRouter -router_id=0 - -[system.ruby.network.topology.routers1] -type=BasicRouter -router_id=1 - -[system.ruby.network.topology.routers2] -type=BasicRouter -router_id=2 - -[system.ruby.network.topology.routers3] -type=BasicRouter -router_id=3 - -[system.ruby.profiler] -type=RubyProfiler -all_instructions=false -hot_lines=false -num_of_sequencers=1 -ruby_system=system.ruby - -[system.sys_port_proxy] -type=RubyPortProxy -access_phys_mem=true -physmem=system.physmem -ruby_system=system.ruby -using_network_tester=false -using_ruby_tester=false -version=0 -physMemPort=system.physmem.port[1] -port=system.system_port - diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/ruby.stats b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/ruby.stats deleted file mode 100644 index 2d266c770..000000000 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/ruby.stats +++ /dev/null @@ -1,1036 +0,0 @@ - -================ Begin RubySystem Configuration Print ================ - -RubySystem config: - random_seed: 1234 - randomization: 0 - cycle_period: 1 - block_size_bytes: 64 - block_size_bits: 6 - memory_size_bytes: 134217728 - memory_size_bits: 27 - -Network Configuration ---------------------- -network: SIMPLE_NETWORK -topology: - -virtual_net_0: active, ordered -virtual_net_1: active, unordered -virtual_net_2: active, unordered -virtual_net_3: active, ordered -virtual_net_4: active, unordered -virtual_net_5: active, ordered -virtual_net_6: inactive -virtual_net_7: inactive -virtual_net_8: inactive -virtual_net_9: inactive - - -Profiler Configuration ----------------------- -periodic_stats_period: 1000000 - -================ End RubySystem Configuration Print ================ - - -Real time: Jan/23/2012 04:22:26 - -Profiler Stats --------------- -Elapsed_time_in_seconds: 1 -Elapsed_time_in_minutes: 0.0166667 -Elapsed_time_in_hours: 0.000277778 -Elapsed_time_in_days: 1.15741e-05 - -Virtual_time_in_seconds: 0.22 -Virtual_time_in_minutes: 0.00366667 -Virtual_time_in_hours: 6.11111e-05 -Virtual_time_in_days: 2.5463e-06 - -Ruby_current_time: 87899 -Ruby_start_time: 0 -Ruby_cycles: 87899 - -mbytes_resident: 42.2227 -mbytes_total: 211.34 -resident_ratio: 0.199786 - -ruby_cycles_executed: [ 87900 ] - -Busy Controller Counts: -L1Cache-0:0 -L2Cache-0:0 -Directory-0:0 - - -Busy Bank Count:0 - -sequencer_requests_outstanding: [binsize: 1 max: 1 count: 3295 average: 1 | standard deviation: 0 | 0 3295 ] - -All Non-Zero Cycle Demand Cache Accesses ----------------------------------------- -miss_latency: [binsize: 2 max: 307 count: 3294 average: 25.6846 | standard deviation: 58.8214 | 0 2776 0 0 0 0 0 0 0 0 6 2 62 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 4 58 48 98 72 79 0 1 2 13 9 10 7 26 0 1 0 0 1 1 0 1 1 2 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 2 0 0 0 0 0 0 0 0 0 0 1 2 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_LD: [binsize: 2 max: 307 count: 415 average: 65.2795 | standard deviation: 81.9739 | 0 233 0 0 0 0 0 0 0 0 0 1 32 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 16 14 37 32 18 0 0 0 9 2 2 2 8 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_ST: [binsize: 2 max: 307 count: 294 average: 34.5782 | standard deviation: 69.4748 | 0 228 0 0 0 0 0 0 0 0 6 1 7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6 5 15 8 5 0 0 0 0 1 1 0 5 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_IFETCH: [binsize: 2 max: 277 count: 2585 average: 18.3164 | standard deviation: 49.7019 | 0 2315 0 0 0 0 0 0 0 0 0 0 23 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 2 36 29 46 32 56 0 1 2 4 6 7 5 13 0 0 0 0 0 1 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_L1Cache: [binsize: 1 max: 2 count: 2776 average: 2 | standard deviation: 0 | 0 0 2776 ] -miss_latency_L2Cache: [binsize: 1 max: 25 count: 70 average: 24.6 | standard deviation: 1.16096 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6 0 2 0 62 ] -miss_latency_Directory: [binsize: 2 max: 307 count: 448 average: 172.614 | standard deviation: 19.1957 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 4 58 48 98 72 79 0 1 2 13 9 10 7 26 0 1 0 0 1 1 0 1 1 2 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 2 0 0 0 0 0 0 0 0 0 0 1 2 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] -miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] -miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] -miss_latency_wCC_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] -imcomplete_wCC_Times: 0 -miss_latency_dir_issue_to_initial_request: [binsize: 1 max: 0 count: 1 average: 0 | standard deviation: 0 | 1 ] -miss_latency_dir_initial_forward_request: [binsize: 1 max: 0 count: 1 average: 0 | standard deviation: 0 | 1 ] -miss_latency_dir_forward_to_first_response: [binsize: 1 max: 0 count: 1 average: 0 | standard deviation: 0 | 1 ] -miss_latency_dir_first_response_to_completion: [binsize: 1 max: 169 count: 1 average: 169 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ] -imcomplete_dir_Times: 447 -miss_latency_LD_L1Cache: [binsize: 1 max: 2 count: 233 average: 2 | standard deviation: 0 | 0 0 233 ] -miss_latency_LD_L2Cache: [binsize: 1 max: 25 count: 33 average: 24.9394 | standard deviation: 0.353553 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 32 ] -miss_latency_LD_Directory: [binsize: 2 max: 307 count: 149 average: 173.168 | standard deviation: 20.2876 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 16 14 37 32 18 0 0 0 9 2 2 2 8 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_ST_L1Cache: [binsize: 1 max: 2 count: 228 average: 2 | standard deviation: 0 | 0 0 228 ] -miss_latency_ST_L2Cache: [binsize: 1 max: 25 count: 14 average: 23.1429 | standard deviation: 2 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6 0 1 0 7 ] -miss_latency_ST_Directory: [binsize: 2 max: 307 count: 52 average: 180.5 | standard deviation: 35.1816 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6 5 15 8 5 0 0 0 0 1 1 0 5 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_IFETCH_L1Cache: [binsize: 1 max: 2 count: 2315 average: 2 | standard deviation: 0 | 0 0 2315 ] -miss_latency_IFETCH_L2Cache: [binsize: 1 max: 25 count: 23 average: 25 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 23 ] -miss_latency_IFETCH_Directory: [binsize: 2 max: 277 count: 247 average: 170.619 | standard deviation: 12.1654 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 2 36 29 46 32 56 0 1 2 4 6 7 5 13 0 0 0 0 0 1 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] - -All Non-Zero Cycle SW Prefetch Requests ------------------------------------- -prefetch_latency: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] -prefetch_latency_L2Miss:[binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] -Request vs. RubySystem State Profile --------------------------------- - - -filter_action: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - -Message Delayed Cycles ----------------------- -Total_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] -Total_nonPF_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - virtual_network_0_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - virtual_network_1_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - virtual_network_2_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - virtual_network_3_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - virtual_network_4_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - virtual_network_5_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - virtual_network_6_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - virtual_network_7_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - virtual_network_8_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - virtual_network_9_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - -Resource Usage --------------- -page_size: 4096 -user_time: 0 -system_time: 0 -page_reclaims: 11088 -page_faults: 5 -swaps: 0 -block_inputs: 1064 -block_outputs: 104 - -Network Stats -------------- - -total_msg_count_Request_Control: 2916 23328 -total_msg_count_Response_Data: 1344 96768 -total_msg_count_ResponseL2hit_Data: 210 15120 -total_msg_count_Response_Control: 3 24 -total_msg_count_Writeback_Data: 1758 126576 -total_msg_count_Writeback_Control: 1095 8760 -total_msgs: 7326 total_bytes: 270576 - -switch_0_inlinks: 2 -switch_0_outlinks: 2 -links_utilized_percent_switch_0: 2.75856 - links_utilized_percent_switch_0_link_0: 2.65248 bw: 16000 base_latency: 1 - links_utilized_percent_switch_0_link_1: 2.86465 bw: 16000 base_latency: 1 - - outgoing_messages_switch_0_link_0_Response_Data: 448 32256 [ 0 0 0 0 448 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_0_ResponseL2hit_Data: 70 5040 [ 0 0 0 0 70 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_0_Response_Control: 1 8 [ 0 0 0 0 1 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Request_Control: 518 4144 [ 0 518 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Writeback_Data: 502 36144 [ 0 0 0 0 502 0 0 0 0 0 ] base_latency: 1 - -switch_1_inlinks: 2 -switch_1_outlinks: 2 -links_utilized_percent_switch_1: 2.05975 - links_utilized_percent_switch_1_link_0: 2.86465 bw: 16000 base_latency: 1 - links_utilized_percent_switch_1_link_1: 1.25485 bw: 16000 base_latency: 1 - - outgoing_messages_switch_1_link_0_Request_Control: 518 4144 [ 0 518 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_0_Writeback_Data: 502 36144 [ 0 0 0 0 502 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_Request_Control: 454 3632 [ 0 0 454 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_ResponseL2hit_Data: 70 5040 [ 0 0 0 0 70 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_Response_Control: 1 8 [ 0 0 0 0 1 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_Writeback_Data: 84 6048 [ 0 0 0 0 84 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_Writeback_Control: 365 2920 [ 0 0 0 0 365 0 0 0 0 0 ] base_latency: 1 - -switch_2_inlinks: 2 -switch_2_outlinks: 2 -links_utilized_percent_switch_2: 1.59473 - links_utilized_percent_switch_2_link_0: 0.895915 bw: 16000 base_latency: 1 - links_utilized_percent_switch_2_link_1: 2.29354 bw: 16000 base_latency: 1 - - outgoing_messages_switch_2_link_0_Request_Control: 454 3632 [ 0 0 454 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_0_Writeback_Data: 84 6048 [ 0 0 0 0 84 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_0_Writeback_Control: 365 2920 [ 0 0 0 0 365 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_1_Response_Data: 448 32256 [ 0 0 0 0 448 0 0 0 0 0 ] base_latency: 1 - -switch_3_inlinks: 3 -switch_3_outlinks: 3 -links_utilized_percent_switch_3: 2.13768 - links_utilized_percent_switch_3_link_0: 2.65248 bw: 16000 base_latency: 1 - links_utilized_percent_switch_3_link_1: 2.86465 bw: 16000 base_latency: 1 - links_utilized_percent_switch_3_link_2: 0.895915 bw: 16000 base_latency: 1 - - outgoing_messages_switch_3_link_0_Response_Data: 448 32256 [ 0 0 0 0 448 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_0_ResponseL2hit_Data: 70 5040 [ 0 0 0 0 70 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_0_Response_Control: 1 8 [ 0 0 0 0 1 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_1_Request_Control: 518 4144 [ 0 518 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_1_Writeback_Data: 502 36144 [ 0 0 0 0 502 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_2_Request_Control: 454 3632 [ 0 0 454 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_2_Writeback_Data: 84 6048 [ 0 0 0 0 84 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_2_Writeback_Control: 365 2920 [ 0 0 0 0 365 0 0 0 0 0 ] base_latency: 1 - -Cache Stats: system.l1_cntrl0.L1IcacheMemory - system.l1_cntrl0.L1IcacheMemory_total_misses: 270 - system.l1_cntrl0.L1IcacheMemory_total_demand_misses: 270 - system.l1_cntrl0.L1IcacheMemory_total_prefetches: 0 - system.l1_cntrl0.L1IcacheMemory_total_sw_prefetches: 0 - system.l1_cntrl0.L1IcacheMemory_total_hw_prefetches: 0 - - system.l1_cntrl0.L1IcacheMemory_request_type_IFETCH: 100% - - system.l1_cntrl0.L1IcacheMemory_access_mode_type_Supervisor: 270 100% - -Cache Stats: system.l1_cntrl0.L1DcacheMemory - system.l1_cntrl0.L1DcacheMemory_total_misses: 248 - system.l1_cntrl0.L1DcacheMemory_total_demand_misses: 248 - system.l1_cntrl0.L1DcacheMemory_total_prefetches: 0 - system.l1_cntrl0.L1DcacheMemory_total_sw_prefetches: 0 - system.l1_cntrl0.L1DcacheMemory_total_hw_prefetches: 0 - - system.l1_cntrl0.L1DcacheMemory_request_type_LD: 73.3871% - system.l1_cntrl0.L1DcacheMemory_request_type_ST: 26.6129% - - system.l1_cntrl0.L1DcacheMemory_access_mode_type_Supervisor: 248 100% - - --- L1Cache --- - - Event Counts - -Load [415 ] 415 -Ifetch [2585 ] 2585 -Store [294 ] 294 -Atomic [0 ] 0 -L1_Replacement [504 ] 504 -Data_Shared [56 ] 56 -Data_Owner [0 ] 0 -Data_All_Tokens [462 ] 462 -Ack [1 ] 1 -Ack_All_Tokens [0 ] 0 -Transient_GETX [0 ] 0 -Transient_Local_GETX [0 ] 0 -Transient_GETS [0 ] 0 -Transient_Local_GETS [0 ] 0 -Transient_GETS_Last_Token [0 ] 0 -Transient_Local_GETS_Last_Token [0 ] 0 -Persistent_GETX [0 ] 0 -Persistent_GETS [0 ] 0 -Persistent_GETS_Last_Token [0 ] 0 -Own_Lock_or_Unlock [0 ] 0 -Request_Timeout [0 ] 0 -Use_TimeoutStarverX [0 ] 0 -Use_TimeoutStarverS [0 ] 0 -Use_TimeoutNoStarvers [461 ] 461 -Use_TimeoutNoStarvers_NoMig [0 ] 0 - - - Transitions - -NP Load [182 ] 182 -NP Ifetch [270 ] 270 -NP Store [58 ] 58 -NP Atomic [0 ] 0 -NP Data_Shared [0 ] 0 -NP Data_Owner [0 ] 0 -NP Data_All_Tokens [0 ] 0 -NP Ack [0 ] 0 -NP Transient_GETX [0 ] 0 -NP Transient_Local_GETX [0 ] 0 -NP Transient_GETS [0 ] 0 -NP Transient_Local_GETS [0 ] 0 -NP Persistent_GETX [0 ] 0 -NP Persistent_GETS [0 ] 0 -NP Persistent_GETS_Last_Token [0 ] 0 -NP Own_Lock_or_Unlock [0 ] 0 - -I Load [0 ] 0 -I Ifetch [0 ] 0 -I Store [0 ] 0 -I Atomic [0 ] 0 -I L1_Replacement [0 ] 0 -I Data_Shared [0 ] 0 -I Data_Owner [0 ] 0 -I Data_All_Tokens [0 ] 0 -I Ack [0 ] 0 -I Transient_GETX [0 ] 0 -I Transient_Local_GETX [0 ] 0 -I Transient_GETS [0 ] 0 -I Transient_Local_GETS [0 ] 0 -I Transient_GETS_Last_Token [0 ] 0 -I Transient_Local_GETS_Last_Token [0 ] 0 -I Persistent_GETX [0 ] 0 -I Persistent_GETS [0 ] 0 -I Persistent_GETS_Last_Token [0 ] 0 -I Own_Lock_or_Unlock [0 ] 0 - -S Load [29 ] 29 -S Ifetch [158 ] 158 -S Store [8 ] 8 -S Atomic [0 ] 0 -S L1_Replacement [48 ] 48 -S Data_Shared [0 ] 0 -S Data_Owner [0 ] 0 -S Data_All_Tokens [0 ] 0 -S Ack [0 ] 0 -S Transient_GETX [0 ] 0 -S Transient_Local_GETX [0 ] 0 -S Transient_GETS [0 ] 0 -S Transient_Local_GETS [0 ] 0 -S Transient_GETS_Last_Token [0 ] 0 -S Transient_Local_GETS_Last_Token [0 ] 0 -S Persistent_GETX [0 ] 0 -S Persistent_GETS [0 ] 0 -S Persistent_GETS_Last_Token [0 ] 0 -S Own_Lock_or_Unlock [0 ] 0 - -O Load [0 ] 0 -O Ifetch [0 ] 0 -O Store [0 ] 0 -O Atomic [0 ] 0 -O L1_Replacement [0 ] 0 -O Data_Shared [0 ] 0 -O Data_All_Tokens [0 ] 0 -O Ack [0 ] 0 -O Ack_All_Tokens [0 ] 0 -O Transient_GETX [0 ] 0 -O Transient_Local_GETX [0 ] 0 -O Transient_GETS [0 ] 0 -O Transient_Local_GETS [0 ] 0 -O Transient_GETS_Last_Token [0 ] 0 -O Transient_Local_GETS_Last_Token [0 ] 0 -O Persistent_GETX [0 ] 0 -O Persistent_GETS [0 ] 0 -O Persistent_GETS_Last_Token [0 ] 0 -O Own_Lock_or_Unlock [0 ] 0 - -M Load [66 ] 66 -M Ifetch [1161 ] 1161 -M Store [29 ] 29 -M Atomic [0 ] 0 -M L1_Replacement [358 ] 358 -M Transient_GETX [0 ] 0 -M Transient_Local_GETX [0 ] 0 -M Transient_GETS [0 ] 0 -M Transient_Local_GETS [0 ] 0 -M Persistent_GETX [0 ] 0 -M Persistent_GETS [0 ] 0 -M Own_Lock_or_Unlock [0 ] 0 - -MM Load [96 ] 96 -MM Ifetch [0 ] 0 -MM Store [104 ] 104 -MM Atomic [0 ] 0 -MM L1_Replacement [96 ] 96 -MM Transient_GETX [0 ] 0 -MM Transient_Local_GETX [0 ] 0 -MM Transient_GETS [0 ] 0 -MM Transient_Local_GETS [0 ] 0 -MM Persistent_GETX [0 ] 0 -MM Persistent_GETS [0 ] 0 -MM Own_Lock_or_Unlock [0 ] 0 - -M_W Load [36 ] 36 -M_W Ifetch [996 ] 996 -M_W Store [3 ] 3 -M_W Atomic [0 ] 0 -M_W L1_Replacement [1 ] 1 -M_W Transient_GETX [0 ] 0 -M_W Transient_Local_GETX [0 ] 0 -M_W Transient_GETS [0 ] 0 -M_W Transient_Local_GETS [0 ] 0 -M_W Persistent_GETX [0 ] 0 -M_W Persistent_GETS [0 ] 0 -M_W Own_Lock_or_Unlock [0 ] 0 -M_W Use_TimeoutStarverX [0 ] 0 -M_W Use_TimeoutStarverS [0 ] 0 -M_W Use_TimeoutNoStarvers [392 ] 392 -M_W Use_TimeoutNoStarvers_NoMig [0 ] 0 - -MM_W Load [6 ] 6 -MM_W Ifetch [0 ] 0 -MM_W Store [92 ] 92 -MM_W Atomic [0 ] 0 -MM_W L1_Replacement [1 ] 1 -MM_W Transient_GETX [0 ] 0 -MM_W Transient_Local_GETX [0 ] 0 -MM_W Transient_GETS [0 ] 0 -MM_W Transient_Local_GETS [0 ] 0 -MM_W Persistent_GETX [0 ] 0 -MM_W Persistent_GETS [0 ] 0 -MM_W Own_Lock_or_Unlock [0 ] 0 -MM_W Use_TimeoutStarverX [0 ] 0 -MM_W Use_TimeoutStarverS [0 ] 0 -MM_W Use_TimeoutNoStarvers [69 ] 69 -MM_W Use_TimeoutNoStarvers_NoMig [0 ] 0 - -IM Load [0 ] 0 -IM Ifetch [0 ] 0 -IM Store [0 ] 0 -IM Atomic [0 ] 0 -IM L1_Replacement [0 ] 0 -IM Data_Shared [0 ] 0 -IM Data_Owner [0 ] 0 -IM Data_All_Tokens [58 ] 58 -IM Ack [1 ] 1 -IM Transient_GETX [0 ] 0 -IM Transient_Local_GETX [0 ] 0 -IM Transient_GETS [0 ] 0 -IM Transient_Local_GETS [0 ] 0 -IM Transient_GETS_Last_Token [0 ] 0 -IM Transient_Local_GETS_Last_Token [0 ] 0 -IM Persistent_GETX [0 ] 0 -IM Persistent_GETS [0 ] 0 -IM Persistent_GETS_Last_Token [0 ] 0 -IM Own_Lock_or_Unlock [0 ] 0 -IM Request_Timeout [0 ] 0 - -SM Load [0 ] 0 -SM Ifetch [0 ] 0 -SM Store [0 ] 0 -SM Atomic [0 ] 0 -SM L1_Replacement [0 ] 0 -SM Data_Shared [0 ] 0 -SM Data_Owner [0 ] 0 -SM Data_All_Tokens [8 ] 8 -SM Ack [0 ] 0 -SM Transient_GETX [0 ] 0 -SM Transient_Local_GETX [0 ] 0 -SM Transient_GETS [0 ] 0 -SM Transient_Local_GETS [0 ] 0 -SM Transient_GETS_Last_Token [0 ] 0 -SM Transient_Local_GETS_Last_Token [0 ] 0 -SM Persistent_GETX [0 ] 0 -SM Persistent_GETS [0 ] 0 -SM Persistent_GETS_Last_Token [0 ] 0 -SM Own_Lock_or_Unlock [0 ] 0 -SM Request_Timeout [0 ] 0 - -OM Load [0 ] 0 -OM Ifetch [0 ] 0 -OM Store [0 ] 0 -OM Atomic [0 ] 0 -OM L1_Replacement [0 ] 0 -OM Data_Shared [0 ] 0 -OM Data_All_Tokens [0 ] 0 -OM Ack [0 ] 0 -OM Ack_All_Tokens [0 ] 0 -OM Transient_GETX [0 ] 0 -OM Transient_Local_GETX [0 ] 0 -OM Transient_GETS [0 ] 0 -OM Transient_Local_GETS [0 ] 0 -OM Transient_GETS_Last_Token [0 ] 0 -OM Transient_Local_GETS_Last_Token [0 ] 0 -OM Persistent_GETX [0 ] 0 -OM Persistent_GETS [0 ] 0 -OM Persistent_GETS_Last_Token [0 ] 0 -OM Own_Lock_or_Unlock [0 ] 0 -OM Request_Timeout [0 ] 0 - -IS Load [0 ] 0 -IS Ifetch [0 ] 0 -IS Store [0 ] 0 -IS Atomic [0 ] 0 -IS L1_Replacement [0 ] 0 -IS Data_Shared [56 ] 56 -IS Data_Owner [0 ] 0 -IS Data_All_Tokens [396 ] 396 -IS Ack [0 ] 0 -IS Transient_GETX [0 ] 0 -IS Transient_Local_GETX [0 ] 0 -IS Transient_GETS [0 ] 0 -IS Transient_Local_GETS [0 ] 0 -IS Transient_GETS_Last_Token [0 ] 0 -IS Transient_Local_GETS_Last_Token [0 ] 0 -IS Persistent_GETX [0 ] 0 -IS Persistent_GETS [0 ] 0 -IS Persistent_GETS_Last_Token [0 ] 0 -IS Own_Lock_or_Unlock [0 ] 0 -IS Request_Timeout [0 ] 0 - -I_L Load [0 ] 0 -I_L Ifetch [0 ] 0 -I_L Store [0 ] 0 -I_L Atomic [0 ] 0 -I_L L1_Replacement [0 ] 0 -I_L Data_Shared [0 ] 0 -I_L Data_Owner [0 ] 0 -I_L Data_All_Tokens [0 ] 0 -I_L Ack [0 ] 0 -I_L Transient_GETX [0 ] 0 -I_L Transient_Local_GETX [0 ] 0 -I_L Transient_GETS [0 ] 0 -I_L Transient_Local_GETS [0 ] 0 -I_L Transient_GETS_Last_Token [0 ] 0 -I_L Transient_Local_GETS_Last_Token [0 ] 0 -I_L Persistent_GETX [0 ] 0 -I_L Persistent_GETS [0 ] 0 -I_L Persistent_GETS_Last_Token [0 ] 0 -I_L Own_Lock_or_Unlock [0 ] 0 - -S_L Load [0 ] 0 -S_L Ifetch [0 ] 0 -S_L Store [0 ] 0 -S_L Atomic [0 ] 0 -S_L L1_Replacement [0 ] 0 -S_L Data_Shared [0 ] 0 -S_L Data_Owner [0 ] 0 -S_L Data_All_Tokens [0 ] 0 -S_L Ack [0 ] 0 -S_L Transient_GETX [0 ] 0 -S_L Transient_Local_GETX [0 ] 0 -S_L Transient_GETS [0 ] 0 -S_L Transient_Local_GETS [0 ] 0 -S_L Transient_GETS_Last_Token [0 ] 0 -S_L Transient_Local_GETS_Last_Token [0 ] 0 -S_L Persistent_GETX [0 ] 0 -S_L Persistent_GETS [0 ] 0 -S_L Persistent_GETS_Last_Token [0 ] 0 -S_L Own_Lock_or_Unlock [0 ] 0 - -IM_L Load [0 ] 0 -IM_L Ifetch [0 ] 0 -IM_L Store [0 ] 0 -IM_L Atomic [0 ] 0 -IM_L L1_Replacement [0 ] 0 -IM_L Data_Shared [0 ] 0 -IM_L Data_Owner [0 ] 0 -IM_L Data_All_Tokens [0 ] 0 -IM_L Ack [0 ] 0 -IM_L Transient_GETX [0 ] 0 -IM_L Transient_Local_GETX [0 ] 0 -IM_L Transient_GETS [0 ] 0 -IM_L Transient_Local_GETS [0 ] 0 -IM_L Transient_GETS_Last_Token [0 ] 0 -IM_L Transient_Local_GETS_Last_Token [0 ] 0 -IM_L Persistent_GETX [0 ] 0 -IM_L Persistent_GETS [0 ] 0 -IM_L Own_Lock_or_Unlock [0 ] 0 -IM_L Request_Timeout [0 ] 0 - -SM_L Load [0 ] 0 -SM_L Ifetch [0 ] 0 -SM_L Store [0 ] 0 -SM_L Atomic [0 ] 0 -SM_L L1_Replacement [0 ] 0 -SM_L Data_Shared [0 ] 0 -SM_L Data_Owner [0 ] 0 -SM_L Data_All_Tokens [0 ] 0 -SM_L Ack [0 ] 0 -SM_L Transient_GETX [0 ] 0 -SM_L Transient_Local_GETX [0 ] 0 -SM_L Transient_GETS [0 ] 0 -SM_L Transient_Local_GETS [0 ] 0 -SM_L Transient_GETS_Last_Token [0 ] 0 -SM_L Transient_Local_GETS_Last_Token [0 ] 0 -SM_L Persistent_GETX [0 ] 0 -SM_L Persistent_GETS [0 ] 0 -SM_L Persistent_GETS_Last_Token [0 ] 0 -SM_L Own_Lock_or_Unlock [0 ] 0 -SM_L Request_Timeout [0 ] 0 - -IS_L Load [0 ] 0 -IS_L Ifetch [0 ] 0 -IS_L Store [0 ] 0 -IS_L Atomic [0 ] 0 -IS_L L1_Replacement [0 ] 0 -IS_L Data_Shared [0 ] 0 -IS_L Data_Owner [0 ] 0 -IS_L Data_All_Tokens [0 ] 0 -IS_L Ack [0 ] 0 -IS_L Transient_GETX [0 ] 0 -IS_L Transient_Local_GETX [0 ] 0 -IS_L Transient_GETS [0 ] 0 -IS_L Transient_Local_GETS [0 ] 0 -IS_L Transient_GETS_Last_Token [0 ] 0 -IS_L Transient_Local_GETS_Last_Token [0 ] 0 -IS_L Persistent_GETX [0 ] 0 -IS_L Persistent_GETS [0 ] 0 -IS_L Own_Lock_or_Unlock [0 ] 0 -IS_L Request_Timeout [0 ] 0 - -Cache Stats: system.l2_cntrl0.L2cacheMemory - system.l2_cntrl0.L2cacheMemory_total_misses: 454 - system.l2_cntrl0.L2cacheMemory_total_demand_misses: 454 - system.l2_cntrl0.L2cacheMemory_total_prefetches: 0 - system.l2_cntrl0.L2cacheMemory_total_sw_prefetches: 0 - system.l2_cntrl0.L2cacheMemory_total_hw_prefetches: 0 - - system.l2_cntrl0.L2cacheMemory_request_type_GETS: 87.2247% - system.l2_cntrl0.L2cacheMemory_request_type_GETX: 12.7753% - - system.l2_cntrl0.L2cacheMemory_access_mode_type_Supervisor: 454 100% - - --- L2Cache --- - - Event Counts - -L1_GETS [448 ] 448 -L1_GETS_Last_Token [4 ] 4 -L1_GETX [66 ] 66 -L1_INV [0 ] 0 -Transient_GETX [0 ] 0 -Transient_GETS [0 ] 0 -Transient_GETS_Last_Token [0 ] 0 -L2_Replacement [458 ] 458 -Writeback_Tokens [0 ] 0 -Writeback_Shared_Data [21 ] 21 -Writeback_All_Tokens [481 ] 481 -Writeback_Owned [0 ] 0 -Data_Shared [0 ] 0 -Data_Owner [0 ] 0 -Data_All_Tokens [0 ] 0 -Ack [0 ] 0 -Ack_All_Tokens [0 ] 0 -Persistent_GETX [0 ] 0 -Persistent_GETS [0 ] 0 -Persistent_GETS_Last_Token [0 ] 0 -Own_Lock_or_Unlock [0 ] 0 - - - Transitions - -NP L1_GETS [396 ] 396 -NP L1_GETX [50 ] 50 -NP L1_INV [0 ] 0 -NP Transient_GETX [0 ] 0 -NP Transient_GETS [0 ] 0 -NP Writeback_Tokens [0 ] 0 -NP Writeback_Shared_Data [18 ] 18 -NP Writeback_All_Tokens [448 ] 448 -NP Writeback_Owned [0 ] 0 -NP Data_Shared [0 ] 0 -NP Data_Owner [0 ] 0 -NP Data_All_Tokens [0 ] 0 -NP Ack [0 ] 0 -NP Persistent_GETX [0 ] 0 -NP Persistent_GETS [0 ] 0 -NP Persistent_GETS_Last_Token [0 ] 0 -NP Own_Lock_or_Unlock [0 ] 0 - -I L1_GETS [0 ] 0 -I L1_GETS_Last_Token [0 ] 0 -I L1_GETX [1 ] 1 -I L1_INV [0 ] 0 -I Transient_GETX [0 ] 0 -I Transient_GETS [0 ] 0 -I Transient_GETS_Last_Token [0 ] 0 -I L2_Replacement [9 ] 9 -I Writeback_Tokens [0 ] 0 -I Writeback_Shared_Data [3 ] 3 -I Writeback_All_Tokens [6 ] 6 -I Writeback_Owned [0 ] 0 -I Data_Shared [0 ] 0 -I Data_Owner [0 ] 0 -I Data_All_Tokens [0 ] 0 -I Ack [0 ] 0 -I Persistent_GETX [0 ] 0 -I Persistent_GETS [0 ] 0 -I Persistent_GETS_Last_Token [0 ] 0 -I Own_Lock_or_Unlock [0 ] 0 - -S L1_GETS [0 ] 0 -S L1_GETS_Last_Token [4 ] 4 -S L1_GETX [1 ] 1 -S L1_INV [0 ] 0 -S Transient_GETX [0 ] 0 -S Transient_GETS [0 ] 0 -S Transient_GETS_Last_Token [0 ] 0 -S L2_Replacement [15 ] 15 -S Writeback_Tokens [0 ] 0 -S Writeback_Shared_Data [0 ] 0 -S Writeback_All_Tokens [0 ] 0 -S Writeback_Owned [0 ] 0 -S Data_Shared [0 ] 0 -S Data_Owner [0 ] 0 -S Data_All_Tokens [0 ] 0 -S Ack [0 ] 0 -S Persistent_GETX [0 ] 0 -S Persistent_GETS [0 ] 0 -S Persistent_GETS_Last_Token [0 ] 0 -S Own_Lock_or_Unlock [0 ] 0 - -O L1_GETS [0 ] 0 -O L1_GETS_Last_Token [0 ] 0 -O L1_GETX [6 ] 6 -O L1_INV [0 ] 0 -O Transient_GETX [0 ] 0 -O Transient_GETS [0 ] 0 -O Transient_GETS_Last_Token [0 ] 0 -O L2_Replacement [19 ] 19 -O Writeback_Tokens [0 ] 0 -O Writeback_Shared_Data [0 ] 0 -O Writeback_All_Tokens [27 ] 27 -O Data_Shared [0 ] 0 -O Data_All_Tokens [0 ] 0 -O Ack [0 ] 0 -O Ack_All_Tokens [0 ] 0 -O Persistent_GETX [0 ] 0 -O Persistent_GETS [0 ] 0 -O Persistent_GETS_Last_Token [0 ] 0 -O Own_Lock_or_Unlock [0 ] 0 - -M L1_GETS [52 ] 52 -M L1_GETX [8 ] 8 -M L1_INV [0 ] 0 -M Transient_GETX [0 ] 0 -M Transient_GETS [0 ] 0 -M L2_Replacement [415 ] 415 -M Persistent_GETX [0 ] 0 -M Persistent_GETS [0 ] 0 -M Own_Lock_or_Unlock [0 ] 0 - -I_L L1_GETS [0 ] 0 -I_L L1_GETX [0 ] 0 -I_L L1_INV [0 ] 0 -I_L Transient_GETX [0 ] 0 -I_L Transient_GETS [0 ] 0 -I_L Transient_GETS_Last_Token [0 ] 0 -I_L L2_Replacement [0 ] 0 -I_L Writeback_Tokens [0 ] 0 -I_L Writeback_Shared_Data [0 ] 0 -I_L Writeback_All_Tokens [0 ] 0 -I_L Writeback_Owned [0 ] 0 -I_L Data_Shared [0 ] 0 -I_L Data_Owner [0 ] 0 -I_L Data_All_Tokens [0 ] 0 -I_L Ack [0 ] 0 -I_L Persistent_GETX [0 ] 0 -I_L Persistent_GETS [0 ] 0 -I_L Own_Lock_or_Unlock [0 ] 0 - -S_L L1_GETS [0 ] 0 -S_L L1_GETS_Last_Token [0 ] 0 -S_L L1_GETX [0 ] 0 -S_L L1_INV [0 ] 0 -S_L Transient_GETX [0 ] 0 -S_L Transient_GETS [0 ] 0 -S_L Transient_GETS_Last_Token [0 ] 0 -S_L L2_Replacement [0 ] 0 -S_L Writeback_Tokens [0 ] 0 -S_L Writeback_Shared_Data [0 ] 0 -S_L Writeback_All_Tokens [0 ] 0 -S_L Writeback_Owned [0 ] 0 -S_L Data_Shared [0 ] 0 -S_L Data_Owner [0 ] 0 -S_L Data_All_Tokens [0 ] 0 -S_L Ack [0 ] 0 -S_L Persistent_GETX [0 ] 0 -S_L Persistent_GETS [0 ] 0 -S_L Persistent_GETS_Last_Token [0 ] 0 -S_L Own_Lock_or_Unlock [0 ] 0 - -Memory controller: system.dir_cntrl0.memBuffer: - memory_total_requests: 532 - memory_reads: 448 - memory_writes: 84 - memory_refreshes: 184 - memory_total_request_delays: 169 - memory_delays_per_request: 0.317669 - memory_delays_in_input_queue: 45 - memory_delays_behind_head_of_bank_queue: 0 - memory_delays_stalled_at_head_of_bank_queue: 124 - memory_stalls_for_bank_busy: 31 - memory_stalls_for_random_busy: 0 - memory_stalls_for_anti_starvation: 0 - memory_stalls_for_arbitration: 10 - memory_stalls_for_bus: 81 - memory_stalls_for_tfaw: 0 - memory_stalls_for_read_write_turnaround: 2 - memory_stalls_for_read_read_turnaround: 0 - accesses_per_bank: 19 10 0 39 20 19 31 22 5 3 6 4 22 41 22 3 4 6 7 13 10 18 14 42 16 5 5 12 13 18 14 69 - - --- Directory --- - - Event Counts - -GETX [107 ] 107 -GETS [441 ] 441 -Lockdown [0 ] 0 -Unlockdown [0 ] 0 -Own_Lock_or_Unlock [0 ] 0 -Own_Lock_or_Unlock_Tokens [0 ] 0 -Data_Owner [3 ] 3 -Data_All_Tokens [81 ] 81 -Ack_Owner [16 ] 16 -Ack_Owner_All_Tokens [334 ] 334 -Tokens [0 ] 0 -Ack_All_Tokens [15 ] 15 -Request_Timeout [0 ] 0 -Memory_Data [448 ] 448 -Memory_Ack [84 ] 84 -DMA_READ [0 ] 0 -DMA_WRITE [0 ] 0 -DMA_WRITE_All_Tokens [0 ] 0 - - - Transitions - -O GETX [52 ] 52 -O GETS [396 ] 396 -O Lockdown [0 ] 0 -O Unlockdown [0 ] 0 -O Own_Lock_or_Unlock [0 ] 0 -O Own_Lock_or_Unlock_Tokens [0 ] 0 -O Data_Owner [0 ] 0 -O Data_All_Tokens [0 ] 0 -O Tokens [0 ] 0 -O Ack_All_Tokens [15 ] 15 -O DMA_READ [0 ] 0 -O DMA_WRITE [0 ] 0 -O DMA_WRITE_All_Tokens [0 ] 0 - -NO GETX [6 ] 6 -NO GETS [0 ] 0 -NO Lockdown [0 ] 0 -NO Unlockdown [0 ] 0 -NO Own_Lock_or_Unlock [0 ] 0 -NO Own_Lock_or_Unlock_Tokens [0 ] 0 -NO Data_Owner [3 ] 3 -NO Data_All_Tokens [81 ] 81 -NO Ack_Owner [16 ] 16 -NO Ack_Owner_All_Tokens [334 ] 334 -NO Tokens [0 ] 0 -NO DMA_READ [0 ] 0 -NO DMA_WRITE [0 ] 0 - -L GETX [0 ] 0 -L GETS [0 ] 0 -L Lockdown [0 ] 0 -L Unlockdown [0 ] 0 -L Own_Lock_or_Unlock [0 ] 0 -L Own_Lock_or_Unlock_Tokens [0 ] 0 -L Data_Owner [0 ] 0 -L Data_All_Tokens [0 ] 0 -L Ack_Owner [0 ] 0 -L Ack_Owner_All_Tokens [0 ] 0 -L Tokens [0 ] 0 -L DMA_READ [0 ] 0 -L DMA_WRITE [0 ] 0 -L DMA_WRITE_All_Tokens [0 ] 0 - -O_W GETX [49 ] 49 -O_W GETS [45 ] 45 -O_W Lockdown [0 ] 0 -O_W Unlockdown [0 ] 0 -O_W Own_Lock_or_Unlock [0 ] 0 -O_W Own_Lock_or_Unlock_Tokens [0 ] 0 -O_W Data_Owner [0 ] 0 -O_W Data_All_Tokens [0 ] 0 -O_W Ack_Owner [0 ] 0 -O_W Tokens [0 ] 0 -O_W Ack_All_Tokens [0 ] 0 -O_W Memory_Data [0 ] 0 -O_W Memory_Ack [84 ] 84 -O_W DMA_READ [0 ] 0 -O_W DMA_WRITE [0 ] 0 -O_W DMA_WRITE_All_Tokens [0 ] 0 - -L_O_W GETX [0 ] 0 -L_O_W GETS [0 ] 0 -L_O_W Lockdown [0 ] 0 -L_O_W Unlockdown [0 ] 0 -L_O_W Own_Lock_or_Unlock [0 ] 0 -L_O_W Own_Lock_or_Unlock_Tokens [0 ] 0 -L_O_W Data_Owner [0 ] 0 -L_O_W Data_All_Tokens [0 ] 0 -L_O_W Ack_Owner [0 ] 0 -L_O_W Tokens [0 ] 0 -L_O_W Ack_All_Tokens [0 ] 0 -L_O_W Memory_Data [0 ] 0 -L_O_W Memory_Ack [0 ] 0 -L_O_W DMA_READ [0 ] 0 -L_O_W DMA_WRITE [0 ] 0 -L_O_W DMA_WRITE_All_Tokens [0 ] 0 - -L_NO_W GETX [0 ] 0 -L_NO_W GETS [0 ] 0 -L_NO_W Lockdown [0 ] 0 -L_NO_W Unlockdown [0 ] 0 -L_NO_W Own_Lock_or_Unlock [0 ] 0 -L_NO_W Own_Lock_or_Unlock_Tokens [0 ] 0 -L_NO_W Data_Owner [0 ] 0 -L_NO_W Data_All_Tokens [0 ] 0 -L_NO_W Ack_Owner [0 ] 0 -L_NO_W Tokens [0 ] 0 -L_NO_W Ack_All_Tokens [0 ] 0 -L_NO_W Memory_Data [0 ] 0 -L_NO_W DMA_READ [0 ] 0 -L_NO_W DMA_WRITE [0 ] 0 -L_NO_W DMA_WRITE_All_Tokens [0 ] 0 - -DR_L_W GETX [0 ] 0 -DR_L_W GETS [0 ] 0 -DR_L_W Lockdown [0 ] 0 -DR_L_W Unlockdown [0 ] 0 -DR_L_W Own_Lock_or_Unlock [0 ] 0 -DR_L_W Own_Lock_or_Unlock_Tokens [0 ] 0 -DR_L_W Data_Owner [0 ] 0 -DR_L_W Data_All_Tokens [0 ] 0 -DR_L_W Ack_Owner [0 ] 0 -DR_L_W Tokens [0 ] 0 -DR_L_W Ack_All_Tokens [0 ] 0 -DR_L_W Request_Timeout [0 ] 0 -DR_L_W Memory_Data [0 ] 0 -DR_L_W DMA_READ [0 ] 0 -DR_L_W DMA_WRITE [0 ] 0 -DR_L_W DMA_WRITE_All_Tokens [0 ] 0 - -DW_L_W GETX [0 ] 0 -DW_L_W GETS [0 ] 0 -DW_L_W Lockdown [0 ] 0 -DW_L_W Unlockdown [0 ] 0 -DW_L_W Own_Lock_or_Unlock [0 ] 0 -DW_L_W Own_Lock_or_Unlock_Tokens [0 ] 0 -DW_L_W Data_Owner [0 ] 0 -DW_L_W Data_All_Tokens [0 ] 0 -DW_L_W Ack_Owner [0 ] 0 -DW_L_W Tokens [0 ] 0 -DW_L_W Ack_All_Tokens [0 ] 0 -DW_L_W Request_Timeout [0 ] 0 -DW_L_W Memory_Ack [0 ] 0 -DW_L_W DMA_READ [0 ] 0 -DW_L_W DMA_WRITE [0 ] 0 -DW_L_W DMA_WRITE_All_Tokens [0 ] 0 - -NO_W GETX [0 ] 0 -NO_W GETS [0 ] 0 -NO_W Lockdown [0 ] 0 -NO_W Unlockdown [0 ] 0 -NO_W Own_Lock_or_Unlock [0 ] 0 -NO_W Own_Lock_or_Unlock_Tokens [0 ] 0 -NO_W Data_Owner [0 ] 0 -NO_W Data_All_Tokens [0 ] 0 -NO_W Ack_Owner [0 ] 0 -NO_W Tokens [0 ] 0 -NO_W Ack_All_Tokens [0 ] 0 -NO_W Memory_Data [448 ] 448 -NO_W DMA_READ [0 ] 0 -NO_W DMA_WRITE [0 ] 0 -NO_W DMA_WRITE_All_Tokens [0 ] 0 - -O_DW_W GETX [0 ] 0 -O_DW_W GETS [0 ] 0 -O_DW_W Lockdown [0 ] 0 -O_DW_W Unlockdown [0 ] 0 -O_DW_W Own_Lock_or_Unlock [0 ] 0 -O_DW_W Own_Lock_or_Unlock_Tokens [0 ] 0 -O_DW_W Data_Owner [0 ] 0 -O_DW_W Data_All_Tokens [0 ] 0 -O_DW_W Ack_Owner [0 ] 0 -O_DW_W Tokens [0 ] 0 -O_DW_W Ack_All_Tokens [0 ] 0 -O_DW_W Request_Timeout [0 ] 0 -O_DW_W Memory_Ack [0 ] 0 -O_DW_W DMA_READ [0 ] 0 -O_DW_W DMA_WRITE [0 ] 0 -O_DW_W DMA_WRITE_All_Tokens [0 ] 0 - -O_DR_W GETX [0 ] 0 -O_DR_W GETS [0 ] 0 -O_DR_W Lockdown [0 ] 0 -O_DR_W Unlockdown [0 ] 0 -O_DR_W Own_Lock_or_Unlock [0 ] 0 -O_DR_W Own_Lock_or_Unlock_Tokens [0 ] 0 -O_DR_W Data_Owner [0 ] 0 -O_DR_W Data_All_Tokens [0 ] 0 -O_DR_W Ack_Owner [0 ] 0 -O_DR_W Tokens [0 ] 0 -O_DR_W Ack_All_Tokens [0 ] 0 -O_DR_W Request_Timeout [0 ] 0 -O_DR_W Memory_Data [0 ] 0 -O_DR_W DMA_READ [0 ] 0 -O_DR_W DMA_WRITE [0 ] 0 -O_DR_W DMA_WRITE_All_Tokens [0 ] 0 - -O_DW GETX [0 ] 0 -O_DW GETS [0 ] 0 -O_DW Lockdown [0 ] 0 -O_DW Unlockdown [0 ] 0 -O_DW Own_Lock_or_Unlock [0 ] 0 -O_DW Own_Lock_or_Unlock_Tokens [0 ] 0 -O_DW Data_Owner [0 ] 0 -O_DW Data_All_Tokens [0 ] 0 -O_DW Ack_Owner [0 ] 0 -O_DW Ack_Owner_All_Tokens [0 ] 0 -O_DW Tokens [0 ] 0 -O_DW Ack_All_Tokens [0 ] 0 -O_DW Request_Timeout [0 ] 0 -O_DW DMA_READ [0 ] 0 -O_DW DMA_WRITE [0 ] 0 -O_DW DMA_WRITE_All_Tokens [0 ] 0 - -NO_DW GETX [0 ] 0 -NO_DW GETS [0 ] 0 -NO_DW Lockdown [0 ] 0 -NO_DW Unlockdown [0 ] 0 -NO_DW Own_Lock_or_Unlock [0 ] 0 -NO_DW Own_Lock_or_Unlock_Tokens [0 ] 0 -NO_DW Data_Owner [0 ] 0 -NO_DW Data_All_Tokens [0 ] 0 -NO_DW Tokens [0 ] 0 -NO_DW Request_Timeout [0 ] 0 -NO_DW DMA_READ [0 ] 0 -NO_DW DMA_WRITE [0 ] 0 -NO_DW DMA_WRITE_All_Tokens [0 ] 0 - -NO_DR GETX [0 ] 0 -NO_DR GETS [0 ] 0 -NO_DR Lockdown [0 ] 0 -NO_DR Unlockdown [0 ] 0 -NO_DR Own_Lock_or_Unlock [0 ] 0 -NO_DR Own_Lock_or_Unlock_Tokens [0 ] 0 -NO_DR Data_Owner [0 ] 0 -NO_DR Data_All_Tokens [0 ] 0 -NO_DR Tokens [0 ] 0 -NO_DR Request_Timeout [0 ] 0 -NO_DR DMA_READ [0 ] 0 -NO_DR DMA_WRITE [0 ] 0 -NO_DR DMA_WRITE_All_Tokens [0 ] 0 - -DW_L GETX [0 ] 0 -DW_L GETS [0 ] 0 -DW_L Lockdown [0 ] 0 -DW_L Unlockdown [0 ] 0 -DW_L Own_Lock_or_Unlock [0 ] 0 -DW_L Own_Lock_or_Unlock_Tokens [0 ] 0 -DW_L Data_Owner [0 ] 0 -DW_L Data_All_Tokens [0 ] 0 -DW_L Ack_Owner [0 ] 0 -DW_L Ack_Owner_All_Tokens [0 ] 0 -DW_L Tokens [0 ] 0 -DW_L Request_Timeout [0 ] 0 -DW_L DMA_READ [0 ] 0 -DW_L DMA_WRITE [0 ] 0 -DW_L DMA_WRITE_All_Tokens [0 ] 0 - -DR_L GETX [0 ] 0 -DR_L GETS [0 ] 0 -DR_L Lockdown [0 ] 0 -DR_L Unlockdown [0 ] 0 -DR_L Own_Lock_or_Unlock [0 ] 0 -DR_L Own_Lock_or_Unlock_Tokens [0 ] 0 -DR_L Data_Owner [0 ] 0 -DR_L Data_All_Tokens [0 ] 0 -DR_L Ack_Owner [0 ] 0 -DR_L Ack_Owner_All_Tokens [0 ] 0 -DR_L Tokens [0 ] 0 -DR_L Request_Timeout [0 ] 0 -DR_L DMA_READ [0 ] 0 -DR_L DMA_WRITE [0 ] 0 -DR_L DMA_WRITE_All_Tokens [0 ] 0 - diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simerr b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simerr deleted file mode 100755 index 31ae36f2e..000000000 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simerr +++ /dev/null @@ -1,3 +0,0 @@ -warn: Sockets disabled, not accepting gdb connections -warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...) -hack: be nice to actually delete the event here diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simout b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simout deleted file mode 100755 index 476a0b599..000000000 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simout +++ /dev/null @@ -1,12 +0,0 @@ -gem5 Simulator System. http://gem5.org -gem5 is copyrighted software; use the --copyright option for details. - -gem5 compiled Jan 23 2012 03:50:16 -gem5 started Jan 23 2012 04:22:25 -gem5 executing on zizzer -command line: build/ALPHA_SE_MOESI_CMP_token/gem5.opt -d build/ALPHA_SE_MOESI_CMP_token/tests/opt/quick/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_token -re tests/run.py build/ALPHA_SE_MOESI_CMP_token/tests/opt/quick/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_token -Global frequency set at 1000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -info: Increasing stack size by one page. -Hello world! -Exiting @ tick 87899 because target called exit() diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt deleted file mode 100644 index fd5600236..000000000 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt +++ /dev/null @@ -1,77 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 0.000088 # Number of seconds simulated -sim_ticks 87899 # Number of ticks simulated -final_tick 87899 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 12702 # Simulator instruction rate (inst/s) -host_tick_rate 433208 # Simulator tick rate (ticks/s) -host_mem_usage 216416 # Number of bytes of host memory used -host_seconds 0.20 # Real time elapsed on the host -sim_insts 2577 # Number of instructions simulated -system.physmem.bytes_read 13356 # Number of bytes read from this memory -system.physmem.bytes_inst_read 10340 # Number of instructions bytes read from this memory -system.physmem.bytes_written 2058 # Number of bytes written to this memory -system.physmem.num_reads 3000 # Number of read requests responded to by this memory -system.physmem.num_writes 294 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 151947121 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 117635013 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 23413236 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 175360357 # Total bandwidth to/from this memory (bytes/s) -system.cpu.dtb.fetch_hits 0 # ITB hits -system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.fetch_acv 0 # ITB acv -system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 415 # DTB read hits -system.cpu.dtb.read_misses 4 # DTB read misses -system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 419 # DTB read accesses -system.cpu.dtb.write_hits 294 # DTB write hits -system.cpu.dtb.write_misses 4 # DTB write misses -system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 298 # DTB write accesses -system.cpu.dtb.data_hits 709 # DTB hits -system.cpu.dtb.data_misses 8 # DTB misses -system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 717 # DTB accesses -system.cpu.itb.fetch_hits 2586 # ITB hits -system.cpu.itb.fetch_misses 11 # ITB misses -system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 2597 # ITB accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.read_acv 0 # DTB read access violations -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.write_acv 0 # DTB write access violations -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.data_hits 0 # DTB hits -system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.data_acv 0 # DTB access violations -system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.workload.num_syscalls 4 # Number of system calls -system.cpu.numCycles 87899 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.num_insts 2577 # Number of instructions executed -system.cpu.num_int_alu_accesses 2375 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 6 # Number of float alu accesses -system.cpu.num_func_calls 140 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 238 # number of instructions that are conditional controls -system.cpu.num_int_insts 2375 # number of integer instructions -system.cpu.num_fp_insts 6 # number of float instructions -system.cpu.num_int_register_reads 2998 # number of times the integer registers were read -system.cpu.num_int_register_writes 1768 # number of times the integer registers were written -system.cpu.num_fp_register_reads 6 # number of times the floating registers were read -system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_mem_refs 717 # number of memory refs -system.cpu.num_load_insts 419 # Number of load instructions -system.cpu.num_store_insts 298 # Number of store instructions -system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 87899 # Number of busy cycles -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.idle_fraction 0 # Percentage of idle cycles - ----------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/config.ini b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/config.ini deleted file mode 100644 index 209bb4d8d..000000000 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/config.ini +++ /dev/null @@ -1,302 +0,0 @@ -[root] -type=Root -children=system -time_sync_enable=false -time_sync_period=100000000 -time_sync_spin_threshold=100000 - -[system] -type=System -children=cpu dir_cntrl0 l1_cntrl0 physmem ruby sys_port_proxy -mem_mode=timing -memories=system.physmem -num_work_ids=16 -physmem=system.physmem -work_begin_ckpt_count=0 -work_begin_cpu_id_exit=-1 -work_begin_exit_count=0 -work_cpus_ckpt_count=0 -work_end_ckpt_count=0 -work_end_exit_count=0 -work_item_id=-1 -system_port=system.sys_port_proxy.port[0] - -[system.cpu] -type=TimingSimpleCPU -children=dtb itb tracer workload -checker=Null -clock=1 -cpu_id=0 -defer_registration=false -do_checkpoint_insts=true -do_statistics_insts=true -dtb=system.cpu.dtb -function_trace=false -function_trace_start=0 -itb=system.cpu.itb -max_insts_all_threads=0 -max_insts_any_thread=0 -max_loads_all_threads=0 -max_loads_any_thread=0 -numThreads=1 -phase=0 -progress_interval=0 -system=system -tracer=system.cpu.tracer -workload=system.cpu.workload -dcache_port=system.l1_cntrl0.sequencer.port[1] -icache_port=system.l1_cntrl0.sequencer.port[0] - -[system.cpu.dtb] -type=AlphaTLB -size=64 - -[system.cpu.itb] -type=AlphaTLB -size=48 - -[system.cpu.tracer] -type=ExeTracer - -[system.cpu.workload] -type=LiveProcess -cmd=hello -cwd= -egid=100 -env= -errout=cerr -euid=100 -executable=/dist/m5/regression/test-progs/hello/bin/alpha/tru64/hello -gid=100 -input=cin -max_stack_size=67108864 -output=cout -pid=100 -ppid=99 -simpoint=0 -system=system -uid=100 - -[system.dir_cntrl0] -type=Directory_Controller -children=directory memBuffer probeFilter -buffer_size=0 -cntrl_id=1 -directory=system.dir_cntrl0.directory -full_bit_dir_enabled=false -memBuffer=system.dir_cntrl0.memBuffer -memory_controller_latency=2 -number_of_TBEs=256 -probeFilter=system.dir_cntrl0.probeFilter -probe_filter_enabled=false -recycle_latency=10 -ruby_system=system.ruby -transitions_per_cycle=32 -version=0 - -[system.dir_cntrl0.directory] -type=RubyDirectoryMemory -map_levels=4 -numa_high_bit=6 -size=134217728 -use_map=false -version=0 - -[system.dir_cntrl0.memBuffer] -type=RubyMemoryControl -bank_bit_0=8 -bank_busy_time=11 -bank_queue_size=12 -banks_per_rank=8 -basic_bus_busy_time=2 -dimm_bit_0=12 -dimms_per_channel=2 -mem_bus_cycle_multiplier=10 -mem_ctl_latency=12 -mem_fixed_delay=0 -mem_random_arbitrate=0 -rank_bit_0=11 -rank_rank_delay=1 -ranks_per_dimm=2 -read_write_delay=2 -refresh_period=1560 -tFaw=0 -version=0 - -[system.dir_cntrl0.probeFilter] -type=RubyCache -assoc=4 -is_icache=false -latency=1 -replacement_policy=PSEUDO_LRU -size=1024 -start_index_bit=6 - -[system.l1_cntrl0] -type=L1Cache_Controller -children=L1DcacheMemory L1IcacheMemory L2cacheMemory sequencer -L1DcacheMemory=system.l1_cntrl0.L1DcacheMemory -L1IcacheMemory=system.l1_cntrl0.L1IcacheMemory -L2cacheMemory=system.l1_cntrl0.L2cacheMemory -buffer_size=0 -cache_response_latency=10 -cntrl_id=0 -issue_latency=2 -l2_cache_hit_latency=10 -no_mig_atomic=true -number_of_TBEs=256 -recycle_latency=10 -ruby_system=system.ruby -sequencer=system.l1_cntrl0.sequencer -transitions_per_cycle=32 -version=0 - -[system.l1_cntrl0.L1DcacheMemory] -type=RubyCache -assoc=2 -is_icache=false -latency=2 -replacement_policy=PSEUDO_LRU -size=256 -start_index_bit=6 - -[system.l1_cntrl0.L1IcacheMemory] -type=RubyCache -assoc=2 -is_icache=true -latency=2 -replacement_policy=PSEUDO_LRU -size=256 -start_index_bit=6 - -[system.l1_cntrl0.L2cacheMemory] -type=RubyCache -assoc=2 -is_icache=false -latency=10 -replacement_policy=PSEUDO_LRU -size=512 -start_index_bit=6 - -[system.l1_cntrl0.sequencer] -type=RubySequencer -access_phys_mem=true -dcache=system.l1_cntrl0.L1DcacheMemory -deadlock_threshold=500000 -icache=system.l1_cntrl0.L1IcacheMemory -max_outstanding_requests=16 -physmem=system.physmem -ruby_system=system.ruby -using_network_tester=false -using_ruby_tester=false -version=0 -physMemPort=system.physmem.port[0] -port=system.cpu.icache_port system.cpu.dcache_port - -[system.physmem] -type=PhysicalMemory -file= -latency=30 -latency_var=0 -null=false -range=0:134217727 -zero=false -port=system.l1_cntrl0.sequencer.physMemPort system.sys_port_proxy.physMemPort - -[system.ruby] -type=RubySystem -children=network profiler -block_size_bytes=64 -clock=1 -mem_size=134217728 -no_mem_vec=false -random_seed=1234 -randomization=false -stats_filename=ruby.stats - -[system.ruby.network] -type=SimpleNetwork -children=topology -adaptive_routing=false -buffer_size=0 -control_msg_size=8 -endpoint_bandwidth=1000 -number_of_virtual_networks=10 -ruby_system=system.ruby -topology=system.ruby.network.topology - -[system.ruby.network.topology] -type=Topology -children=ext_links0 ext_links1 int_links0 int_links1 routers0 routers1 routers2 -description=Crossbar -ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1 -int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1 -print_config=false -routers=system.ruby.network.topology.routers0 system.ruby.network.topology.routers1 system.ruby.network.topology.routers2 - -[system.ruby.network.topology.ext_links0] -type=SimpleExtLink -bandwidth_factor=16 -ext_node=system.l1_cntrl0 -int_node=system.ruby.network.topology.routers0 -latency=1 -link_id=0 -weight=1 - -[system.ruby.network.topology.ext_links1] -type=SimpleExtLink -bandwidth_factor=16 -ext_node=system.dir_cntrl0 -int_node=system.ruby.network.topology.routers1 -latency=1 -link_id=1 -weight=1 - -[system.ruby.network.topology.int_links0] -type=SimpleIntLink -bandwidth_factor=16 -latency=1 -link_id=2 -node_a=system.ruby.network.topology.routers0 -node_b=system.ruby.network.topology.routers2 -weight=1 - -[system.ruby.network.topology.int_links1] -type=SimpleIntLink -bandwidth_factor=16 -latency=1 -link_id=3 -node_a=system.ruby.network.topology.routers1 -node_b=system.ruby.network.topology.routers2 -weight=1 - -[system.ruby.network.topology.routers0] -type=BasicRouter -router_id=0 - -[system.ruby.network.topology.routers1] -type=BasicRouter -router_id=1 - -[system.ruby.network.topology.routers2] -type=BasicRouter -router_id=2 - -[system.ruby.profiler] -type=RubyProfiler -all_instructions=false -hot_lines=false -num_of_sequencers=1 -ruby_system=system.ruby - -[system.sys_port_proxy] -type=RubyPortProxy -access_phys_mem=true -physmem=system.physmem -ruby_system=system.ruby -using_network_tester=false -using_ruby_tester=false -version=0 -physMemPort=system.physmem.port[1] -port=system.system_port - diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/ruby.stats b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/ruby.stats deleted file mode 100644 index 452952d26..000000000 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/ruby.stats +++ /dev/null @@ -1,973 +0,0 @@ - -================ Begin RubySystem Configuration Print ================ - -RubySystem config: - random_seed: 1234 - randomization: 0 - cycle_period: 1 - block_size_bytes: 64 - block_size_bits: 6 - memory_size_bytes: 134217728 - memory_size_bits: 27 - -Network Configuration ---------------------- -network: SIMPLE_NETWORK -topology: - -virtual_net_0: active, ordered -virtual_net_1: active, ordered -virtual_net_2: active, unordered -virtual_net_3: active, unordered -virtual_net_4: active, unordered -virtual_net_5: active, unordered -virtual_net_6: inactive -virtual_net_7: inactive -virtual_net_8: inactive -virtual_net_9: inactive - - -Profiler Configuration ----------------------- -periodic_stats_period: 1000000 - -================ End RubySystem Configuration Print ================ - - -Real time: Jan/23/2012 04:21:49 - -Profiler Stats --------------- -Elapsed_time_in_seconds: 0 -Elapsed_time_in_minutes: 0 -Elapsed_time_in_hours: 0 -Elapsed_time_in_days: 0 - -Virtual_time_in_seconds: 0.23 -Virtual_time_in_minutes: 0.00383333 -Virtual_time_in_hours: 6.38889e-05 -Virtual_time_in_days: 2.66204e-06 - -Ruby_current_time: 78448 -Ruby_start_time: 0 -Ruby_cycles: 78448 - -mbytes_resident: 41.5938 -mbytes_total: 210.898 -resident_ratio: 0.197222 - -ruby_cycles_executed: [ 78449 ] - -Busy Controller Counts: -L1Cache-0:0 -Directory-0:0 - - -Busy Bank Count:0 - -sequencer_requests_outstanding: [binsize: 1 max: 1 count: 3295 average: 1 | standard deviation: 0 | 0 3295 ] - -All Non-Zero Cycle Demand Cache Accesses ----------------------------------------- -miss_latency: [binsize: 2 max: 320 count: 3294 average: 22.8154 | standard deviation: 52.8821 | 0 2784 0 0 0 0 69 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 35 77 95 66 57 76 2 2 1 4 2 0 1 2 2 5 1 4 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 3 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_LD: [binsize: 2 max: 319 count: 415 average: 57.3952 | standard deviation: 74.7751 | 0 233 0 0 0 0 36 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 35 24 16 16 26 0 1 1 0 1 0 0 1 2 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_ST: [binsize: 2 max: 320 count: 294 average: 28.9728 | standard deviation: 63.5282 | 0 236 0 0 0 0 11 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3 7 6 7 5 10 0 0 0 1 1 0 1 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 2 0 1 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_IFETCH: [binsize: 1 max: 181 count: 2585 average: 16.5636 | standard deviation: 44.4401 | 0 0 2315 0 0 0 0 0 0 0 0 0 0 22 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 47 18 11 32 22 14 39 1 1 1 1 0 0 0 2 1 0 0 0 0 0 0 0 1 0 0 0 2 1 0 2 1 ] -miss_latency_L1Cache: [binsize: 1 max: 2 count: 2784 average: 2 | standard deviation: 0 | 0 0 2784 ] -miss_latency_L2Cache: [binsize: 1 max: 13 count: 69 average: 13 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 69 ] -miss_latency_Directory: [binsize: 2 max: 320 count: 441 average: 155.757 | standard deviation: 21.4255 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 35 77 95 66 57 76 2 2 1 4 2 0 1 2 2 5 1 4 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 3 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] -miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] -miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] -miss_latency_wCC_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] -imcomplete_wCC_Times: 0 -miss_latency_dir_issue_to_initial_request: [binsize: 1 max: 0 count: 1 average: 0 | standard deviation: 0 | 1 ] -miss_latency_dir_initial_forward_request: [binsize: 1 max: 0 count: 1 average: 0 | standard deviation: 0 | 1 ] -miss_latency_dir_forward_to_first_response: [binsize: 1 max: 158 count: 1 average: 158 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ] -miss_latency_dir_first_response_to_completion: [binsize: 1 max: 0 count: 1 average: 0 | standard deviation: 0 | 1 ] -imcomplete_dir_Times: 440 -miss_latency_LD_L1Cache: [binsize: 1 max: 2 count: 233 average: 2 | standard deviation: 0 | 0 0 233 ] -miss_latency_LD_L2Cache: [binsize: 1 max: 13 count: 36 average: 13 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 36 ] -miss_latency_LD_Directory: [binsize: 2 max: 319 count: 146 average: 156.747 | standard deviation: 24.5989 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 35 24 16 16 26 0 1 1 0 1 0 0 1 2 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_ST_L1Cache: [binsize: 1 max: 2 count: 236 average: 2 | standard deviation: 0 | 0 0 236 ] -miss_latency_ST_L2Cache: [binsize: 1 max: 13 count: 11 average: 13 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 11 ] -miss_latency_ST_Directory: [binsize: 2 max: 320 count: 47 average: 168.149 | standard deviation: 46.0633 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3 7 6 7 5 10 0 0 0 1 1 0 1 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 2 0 1 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_IFETCH_L1Cache: [binsize: 1 max: 2 count: 2315 average: 2 | standard deviation: 0 | 0 0 2315 ] -miss_latency_IFETCH_L2Cache: [binsize: 1 max: 13 count: 22 average: 13 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 22 ] -miss_latency_IFETCH_Directory: [binsize: 1 max: 181 count: 248 average: 152.827 | standard deviation: 5.37952 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 47 18 11 32 22 14 39 1 1 1 1 0 0 0 2 1 0 0 0 0 0 0 0 1 0 0 0 2 1 0 2 1 ] - -All Non-Zero Cycle SW Prefetch Requests ------------------------------------- -prefetch_latency: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] -prefetch_latency_L2Miss:[binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] -Request vs. RubySystem State Profile --------------------------------- - - -filter_action: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - -Message Delayed Cycles ----------------------- -Total_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] -Total_nonPF_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - virtual_network_0_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - virtual_network_1_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - virtual_network_2_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - virtual_network_3_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - virtual_network_4_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - virtual_network_5_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - virtual_network_6_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - virtual_network_7_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - virtual_network_8_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - virtual_network_9_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - -Resource Usage --------------- -page_size: 4096 -user_time: 0 -system_time: 0 -page_reclaims: 10974 -page_faults: 0 -swaps: 0 -block_inputs: 0 -block_outputs: 88 - -Network Stats -------------- - -total_msg_count_Request_Control: 1323 10584 -total_msg_count_Response_Data: 1323 95256 -total_msg_count_Writeback_Data: 243 17496 -total_msg_count_Writeback_Control: 3582 28656 -total_msg_count_Unblock_Control: 1320 10560 -total_msgs: 7791 total_bytes: 162552 - -switch_0_inlinks: 2 -switch_0_outlinks: 2 -links_utilized_percent_switch_0: 2.15844 - links_utilized_percent_switch_0_link_0: 2.80058 bw: 16000 base_latency: 1 - links_utilized_percent_switch_0_link_1: 1.51629 bw: 16000 base_latency: 1 - - outgoing_messages_switch_0_link_0_Response_Data: 441 31752 [ 0 0 0 0 441 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_0_Writeback_Control: 425 3400 [ 0 0 0 425 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Request_Control: 441 3528 [ 0 0 441 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Writeback_Data: 81 5832 [ 0 0 0 0 0 81 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Writeback_Control: 769 6152 [ 0 0 425 0 0 344 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Unblock_Control: 440 3520 [ 0 0 0 0 0 440 0 0 0 0 ] base_latency: 1 - -switch_1_inlinks: 2 -switch_1_outlinks: 2 -links_utilized_percent_switch_1: 2.15844 - links_utilized_percent_switch_1_link_0: 1.51629 bw: 16000 base_latency: 1 - links_utilized_percent_switch_1_link_1: 2.80058 bw: 16000 base_latency: 1 - - outgoing_messages_switch_1_link_0_Request_Control: 441 3528 [ 0 0 441 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_0_Writeback_Data: 81 5832 [ 0 0 0 0 0 81 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_0_Writeback_Control: 769 6152 [ 0 0 425 0 0 344 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_0_Unblock_Control: 440 3520 [ 0 0 0 0 0 440 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_Response_Data: 441 31752 [ 0 0 0 0 441 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_Writeback_Control: 425 3400 [ 0 0 0 425 0 0 0 0 0 0 ] base_latency: 1 - -switch_2_inlinks: 2 -switch_2_outlinks: 2 -links_utilized_percent_switch_2: 2.15844 - links_utilized_percent_switch_2_link_0: 2.80058 bw: 16000 base_latency: 1 - links_utilized_percent_switch_2_link_1: 1.51629 bw: 16000 base_latency: 1 - - outgoing_messages_switch_2_link_0_Response_Data: 441 31752 [ 0 0 0 0 441 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_0_Writeback_Control: 425 3400 [ 0 0 0 425 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_1_Request_Control: 441 3528 [ 0 0 441 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_1_Writeback_Data: 81 5832 [ 0 0 0 0 0 81 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_1_Writeback_Control: 769 6152 [ 0 0 425 0 0 344 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_1_Unblock_Control: 440 3520 [ 0 0 0 0 0 440 0 0 0 0 ] base_latency: 1 - -Cache Stats: system.l1_cntrl0.L1IcacheMemory - system.l1_cntrl0.L1IcacheMemory_total_misses: 270 - system.l1_cntrl0.L1IcacheMemory_total_demand_misses: 270 - system.l1_cntrl0.L1IcacheMemory_total_prefetches: 0 - system.l1_cntrl0.L1IcacheMemory_total_sw_prefetches: 0 - system.l1_cntrl0.L1IcacheMemory_total_hw_prefetches: 0 - - system.l1_cntrl0.L1IcacheMemory_request_type_IFETCH: 100% - - system.l1_cntrl0.L1IcacheMemory_access_mode_type_Supervisor: 270 100% - -Cache Stats: system.l1_cntrl0.L1DcacheMemory - system.l1_cntrl0.L1DcacheMemory_total_misses: 240 - system.l1_cntrl0.L1DcacheMemory_total_demand_misses: 240 - system.l1_cntrl0.L1DcacheMemory_total_prefetches: 0 - system.l1_cntrl0.L1DcacheMemory_total_sw_prefetches: 0 - system.l1_cntrl0.L1DcacheMemory_total_hw_prefetches: 0 - - system.l1_cntrl0.L1DcacheMemory_request_type_LD: 75.8333% - system.l1_cntrl0.L1DcacheMemory_request_type_ST: 24.1667% - - system.l1_cntrl0.L1DcacheMemory_access_mode_type_Supervisor: 240 100% - -Cache Stats: system.l1_cntrl0.L2cacheMemory - system.l1_cntrl0.L2cacheMemory_total_misses: 510 - system.l1_cntrl0.L2cacheMemory_total_demand_misses: 510 - system.l1_cntrl0.L2cacheMemory_total_prefetches: 0 - system.l1_cntrl0.L2cacheMemory_total_sw_prefetches: 0 - system.l1_cntrl0.L2cacheMemory_total_hw_prefetches: 0 - - system.l1_cntrl0.L2cacheMemory_request_type_LD: 35.6863% - system.l1_cntrl0.L2cacheMemory_request_type_ST: 11.3725% - system.l1_cntrl0.L2cacheMemory_request_type_IFETCH: 52.9412% - - system.l1_cntrl0.L2cacheMemory_access_mode_type_Supervisor: 510 100% - - --- L1Cache --- - - Event Counts - -Load [422 ] 422 -Ifetch [2591 ] 2591 -Store [298 ] 298 -L2_Replacement [425 ] 425 -L1_to_L2 [502 ] 502 -Trigger_L2_to_L1D [47 ] 47 -Trigger_L2_to_L1I [22 ] 22 -Complete_L2_to_L1 [69 ] 69 -Other_GETX [0 ] 0 -Other_GETS [0 ] 0 -Merged_GETS [0 ] 0 -Other_GETS_No_Mig [0 ] 0 -NC_DMA_GETS [0 ] 0 -Invalidate [0 ] 0 -Ack [0 ] 0 -Shared_Ack [0 ] 0 -Data [0 ] 0 -Shared_Data [0 ] 0 -Exclusive_Data [441 ] 441 -Writeback_Ack [425 ] 425 -Writeback_Nack [0 ] 0 -All_acks [0 ] 0 -All_acks_no_sharers [441 ] 441 -Flush_line [0 ] 0 -Block_Ack [0 ] 0 - - - Transitions - -I Load [146 ] 146 -I Ifetch [248 ] 248 -I Store [47 ] 47 -I L2_Replacement [0 ] 0 -I L1_to_L2 [0 ] 0 -I Trigger_L2_to_L1D [0 ] 0 -I Trigger_L2_to_L1I [0 ] 0 -I Other_GETX [0 ] 0 -I Other_GETS [0 ] 0 -I Other_GETS_No_Mig [0 ] 0 -I NC_DMA_GETS [0 ] 0 -I Invalidate [0 ] 0 -I Flush_line [0 ] 0 - -S Load [0 ] 0 -S Ifetch [0 ] 0 -S Store [0 ] 0 -S L2_Replacement [0 ] 0 -S L1_to_L2 [0 ] 0 -S Trigger_L2_to_L1D [0 ] 0 -S Trigger_L2_to_L1I [0 ] 0 -S Other_GETX [0 ] 0 -S Other_GETS [0 ] 0 -S Other_GETS_No_Mig [0 ] 0 -S NC_DMA_GETS [0 ] 0 -S Invalidate [0 ] 0 -S Flush_line [0 ] 0 - -O Load [0 ] 0 -O Ifetch [0 ] 0 -O Store [0 ] 0 -O L2_Replacement [0 ] 0 -O L1_to_L2 [0 ] 0 -O Trigger_L2_to_L1D [0 ] 0 -O Trigger_L2_to_L1I [0 ] 0 -O Other_GETX [0 ] 0 -O Other_GETS [0 ] 0 -O Merged_GETS [0 ] 0 -O Other_GETS_No_Mig [0 ] 0 -O NC_DMA_GETS [0 ] 0 -O Invalidate [0 ] 0 -O Flush_line [0 ] 0 - -M Load [109 ] 109 -M Ifetch [2315 ] 2315 -M Store [35 ] 35 -M L2_Replacement [344 ] 344 -M L1_to_L2 [397 ] 397 -M Trigger_L2_to_L1D [23 ] 23 -M Trigger_L2_to_L1I [22 ] 22 -M Other_GETX [0 ] 0 -M Other_GETS [0 ] 0 -M Merged_GETS [0 ] 0 -M Other_GETS_No_Mig [0 ] 0 -M NC_DMA_GETS [0 ] 0 -M Invalidate [0 ] 0 -M Flush_line [0 ] 0 - -MM Load [124 ] 124 -MM Ifetch [0 ] 0 -MM Store [201 ] 201 -MM L2_Replacement [81 ] 81 -MM L1_to_L2 [105 ] 105 -MM Trigger_L2_to_L1D [24 ] 24 -MM Trigger_L2_to_L1I [0 ] 0 -MM Other_GETX [0 ] 0 -MM Other_GETS [0 ] 0 -MM Merged_GETS [0 ] 0 -MM Other_GETS_No_Mig [0 ] 0 -MM NC_DMA_GETS [0 ] 0 -MM Invalidate [0 ] 0 -MM Flush_line [0 ] 0 - -IR Load [0 ] 0 -IR Ifetch [0 ] 0 -IR Store [0 ] 0 -IR L1_to_L2 [0 ] 0 -IR Flush_line [0 ] 0 - -SR Load [0 ] 0 -SR Ifetch [0 ] 0 -SR Store [0 ] 0 -SR L1_to_L2 [0 ] 0 -SR Flush_line [0 ] 0 - -OR Load [0 ] 0 -OR Ifetch [0 ] 0 -OR Store [0 ] 0 -OR L1_to_L2 [0 ] 0 -OR Flush_line [0 ] 0 - -MR Load [22 ] 22 -MR Ifetch [22 ] 22 -MR Store [1 ] 1 -MR L1_to_L2 [0 ] 0 -MR Flush_line [0 ] 0 - -MMR Load [14 ] 14 -MMR Ifetch [0 ] 0 -MMR Store [10 ] 10 -MMR L1_to_L2 [0 ] 0 -MMR Flush_line [0 ] 0 - -IM Load [0 ] 0 -IM Ifetch [0 ] 0 -IM Store [0 ] 0 -IM L2_Replacement [0 ] 0 -IM L1_to_L2 [0 ] 0 -IM Other_GETX [0 ] 0 -IM Other_GETS [0 ] 0 -IM Other_GETS_No_Mig [0 ] 0 -IM NC_DMA_GETS [0 ] 0 -IM Invalidate [0 ] 0 -IM Ack [0 ] 0 -IM Data [0 ] 0 -IM Exclusive_Data [47 ] 47 -IM Flush_line [0 ] 0 - -SM Load [0 ] 0 -SM Ifetch [0 ] 0 -SM Store [0 ] 0 -SM L2_Replacement [0 ] 0 -SM L1_to_L2 [0 ] 0 -SM Other_GETX [0 ] 0 -SM Other_GETS [0 ] 0 -SM Other_GETS_No_Mig [0 ] 0 -SM NC_DMA_GETS [0 ] 0 -SM Invalidate [0 ] 0 -SM Ack [0 ] 0 -SM Data [0 ] 0 -SM Exclusive_Data [0 ] 0 -SM Flush_line [0 ] 0 - -OM Load [0 ] 0 -OM Ifetch [0 ] 0 -OM Store [0 ] 0 -OM L2_Replacement [0 ] 0 -OM L1_to_L2 [0 ] 0 -OM Other_GETX [0 ] 0 -OM Other_GETS [0 ] 0 -OM Merged_GETS [0 ] 0 -OM Other_GETS_No_Mig [0 ] 0 -OM NC_DMA_GETS [0 ] 0 -OM Invalidate [0 ] 0 -OM Ack [0 ] 0 -OM All_acks [0 ] 0 -OM All_acks_no_sharers [0 ] 0 -OM Flush_line [0 ] 0 - -ISM Load [0 ] 0 -ISM Ifetch [0 ] 0 -ISM Store [0 ] 0 -ISM L2_Replacement [0 ] 0 -ISM L1_to_L2 [0 ] 0 -ISM Ack [0 ] 0 -ISM All_acks_no_sharers [0 ] 0 -ISM Flush_line [0 ] 0 - -M_W Load [0 ] 0 -M_W Ifetch [0 ] 0 -M_W Store [0 ] 0 -M_W L2_Replacement [0 ] 0 -M_W L1_to_L2 [0 ] 0 -M_W Ack [0 ] 0 -M_W All_acks_no_sharers [394 ] 394 -M_W Flush_line [0 ] 0 - -MM_W Load [0 ] 0 -MM_W Ifetch [0 ] 0 -MM_W Store [0 ] 0 -MM_W L2_Replacement [0 ] 0 -MM_W L1_to_L2 [0 ] 0 -MM_W Ack [0 ] 0 -MM_W All_acks_no_sharers [47 ] 47 -MM_W Flush_line [0 ] 0 - -IS Load [0 ] 0 -IS Ifetch [0 ] 0 -IS Store [0 ] 0 -IS L2_Replacement [0 ] 0 -IS L1_to_L2 [0 ] 0 -IS Other_GETX [0 ] 0 -IS Other_GETS [0 ] 0 -IS Other_GETS_No_Mig [0 ] 0 -IS NC_DMA_GETS [0 ] 0 -IS Invalidate [0 ] 0 -IS Ack [0 ] 0 -IS Shared_Ack [0 ] 0 -IS Data [0 ] 0 -IS Shared_Data [0 ] 0 -IS Exclusive_Data [394 ] 394 -IS Flush_line [0 ] 0 - -SS Load [0 ] 0 -SS Ifetch [0 ] 0 -SS Store [0 ] 0 -SS L2_Replacement [0 ] 0 -SS L1_to_L2 [0 ] 0 -SS Ack [0 ] 0 -SS Shared_Ack [0 ] 0 -SS All_acks [0 ] 0 -SS All_acks_no_sharers [0 ] 0 -SS Flush_line [0 ] 0 - -OI Load [0 ] 0 -OI Ifetch [0 ] 0 -OI Store [0 ] 0 -OI L2_Replacement [0 ] 0 -OI L1_to_L2 [0 ] 0 -OI Other_GETX [0 ] 0 -OI Other_GETS [0 ] 0 -OI Merged_GETS [0 ] 0 -OI Other_GETS_No_Mig [0 ] 0 -OI NC_DMA_GETS [0 ] 0 -OI Invalidate [0 ] 0 -OI Writeback_Ack [0 ] 0 -OI Flush_line [0 ] 0 - -MI Load [7 ] 7 -MI Ifetch [6 ] 6 -MI Store [4 ] 4 -MI L2_Replacement [0 ] 0 -MI L1_to_L2 [0 ] 0 -MI Other_GETX [0 ] 0 -MI Other_GETS [0 ] 0 -MI Merged_GETS [0 ] 0 -MI Other_GETS_No_Mig [0 ] 0 -MI NC_DMA_GETS [0 ] 0 -MI Invalidate [0 ] 0 -MI Writeback_Ack [425 ] 425 -MI Flush_line [0 ] 0 - -II Load [0 ] 0 -II Ifetch [0 ] 0 -II Store [0 ] 0 -II L2_Replacement [0 ] 0 -II L1_to_L2 [0 ] 0 -II Other_GETX [0 ] 0 -II Other_GETS [0 ] 0 -II Other_GETS_No_Mig [0 ] 0 -II NC_DMA_GETS [0 ] 0 -II Invalidate [0 ] 0 -II Writeback_Ack [0 ] 0 -II Writeback_Nack [0 ] 0 -II Flush_line [0 ] 0 - -IT Load [0 ] 0 -IT Ifetch [0 ] 0 -IT Store [0 ] 0 -IT L2_Replacement [0 ] 0 -IT L1_to_L2 [0 ] 0 -IT Complete_L2_to_L1 [0 ] 0 - -ST Load [0 ] 0 -ST Ifetch [0 ] 0 -ST Store [0 ] 0 -ST L2_Replacement [0 ] 0 -ST L1_to_L2 [0 ] 0 -ST Complete_L2_to_L1 [0 ] 0 - -OT Load [0 ] 0 -OT Ifetch [0 ] 0 -OT Store [0 ] 0 -OT L2_Replacement [0 ] 0 -OT L1_to_L2 [0 ] 0 -OT Complete_L2_to_L1 [0 ] 0 - -MT Load [0 ] 0 -MT Ifetch [0 ] 0 -MT Store [0 ] 0 -MT L2_Replacement [0 ] 0 -MT L1_to_L2 [0 ] 0 -MT Complete_L2_to_L1 [45 ] 45 - -MMT Load [0 ] 0 -MMT Ifetch [0 ] 0 -MMT Store [0 ] 0 -MMT L2_Replacement [0 ] 0 -MMT L1_to_L2 [0 ] 0 -MMT Complete_L2_to_L1 [24 ] 24 - -MI_F Load [0 ] 0 -MI_F Ifetch [0 ] 0 -MI_F Store [0 ] 0 -MI_F L1_to_L2 [0 ] 0 -MI_F Writeback_Ack [0 ] 0 -MI_F Flush_line [0 ] 0 - -MM_F Load [0 ] 0 -MM_F Ifetch [0 ] 0 -MM_F Store [0 ] 0 -MM_F L1_to_L2 [0 ] 0 -MM_F Other_GETX [0 ] 0 -MM_F Other_GETS [0 ] 0 -MM_F Merged_GETS [0 ] 0 -MM_F Other_GETS_No_Mig [0 ] 0 -MM_F NC_DMA_GETS [0 ] 0 -MM_F Invalidate [0 ] 0 -MM_F Ack [0 ] 0 -MM_F All_acks [0 ] 0 -MM_F All_acks_no_sharers [0 ] 0 -MM_F Flush_line [0 ] 0 -MM_F Block_Ack [0 ] 0 - -IM_F Load [0 ] 0 -IM_F Ifetch [0 ] 0 -IM_F Store [0 ] 0 -IM_F L2_Replacement [0 ] 0 -IM_F L1_to_L2 [0 ] 0 -IM_F Other_GETX [0 ] 0 -IM_F Other_GETS [0 ] 0 -IM_F Other_GETS_No_Mig [0 ] 0 -IM_F NC_DMA_GETS [0 ] 0 -IM_F Invalidate [0 ] 0 -IM_F Ack [0 ] 0 -IM_F Data [0 ] 0 -IM_F Exclusive_Data [0 ] 0 -IM_F Flush_line [0 ] 0 - -ISM_F Load [0 ] 0 -ISM_F Ifetch [0 ] 0 -ISM_F Store [0 ] 0 -ISM_F L2_Replacement [0 ] 0 -ISM_F L1_to_L2 [0 ] 0 -ISM_F Ack [0 ] 0 -ISM_F All_acks_no_sharers [0 ] 0 -ISM_F Flush_line [0 ] 0 - -SM_F Load [0 ] 0 -SM_F Ifetch [0 ] 0 -SM_F Store [0 ] 0 -SM_F L2_Replacement [0 ] 0 -SM_F L1_to_L2 [0 ] 0 -SM_F Other_GETX [0 ] 0 -SM_F Other_GETS [0 ] 0 -SM_F Other_GETS_No_Mig [0 ] 0 -SM_F NC_DMA_GETS [0 ] 0 -SM_F Invalidate [0 ] 0 -SM_F Ack [0 ] 0 -SM_F Data [0 ] 0 -SM_F Exclusive_Data [0 ] 0 -SM_F Flush_line [0 ] 0 - -OM_F Load [0 ] 0 -OM_F Ifetch [0 ] 0 -OM_F Store [0 ] 0 -OM_F L2_Replacement [0 ] 0 -OM_F L1_to_L2 [0 ] 0 -OM_F Other_GETX [0 ] 0 -OM_F Other_GETS [0 ] 0 -OM_F Merged_GETS [0 ] 0 -OM_F Other_GETS_No_Mig [0 ] 0 -OM_F NC_DMA_GETS [0 ] 0 -OM_F Invalidate [0 ] 0 -OM_F Ack [0 ] 0 -OM_F All_acks [0 ] 0 -OM_F All_acks_no_sharers [0 ] 0 -OM_F Flush_line [0 ] 0 - -MM_WF Load [0 ] 0 -MM_WF Ifetch [0 ] 0 -MM_WF Store [0 ] 0 -MM_WF L2_Replacement [0 ] 0 -MM_WF L1_to_L2 [0 ] 0 -MM_WF Ack [0 ] 0 -MM_WF All_acks_no_sharers [0 ] 0 -MM_WF Flush_line [0 ] 0 - -Cache Stats: system.dir_cntrl0.probeFilter - system.dir_cntrl0.probeFilter_total_misses: 0 - system.dir_cntrl0.probeFilter_total_demand_misses: 0 - system.dir_cntrl0.probeFilter_total_prefetches: 0 - system.dir_cntrl0.probeFilter_total_sw_prefetches: 0 - system.dir_cntrl0.probeFilter_total_hw_prefetches: 0 - - -Memory controller: system.dir_cntrl0.memBuffer: - memory_total_requests: 522 - memory_reads: 441 - memory_writes: 81 - memory_refreshes: 164 - memory_total_request_delays: 151 - memory_delays_per_request: 0.289272 - memory_delays_in_input_queue: 2 - memory_delays_behind_head_of_bank_queue: 0 - memory_delays_stalled_at_head_of_bank_queue: 149 - memory_stalls_for_bank_busy: 22 - memory_stalls_for_random_busy: 0 - memory_stalls_for_anti_starvation: 0 - memory_stalls_for_arbitration: 7 - memory_stalls_for_bus: 26 - memory_stalls_for_tfaw: 0 - memory_stalls_for_read_write_turnaround: 94 - memory_stalls_for_read_read_turnaround: 0 - accesses_per_bank: 18 10 0 36 20 19 31 22 5 4 7 4 22 41 22 3 4 6 7 13 10 18 14 41 16 5 5 12 13 18 14 62 - - --- Directory --- - - Event Counts - -GETX [53 ] 53 -GETS [410 ] 410 -PUT [425 ] 425 -Unblock [0 ] 0 -UnblockS [0 ] 0 -UnblockM [440 ] 440 -Writeback_Clean [0 ] 0 -Writeback_Dirty [0 ] 0 -Writeback_Exclusive_Clean [344 ] 344 -Writeback_Exclusive_Dirty [81 ] 81 -Pf_Replacement [0 ] 0 -DMA_READ [0 ] 0 -DMA_WRITE [0 ] 0 -Memory_Data [441 ] 441 -Memory_Ack [81 ] 81 -Ack [0 ] 0 -Shared_Ack [0 ] 0 -Shared_Data [0 ] 0 -Data [0 ] 0 -Exclusive_Data [0 ] 0 -All_acks_and_shared_data [0 ] 0 -All_acks_and_owner_data [0 ] 0 -All_acks_and_data_no_sharers [0 ] 0 -All_Unblocks [0 ] 0 -GETF [0 ] 0 -PUTF [0 ] 0 - - - Transitions - -NX GETX [0 ] 0 -NX GETS [0 ] 0 -NX PUT [0 ] 0 -NX Pf_Replacement [0 ] 0 -NX DMA_READ [0 ] 0 -NX DMA_WRITE [0 ] 0 -NX GETF [0 ] 0 - -NO GETX [0 ] 0 -NO GETS [0 ] 0 -NO PUT [425 ] 425 -NO Pf_Replacement [0 ] 0 -NO DMA_READ [0 ] 0 -NO DMA_WRITE [0 ] 0 -NO GETF [0 ] 0 - -S GETX [0 ] 0 -S GETS [0 ] 0 -S PUT [0 ] 0 -S Pf_Replacement [0 ] 0 -S DMA_READ [0 ] 0 -S DMA_WRITE [0 ] 0 -S GETF [0 ] 0 - -O GETX [0 ] 0 -O GETS [0 ] 0 -O PUT [0 ] 0 -O Pf_Replacement [0 ] 0 -O DMA_READ [0 ] 0 -O DMA_WRITE [0 ] 0 -O GETF [0 ] 0 - -E GETX [47 ] 47 -E GETS [394 ] 394 -E PUT [0 ] 0 -E DMA_READ [0 ] 0 -E DMA_WRITE [0 ] 0 -E GETF [0 ] 0 - -O_R GETX [0 ] 0 -O_R GETS [0 ] 0 -O_R PUT [0 ] 0 -O_R Pf_Replacement [0 ] 0 -O_R DMA_READ [0 ] 0 -O_R DMA_WRITE [0 ] 0 -O_R Ack [0 ] 0 -O_R All_acks_and_data_no_sharers [0 ] 0 -O_R GETF [0 ] 0 - -S_R GETX [0 ] 0 -S_R GETS [0 ] 0 -S_R PUT [0 ] 0 -S_R Pf_Replacement [0 ] 0 -S_R DMA_READ [0 ] 0 -S_R DMA_WRITE [0 ] 0 -S_R Ack [0 ] 0 -S_R Data [0 ] 0 -S_R All_acks_and_data_no_sharers [0 ] 0 -S_R GETF [0 ] 0 - -NO_R GETX [0 ] 0 -NO_R GETS [0 ] 0 -NO_R PUT [0 ] 0 -NO_R Pf_Replacement [0 ] 0 -NO_R DMA_READ [0 ] 0 -NO_R DMA_WRITE [0 ] 0 -NO_R Ack [0 ] 0 -NO_R Data [0 ] 0 -NO_R Exclusive_Data [0 ] 0 -NO_R All_acks_and_data_no_sharers [0 ] 0 -NO_R GETF [0 ] 0 - -NO_B GETX [0 ] 0 -NO_B GETS [0 ] 0 -NO_B PUT [0 ] 0 -NO_B UnblockS [0 ] 0 -NO_B UnblockM [440 ] 440 -NO_B Pf_Replacement [0 ] 0 -NO_B DMA_READ [0 ] 0 -NO_B DMA_WRITE [0 ] 0 -NO_B GETF [0 ] 0 - -NO_B_X GETX [0 ] 0 -NO_B_X GETS [0 ] 0 -NO_B_X PUT [0 ] 0 -NO_B_X UnblockS [0 ] 0 -NO_B_X UnblockM [0 ] 0 -NO_B_X Pf_Replacement [0 ] 0 -NO_B_X DMA_READ [0 ] 0 -NO_B_X DMA_WRITE [0 ] 0 -NO_B_X GETF [0 ] 0 - -NO_B_S GETX [0 ] 0 -NO_B_S GETS [0 ] 0 -NO_B_S PUT [0 ] 0 -NO_B_S UnblockS [0 ] 0 -NO_B_S UnblockM [0 ] 0 -NO_B_S Pf_Replacement [0 ] 0 -NO_B_S DMA_READ [0 ] 0 -NO_B_S DMA_WRITE [0 ] 0 -NO_B_S GETF [0 ] 0 - -NO_B_S_W GETX [0 ] 0 -NO_B_S_W GETS [0 ] 0 -NO_B_S_W PUT [0 ] 0 -NO_B_S_W UnblockS [0 ] 0 -NO_B_S_W Pf_Replacement [0 ] 0 -NO_B_S_W DMA_READ [0 ] 0 -NO_B_S_W DMA_WRITE [0 ] 0 -NO_B_S_W All_Unblocks [0 ] 0 -NO_B_S_W GETF [0 ] 0 - -O_B GETX [0 ] 0 -O_B GETS [0 ] 0 -O_B PUT [0 ] 0 -O_B UnblockS [0 ] 0 -O_B UnblockM [0 ] 0 -O_B Pf_Replacement [0 ] 0 -O_B DMA_READ [0 ] 0 -O_B DMA_WRITE [0 ] 0 -O_B GETF [0 ] 0 - -NO_B_W GETX [0 ] 0 -NO_B_W GETS [0 ] 0 -NO_B_W PUT [0 ] 0 -NO_B_W UnblockS [0 ] 0 -NO_B_W UnblockM [0 ] 0 -NO_B_W Pf_Replacement [0 ] 0 -NO_B_W DMA_READ [0 ] 0 -NO_B_W DMA_WRITE [0 ] 0 -NO_B_W Memory_Data [441 ] 441 -NO_B_W GETF [0 ] 0 - -O_B_W GETX [0 ] 0 -O_B_W GETS [0 ] 0 -O_B_W PUT [0 ] 0 -O_B_W UnblockS [0 ] 0 -O_B_W Pf_Replacement [0 ] 0 -O_B_W DMA_READ [0 ] 0 -O_B_W DMA_WRITE [0 ] 0 -O_B_W Memory_Data [0 ] 0 -O_B_W GETF [0 ] 0 - -NO_W GETX [0 ] 0 -NO_W GETS [0 ] 0 -NO_W PUT [0 ] 0 -NO_W Pf_Replacement [0 ] 0 -NO_W DMA_READ [0 ] 0 -NO_W DMA_WRITE [0 ] 0 -NO_W Memory_Data [0 ] 0 -NO_W GETF [0 ] 0 - -O_W GETX [0 ] 0 -O_W GETS [0 ] 0 -O_W PUT [0 ] 0 -O_W Pf_Replacement [0 ] 0 -O_W DMA_READ [0 ] 0 -O_W DMA_WRITE [0 ] 0 -O_W Memory_Data [0 ] 0 -O_W GETF [0 ] 0 - -NO_DW_B_W GETX [0 ] 0 -NO_DW_B_W GETS [0 ] 0 -NO_DW_B_W PUT [0 ] 0 -NO_DW_B_W Pf_Replacement [0 ] 0 -NO_DW_B_W DMA_READ [0 ] 0 -NO_DW_B_W DMA_WRITE [0 ] 0 -NO_DW_B_W Ack [0 ] 0 -NO_DW_B_W Data [0 ] 0 -NO_DW_B_W Exclusive_Data [0 ] 0 -NO_DW_B_W All_acks_and_data_no_sharers [0 ] 0 -NO_DW_B_W GETF [0 ] 0 - -NO_DR_B_W GETX [0 ] 0 -NO_DR_B_W GETS [0 ] 0 -NO_DR_B_W PUT [0 ] 0 -NO_DR_B_W Pf_Replacement [0 ] 0 -NO_DR_B_W DMA_READ [0 ] 0 -NO_DR_B_W DMA_WRITE [0 ] 0 -NO_DR_B_W Memory_Data [0 ] 0 -NO_DR_B_W Ack [0 ] 0 -NO_DR_B_W Shared_Ack [0 ] 0 -NO_DR_B_W Shared_Data [0 ] 0 -NO_DR_B_W Data [0 ] 0 -NO_DR_B_W Exclusive_Data [0 ] 0 -NO_DR_B_W GETF [0 ] 0 - -NO_DR_B_D GETX [0 ] 0 -NO_DR_B_D GETS [0 ] 0 -NO_DR_B_D PUT [0 ] 0 -NO_DR_B_D Pf_Replacement [0 ] 0 -NO_DR_B_D DMA_READ [0 ] 0 -NO_DR_B_D DMA_WRITE [0 ] 0 -NO_DR_B_D Ack [0 ] 0 -NO_DR_B_D Shared_Ack [0 ] 0 -NO_DR_B_D Shared_Data [0 ] 0 -NO_DR_B_D Data [0 ] 0 -NO_DR_B_D Exclusive_Data [0 ] 0 -NO_DR_B_D All_acks_and_shared_data [0 ] 0 -NO_DR_B_D All_acks_and_owner_data [0 ] 0 -NO_DR_B_D All_acks_and_data_no_sharers [0 ] 0 -NO_DR_B_D GETF [0 ] 0 - -NO_DR_B GETX [0 ] 0 -NO_DR_B GETS [0 ] 0 -NO_DR_B PUT [0 ] 0 -NO_DR_B Pf_Replacement [0 ] 0 -NO_DR_B DMA_READ [0 ] 0 -NO_DR_B DMA_WRITE [0 ] 0 -NO_DR_B Ack [0 ] 0 -NO_DR_B Shared_Ack [0 ] 0 -NO_DR_B Shared_Data [0 ] 0 -NO_DR_B Data [0 ] 0 -NO_DR_B Exclusive_Data [0 ] 0 -NO_DR_B All_acks_and_shared_data [0 ] 0 -NO_DR_B All_acks_and_owner_data [0 ] 0 -NO_DR_B All_acks_and_data_no_sharers [0 ] 0 -NO_DR_B GETF [0 ] 0 - -NO_DW_W GETX [0 ] 0 -NO_DW_W GETS [0 ] 0 -NO_DW_W PUT [0 ] 0 -NO_DW_W Pf_Replacement [0 ] 0 -NO_DW_W DMA_READ [0 ] 0 -NO_DW_W DMA_WRITE [0 ] 0 -NO_DW_W Memory_Ack [0 ] 0 -NO_DW_W GETF [0 ] 0 - -O_DR_B_W GETX [0 ] 0 -O_DR_B_W GETS [0 ] 0 -O_DR_B_W PUT [0 ] 0 -O_DR_B_W Pf_Replacement [0 ] 0 -O_DR_B_W DMA_READ [0 ] 0 -O_DR_B_W DMA_WRITE [0 ] 0 -O_DR_B_W Memory_Data [0 ] 0 -O_DR_B_W Ack [0 ] 0 -O_DR_B_W Shared_Ack [0 ] 0 -O_DR_B_W GETF [0 ] 0 - -O_DR_B GETX [0 ] 0 -O_DR_B GETS [0 ] 0 -O_DR_B PUT [0 ] 0 -O_DR_B Pf_Replacement [0 ] 0 -O_DR_B DMA_READ [0 ] 0 -O_DR_B DMA_WRITE [0 ] 0 -O_DR_B Ack [0 ] 0 -O_DR_B Shared_Ack [0 ] 0 -O_DR_B All_acks_and_owner_data [0 ] 0 -O_DR_B All_acks_and_data_no_sharers [0 ] 0 -O_DR_B GETF [0 ] 0 - -WB GETX [4 ] 4 -WB GETS [14 ] 14 -WB PUT [0 ] 0 -WB Unblock [0 ] 0 -WB Writeback_Clean [0 ] 0 -WB Writeback_Dirty [0 ] 0 -WB Writeback_Exclusive_Clean [344 ] 344 -WB Writeback_Exclusive_Dirty [81 ] 81 -WB Pf_Replacement [0 ] 0 -WB DMA_READ [0 ] 0 -WB DMA_WRITE [0 ] 0 -WB GETF [0 ] 0 - -WB_O_W GETX [0 ] 0 -WB_O_W GETS [0 ] 0 -WB_O_W PUT [0 ] 0 -WB_O_W Pf_Replacement [0 ] 0 -WB_O_W DMA_READ [0 ] 0 -WB_O_W DMA_WRITE [0 ] 0 -WB_O_W Memory_Ack [0 ] 0 -WB_O_W GETF [0 ] 0 - -WB_E_W GETX [2 ] 2 -WB_E_W GETS [2 ] 2 -WB_E_W PUT [0 ] 0 -WB_E_W Pf_Replacement [0 ] 0 -WB_E_W DMA_READ [0 ] 0 -WB_E_W DMA_WRITE [0 ] 0 -WB_E_W Memory_Ack [81 ] 81 -WB_E_W GETF [0 ] 0 - -NO_F GETX [0 ] 0 -NO_F GETS [0 ] 0 -NO_F PUT [0 ] 0 -NO_F UnblockM [0 ] 0 -NO_F Pf_Replacement [0 ] 0 -NO_F GETF [0 ] 0 -NO_F PUTF [0 ] 0 - -NO_F_W GETX [0 ] 0 -NO_F_W GETS [0 ] 0 -NO_F_W PUT [0 ] 0 -NO_F_W Pf_Replacement [0 ] 0 -NO_F_W DMA_READ [0 ] 0 -NO_F_W DMA_WRITE [0 ] 0 -NO_F_W Memory_Data [0 ] 0 -NO_F_W GETF [0 ] 0 - diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simerr b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simerr deleted file mode 100755 index 31ae36f2e..000000000 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simerr +++ /dev/null @@ -1,3 +0,0 @@ -warn: Sockets disabled, not accepting gdb connections -warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...) -hack: be nice to actually delete the event here diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simout b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simout deleted file mode 100755 index 20c68eff3..000000000 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simout +++ /dev/null @@ -1,12 +0,0 @@ -gem5 Simulator System. http://gem5.org -gem5 is copyrighted software; use the --copyright option for details. - -gem5 compiled Jan 23 2012 03:42:19 -gem5 started Jan 23 2012 04:21:49 -gem5 executing on zizzer -command line: build/ALPHA_SE_MOESI_hammer/gem5.opt -d build/ALPHA_SE_MOESI_hammer/tests/opt/quick/00.hello/alpha/tru64/simple-timing-ruby-MOESI_hammer -re tests/run.py build/ALPHA_SE_MOESI_hammer/tests/opt/quick/00.hello/alpha/tru64/simple-timing-ruby-MOESI_hammer -Global frequency set at 1000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -info: Increasing stack size by one page. -Hello world! -Exiting @ tick 78448 because target called exit() diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt deleted file mode 100644 index 5c579e1af..000000000 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt +++ /dev/null @@ -1,77 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 0.000078 # Number of seconds simulated -sim_ticks 78448 # Number of ticks simulated -final_tick 78448 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 29294 # Simulator instruction rate (inst/s) -host_tick_rate 891567 # Simulator tick rate (ticks/s) -host_mem_usage 215964 # Number of bytes of host memory used -host_seconds 0.09 # Real time elapsed on the host -sim_insts 2577 # Number of instructions simulated -system.physmem.bytes_read 13356 # Number of bytes read from this memory -system.physmem.bytes_inst_read 10340 # Number of instructions bytes read from this memory -system.physmem.bytes_written 2058 # Number of bytes written to this memory -system.physmem.num_reads 3000 # Number of read requests responded to by this memory -system.physmem.num_writes 294 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 170252906 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 131807057 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 26233938 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 196486845 # Total bandwidth to/from this memory (bytes/s) -system.cpu.dtb.fetch_hits 0 # ITB hits -system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.fetch_acv 0 # ITB acv -system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 415 # DTB read hits -system.cpu.dtb.read_misses 4 # DTB read misses -system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 419 # DTB read accesses -system.cpu.dtb.write_hits 294 # DTB write hits -system.cpu.dtb.write_misses 4 # DTB write misses -system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 298 # DTB write accesses -system.cpu.dtb.data_hits 709 # DTB hits -system.cpu.dtb.data_misses 8 # DTB misses -system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 717 # DTB accesses -system.cpu.itb.fetch_hits 2586 # ITB hits -system.cpu.itb.fetch_misses 11 # ITB misses -system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 2597 # ITB accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.read_acv 0 # DTB read access violations -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.write_acv 0 # DTB write access violations -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.data_hits 0 # DTB hits -system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.data_acv 0 # DTB access violations -system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.workload.num_syscalls 4 # Number of system calls -system.cpu.numCycles 78448 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.num_insts 2577 # Number of instructions executed -system.cpu.num_int_alu_accesses 2375 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 6 # Number of float alu accesses -system.cpu.num_func_calls 140 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 238 # number of instructions that are conditional controls -system.cpu.num_int_insts 2375 # number of integer instructions -system.cpu.num_fp_insts 6 # number of float instructions -system.cpu.num_int_register_reads 2998 # number of times the integer registers were read -system.cpu.num_int_register_writes 1768 # number of times the integer registers were written -system.cpu.num_fp_register_reads 6 # number of times the floating registers were read -system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_mem_refs 717 # number of memory refs -system.cpu.num_load_insts 419 # Number of load instructions -system.cpu.num_store_insts 298 # Number of store instructions -system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 78448 # Number of busy cycles -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.idle_fraction 0 # Percentage of idle cycles - ----------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/config.ini b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/config.ini deleted file mode 100644 index 2d5b16f7e..000000000 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/config.ini +++ /dev/null @@ -1,268 +0,0 @@ -[root] -type=Root -children=system -time_sync_enable=false -time_sync_period=100000000 -time_sync_spin_threshold=100000 - -[system] -type=System -children=cpu dir_cntrl0 l1_cntrl0 physmem ruby sys_port_proxy -mem_mode=timing -memories=system.physmem -num_work_ids=16 -physmem=system.physmem -work_begin_ckpt_count=0 -work_begin_cpu_id_exit=-1 -work_begin_exit_count=0 -work_cpus_ckpt_count=0 -work_end_ckpt_count=0 -work_end_exit_count=0 -work_item_id=-1 -system_port=system.sys_port_proxy.port[0] - -[system.cpu] -type=TimingSimpleCPU -children=dtb itb tracer workload -checker=Null -clock=1 -cpu_id=0 -defer_registration=false -do_checkpoint_insts=true -do_statistics_insts=true -dtb=system.cpu.dtb -function_trace=false -function_trace_start=0 -itb=system.cpu.itb -max_insts_all_threads=0 -max_insts_any_thread=0 -max_loads_all_threads=0 -max_loads_any_thread=0 -numThreads=1 -phase=0 -progress_interval=0 -system=system -tracer=system.cpu.tracer -workload=system.cpu.workload -dcache_port=system.l1_cntrl0.sequencer.port[1] -icache_port=system.l1_cntrl0.sequencer.port[0] - -[system.cpu.dtb] -type=AlphaTLB -size=64 - -[system.cpu.itb] -type=AlphaTLB -size=48 - -[system.cpu.tracer] -type=ExeTracer - -[system.cpu.workload] -type=LiveProcess -cmd=hello -cwd= -egid=100 -env= -errout=cerr -euid=100 -executable=/dist/m5/regression/test-progs/hello/bin/alpha/tru64/hello -gid=100 -input=cin -max_stack_size=67108864 -output=cout -pid=100 -ppid=99 -simpoint=0 -system=system -uid=100 - -[system.dir_cntrl0] -type=Directory_Controller -children=directory memBuffer -buffer_size=0 -cntrl_id=1 -directory=system.dir_cntrl0.directory -directory_latency=12 -memBuffer=system.dir_cntrl0.memBuffer -number_of_TBEs=256 -recycle_latency=10 -ruby_system=system.ruby -transitions_per_cycle=32 -version=0 - -[system.dir_cntrl0.directory] -type=RubyDirectoryMemory -map_levels=4 -numa_high_bit=6 -size=134217728 -use_map=false -version=0 - -[system.dir_cntrl0.memBuffer] -type=RubyMemoryControl -bank_bit_0=8 -bank_busy_time=11 -bank_queue_size=12 -banks_per_rank=8 -basic_bus_busy_time=2 -dimm_bit_0=12 -dimms_per_channel=2 -mem_bus_cycle_multiplier=10 -mem_ctl_latency=12 -mem_fixed_delay=0 -mem_random_arbitrate=0 -rank_bit_0=11 -rank_rank_delay=1 -ranks_per_dimm=2 -read_write_delay=2 -refresh_period=1560 -tFaw=0 -version=0 - -[system.l1_cntrl0] -type=L1Cache_Controller -children=cacheMemory sequencer -buffer_size=0 -cacheMemory=system.l1_cntrl0.cacheMemory -cache_response_latency=12 -cntrl_id=0 -issue_latency=2 -number_of_TBEs=256 -recycle_latency=10 -ruby_system=system.ruby -sequencer=system.l1_cntrl0.sequencer -transitions_per_cycle=32 -version=0 - -[system.l1_cntrl0.cacheMemory] -type=RubyCache -assoc=2 -is_icache=false -latency=3 -replacement_policy=PSEUDO_LRU -size=256 -start_index_bit=6 - -[system.l1_cntrl0.sequencer] -type=RubySequencer -access_phys_mem=true -dcache=system.l1_cntrl0.cacheMemory -deadlock_threshold=500000 -icache=system.l1_cntrl0.cacheMemory -max_outstanding_requests=16 -physmem=system.physmem -ruby_system=system.ruby -using_network_tester=false -using_ruby_tester=false -version=0 -physMemPort=system.physmem.port[0] -port=system.cpu.icache_port system.cpu.dcache_port - -[system.physmem] -type=PhysicalMemory -file= -latency=30 -latency_var=0 -null=false -range=0:134217727 -zero=false -port=system.l1_cntrl0.sequencer.physMemPort system.sys_port_proxy.physMemPort - -[system.ruby] -type=RubySystem -children=network profiler -block_size_bytes=64 -clock=1 -mem_size=134217728 -no_mem_vec=false -random_seed=1234 -randomization=false -stats_filename=ruby.stats - -[system.ruby.network] -type=SimpleNetwork -children=topology -adaptive_routing=false -buffer_size=0 -control_msg_size=8 -endpoint_bandwidth=1000 -number_of_virtual_networks=10 -ruby_system=system.ruby -topology=system.ruby.network.topology - -[system.ruby.network.topology] -type=Topology -children=ext_links0 ext_links1 int_links0 int_links1 routers0 routers1 routers2 -description=Crossbar -ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1 -int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1 -print_config=false -routers=system.ruby.network.topology.routers0 system.ruby.network.topology.routers1 system.ruby.network.topology.routers2 - -[system.ruby.network.topology.ext_links0] -type=SimpleExtLink -bandwidth_factor=16 -ext_node=system.l1_cntrl0 -int_node=system.ruby.network.topology.routers0 -latency=1 -link_id=0 -weight=1 - -[system.ruby.network.topology.ext_links1] -type=SimpleExtLink -bandwidth_factor=16 -ext_node=system.dir_cntrl0 -int_node=system.ruby.network.topology.routers1 -latency=1 -link_id=1 -weight=1 - -[system.ruby.network.topology.int_links0] -type=SimpleIntLink -bandwidth_factor=16 -latency=1 -link_id=2 -node_a=system.ruby.network.topology.routers0 -node_b=system.ruby.network.topology.routers2 -weight=1 - -[system.ruby.network.topology.int_links1] -type=SimpleIntLink -bandwidth_factor=16 -latency=1 -link_id=3 -node_a=system.ruby.network.topology.routers1 -node_b=system.ruby.network.topology.routers2 -weight=1 - -[system.ruby.network.topology.routers0] -type=BasicRouter -router_id=0 - -[system.ruby.network.topology.routers1] -type=BasicRouter -router_id=1 - -[system.ruby.network.topology.routers2] -type=BasicRouter -router_id=2 - -[system.ruby.profiler] -type=RubyProfiler -all_instructions=false -hot_lines=false -num_of_sequencers=1 -ruby_system=system.ruby - -[system.sys_port_proxy] -type=RubyPortProxy -access_phys_mem=true -physmem=system.physmem -ruby_system=system.ruby -using_network_tester=false -using_ruby_tester=false -version=0 -physMemPort=system.physmem.port[1] -port=system.system_port - diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/ruby.stats b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/ruby.stats deleted file mode 100644 index 2c26f3344..000000000 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/ruby.stats +++ /dev/null @@ -1,311 +0,0 @@ - -================ Begin RubySystem Configuration Print ================ - -RubySystem config: - random_seed: 1234 - randomization: 0 - cycle_period: 1 - block_size_bytes: 64 - block_size_bits: 6 - memory_size_bytes: 134217728 - memory_size_bits: 27 - -Network Configuration ---------------------- -network: SIMPLE_NETWORK -topology: - -virtual_net_0: active, ordered -virtual_net_1: active, ordered -virtual_net_2: active, ordered -virtual_net_3: active, ordered -virtual_net_4: active, ordered -virtual_net_5: inactive -virtual_net_6: inactive -virtual_net_7: inactive -virtual_net_8: inactive -virtual_net_9: inactive - - -Profiler Configuration ----------------------- -periodic_stats_period: 1000000 - -================ End RubySystem Configuration Print ================ - - -Real time: Jan/23/2012 04:59:27 - -Profiler Stats --------------- -Elapsed_time_in_seconds: 0 -Elapsed_time_in_minutes: 0 -Elapsed_time_in_hours: 0 -Elapsed_time_in_days: 0 - -Virtual_time_in_seconds: 0.24 -Virtual_time_in_minutes: 0.004 -Virtual_time_in_hours: 6.66667e-05 -Virtual_time_in_days: 2.77778e-06 - -Ruby_current_time: 123378 -Ruby_start_time: 0 -Ruby_cycles: 123378 - -mbytes_resident: 42.25 -mbytes_total: 211.328 -resident_ratio: 0.199926 - -ruby_cycles_executed: [ 123379 ] - -Busy Controller Counts: -L1Cache-0:0 -Directory-0:0 - - -Busy Bank Count:0 - -sequencer_requests_outstanding: [binsize: 1 max: 1 count: 3295 average: 1 | standard deviation: 0 | 0 3295 ] - -All Non-Zero Cycle Demand Cache Accesses ----------------------------------------- -miss_latency: [binsize: 2 max: 375 count: 3294 average: 36.4554 | standard deviation: 69.7725 | 0 2668 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 2 0 0 0 3 1 1 4 2 101 88 63 177 126 0 1 1 8 0 2 1 1 4 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7 4 5 13 2 0 0 0 1 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 ] -miss_latency_LD: [binsize: 2 max: 281 count: 415 average: 107.304 | standard deviation: 88.8453 | 0 170 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 1 0 2 0 56 24 27 75 32 0 0 1 3 0 1 0 0 2 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5 0 4 7 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_ST: [binsize: 2 max: 265 count: 294 average: 53.2585 | standard deviation: 80.456 | 0 210 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 14 11 7 31 12 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_IFETCH: [binsize: 2 max: 375 count: 2585 average: 23.1702 | standard deviation: 56.4841 | 0 2288 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 2 0 0 2 2 31 53 29 71 82 0 1 0 5 0 1 1 1 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 2 1 3 2 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ] -miss_latency_L1Cache: [binsize: 1 max: 3 count: 2668 average: 3 | standard deviation: 0 | 0 0 0 2668 ] -miss_latency_Directory: [binsize: 2 max: 375 count: 626 average: 179.042 | standard deviation: 22.5462 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 2 0 0 0 3 1 1 4 2 101 88 63 177 126 0 1 1 8 0 2 1 1 4 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7 4 5 13 2 0 0 0 1 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 ] -miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] -miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] -miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] -miss_latency_wCC_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] -imcomplete_wCC_Times: 0 -miss_latency_dir_issue_to_initial_request: [binsize: 1 max: 0 count: 1 average: 0 | standard deviation: 0 | 1 ] -miss_latency_dir_initial_forward_request: [binsize: 1 max: 0 count: 1 average: 0 | standard deviation: 0 | 1 ] -miss_latency_dir_forward_to_first_response: [binsize: 1 max: 0 count: 1 average: 0 | standard deviation: 0 | 1 ] -miss_latency_dir_first_response_to_completion: [binsize: 1 max: 159 count: 1 average: 159 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ] -imcomplete_dir_Times: 625 -miss_latency_LD_L1Cache: [binsize: 1 max: 3 count: 170 average: 3 | standard deviation: 0 | 0 0 0 170 ] -miss_latency_LD_Directory: [binsize: 2 max: 281 count: 245 average: 179.678 | standard deviation: 23.5327 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 1 0 2 0 56 24 27 75 32 0 0 1 3 0 1 0 0 2 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5 0 4 7 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_ST_L1Cache: [binsize: 1 max: 3 count: 210 average: 3 | standard deviation: 0 | 0 0 0 210 ] -miss_latency_ST_Directory: [binsize: 2 max: 265 count: 84 average: 178.905 | standard deviation: 21.977 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 14 11 7 31 12 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_IFETCH_L1Cache: [binsize: 1 max: 3 count: 2288 average: 3 | standard deviation: 0 | 0 0 0 2288 ] -miss_latency_IFETCH_Directory: [binsize: 2 max: 375 count: 297 average: 178.556 | standard deviation: 21.9279 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 2 0 0 2 2 31 53 29 71 82 0 1 0 5 0 1 1 1 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 2 1 3 2 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ] - -All Non-Zero Cycle SW Prefetch Requests ------------------------------------- -prefetch_latency: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] -prefetch_latency_L2Miss:[binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] -Request vs. RubySystem State Profile --------------------------------- - - -filter_action: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - -Message Delayed Cycles ----------------------- -Total_delay_cycles: [binsize: 1 max: 0 count: 1248 average: 0 | standard deviation: 0 | 1248 ] -Total_nonPF_delay_cycles: [binsize: 1 max: 0 count: 1248 average: 0 | standard deviation: 0 | 1248 ] - virtual_network_0_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - virtual_network_1_delay_cycles: [binsize: 1 max: 0 count: 626 average: 0 | standard deviation: 0 | 626 ] - virtual_network_2_delay_cycles: [binsize: 1 max: 0 count: 622 average: 0 | standard deviation: 0 | 622 ] - virtual_network_3_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - virtual_network_4_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - virtual_network_5_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - virtual_network_6_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - virtual_network_7_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - virtual_network_8_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - virtual_network_9_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - -Resource Usage --------------- -page_size: 4096 -user_time: 0 -system_time: 0 -page_reclaims: 11154 -page_faults: 0 -swaps: 0 -block_inputs: 0 -block_outputs: 88 - -Network Stats -------------- - -total_msg_count_Control: 1878 15024 -total_msg_count_Data: 1866 134352 -total_msg_count_Response_Data: 1878 135216 -total_msg_count_Writeback_Control: 1866 14928 -total_msgs: 7488 total_bytes: 299520 - -switch_0_inlinks: 2 -switch_0_outlinks: 2 -links_utilized_percent_switch_0: 2.52881 - links_utilized_percent_switch_0_link_0: 2.5353 bw: 16000 base_latency: 1 - links_utilized_percent_switch_0_link_1: 2.52233 bw: 16000 base_latency: 1 - - outgoing_messages_switch_0_link_0_Response_Data: 626 45072 [ 0 0 0 0 626 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_0_Writeback_Control: 622 4976 [ 0 0 0 622 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Control: 626 5008 [ 0 0 626 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Data: 622 44784 [ 0 0 622 0 0 0 0 0 0 0 ] base_latency: 1 - -switch_1_inlinks: 2 -switch_1_outlinks: 2 -links_utilized_percent_switch_1: 2.52881 - links_utilized_percent_switch_1_link_0: 2.52233 bw: 16000 base_latency: 1 - links_utilized_percent_switch_1_link_1: 2.5353 bw: 16000 base_latency: 1 - - outgoing_messages_switch_1_link_0_Control: 626 5008 [ 0 0 626 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_0_Data: 622 44784 [ 0 0 622 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_Response_Data: 626 45072 [ 0 0 0 0 626 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_Writeback_Control: 622 4976 [ 0 0 0 622 0 0 0 0 0 0 ] base_latency: 1 - -switch_2_inlinks: 2 -switch_2_outlinks: 2 -links_utilized_percent_switch_2: 2.52881 - links_utilized_percent_switch_2_link_0: 2.5353 bw: 16000 base_latency: 1 - links_utilized_percent_switch_2_link_1: 2.52233 bw: 16000 base_latency: 1 - - outgoing_messages_switch_2_link_0_Response_Data: 626 45072 [ 0 0 0 0 626 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_0_Writeback_Control: 622 4976 [ 0 0 0 622 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_1_Control: 626 5008 [ 0 0 626 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_1_Data: 622 44784 [ 0 0 622 0 0 0 0 0 0 0 ] base_latency: 1 - -Cache Stats: system.l1_cntrl0.cacheMemory - system.l1_cntrl0.cacheMemory_total_misses: 626 - system.l1_cntrl0.cacheMemory_total_demand_misses: 626 - system.l1_cntrl0.cacheMemory_total_prefetches: 0 - system.l1_cntrl0.cacheMemory_total_sw_prefetches: 0 - system.l1_cntrl0.cacheMemory_total_hw_prefetches: 0 - - system.l1_cntrl0.cacheMemory_request_type_LD: 39.1374% - system.l1_cntrl0.cacheMemory_request_type_ST: 13.4185% - system.l1_cntrl0.cacheMemory_request_type_IFETCH: 47.4441% - - system.l1_cntrl0.cacheMemory_access_mode_type_Supervisor: 626 100% - - --- L1Cache --- - - Event Counts - -Load [415 ] 415 -Ifetch [2585 ] 2585 -Store [294 ] 294 -Data [626 ] 626 -Fwd_GETX [0 ] 0 -Inv [0 ] 0 -Replacement [622 ] 622 -Writeback_Ack [622 ] 622 -Writeback_Nack [0 ] 0 - - - Transitions - -I Load [245 ] 245 -I Ifetch [297 ] 297 -I Store [84 ] 84 -I Inv [0 ] 0 -I Replacement [0 ] 0 - -II Writeback_Nack [0 ] 0 - -M Load [170 ] 170 -M Ifetch [2288 ] 2288 -M Store [210 ] 210 -M Fwd_GETX [0 ] 0 -M Inv [0 ] 0 -M Replacement [622 ] 622 - -MI Fwd_GETX [0 ] 0 -MI Inv [0 ] 0 -MI Writeback_Ack [622 ] 622 -MI Writeback_Nack [0 ] 0 - -MII Fwd_GETX [0 ] 0 - -IS Data [542 ] 542 - -IM Data [84 ] 84 - -Memory controller: system.dir_cntrl0.memBuffer: - memory_total_requests: 1248 - memory_reads: 626 - memory_writes: 622 - memory_refreshes: 258 - memory_total_request_delays: 1502 - memory_delays_per_request: 1.20353 - memory_delays_in_input_queue: 414 - memory_delays_behind_head_of_bank_queue: 3 - memory_delays_stalled_at_head_of_bank_queue: 1085 - memory_stalls_for_bank_busy: 404 - memory_stalls_for_random_busy: 0 - memory_stalls_for_anti_starvation: 0 - memory_stalls_for_arbitration: 39 - memory_stalls_for_bus: 620 - memory_stalls_for_tfaw: 0 - memory_stalls_for_read_write_turnaround: 22 - memory_stalls_for_read_read_turnaround: 0 - accesses_per_bank: 55 40 0 100 42 42 88 45 14 10 14 10 46 82 38 6 22 14 14 48 20 52 26 92 34 10 12 24 28 44 38 138 - - --- Directory --- - - Event Counts - -GETX [626 ] 626 -GETS [0 ] 0 -PUTX [622 ] 622 -PUTX_NotOwner [0 ] 0 -DMA_READ [0 ] 0 -DMA_WRITE [0 ] 0 -Memory_Data [626 ] 626 -Memory_Ack [622 ] 622 - - - Transitions - -I GETX [626 ] 626 -I PUTX_NotOwner [0 ] 0 -I DMA_READ [0 ] 0 -I DMA_WRITE [0 ] 0 - -M GETX [0 ] 0 -M PUTX [622 ] 622 -M PUTX_NotOwner [0 ] 0 -M DMA_READ [0 ] 0 -M DMA_WRITE [0 ] 0 - -M_DRD GETX [0 ] 0 -M_DRD PUTX [0 ] 0 - -M_DWR GETX [0 ] 0 -M_DWR PUTX [0 ] 0 - -M_DWRI GETX [0 ] 0 -M_DWRI Memory_Ack [0 ] 0 - -M_DRDI GETX [0 ] 0 -M_DRDI Memory_Ack [0 ] 0 - -IM GETX [0 ] 0 -IM GETS [0 ] 0 -IM PUTX [0 ] 0 -IM PUTX_NotOwner [0 ] 0 -IM DMA_READ [0 ] 0 -IM DMA_WRITE [0 ] 0 -IM Memory_Data [626 ] 626 - -MI GETX [0 ] 0 -MI GETS [0 ] 0 -MI PUTX [0 ] 0 -MI PUTX_NotOwner [0 ] 0 -MI DMA_READ [0 ] 0 -MI DMA_WRITE [0 ] 0 -MI Memory_Ack [622 ] 622 - -ID GETX [0 ] 0 -ID GETS [0 ] 0 -ID PUTX [0 ] 0 -ID PUTX_NotOwner [0 ] 0 -ID DMA_READ [0 ] 0 -ID DMA_WRITE [0 ] 0 -ID Memory_Data [0 ] 0 - -ID_W GETX [0 ] 0 -ID_W GETS [0 ] 0 -ID_W PUTX [0 ] 0 -ID_W PUTX_NotOwner [0 ] 0 -ID_W DMA_READ [0 ] 0 -ID_W DMA_WRITE [0 ] 0 -ID_W Memory_Ack [0 ] 0 - diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/simerr b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/simerr deleted file mode 100755 index 31ae36f2e..000000000 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/simerr +++ /dev/null @@ -1,3 +0,0 @@ -warn: Sockets disabled, not accepting gdb connections -warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...) -hack: be nice to actually delete the event here diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/simout b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/simout deleted file mode 100755 index af1c56980..000000000 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/simout +++ /dev/null @@ -1,12 +0,0 @@ -gem5 Simulator System. http://gem5.org -gem5 is copyrighted software; use the --copyright option for details. - -gem5 compiled Jan 23 2012 04:48:33 -gem5 started Jan 23 2012 04:59:27 -gem5 executing on zizzer -command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/tru64/simple-timing-ruby -re tests/run.py build/ALPHA_SE/tests/opt/quick/00.hello/alpha/tru64/simple-timing-ruby -Global frequency set at 1000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -info: Increasing stack size by one page. -Hello world! -Exiting @ tick 123378 because target called exit() diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt deleted file mode 100644 index bcff12bb9..000000000 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt +++ /dev/null @@ -1,77 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 0.000123 # Number of seconds simulated -sim_ticks 123378 # Number of ticks simulated -final_tick 123378 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 44691 # Simulator instruction rate (inst/s) -host_tick_rate 2138947 # Simulator tick rate (ticks/s) -host_mem_usage 216404 # Number of bytes of host memory used -host_seconds 0.06 # Real time elapsed on the host -sim_insts 2577 # Number of instructions simulated -system.physmem.bytes_read 13356 # Number of bytes read from this memory -system.physmem.bytes_inst_read 10340 # Number of instructions bytes read from this memory -system.physmem.bytes_written 2058 # Number of bytes written to this memory -system.physmem.num_reads 3000 # Number of read requests responded to by this memory -system.physmem.num_writes 294 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 108252687 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 83807486 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 16680445 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 124933132 # Total bandwidth to/from this memory (bytes/s) -system.cpu.dtb.fetch_hits 0 # ITB hits -system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.fetch_acv 0 # ITB acv -system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 415 # DTB read hits -system.cpu.dtb.read_misses 4 # DTB read misses -system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 419 # DTB read accesses -system.cpu.dtb.write_hits 294 # DTB write hits -system.cpu.dtb.write_misses 4 # DTB write misses -system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 298 # DTB write accesses -system.cpu.dtb.data_hits 709 # DTB hits -system.cpu.dtb.data_misses 8 # DTB misses -system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 717 # DTB accesses -system.cpu.itb.fetch_hits 2586 # ITB hits -system.cpu.itb.fetch_misses 11 # ITB misses -system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 2597 # ITB accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.read_acv 0 # DTB read access violations -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.write_acv 0 # DTB write access violations -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.data_hits 0 # DTB hits -system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.data_acv 0 # DTB access violations -system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.workload.num_syscalls 4 # Number of system calls -system.cpu.numCycles 123378 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.num_insts 2577 # Number of instructions executed -system.cpu.num_int_alu_accesses 2375 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 6 # Number of float alu accesses -system.cpu.num_func_calls 140 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 238 # number of instructions that are conditional controls -system.cpu.num_int_insts 2375 # number of integer instructions -system.cpu.num_fp_insts 6 # number of float instructions -system.cpu.num_int_register_reads 2998 # number of times the integer registers were read -system.cpu.num_int_register_writes 1768 # number of times the integer registers were written -system.cpu.num_fp_register_reads 6 # number of times the floating registers were read -system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_mem_refs 717 # number of memory refs -system.cpu.num_load_insts 419 # Number of load instructions -system.cpu.num_store_insts 298 # Number of store instructions -system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 123378 # Number of busy cycles -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.idle_fraction 0 # Percentage of idle cycles - ----------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini deleted file mode 100644 index 72df69882..000000000 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini +++ /dev/null @@ -1,205 +0,0 @@ -[root] -type=Root -children=system -time_sync_enable=false -time_sync_period=100000000000 -time_sync_spin_threshold=100000000 - -[system] -type=System -children=cpu membus physmem -mem_mode=atomic -memories=system.physmem -num_work_ids=16 -physmem=system.physmem -work_begin_ckpt_count=0 -work_begin_cpu_id_exit=-1 -work_begin_exit_count=0 -work_cpus_ckpt_count=0 -work_end_ckpt_count=0 -work_end_exit_count=0 -work_item_id=-1 -system_port=system.membus.port[0] - -[system.cpu] -type=TimingSimpleCPU -children=dcache dtb icache itb l2cache toL2Bus tracer workload -checker=Null -clock=500 -cpu_id=0 -defer_registration=false -do_checkpoint_insts=true -do_statistics_insts=true -dtb=system.cpu.dtb -function_trace=false -function_trace_start=0 -itb=system.cpu.itb -max_insts_all_threads=0 -max_insts_any_thread=0 -max_loads_all_threads=0 -max_loads_any_thread=0 -numThreads=1 -phase=0 -progress_interval=0 -system=system -tracer=system.cpu.tracer -workload=system.cpu.workload -dcache_port=system.cpu.dcache.cpu_side -icache_port=system.cpu.icache.cpu_side - -[system.cpu.dcache] -type=BaseCache -addr_range=0:18446744073709551615 -assoc=2 -block_size=64 -forward_snoops=true -hash_delay=1 -is_top_level=true -latency=1000 -max_miss_count=0 -mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 -prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 -prioritizeRequests=false -repl=Null -size=262144 -subblock_size=0 -tgts_per_mshr=5 -trace_addr=0 -two_queue=false -write_buffers=8 -cpu_side=system.cpu.dcache_port -mem_side=system.cpu.toL2Bus.port[1] - -[system.cpu.dtb] -type=AlphaTLB -size=64 - -[system.cpu.icache] -type=BaseCache -addr_range=0:18446744073709551615 -assoc=2 -block_size=64 -forward_snoops=true -hash_delay=1 -is_top_level=true -latency=1000 -max_miss_count=0 -mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 -prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 -prioritizeRequests=false -repl=Null -size=131072 -subblock_size=0 -tgts_per_mshr=5 -trace_addr=0 -two_queue=false -write_buffers=8 -cpu_side=system.cpu.icache_port -mem_side=system.cpu.toL2Bus.port[0] - -[system.cpu.itb] -type=AlphaTLB -size=48 - -[system.cpu.l2cache] -type=BaseCache -addr_range=0:18446744073709551615 -assoc=2 -block_size=64 -forward_snoops=true -hash_delay=1 -is_top_level=false -latency=10000 -max_miss_count=0 -mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=100000 -prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 -prioritizeRequests=false -repl=Null -size=2097152 -subblock_size=0 -tgts_per_mshr=5 -trace_addr=0 -two_queue=false -write_buffers=8 -cpu_side=system.cpu.toL2Bus.port[2] -mem_side=system.membus.port[2] - -[system.cpu.toL2Bus] -type=Bus -block_size=64 -bus_id=0 -clock=1000 -header_cycles=1 -use_default_range=false -width=64 -port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side - -[system.cpu.tracer] -type=ExeTracer - -[system.cpu.workload] -type=LiveProcess -cmd=hello -cwd= -egid=100 -env= -errout=cerr -euid=100 -executable=/dist/m5/regression/test-progs/hello/bin/alpha/tru64/hello -gid=100 -input=cin -max_stack_size=67108864 -output=cout -pid=100 -ppid=99 -simpoint=0 -system=system -uid=100 - -[system.membus] -type=Bus -block_size=64 -bus_id=0 -clock=1000 -header_cycles=1 -use_default_range=false -width=64 -port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side - -[system.physmem] -type=PhysicalMemory -file= -latency=30000 -latency_var=0 -null=false -range=0:134217727 -zero=false -port=system.membus.port[1] - diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/simerr b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/simerr deleted file mode 100755 index 31ae36f2e..000000000 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/simerr +++ /dev/null @@ -1,3 +0,0 @@ -warn: Sockets disabled, not accepting gdb connections -warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...) -hack: be nice to actually delete the event here diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/simout b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/simout deleted file mode 100755 index 6a994fb76..000000000 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/simout +++ /dev/null @@ -1,12 +0,0 @@ -gem5 Simulator System. http://gem5.org -gem5 is copyrighted software; use the --copyright option for details. - -gem5 compiled Jan 23 2012 04:48:33 -gem5 started Jan 23 2012 04:59:27 -gem5 executing on zizzer -command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/opt/quick/00.hello/alpha/tru64/simple-timing -Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -info: Increasing stack size by one page. -Hello world! -Exiting @ tick 16769000 because target called exit() diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stats.txt b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stats.txt deleted file mode 100644 index e3a7a00a0..000000000 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stats.txt +++ /dev/null @@ -1,259 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 0.000017 # Number of seconds simulated -sim_ticks 16769000 # Number of ticks simulated -final_tick 16769000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 297044 # Simulator instruction rate (inst/s) -host_tick_rate 1928782837 # Simulator tick rate (ticks/s) -host_mem_usage 206044 # Number of bytes of host memory used -host_seconds 0.01 # Real time elapsed on the host -sim_insts 2577 # Number of instructions simulated -system.physmem.bytes_read 15680 # Number of bytes read from this memory -system.physmem.bytes_inst_read 10432 # Number of instructions bytes read from this memory -system.physmem.bytes_written 0 # Number of bytes written to this memory -system.physmem.num_reads 245 # Number of read requests responded to by this memory -system.physmem.num_writes 0 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 935058739 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 622100304 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total 935058739 # Total bandwidth to/from this memory (bytes/s) -system.cpu.dtb.fetch_hits 0 # ITB hits -system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.fetch_acv 0 # ITB acv -system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 415 # DTB read hits -system.cpu.dtb.read_misses 4 # DTB read misses -system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 419 # DTB read accesses -system.cpu.dtb.write_hits 294 # DTB write hits -system.cpu.dtb.write_misses 4 # DTB write misses -system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 298 # DTB write accesses -system.cpu.dtb.data_hits 709 # DTB hits -system.cpu.dtb.data_misses 8 # DTB misses -system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 717 # DTB accesses -system.cpu.itb.fetch_hits 2586 # ITB hits -system.cpu.itb.fetch_misses 11 # ITB misses -system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 2597 # ITB accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.read_acv 0 # DTB read access violations -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.write_acv 0 # DTB write access violations -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.data_hits 0 # DTB hits -system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.data_acv 0 # DTB access violations -system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.workload.num_syscalls 4 # Number of system calls -system.cpu.numCycles 33538 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.num_insts 2577 # Number of instructions executed -system.cpu.num_int_alu_accesses 2375 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 6 # Number of float alu accesses -system.cpu.num_func_calls 140 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 238 # number of instructions that are conditional controls -system.cpu.num_int_insts 2375 # number of integer instructions -system.cpu.num_fp_insts 6 # number of float instructions -system.cpu.num_int_register_reads 2998 # number of times the integer registers were read -system.cpu.num_int_register_writes 1768 # number of times the integer registers were written -system.cpu.num_fp_register_reads 6 # number of times the floating registers were read -system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_mem_refs 717 # number of memory refs -system.cpu.num_load_insts 419 # Number of load instructions -system.cpu.num_store_insts 298 # Number of store instructions -system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 33538 # Number of busy cycles -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 80.003762 # Cycle average of tags in use -system.cpu.icache.total_refs 2423 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 163 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 14.865031 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 80.003762 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.039064 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 2423 # number of ReadReq hits -system.cpu.icache.demand_hits 2423 # number of demand (read+write) hits -system.cpu.icache.overall_hits 2423 # number of overall hits -system.cpu.icache.ReadReq_misses 163 # number of ReadReq misses -system.cpu.icache.demand_misses 163 # number of demand (read+write) misses -system.cpu.icache.overall_misses 163 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 9128000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 9128000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 9128000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 2586 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 2586 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 2586 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.063032 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.063032 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.063032 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 56000 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 163 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 163 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 163 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 8639000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 8639000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 8639000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.063032 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.063032 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.063032 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 47.418751 # Cycle average of tags in use -system.cpu.dcache.total_refs 627 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 82 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 7.646341 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 47.418751 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.011577 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 360 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 267 # number of WriteReq hits -system.cpu.dcache.demand_hits 627 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 627 # number of overall hits -system.cpu.dcache.ReadReq_misses 55 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 27 # number of WriteReq misses -system.cpu.dcache.demand_misses 82 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 82 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 3080000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 1512000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency 4592000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 4592000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 415 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses 294 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 709 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 709 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.132530 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.091837 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate 0.115656 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.115656 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency 56000 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 56000 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 55 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 27 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 82 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 82 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 2915000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 1431000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 4346000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 4346000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.132530 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate 0.091837 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.115656 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.115656 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 107.101205 # Cycle average of tags in use -system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 218 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 107.101205 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.003268 # Average percentage of cache occupancy -system.cpu.l2cache.demand_hits 0 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 0 # number of overall hits -system.cpu.l2cache.ReadReq_misses 218 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses 27 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 245 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 245 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 11336000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 1404000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 12740000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 12740000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 218 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 27 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 245 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 245 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 1 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 1 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 218 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 27 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 245 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 245 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 8720000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 1080000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 9800000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 9800000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate - ----------- End Simulation Statistics ---------- |