diff options
Diffstat (limited to 'tests/quick/00.hello/ref/alpha')
12 files changed, 682 insertions, 720 deletions
diff --git a/tests/quick/00.hello/ref/alpha/linux/inorder-timing/simout b/tests/quick/00.hello/ref/alpha/linux/inorder-timing/simout index 0966923f5..c90d08af7 100755 --- a/tests/quick/00.hello/ref/alpha/linux/inorder-timing/simout +++ b/tests/quick/00.hello/ref/alpha/linux/inorder-timing/simout @@ -1,3 +1,5 @@ +Redirecting stdout to build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/inorder-timing/simout +Redirecting stderr to build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/inorder-timing/simerr M5 Simulator System Copyright (c) 2001-2008 @@ -5,13 +7,13 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jun 25 2010 15:39:10 -M5 revision 93b1ca421839 7482 default qtip tip update_regr -M5 started Jun 25 2010 15:39:11 -M5 executing on zooks -command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/inorder-timing -re tests/run.py build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/inorder-timing +M5 compiled Aug 26 2010 11:51:59 +M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix +M5 started Aug 26 2010 11:52:02 +M5 executing on zizzer +command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/inorder-timing -re tests/run.py build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/inorder-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello world! -Exiting @ tick 31194000 because target called exit() +Exiting @ tick 30538000 because target called exit() diff --git a/tests/quick/00.hello/ref/alpha/linux/inorder-timing/stats.txt b/tests/quick/00.hello/ref/alpha/linux/inorder-timing/stats.txt index baac829f6..9ad72b38e 100644 --- a/tests/quick/00.hello/ref/alpha/linux/inorder-timing/stats.txt +++ b/tests/quick/00.hello/ref/alpha/linux/inorder-timing/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 22440 # Simulator instruction rate (inst/s) -host_mem_usage 153392 # Number of bytes of host memory used -host_seconds 0.29 # Real time elapsed on the host -host_tick_rate 109185606 # Simulator tick rate (ticks/s) +host_inst_rate 4413 # Simulator instruction rate (inst/s) +host_mem_usage 204480 # Number of bytes of host memory used +host_seconds 1.45 # Real time elapsed on the host +host_tick_rate 21040041 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 6404 # Number of instructions simulated sim_seconds 0.000031 # Number of seconds simulated -sim_ticks 31194000 # Number of ticks simulated +sim_ticks 30538000 # Number of ticks simulated system.cpu.AGEN-Unit.agens 2050 # Number of Address Generations system.cpu.Branch-Predictor.BTBHitPct 29.967427 # BTB Hit Percentage system.cpu.Branch-Predictor.BTBHits 92 # Number of BTB hits @@ -27,11 +27,11 @@ system.cpu.Execution-Unit.predictedNotTakenIncorrect 523 system.cpu.Execution-Unit.predictedTakenIncorrect 6 # Number of Branches Incorrectly Predicted As Taken. system.cpu.Mult-Div-Unit.divides 0 # Number of Divide Operations Executed system.cpu.Mult-Div-Unit.multiplies 1 # Number of Multipy Operations Executed -system.cpu.RegFile-Manager.regFileAccesses 12569 # Number of Total Accesses (Read+Write) to the Register File -system.cpu.RegFile-Manager.regFileReads 7986 # Number of Reads from Register File +system.cpu.RegFile-Manager.regFileAccesses 12573 # Number of Total Accesses (Read+Write) to the Register File +system.cpu.RegFile-Manager.regFileReads 7990 # Number of Reads from Register File system.cpu.RegFile-Manager.regFileWrites 4583 # Number of Writes to Register File -system.cpu.RegFile-Manager.regForwards 315 # Number of Registers Read Through Forwarding Logic -system.cpu.activity 21.904502 # Percentage of cycles cpu is active +system.cpu.RegFile-Manager.regForwards 311 # Number of Registers Read Through Forwarding Logic +system.cpu.activity 22.376672 # Percentage of cycles cpu is active system.cpu.comBranches 1051 # Number of Branches instructions committed system.cpu.comFloats 2 # Number of Floating Point instructions committed system.cpu.comInts 3265 # Number of Integer instructions committed @@ -42,8 +42,8 @@ system.cpu.comStores 865 # Nu system.cpu.committedInsts 6404 # Number of Instructions Simulated (Per-Thread) system.cpu.committedInsts_total 6404 # Number of Instructions Simulated (Total) system.cpu.contextSwitches 1 # Number of context switches -system.cpu.cpi 9.742192 # CPI: Cycles Per Instruction (Per-Thread) -system.cpu.cpi_total 9.742192 # CPI: Total CPI of All Threads +system.cpu.cpi 9.537320 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi_total 9.537320 # CPI: Total CPI of All Threads system.cpu.dcache.ReadReq_accesses 1185 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_avg_miss_latency 56384.210526 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53384.210526 # average ReadReq mshr miss latency @@ -55,15 +55,15 @@ system.cpu.dcache.ReadReq_mshr_miss_latency 5071500 # system.cpu.dcache.ReadReq_mshr_miss_rate 0.080169 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 95 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 865 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 56068.965517 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53068.965517 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 778 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 4878000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.100578 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 87 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 4617000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.100578 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 87 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_avg_miss_latency 56068.493151 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53068.493151 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 792 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 4093000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.084393 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 73 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_miss_latency 3874000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.084393 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 73 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.avg_refs 11.202381 # Average number of references to valid blocks. @@ -73,39 +73,39 @@ system.cpu.dcache.blocked_cycles::no_mshrs 0 # system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 2050 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 56233.516484 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 53233.516484 # average overall mshr miss latency -system.cpu.dcache.demand_hits 1868 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 10234500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.088780 # miss rate for demand accesses -system.cpu.dcache.demand_misses 182 # number of demand (read+write) misses +system.cpu.dcache.demand_avg_miss_latency 56247.023810 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 53247.023810 # average overall mshr miss latency +system.cpu.dcache.demand_hits 1882 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 9449500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.081951 # miss rate for demand accesses +system.cpu.dcache.demand_misses 168 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 9688500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.088780 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 182 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_miss_latency 8945500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.081951 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 168 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.025297 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 103.617621 # Average occupied blocks per context +system.cpu.dcache.occ_%::0 0.025183 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 103.151125 # Average occupied blocks per context system.cpu.dcache.overall_accesses 2050 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 56233.516484 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 53233.516484 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 56247.023810 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 53247.023810 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 1868 # number of overall hits -system.cpu.dcache.overall_miss_latency 10234500 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.088780 # miss rate for overall accesses -system.cpu.dcache.overall_misses 182 # number of overall misses +system.cpu.dcache.overall_hits 1882 # number of overall hits +system.cpu.dcache.overall_miss_latency 9449500 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.081951 # miss rate for overall accesses +system.cpu.dcache.overall_misses 168 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 9688500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.088780 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 182 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_miss_latency 8945500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.081951 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 168 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.sampled_refs 168 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 103.617621 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 103.151125 # Cycle average of tags in use system.cpu.dcache.total_refs 1882 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks @@ -126,14 +126,14 @@ system.cpu.dtb.write_acv 0 # DT system.cpu.dtb.write_hits 865 # DTB write hits system.cpu.dtb.write_misses 3 # DTB write misses system.cpu.icache.ReadReq_accesses 7169 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 55706.484642 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 52877.192982 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_miss_latency 55703.071672 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 52873.684211 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_hits 6876 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 16322000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency 16321000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.040870 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 293 # number of ReadReq misses system.cpu.icache.ReadReq_mshr_hits 8 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 15070000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 15069000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.039754 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 285 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked @@ -145,31 +145,31 @@ system.cpu.icache.blocked_cycles::no_mshrs 0 # system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.demand_accesses 7169 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 55706.484642 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 52877.192982 # average overall mshr miss latency +system.cpu.icache.demand_avg_miss_latency 55703.071672 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 52873.684211 # average overall mshr miss latency system.cpu.icache.demand_hits 6876 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 16322000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency 16321000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.040870 # miss rate for demand accesses system.cpu.icache.demand_misses 293 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 8 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 15070000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 15069000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.039754 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 285 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.063594 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 130.240724 # Average occupied blocks per context +system.cpu.icache.occ_%::0 0.063218 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 129.469682 # Average occupied blocks per context system.cpu.icache.overall_accesses 7169 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 55706.484642 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 52877.192982 # average overall mshr miss latency +system.cpu.icache.overall_avg_miss_latency 55703.071672 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 52873.684211 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.overall_hits 6876 # number of overall hits -system.cpu.icache.overall_miss_latency 16322000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency 16321000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.040870 # miss rate for overall accesses system.cpu.icache.overall_misses 293 # number of overall misses system.cpu.icache.overall_mshr_hits 8 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 15070000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 15069000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.039754 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 285 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -177,13 +177,13 @@ system.cpu.icache.overall_mshr_uncacheable_misses 0 system.cpu.icache.replacements 0 # number of replacements system.cpu.icache.sampled_refs 284 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 130.240724 # Cycle average of tags in use +system.cpu.icache.tagsinuse 129.469682 # Cycle average of tags in use system.cpu.icache.total_refs 6876 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 48723 # Number of cycles cpu's stages were not processed -system.cpu.ipc 0.102646 # IPC: Instructions Per Cycle (Per-Thread) -system.cpu.ipc_total 0.102646 # IPC: Total IPC of All Threads +system.cpu.idleCycles 47410 # Number of cycles cpu's stages were not processed +system.cpu.ipc 0.104851 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.ipc_total 0.104851 # IPC: Total IPC of All Threads system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_hits 0 # DTB hits @@ -201,36 +201,27 @@ system.cpu.itb.write_acv 0 # DT system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses system.cpu.l2cache.ReadExReq_accesses 73 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 52075.342466 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 52068.493151 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40013.698630 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 3801500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 3801000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_misses 73 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_mshr_miss_latency 2921000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_misses 73 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadReq_accesses 380 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 52085.751979 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency 52087.071240 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 39947.229551 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 1 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 19740500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency 19741000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 0.997368 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_misses 379 # number of ReadReq misses system.cpu.l2cache.ReadReq_mshr_miss_latency 15140000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 0.997368 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 379 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_accesses 14 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 52035.714286 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 728500 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_misses 14 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 560000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_misses 14 # number of UpgradeReq MSHR misses system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.002747 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 0.002646 # Average number of references to valid blocks. system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked @@ -250,8 +241,8 @@ system.cpu.l2cache.demand_mshr_misses 452 # nu system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.005535 # Average percentage of cache occupancy -system.cpu.l2cache.occ_blocks::0 181.374052 # Average occupied blocks per context +system.cpu.l2cache.occ_%::0 0.005668 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 185.735123 # Average occupied blocks per context system.cpu.l2cache.overall_accesses 453 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 52084.070796 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 39957.964602 # average overall mshr miss latency @@ -267,34 +258,34 @@ system.cpu.l2cache.overall_mshr_misses 452 # nu system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 364 # Sample count of references to valid blocks. +system.cpu.l2cache.sampled_refs 378 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 181.374052 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 185.735123 # Cycle average of tags in use system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.numCycles 62389 # number of cpu cycles simulated -system.cpu.runCycles 13666 # Number of cycles cpu stages are processed. +system.cpu.numCycles 61077 # number of cpu cycles simulated +system.cpu.runCycles 13667 # Number of cycles cpu stages are processed. system.cpu.smtCommittedInsts 0 # Number of SMT Instructions Simulated (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode system.cpu.smt_cpi no_value # CPI: Total SMT-CPI system.cpu.smt_ipc no_value # IPC: Total SMT-IPC -system.cpu.stage-0.idleCycles 55203 # Number of cycles 0 instructions are processed. +system.cpu.stage-0.idleCycles 53891 # Number of cycles 0 instructions are processed. system.cpu.stage-0.runCycles 7186 # Number of cycles 1+ instructions are processed. -system.cpu.stage-0.utilization 11.518056 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage-1.idleCycles 55836 # Number of cycles 0 instructions are processed. -system.cpu.stage-1.runCycles 6553 # Number of cycles 1+ instructions are processed. -system.cpu.stage-1.utilization 10.503454 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage-2.idleCycles 55919 # Number of cycles 0 instructions are processed. +system.cpu.stage-0.utilization 11.765476 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage-1.idleCycles 54525 # Number of cycles 0 instructions are processed. +system.cpu.stage-1.runCycles 6552 # Number of cycles 1+ instructions are processed. +system.cpu.stage-1.utilization 10.727442 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage-2.idleCycles 54607 # Number of cycles 0 instructions are processed. system.cpu.stage-2.runCycles 6470 # Number of cycles 1+ instructions are processed. -system.cpu.stage-2.utilization 10.370418 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage-3.idleCycles 60336 # Number of cycles 0 instructions are processed. +system.cpu.stage-2.utilization 10.593186 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage-3.idleCycles 59024 # Number of cycles 0 instructions are processed. system.cpu.stage-3.runCycles 2053 # Number of cycles 1+ instructions are processed. -system.cpu.stage-3.utilization 3.290644 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage-4.idleCycles 55985 # Number of cycles 0 instructions are processed. +system.cpu.stage-3.utilization 3.361331 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage-4.idleCycles 54673 # Number of cycles 0 instructions are processed. system.cpu.stage-4.runCycles 6404 # Number of cycles 1+ instructions are processed. -system.cpu.stage-4.utilization 10.264630 # Percentage of cycles stage was utilized (processing insts). -system.cpu.threadCycles 62389 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.stage-4.utilization 10.485125 # Percentage of cycles stage was utilized (processing insts). +system.cpu.threadCycles 61077 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.workload.PROG:num_syscalls 17 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/simout b/tests/quick/00.hello/ref/alpha/linux/o3-timing/simout index 4261d2ba3..63bbf8869 100755 --- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/simout +++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/simout @@ -1,5 +1,5 @@ -Redirecting stdout to build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/o3-timing/simout -Redirecting stderr to build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/o3-timing/simerr +Redirecting stdout to build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/o3-timing/simout +Redirecting stderr to build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/o3-timing/simerr M5 Simulator System Copyright (c) 2001-2008 @@ -7,13 +7,13 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jun 6 2010 03:04:38 -M5 revision ba1a0193c050 7448 default tip -M5 started Jun 6 2010 03:09:06 +M5 compiled Aug 26 2010 11:51:59 +M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix +M5 started Aug 26 2010 11:52:04 M5 executing on zizzer -command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/o3-timing +command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello world! -Exiting @ tick 12497500 because target called exit() +Exiting @ tick 12412500 because target called exit() diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/00.hello/ref/alpha/linux/o3-timing/stats.txt index fd2b0ddaf..a57aece07 100644 --- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/stats.txt +++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/stats.txt @@ -1,41 +1,41 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 80384 # Simulator instruction rate (inst/s) -host_mem_usage 204420 # Number of bytes of host memory used -host_seconds 0.08 # Real time elapsed on the host -host_tick_rate 156814646 # Simulator tick rate (ticks/s) +host_inst_rate 44712 # Simulator instruction rate (inst/s) +host_mem_usage 204968 # Number of bytes of host memory used +host_seconds 0.14 # Real time elapsed on the host +host_tick_rate 86758837 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 6386 # Number of instructions simulated sim_seconds 0.000012 # Number of seconds simulated -sim_ticks 12497500 # Number of ticks simulated +sim_ticks 12412500 # Number of ticks simulated system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.BTBHits 692 # Number of BTB hits -system.cpu.BPredUnit.BTBLookups 1820 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 680 # Number of BTB hits +system.cpu.BPredUnit.BTBLookups 1800 # Number of BTB lookups system.cpu.BPredUnit.RASInCorrect 65 # Number of incorrect RAS predictions. system.cpu.BPredUnit.condIncorrect 443 # Number of conditional branches incorrect -system.cpu.BPredUnit.condPredicted 1337 # Number of conditional branches predicted -system.cpu.BPredUnit.lookups 2245 # Number of BP lookups -system.cpu.BPredUnit.usedRAS 315 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.condPredicted 1320 # Number of conditional branches predicted +system.cpu.BPredUnit.lookups 2222 # Number of BP lookups +system.cpu.BPredUnit.usedRAS 313 # Number of times the RAS was used to get a target. system.cpu.commit.COM:branches 1051 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 119 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_lim_events 117 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle::samples 12431 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::mean 0.515083 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::stdev 1.305811 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::samples 12265 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::mean 0.522055 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::stdev 1.306636 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::0 9528 76.65% 76.65% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::1 1629 13.10% 89.75% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::2 491 3.95% 93.70% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::3 259 2.08% 95.78% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::4 156 1.25% 97.04% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::5 104 0.84% 97.88% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::6 96 0.77% 98.65% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::7 49 0.39% 99.04% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::8 119 0.96% 100.00% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::0 9355 76.27% 76.27% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::1 1631 13.30% 89.57% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::2 489 3.99% 93.56% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::3 266 2.17% 95.73% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::4 144 1.17% 96.90% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::5 131 1.07% 97.97% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::6 95 0.77% 98.74% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::7 37 0.30% 99.05% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::8 117 0.95% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::total 12431 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::total 12265 # Number of insts commited each cycle system.cpu.commit.COM:count 6403 # Number of instructions committed system.cpu.commit.COM:loads 1185 # Number of loads committed system.cpu.commit.COM:membars 0 # Number of memory barriers committed @@ -44,295 +44,295 @@ system.cpu.commit.COM:swp_count 0 # Nu system.cpu.commit.branchMispredicts 369 # The number of times a branch was mispredicted system.cpu.commit.commitCommittedInsts 6403 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 4622 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 4518 # The number of squashed insts skipped by commit system.cpu.committedInsts 6386 # Number of Instructions Simulated system.cpu.committedInsts_total 6386 # Number of Instructions Simulated -system.cpu.cpi 3.914187 # CPI: Cycles Per Instruction -system.cpu.cpi_total 3.914187 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 1782 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 34993.902439 # average ReadReq miss latency +system.cpu.cpi 3.887567 # CPI: Cycles Per Instruction +system.cpu.cpi_total 3.887567 # CPI: Total CPI of All Threads +system.cpu.dcache.ReadReq_accesses 1765 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 35761.146497 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency 36257.425743 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 1618 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 5739000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.092031 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 164 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 63 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_hits 1608 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 5614500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.088952 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 157 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 56 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_miss_latency 3662000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.056678 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate 0.057224 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 101 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 865 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 35082.894737 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35729.885057 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 485 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 13331500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.439306 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 380 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 293 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 3108500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.100578 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 87 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_avg_miss_latency 34971.751412 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35815.068493 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 511 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 12380000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.409249 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 354 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 281 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 2614500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.084393 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 73 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 12.275862 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 12.178161 # Average number of references to valid blocks. system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 2647 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 35056.066176 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 36013.297872 # average overall mshr miss latency -system.cpu.dcache.demand_hits 2103 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 19070500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.205516 # miss rate for demand accesses -system.cpu.dcache.demand_misses 544 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 356 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 6770500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.071024 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 188 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_accesses 2630 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 35214.285714 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 36071.839080 # average overall mshr miss latency +system.cpu.dcache.demand_hits 2119 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 17994500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.194297 # miss rate for demand accesses +system.cpu.dcache.demand_misses 511 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 337 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 6276500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.066160 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 174 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.occ_%::0 0.026868 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 110.050975 # Average occupied blocks per context -system.cpu.dcache.overall_accesses 2647 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 35056.066176 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 36013.297872 # average overall mshr miss latency +system.cpu.dcache.occ_blocks::0 110.049713 # Average occupied blocks per context +system.cpu.dcache.overall_accesses 2630 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 35214.285714 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 36071.839080 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 2103 # number of overall hits -system.cpu.dcache.overall_miss_latency 19070500 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.205516 # miss rate for overall accesses -system.cpu.dcache.overall_misses 544 # number of overall misses -system.cpu.dcache.overall_mshr_hits 356 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 6770500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.071024 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 188 # number of overall MSHR misses +system.cpu.dcache.overall_hits 2119 # number of overall hits +system.cpu.dcache.overall_miss_latency 17994500 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.194297 # miss rate for overall accesses +system.cpu.dcache.overall_misses 511 # number of overall misses +system.cpu.dcache.overall_mshr_hits 337 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 6276500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.066160 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 174 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.sampled_refs 174 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 110.050975 # Cycle average of tags in use -system.cpu.dcache.total_refs 2136 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 110.049713 # Cycle average of tags in use +system.cpu.dcache.total_refs 2119 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 1123 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BlockedCycles 1016 # Number of cycles decode is blocked system.cpu.decode.DECODE:BranchMispred 75 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 188 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 12474 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 8945 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 2313 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 900 # Number of cycles decode is squashing +system.cpu.decode.DECODE:BranchResolved 185 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 12350 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 8913 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 2277 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 884 # Number of cycles decode is squashing system.cpu.decode.DECODE:SquashedInsts 209 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 50 # Number of cycles decode is unblocking -system.cpu.dtb.data_accesses 2948 # DTB accesses +system.cpu.decode.DECODE:UnblockCycles 59 # Number of cycles decode is unblocking +system.cpu.dtb.data_accesses 2921 # DTB accesses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_hits 2887 # DTB hits +system.cpu.dtb.data_hits 2860 # DTB hits system.cpu.dtb.data_misses 61 # DTB misses system.cpu.dtb.fetch_accesses 0 # ITB accesses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.read_accesses 1865 # DTB read accesses +system.cpu.dtb.read_accesses 1845 # DTB read accesses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_hits 1829 # DTB read hits +system.cpu.dtb.read_hits 1809 # DTB read hits system.cpu.dtb.read_misses 36 # DTB read misses -system.cpu.dtb.write_accesses 1083 # DTB write accesses +system.cpu.dtb.write_accesses 1076 # DTB write accesses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_hits 1058 # DTB write hits +system.cpu.dtb.write_hits 1051 # DTB write hits system.cpu.dtb.write_misses 25 # DTB write misses -system.cpu.fetch.Branches 2245 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 1792 # Number of cache lines fetched -system.cpu.fetch.Cycles 4238 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 269 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 13309 # Number of instructions fetch has processed -system.cpu.fetch.SquashCycles 504 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.089814 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 1792 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 1007 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 0.532445 # Number of inst fetches per cycle -system.cpu.fetch.rateDist::samples 13331 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.998350 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.390717 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.Branches 2222 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 1774 # Number of cache lines fetched +system.cpu.fetch.Cycles 4193 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 267 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 13186 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 503 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.089503 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 1774 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 993 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 0.531137 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 13149 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.002814 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.396074 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 10920 81.91% 81.91% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 245 1.84% 83.75% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 221 1.66% 85.41% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 185 1.39% 86.80% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 233 1.75% 88.55% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 164 1.23% 89.78% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 228 1.71% 91.49% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 133 1.00% 92.48% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 1002 7.52% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 10764 81.86% 81.86% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 240 1.83% 83.69% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 218 1.66% 85.34% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 183 1.39% 86.74% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 231 1.76% 88.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 163 1.24% 89.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 224 1.70% 91.44% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 130 0.99% 92.43% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 996 7.57% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 13331 # Number of instructions fetched each cycle (Total) -system.cpu.icache.ReadReq_accesses 1792 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 35303.990610 # average ReadReq miss latency +system.cpu.fetch.rateDist::total 13149 # Number of instructions fetched each cycle (Total) +system.cpu.icache.ReadReq_accesses 1774 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 35292.253521 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 35283.387622 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 1366 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 15039500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.237723 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_hits 1348 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 15034500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.240135 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 426 # number of ReadReq misses system.cpu.icache.ReadReq_mshr_hits 119 # number of ReadReq MSHR hits system.cpu.icache.ReadReq_mshr_miss_latency 10832000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.171317 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate 0.173055 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 307 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 4.449511 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 4.390879 # Average number of references to valid blocks. system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 1792 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 35303.990610 # average overall miss latency +system.cpu.icache.demand_accesses 1774 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 35292.253521 # average overall miss latency system.cpu.icache.demand_avg_mshr_miss_latency 35283.387622 # average overall mshr miss latency -system.cpu.icache.demand_hits 1366 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 15039500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.237723 # miss rate for demand accesses +system.cpu.icache.demand_hits 1348 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 15034500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.240135 # miss rate for demand accesses system.cpu.icache.demand_misses 426 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 119 # number of demand (read+write) MSHR hits system.cpu.icache.demand_mshr_miss_latency 10832000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.171317 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate 0.173055 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 307 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.077094 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 157.888110 # Average occupied blocks per context -system.cpu.icache.overall_accesses 1792 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 35303.990610 # average overall miss latency +system.cpu.icache.occ_%::0 0.077067 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 157.832479 # Average occupied blocks per context +system.cpu.icache.overall_accesses 1774 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 35292.253521 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 35283.387622 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 1366 # number of overall hits -system.cpu.icache.overall_miss_latency 15039500 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.237723 # miss rate for overall accesses +system.cpu.icache.overall_hits 1348 # number of overall hits +system.cpu.icache.overall_miss_latency 15034500 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.240135 # miss rate for overall accesses system.cpu.icache.overall_misses 426 # number of overall misses system.cpu.icache.overall_mshr_hits 119 # number of overall MSHR hits system.cpu.icache.overall_mshr_miss_latency 10832000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.171317 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate 0.173055 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 307 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.replacements 0 # number of replacements system.cpu.icache.sampled_refs 307 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 157.888110 # Cycle average of tags in use -system.cpu.icache.total_refs 1366 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 157.832479 # Cycle average of tags in use +system.cpu.icache.total_refs 1348 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 11665 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 1448 # Number of branches executed -system.cpu.iew.EXEC:nop 83 # number of nop insts executed -system.cpu.iew.EXEC:rate 0.362498 # Inst execution rate -system.cpu.iew.EXEC:refs 2956 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 1085 # Number of stores executed +system.cpu.idleCycles 11677 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 1435 # Number of branches executed +system.cpu.iew.EXEC:nop 82 # number of nop insts executed +system.cpu.iew.EXEC:rate 0.361798 # Inst execution rate +system.cpu.iew.EXEC:refs 2929 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 1078 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 6049 # num instructions consuming a value -system.cpu.iew.WB:count 8759 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.745247 # average fanout of values written-back +system.cpu.iew.WB:consumers 6007 # num instructions consuming a value +system.cpu.iew.WB:count 8682 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.744798 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 4508 # num instructions producing a value -system.cpu.iew.WB:rate 0.350416 # insts written-back per cycle -system.cpu.iew.WB:sent 8858 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 427 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 73 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 2269 # Number of dispatched load instructions +system.cpu.iew.WB:producers 4474 # num instructions producing a value +system.cpu.iew.WB:rate 0.349714 # insts written-back per cycle +system.cpu.iew.WB:sent 8783 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 428 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 63 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 2242 # Number of dispatched load instructions system.cpu.iew.iewDispNonSpecInsts 25 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 191 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 1271 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 11059 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 1871 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 304 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 9061 # Number of executed instructions +system.cpu.iew.iewDispSquashedInsts 193 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 1259 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 10955 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 1851 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 291 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 8982 # Number of executed instructions system.cpu.iew.iewIQFullEvents 7 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 900 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 11 # Number of cycles IEW is unblocking +system.cpu.iew.iewSquashCycles 884 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 9 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 46 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.forwLoads 43 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread.0.ignoredResponses 6 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 64 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.memOrderViolation 63 # Number of memory ordering violations system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 1084 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 406 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 64 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 302 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.lsq.thread.0.squashedLoads 1057 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 394 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 63 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 303 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedTakenIncorrect 125 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 0.255481 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.255481 # IPC: Total IPC of All Threads +system.cpu.ipc 0.257230 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.257230 # IPC: Total IPC of All Threads system.cpu.iq.ISSUE:FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntAlu 6287 67.13% 67.15% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntMult 1 0.01% 67.16% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 67.16% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatAdd 2 0.02% 67.19% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 67.19% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 67.19% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 67.19% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 67.19% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 67.19% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemRead 1968 21.01% 88.20% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemWrite 1105 11.80% 100.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntAlu 6230 67.18% 67.21% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntMult 1 0.01% 67.22% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 67.22% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatAdd 2 0.02% 67.24% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 67.24% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 67.24% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 67.24% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 67.24% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 67.24% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemRead 1943 20.95% 88.19% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemWrite 1095 11.81% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::total 9365 # Type of FU issued -system.cpu.iq.ISSUE:fu_busy_cnt 92 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.009824 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:FU_type_0::total 9273 # Type of FU issued +system.cpu.iq.ISSUE:fu_busy_cnt 91 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.009813 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntAlu 1 1.09% 1.09% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 1.09% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 1.09% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 1.09% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 1.09% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 1.09% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 1.09% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 1.09% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 1.09% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemRead 56 60.87% 61.96% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemWrite 35 38.04% 100.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntAlu 1 1.10% 1.10% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 1.10% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 1.10% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 1.10% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 1.10% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 1.10% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 1.10% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 1.10% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 1.10% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemRead 55 60.44% 61.54% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemWrite 35 38.46% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:issued_per_cycle::samples 13331 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::mean 0.702498 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.304735 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::samples 13149 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::mean 0.705225 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.302669 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::0 9142 68.58% 68.58% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::1 1697 12.73% 81.31% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::2 1062 7.97% 89.27% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::3 730 5.48% 94.75% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::4 359 2.69% 97.44% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::5 188 1.41% 98.85% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::6 105 0.79% 99.64% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::7 36 0.27% 99.91% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::0 8989 68.36% 68.36% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::1 1668 12.69% 81.05% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::2 1105 8.40% 89.45% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::3 696 5.29% 94.74% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::4 356 2.71% 97.45% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::5 185 1.41% 98.86% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::6 104 0.79% 99.65% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::7 34 0.26% 99.91% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::8 12 0.09% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::total 13331 # Number of insts issued each cycle -system.cpu.iq.ISSUE:rate 0.374660 # Inst issue rate -system.cpu.iq.iqInstsAdded 10951 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 9365 # Number of instructions issued +system.cpu.iq.ISSUE:issued_per_cycle::total 13149 # Number of insts issued each cycle +system.cpu.iq.ISSUE:rate 0.373520 # Inst issue rate +system.cpu.iq.iqInstsAdded 10848 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 9273 # Number of instructions issued system.cpu.iq.iqNonSpecInstsAdded 25 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 4181 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 44 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 4076 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 42 # Number of squashed instructions issued system.cpu.iq.iqSquashedNonSpecRemoved 8 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 2504 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedOperandsExamined 2476 # Number of squashed operands that are examined and possibly removed from graph system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_hits 0 # DTB hits system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.fetch_accesses 1827 # ITB accesses +system.cpu.itb.fetch_accesses 1808 # ITB accesses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_hits 1792 # ITB hits -system.cpu.itb.fetch_misses 35 # ITB misses +system.cpu.itb.fetch_hits 1774 # ITB hits +system.cpu.itb.fetch_misses 34 # ITB misses system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.read_acv 0 # DTB read access violations system.cpu.itb.read_hits 0 # DTB read hits @@ -342,100 +342,91 @@ system.cpu.itb.write_acv 0 # DT system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses system.cpu.l2cache.ReadExReq_accesses 73 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 34465.753425 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31376.712329 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 2516000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_avg_miss_latency 34506.849315 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31424.657534 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_miss_latency 2519000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_misses 73 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 2290500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 2294000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_misses 73 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadReq_accesses 408 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 34418.918919 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31239.557740 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency 34420.147420 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31243.243243 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 1 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 14008500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency 14009000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 0.997549 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_misses 407 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 12714500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 12716000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 0.997549 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 407 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_accesses 14 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 34250 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31035.714286 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 479500 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_misses 14 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 434500 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_misses 14 # number of UpgradeReq MSHR misses system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.002545 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 0.002457 # Average number of references to valid blocks. system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 481 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 34426.041667 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31260.416667 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_miss_latency 34433.333333 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31270.833333 # average overall mshr miss latency system.cpu.l2cache.demand_hits 1 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 16524500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency 16528000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate 0.997921 # miss rate for demand accesses system.cpu.l2cache.demand_misses 480 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 15005000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 15010000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_rate 0.997921 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_misses 480 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.006535 # Average percentage of cache occupancy -system.cpu.l2cache.occ_blocks::0 214.135921 # Average occupied blocks per context +system.cpu.l2cache.occ_%::0 0.006704 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 219.690126 # Average occupied blocks per context system.cpu.l2cache.overall_accesses 481 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 34426.041667 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31260.416667 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_miss_latency 34433.333333 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31270.833333 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 1 # number of overall hits -system.cpu.l2cache.overall_miss_latency 16524500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency 16528000 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 0.997921 # miss rate for overall accesses system.cpu.l2cache.overall_misses 480 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 15005000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 15010000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_rate 0.997921 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_misses 480 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 393 # Sample count of references to valid blocks. +system.cpu.l2cache.sampled_refs 407 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 214.135921 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 219.690126 # Cycle average of tags in use system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.memDep0.conflictingLoads 36 # Number of conflicting loads. +system.cpu.memDep0.conflictingLoads 34 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 26 # Number of conflicting stores. -system.cpu.memDep0.insertedLoads 2269 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1271 # Number of stores inserted to the mem dependence unit. -system.cpu.numCycles 24996 # number of cpu cycles simulated -system.cpu.rename.RENAME:BlockCycles 340 # Number of cycles rename is blocking +system.cpu.memDep0.insertedLoads 2242 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1259 # Number of stores inserted to the mem dependence unit. +system.cpu.numCycles 24826 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 346 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 4583 # Number of HB maps that are committed -system.cpu.rename.RENAME:IQFullEvents 9 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 9098 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 255 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:RenameLookups 15174 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 12043 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 8961 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 2203 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 900 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 292 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 4378 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:serializeStallCycles 498 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:IQFullEvents 8 # Number of times rename has blocked due to IQ full +system.cpu.rename.RENAME:IdleCycles 9063 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 234 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:RenameLookups 15033 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 11933 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 8883 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 2180 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 884 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 270 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 4300 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 406 # count of cycles rename stalled for serializing inst system.cpu.rename.RENAME:serializingInsts 28 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 750 # count of insts added to the skid buffer +system.cpu.rename.RENAME:skidInsts 694 # count of insts added to the skid buffer system.cpu.rename.RENAME:tempSerializingInsts 22 # count of temporary serializing insts renamed -system.cpu.timesIdled 240 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.timesIdled 239 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 17 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini b/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini index b9c9ec747..17f796bc5 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini @@ -157,7 +157,7 @@ egid=100 env= errout=cerr euid=100 -executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/alpha/linux/hello +executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello gid=100 input=cin max_stack_size=67108864 diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing/simout b/tests/quick/00.hello/ref/alpha/linux/simple-timing/simout index 7ee1b22c1..2df06d2e2 100755 --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing/simout +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing/simout @@ -1,3 +1,5 @@ +Redirecting stdout to build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/simple-timing/simout +Redirecting stderr to build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/simple-timing/simerr M5 Simulator System Copyright (c) 2001-2008 @@ -5,13 +7,13 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 24 2010 23:12:40 -M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip -M5 started Feb 25 2010 02:20:02 -M5 executing on SC2B0619 -command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-timing -re tests/run.py build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-timing +M5 compiled Aug 26 2010 11:51:59 +M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix +M5 started Aug 26 2010 11:59:22 +M5 executing on zizzer +command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/simple-timing -re tests/run.py build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello world! -Exiting @ tick 33777000 because target called exit() +Exiting @ tick 33007000 because target called exit() diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing/stats.txt b/tests/quick/00.hello/ref/alpha/linux/simple-timing/stats.txt index 998b710c1..0a6e1d861 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing/stats.txt +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 605866 # Simulator instruction rate (inst/s) -host_mem_usage 190120 # Number of bytes of host memory used -host_seconds 0.01 # Real time elapsed on the host -host_tick_rate 3109075847 # Simulator tick rate (ticks/s) +host_inst_rate 332796 # Simulator instruction rate (inst/s) +host_mem_usage 204128 # Number of bytes of host memory used +host_seconds 0.02 # Real time elapsed on the host +host_tick_rate 1691799077 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 6404 # Number of instructions simulated -sim_seconds 0.000034 # Number of seconds simulated -sim_ticks 33777000 # Number of ticks simulated +sim_seconds 0.000033 # Number of seconds simulated +sim_ticks 33007000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 1185 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency @@ -21,13 +21,13 @@ system.cpu.dcache.ReadReq_mshr_misses 95 # nu system.cpu.dcache.WriteReq_accesses 865 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 778 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 4872000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.100578 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 87 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 4611000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.100578 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 87 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_hits 792 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 4088000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.084393 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 73 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_miss_latency 3869000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.084393 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 73 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.avg_refs 11.202381 # Average number of references to valid blocks. @@ -39,37 +39,37 @@ system.cpu.dcache.cache_copies 0 # nu system.cpu.dcache.demand_accesses 2050 # number of demand (read+write) accesses system.cpu.dcache.demand_avg_miss_latency 56000 # average overall miss latency system.cpu.dcache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency -system.cpu.dcache.demand_hits 1868 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 10192000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.088780 # miss rate for demand accesses -system.cpu.dcache.demand_misses 182 # number of demand (read+write) misses +system.cpu.dcache.demand_hits 1882 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 9408000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.081951 # miss rate for demand accesses +system.cpu.dcache.demand_misses 168 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 9646000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.088780 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 182 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_miss_latency 8904000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.081951 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 168 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.025418 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 104.111261 # Average occupied blocks per context +system.cpu.dcache.occ_%::0 0.025313 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 103.680615 # Average occupied blocks per context system.cpu.dcache.overall_accesses 2050 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 56000 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 1868 # number of overall hits -system.cpu.dcache.overall_miss_latency 10192000 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.088780 # miss rate for overall accesses -system.cpu.dcache.overall_misses 182 # number of overall misses +system.cpu.dcache.overall_hits 1882 # number of overall hits +system.cpu.dcache.overall_miss_latency 9408000 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.081951 # miss rate for overall accesses +system.cpu.dcache.overall_misses 168 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 9646000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.088780 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 182 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_miss_latency 8904000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.081951 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 168 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.sampled_refs 168 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 104.111261 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 103.680615 # Cycle average of tags in use system.cpu.dcache.total_refs 1882 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks @@ -121,8 +121,8 @@ system.cpu.icache.demand_mshr_misses 279 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.062817 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 128.649737 # Average occupied blocks per context +system.cpu.icache.occ_%::0 0.062443 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 127.883393 # Average occupied blocks per context system.cpu.icache.overall_accesses 6415 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 55849.462366 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 52849.462366 # average overall mshr miss latency @@ -140,7 +140,7 @@ system.cpu.icache.overall_mshr_uncacheable_misses 0 system.cpu.icache.replacements 0 # number of replacements system.cpu.icache.sampled_refs 279 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 128.649737 # Cycle average of tags in use +system.cpu.icache.tagsinuse 127.883393 # Cycle average of tags in use system.cpu.icache.total_refs 6136 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks @@ -180,18 +180,9 @@ system.cpu.l2cache.ReadReq_misses 373 # nu system.cpu.l2cache.ReadReq_mshr_miss_latency 14920000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 0.997326 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 373 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_accesses 14 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 52000 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 728000 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_misses 14 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 560000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_misses 14 # number of UpgradeReq MSHR misses system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.002786 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 0.002681 # Average number of references to valid blocks. system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked @@ -211,8 +202,8 @@ system.cpu.l2cache.demand_mshr_misses 446 # nu system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.005491 # Average percentage of cache occupancy -system.cpu.l2cache.occ_blocks::0 179.928092 # Average occupied blocks per context +system.cpu.l2cache.occ_%::0 0.005626 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 184.342479 # Average occupied blocks per context system.cpu.l2cache.overall_accesses 447 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency @@ -228,14 +219,14 @@ system.cpu.l2cache.overall_mshr_misses 446 # nu system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 359 # Sample count of references to valid blocks. +system.cpu.l2cache.sampled_refs 373 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 179.928092 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 184.342479 # Cycle average of tags in use system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 67554 # number of cpu cycles simulated +system.cpu.numCycles 66014 # number of cpu cycles simulated system.cpu.num_insts 6404 # Number of instructions executed system.cpu.num_refs 2060 # Number of memory references system.cpu.workload.PROG:num_syscalls 17 # Number of system calls diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/simout b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/simout index a969330c7..621a02c83 100755 --- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/simout +++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/simout @@ -1,5 +1,5 @@ -Redirecting stdout to build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/o3-timing/simout -Redirecting stderr to build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/o3-timing/simerr +Redirecting stdout to build/ALPHA_SE/tests/opt/quick/00.hello/alpha/tru64/o3-timing/simout +Redirecting stderr to build/ALPHA_SE/tests/opt/quick/00.hello/alpha/tru64/o3-timing/simerr M5 Simulator System Copyright (c) 2001-2008 @@ -7,13 +7,13 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jun 6 2010 03:04:38 -M5 revision ba1a0193c050 7448 default tip -M5 started Jun 6 2010 03:04:41 +M5 compiled Aug 26 2010 11:51:59 +M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix +M5 started Aug 26 2010 11:52:05 M5 executing on zizzer -command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/o3-timing +command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/quick/00.hello/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello world! -Exiting @ tick 7285000 because target called exit() +Exiting @ tick 7300000 because target called exit() diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt index 7aa7cb16b..a87f9a576 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt @@ -1,41 +1,41 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 8638 # Simulator instruction rate (inst/s) -host_mem_usage 203416 # Number of bytes of host memory used -host_seconds 0.28 # Real time elapsed on the host -host_tick_rate 26335958 # Simulator tick rate (ticks/s) +host_inst_rate 34398 # Simulator instruction rate (inst/s) +host_mem_usage 203876 # Number of bytes of host memory used +host_seconds 0.07 # Real time elapsed on the host +host_tick_rate 104794717 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 2387 # Number of instructions simulated sim_seconds 0.000007 # Number of seconds simulated -sim_ticks 7285000 # Number of ticks simulated +sim_ticks 7300000 # Number of ticks simulated system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.BTBHits 190 # Number of BTB hits -system.cpu.BPredUnit.BTBLookups 674 # Number of BTB lookups +system.cpu.BPredUnit.BTBLookups 683 # Number of BTB lookups system.cpu.BPredUnit.RASInCorrect 35 # Number of incorrect RAS predictions. system.cpu.BPredUnit.condIncorrect 220 # Number of conditional branches incorrect -system.cpu.BPredUnit.condPredicted 463 # Number of conditional branches predicted -system.cpu.BPredUnit.lookups 916 # Number of BP lookups -system.cpu.BPredUnit.usedRAS 178 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.condPredicted 476 # Number of conditional branches predicted +system.cpu.BPredUnit.lookups 926 # Number of BP lookups +system.cpu.BPredUnit.usedRAS 179 # Number of times the RAS was used to get a target. system.cpu.commit.COM:branches 396 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 39 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_lim_events 35 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle::samples 6323 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::mean 0.407402 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::stdev 1.198077 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::samples 6328 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::mean 0.407080 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::stdev 1.186255 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::0 5366 84.86% 84.86% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::1 262 4.14% 89.01% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::2 338 5.35% 94.35% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::3 131 2.07% 96.43% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::4 72 1.14% 97.56% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::5 64 1.01% 98.58% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::6 32 0.51% 99.08% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::7 19 0.30% 99.38% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::8 39 0.62% 100.00% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::0 5362 84.73% 84.73% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::1 264 4.17% 88.91% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::2 341 5.39% 94.30% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::3 139 2.20% 96.49% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::4 71 1.12% 97.61% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::5 66 1.04% 98.66% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::6 31 0.49% 99.15% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::7 19 0.30% 99.45% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::8 35 0.55% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::total 6323 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::total 6328 # Number of insts commited each cycle system.cpu.commit.COM:count 2576 # Number of instructions committed system.cpu.commit.COM:loads 415 # Number of loads committed system.cpu.commit.COM:membars 0 # Number of memory barriers committed @@ -44,248 +44,248 @@ system.cpu.commit.COM:swp_count 0 # Nu system.cpu.commit.branchMispredicts 143 # The number of times a branch was mispredicted system.cpu.commit.commitCommittedInsts 2576 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 4 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 1946 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 1998 # The number of squashed insts skipped by commit system.cpu.committedInsts 2387 # Number of Instructions Simulated system.cpu.committedInsts_total 2387 # Number of Instructions Simulated -system.cpu.cpi 6.104315 # CPI: Cycles Per Instruction -system.cpu.cpi_total 6.104315 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 595 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 35822.222222 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 35663.934426 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 505 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 3224000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.151261 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 90 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 29 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 2175500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.102521 # mshr miss rate for ReadReq accesses +system.cpu.cpi 6.116883 # CPI: Cycles Per Instruction +system.cpu.cpi_total 6.116883 # CPI: Total CPI of All Threads +system.cpu.dcache.ReadReq_accesses 599 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 35045 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 35696.721311 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 499 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 3504500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.166945 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 100 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 39 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 2177500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.101836 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 61 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 294 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 37219.626168 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 37702.702703 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 187 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 3982500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.363946 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 107 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 70 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 1395000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.125850 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 37 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_avg_miss_latency 38819.444444 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 36145.833333 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 222 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 2795000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.244898 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 72 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 48 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 867500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.081633 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 24 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 8.600000 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 8.482353 # Average number of references to valid blocks. system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 889 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 36581.218274 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 36433.673469 # average overall mshr miss latency -system.cpu.dcache.demand_hits 692 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 7206500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.221597 # miss rate for demand accesses -system.cpu.dcache.demand_misses 197 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 99 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 3570500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.110236 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 98 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_accesses 893 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 36625 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 35823.529412 # average overall mshr miss latency +system.cpu.dcache.demand_hits 721 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 6299500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.192609 # miss rate for demand accesses +system.cpu.dcache.demand_misses 172 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 87 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 3045000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.095185 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 85 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.011290 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 46.245716 # Average occupied blocks per context -system.cpu.dcache.overall_accesses 889 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 36581.218274 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 36433.673469 # average overall mshr miss latency +system.cpu.dcache.occ_%::0 0.011350 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 46.490005 # Average occupied blocks per context +system.cpu.dcache.overall_accesses 893 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 36625 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 35823.529412 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 692 # number of overall hits -system.cpu.dcache.overall_miss_latency 7206500 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.221597 # miss rate for overall accesses -system.cpu.dcache.overall_misses 197 # number of overall misses -system.cpu.dcache.overall_mshr_hits 99 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 3570500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.110236 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 98 # number of overall MSHR misses +system.cpu.dcache.overall_hits 721 # number of overall hits +system.cpu.dcache.overall_miss_latency 6299500 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.192609 # miss rate for overall accesses +system.cpu.dcache.overall_misses 172 # number of overall misses +system.cpu.dcache.overall_mshr_hits 87 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 3045000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.095185 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 85 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.sampled_refs 85 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 46.245716 # Cycle average of tags in use -system.cpu.dcache.total_refs 731 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 46.490005 # Cycle average of tags in use +system.cpu.dcache.total_refs 721 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 169 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BlockedCycles 226 # Number of cycles decode is blocked system.cpu.decode.DECODE:BranchMispred 79 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 142 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 5018 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 5179 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 974 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 367 # Number of cycles decode is squashing +system.cpu.decode.DECODE:BranchResolved 136 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 5050 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 5122 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 978 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 373 # Number of cycles decode is squashing system.cpu.decode.DECODE:SquashedInsts 284 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 1 # Number of cycles decode is unblocking -system.cpu.dtb.data_accesses 1010 # DTB accesses +system.cpu.decode.DECODE:UnblockCycles 2 # Number of cycles decode is unblocking +system.cpu.dtb.data_accesses 1016 # DTB accesses system.cpu.dtb.data_acv 1 # DTB access violations -system.cpu.dtb.data_hits 979 # DTB hits -system.cpu.dtb.data_misses 31 # DTB misses +system.cpu.dtb.data_hits 978 # DTB hits +system.cpu.dtb.data_misses 38 # DTB misses system.cpu.dtb.fetch_accesses 0 # ITB accesses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.read_accesses 638 # DTB read accesses +system.cpu.dtb.read_accesses 648 # DTB read accesses system.cpu.dtb.read_acv 1 # DTB read access violations -system.cpu.dtb.read_hits 623 # DTB read hits -system.cpu.dtb.read_misses 15 # DTB read misses -system.cpu.dtb.write_accesses 372 # DTB write accesses +system.cpu.dtb.read_hits 627 # DTB read hits +system.cpu.dtb.read_misses 21 # DTB read misses +system.cpu.dtb.write_accesses 368 # DTB write accesses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_hits 356 # DTB write hits -system.cpu.dtb.write_misses 16 # DTB write misses -system.cpu.fetch.Branches 916 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 789 # Number of cache lines fetched -system.cpu.fetch.Cycles 1801 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 119 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 5736 # Number of instructions fetch has processed -system.cpu.fetch.SquashCycles 250 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.062865 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 789 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 368 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 0.393659 # Number of inst fetches per cycle -system.cpu.fetch.rateDist::samples 6690 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.857399 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.271719 # Number of instructions fetched each cycle (Total) +system.cpu.dtb.write_hits 351 # DTB write hits +system.cpu.dtb.write_misses 17 # DTB write misses +system.cpu.fetch.Branches 926 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 782 # Number of cache lines fetched +system.cpu.fetch.Cycles 1799 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 117 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 5752 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 249 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.063420 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 782 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 369 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 0.393946 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 6701 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.858379 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.271912 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 5707 85.31% 85.31% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 48 0.72% 86.02% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 101 1.51% 87.53% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 74 1.11% 88.64% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 123 1.84% 90.48% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 57 0.85% 91.33% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 51 0.76% 92.09% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 51 0.76% 92.86% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 478 7.14% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 5713 85.26% 85.26% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 53 0.79% 86.05% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 100 1.49% 87.54% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 71 1.06% 88.60% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 125 1.87% 90.46% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 52 0.78% 91.24% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 55 0.82% 92.06% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 60 0.90% 92.96% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 472 7.04% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 6690 # Number of instructions fetched each cycle (Total) -system.cpu.icache.ReadReq_accesses 789 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 36081.196581 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 35312.154696 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 555 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 8443000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.296578 # miss rate for ReadReq accesses +system.cpu.fetch.rateDist::total 6701 # Number of instructions fetched each cycle (Total) +system.cpu.icache.ReadReq_accesses 782 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 36074.786325 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 35303.867403 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 548 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 8441500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.299233 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 234 # number of ReadReq misses system.cpu.icache.ReadReq_mshr_hits 53 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 6391500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.229404 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_latency 6390000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.231458 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 181 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 3.066298 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 3.027624 # Average number of references to valid blocks. system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 789 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 36081.196581 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 35312.154696 # average overall mshr miss latency -system.cpu.icache.demand_hits 555 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 8443000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.296578 # miss rate for demand accesses +system.cpu.icache.demand_accesses 782 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 36074.786325 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 35303.867403 # average overall mshr miss latency +system.cpu.icache.demand_hits 548 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 8441500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.299233 # miss rate for demand accesses system.cpu.icache.demand_misses 234 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 53 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 6391500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.229404 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_latency 6390000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.231458 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 181 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.043805 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 89.711886 # Average occupied blocks per context -system.cpu.icache.overall_accesses 789 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 36081.196581 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 35312.154696 # average overall mshr miss latency +system.cpu.icache.occ_%::0 0.044097 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 90.310423 # Average occupied blocks per context +system.cpu.icache.overall_accesses 782 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 36074.786325 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 35303.867403 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 555 # number of overall hits -system.cpu.icache.overall_miss_latency 8443000 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.296578 # miss rate for overall accesses +system.cpu.icache.overall_hits 548 # number of overall hits +system.cpu.icache.overall_miss_latency 8441500 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.299233 # miss rate for overall accesses system.cpu.icache.overall_misses 234 # number of overall misses system.cpu.icache.overall_mshr_hits 53 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 6391500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.229404 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_latency 6390000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.231458 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 181 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.replacements 0 # number of replacements system.cpu.icache.sampled_refs 181 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 89.711886 # Cycle average of tags in use -system.cpu.icache.total_refs 555 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 90.310423 # Cycle average of tags in use +system.cpu.icache.total_refs 548 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 7881 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 607 # Number of branches executed -system.cpu.iew.EXEC:nop 310 # number of nop insts executed -system.cpu.iew.EXEC:rate 0.241370 # Inst execution rate -system.cpu.iew.EXEC:refs 1013 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 372 # Number of stores executed +system.cpu.idleCycles 7900 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 601 # Number of branches executed +system.cpu.iew.EXEC:nop 306 # number of nop insts executed +system.cpu.iew.EXEC:rate 0.241079 # Inst execution rate +system.cpu.iew.EXEC:refs 1019 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 368 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 1984 # num instructions consuming a value -system.cpu.iew.WB:count 3409 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.798891 # average fanout of values written-back +system.cpu.iew.WB:consumers 1981 # num instructions consuming a value +system.cpu.iew.WB:count 3402 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.795558 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 1585 # num instructions producing a value -system.cpu.iew.WB:rate 0.233958 # insts written-back per cycle +system.cpu.iew.WB:producers 1576 # num instructions producing a value +system.cpu.iew.WB:rate 0.232998 # insts written-back per cycle system.cpu.iew.WB:sent 3452 # cumulative count of insts sent to commit system.cpu.iew.branchMispredicts 164 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 0 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 787 # Number of dispatched load instructions +system.cpu.iew.iewBlockCycles 55 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 795 # Number of dispatched load instructions system.cpu.iew.iewDispNonSpecInsts 6 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 57 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 432 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 4536 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 641 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 117 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 3517 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewDispSquashedInsts 68 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 435 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 4588 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 651 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 111 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 3520 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 3 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 367 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking +system.cpu.iew.iewSquashCycles 373 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 5 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.lsq.thread.0.forwLoads 28 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread.0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 14 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.memOrderViolation 13 # Number of memory ordering violations system.cpu.iew.lsq.thread.0.rescheduledLoads 0 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 372 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 138 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 14 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 110 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 54 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 0.163819 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.163819 # IPC: Total IPC of All Threads +system.cpu.iew.lsq.thread.0.squashedLoads 380 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 141 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 13 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 109 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 55 # Number of branches that were predicted taken incorrectly +system.cpu.ipc 0.163482 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.163482 # IPC: Total IPC of All Threads system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntAlu 2590 71.27% 71.27% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntMult 1 0.03% 71.30% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 71.30% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 71.30% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 71.30% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 71.30% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 71.30% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 71.30% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 71.30% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemRead 666 18.33% 89.63% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemWrite 377 10.37% 100.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntAlu 2582 71.11% 71.11% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntMult 1 0.03% 71.14% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 71.14% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 71.14% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 71.14% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 71.14% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 71.14% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 71.14% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 71.14% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemRead 675 18.59% 89.73% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemWrite 373 10.27% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::total 3634 # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::total 3631 # Type of FU issued system.cpu.iq.ISSUE:fu_busy_cnt 35 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.009631 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_busy_rate 0.009639 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::IntAlu 1 2.86% 2.86% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 2.86% # attempts to use FU when none available @@ -300,38 +300,38 @@ system.cpu.iq.ISSUE:fu_full::MemRead 12 34.29% 37.14% # at system.cpu.iq.ISSUE:fu_full::MemWrite 22 62.86% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:issued_per_cycle::samples 6690 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::mean 0.543199 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.215587 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::samples 6701 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::mean 0.541859 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.220931 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::0 5134 76.74% 76.74% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::1 621 9.28% 86.02% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::2 357 5.34% 91.36% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::3 240 3.59% 94.95% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::4 184 2.75% 97.70% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::5 102 1.52% 99.22% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::6 36 0.54% 99.76% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::7 11 0.16% 99.93% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::8 5 0.07% 100.00% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::0 5144 76.76% 76.76% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::1 631 9.42% 86.18% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::2 352 5.25% 91.43% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::3 241 3.60% 95.03% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::4 180 2.69% 97.72% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::5 94 1.40% 99.12% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::6 38 0.57% 99.69% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::7 13 0.19% 99.88% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::8 8 0.12% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::total 6690 # Number of insts issued each cycle -system.cpu.iq.ISSUE:rate 0.249399 # Inst issue rate -system.cpu.iq.iqInstsAdded 4220 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 3634 # Number of instructions issued +system.cpu.iq.ISSUE:issued_per_cycle::total 6701 # Number of insts issued each cycle +system.cpu.iq.ISSUE:rate 0.248682 # Inst issue rate +system.cpu.iq.iqInstsAdded 4276 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 3631 # Number of instructions issued system.cpu.iq.iqNonSpecInstsAdded 6 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 1660 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 33 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 1710 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 23 # Number of squashed instructions issued system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 874 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedOperandsExamined 972 # Number of squashed operands that are examined and possibly removed from graph system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_hits 0 # DTB hits system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.fetch_accesses 818 # ITB accesses +system.cpu.itb.fetch_accesses 811 # ITB accesses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_hits 789 # ITB hits +system.cpu.itb.fetch_hits 782 # ITB hits system.cpu.itb.fetch_misses 29 # ITB misses system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.read_acv 0 # DTB read access violations @@ -351,23 +351,14 @@ system.cpu.l2cache.ReadExReq_mshr_miss_latency 756000 system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_misses 24 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadReq_accesses 242 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 34324.380165 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31130.165289 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_miss_latency 8306500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_avg_miss_latency 34322.314050 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31132.231405 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_miss_latency 8306000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_misses 242 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 7533500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 7534000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 242 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_accesses 14 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 34250 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31107.142857 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 479500 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_misses 14 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 435500 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_misses 14 # number of UpgradeReq MSHR misses system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_refs 0 # Average number of references to valid blocks. @@ -377,63 +368,64 @@ system.cpu.l2cache.blocked_cycles::no_mshrs 0 # system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 266 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 34349.624060 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31163.533835 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_miss_latency 34347.744361 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31165.413534 # average overall mshr miss latency system.cpu.l2cache.demand_hits 0 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 9137000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency 9136500 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate 1 # miss rate for demand accesses system.cpu.l2cache.demand_misses 266 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 8289500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 8290000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_misses 266 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.003416 # Average percentage of cache occupancy -system.cpu.l2cache.occ_blocks::0 111.924793 # Average occupied blocks per context +system.cpu.l2cache.occ_%::0 0.003651 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 119.628373 # Average occupied blocks per context system.cpu.l2cache.overall_accesses 266 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 34349.624060 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31163.533835 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_miss_latency 34347.744361 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31165.413534 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 0 # number of overall hits -system.cpu.l2cache.overall_miss_latency 9137000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency 9136500 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 1 # miss rate for overall accesses system.cpu.l2cache.overall_misses 266 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 8289500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 8290000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_misses 266 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 228 # Sample count of references to valid blocks. +system.cpu.l2cache.sampled_refs 242 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 111.924793 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 119.628373 # Cycle average of tags in use system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.memDep0.conflictingLoads 12 # Number of conflicting loads. +system.cpu.memDep0.conflictingLoads 16 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 16 # Number of conflicting stores. -system.cpu.memDep0.insertedLoads 787 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 432 # Number of stores inserted to the mem dependence unit. -system.cpu.numCycles 14571 # number of cpu cycles simulated -system.cpu.rename.RENAME:BlockCycles 7 # Number of cycles rename is blocking +system.cpu.memDep0.insertedLoads 795 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 435 # Number of stores inserted to the mem dependence unit. +system.cpu.numCycles 14601 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 63 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 1768 # Number of HB maps that are committed -system.cpu.rename.RENAME:IdleCycles 5259 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 8 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:RenameLookups 5438 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 4848 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 3462 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 895 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 367 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 16 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 1694 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:IQFullEvents 3 # Number of times rename has blocked due to IQ full +system.cpu.rename.RENAME:IdleCycles 5203 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 3 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:RenameLookups 5514 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 4876 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 3481 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 901 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 373 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 15 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 1713 # Number of HB maps that are undone due to squashing system.cpu.rename.RENAME:serializeStallCycles 146 # count of cycles rename stalled for serializing inst system.cpu.rename.RENAME:serializingInsts 8 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 80 # count of insts added to the skid buffer +system.cpu.rename.RENAME:skidInsts 78 # count of insts added to the skid buffer system.cpu.rename.RENAME:tempSerializingInsts 6 # count of temporary serializing insts renamed -system.cpu.timesIdled 153 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.timesIdled 152 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 4 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini index ab47c5c67..c142fa659 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini @@ -157,7 +157,7 @@ egid=100 env= errout=cerr euid=100 -executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/alpha/tru64/hello +executable=/dist/m5/regression/test-progs/hello/bin/alpha/tru64/hello gid=100 input=cin max_stack_size=67108864 diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/simout b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/simout index 2135491a6..6dd6e994b 100755 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/simout +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/simout @@ -1,3 +1,5 @@ +Redirecting stdout to build/ALPHA_SE/tests/opt/quick/00.hello/alpha/tru64/simple-timing/simout +Redirecting stderr to build/ALPHA_SE/tests/opt/quick/00.hello/alpha/tru64/simple-timing/simerr M5 Simulator System Copyright (c) 2001-2008 @@ -5,13 +7,13 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 24 2010 23:12:40 -M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip -M5 started Feb 25 2010 03:11:06 -M5 executing on SC2B0619 -command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-timing +M5 compiled Aug 26 2010 11:51:59 +M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix +M5 started Aug 26 2010 11:52:05 +M5 executing on zizzer +command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/opt/quick/00.hello/alpha/tru64/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello world! -Exiting @ tick 17374000 because target called exit() +Exiting @ tick 16769000 because target called exit() diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stats.txt b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stats.txt index 3c63125e0..f08ca087e 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 400715 # Simulator instruction rate (inst/s) -host_mem_usage 189300 # Number of bytes of host memory used -host_seconds 0.01 # Real time elapsed on the host -host_tick_rate 2582342449 # Simulator tick rate (ticks/s) +host_inst_rate 97740 # Simulator instruction rate (inst/s) +host_mem_usage 203308 # Number of bytes of host memory used +host_seconds 0.03 # Real time elapsed on the host +host_tick_rate 629585132 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 2577 # Number of instructions simulated sim_seconds 0.000017 # Number of seconds simulated -sim_ticks 17374000 # Number of ticks simulated +sim_ticks 16769000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 415 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency @@ -21,13 +21,13 @@ system.cpu.dcache.ReadReq_mshr_misses 55 # nu system.cpu.dcache.WriteReq_accesses 294 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 256 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 2128000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.129252 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 38 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 2014000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.129252 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 38 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_hits 267 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 1512000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.091837 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 27 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_miss_latency 1431000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.091837 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 27 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.avg_refs 7.646341 # Average number of references to valid blocks. @@ -39,37 +39,37 @@ system.cpu.dcache.cache_copies 0 # nu system.cpu.dcache.demand_accesses 709 # number of demand (read+write) accesses system.cpu.dcache.demand_avg_miss_latency 56000 # average overall miss latency system.cpu.dcache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency -system.cpu.dcache.demand_hits 616 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 5208000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.131171 # miss rate for demand accesses -system.cpu.dcache.demand_misses 93 # number of demand (read+write) misses +system.cpu.dcache.demand_hits 627 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 4592000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.115656 # miss rate for demand accesses +system.cpu.dcache.demand_misses 82 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 4929000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.131171 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 93 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_miss_latency 4346000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.115656 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 82 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.011615 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 47.575114 # Average occupied blocks per context +system.cpu.dcache.occ_%::0 0.011577 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 47.418751 # Average occupied blocks per context system.cpu.dcache.overall_accesses 709 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 56000 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 616 # number of overall hits -system.cpu.dcache.overall_miss_latency 5208000 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.131171 # miss rate for overall accesses -system.cpu.dcache.overall_misses 93 # number of overall misses +system.cpu.dcache.overall_hits 627 # number of overall hits +system.cpu.dcache.overall_miss_latency 4592000 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.115656 # miss rate for overall accesses +system.cpu.dcache.overall_misses 82 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 4929000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.131171 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 93 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_miss_latency 4346000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.115656 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 82 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.sampled_refs 82 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 47.575114 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 47.418751 # Cycle average of tags in use system.cpu.dcache.total_refs 627 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks @@ -121,8 +121,8 @@ system.cpu.icache.demand_mshr_misses 163 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.039276 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 80.437325 # Average occupied blocks per context +system.cpu.icache.occ_%::0 0.039064 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 80.003762 # Average occupied blocks per context system.cpu.icache.overall_accesses 2586 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency @@ -140,7 +140,7 @@ system.cpu.icache.overall_mshr_uncacheable_misses 0 system.cpu.icache.replacements 0 # number of replacements system.cpu.icache.sampled_refs 163 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 80.437325 # Cycle average of tags in use +system.cpu.icache.tagsinuse 80.003762 # Cycle average of tags in use system.cpu.icache.total_refs 2423 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks @@ -179,15 +179,6 @@ system.cpu.l2cache.ReadReq_misses 218 # nu system.cpu.l2cache.ReadReq_mshr_miss_latency 8720000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 218 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_accesses 11 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 52000 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 572000 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_misses 11 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 440000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_misses 11 # number of UpgradeReq MSHR misses system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_refs 0 # Average number of references to valid blocks. @@ -210,8 +201,8 @@ system.cpu.l2cache.demand_mshr_misses 245 # nu system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.003139 # Average percentage of cache occupancy -system.cpu.l2cache.occ_blocks::0 102.857609 # Average occupied blocks per context +system.cpu.l2cache.occ_%::0 0.003268 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 107.101205 # Average occupied blocks per context system.cpu.l2cache.overall_accesses 245 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency @@ -227,14 +218,14 @@ system.cpu.l2cache.overall_mshr_misses 245 # nu system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 207 # Sample count of references to valid blocks. +system.cpu.l2cache.sampled_refs 218 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 102.857609 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 107.101205 # Cycle average of tags in use system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 34748 # number of cpu cycles simulated +system.cpu.numCycles 33538 # number of cpu cycles simulated system.cpu.num_insts 2577 # Number of instructions executed system.cpu.num_refs 717 # Number of memory references system.cpu.workload.PROG:num_syscalls 4 # Number of system calls |