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-rw-r--r--tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt28
-rw-r--r--tests/quick/00.hello/ref/alpha/linux/o3-timing/stderr9
-rw-r--r--tests/quick/00.hello/ref/alpha/linux/o3-timing/stdout4
-rw-r--r--tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.ini1
-rw-r--r--tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.out1
-rw-r--r--tests/quick/00.hello/ref/alpha/linux/simple-atomic/m5stats.txt8
-rw-r--r--tests/quick/00.hello/ref/alpha/linux/simple-atomic/stdout4
-rw-r--r--tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini1
-rw-r--r--tests/quick/00.hello/ref/alpha/linux/simple-timing/config.out1
-rw-r--r--tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt28
-rw-r--r--tests/quick/00.hello/ref/alpha/linux/simple-timing/stdout4
-rw-r--r--tests/quick/00.hello/ref/alpha/tru64/o3-timing/m5stats.txt8
-rw-r--r--tests/quick/00.hello/ref/alpha/tru64/o3-timing/stdout4
-rw-r--r--tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.ini1
-rw-r--r--tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.out1
-rw-r--r--tests/quick/00.hello/ref/alpha/tru64/simple-atomic/m5stats.txt8
-rw-r--r--tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stdout4
-rw-r--r--tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini1
-rw-r--r--tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.out1
-rw-r--r--tests/quick/00.hello/ref/alpha/tru64/simple-timing/m5stats.txt8
-rw-r--r--tests/quick/00.hello/ref/alpha/tru64/simple-timing/stdout4
21 files changed, 71 insertions, 58 deletions
diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt b/tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt
index c2c9affca..59cda42d9 100644
--- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt
+++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt
@@ -8,10 +8,10 @@ global.BPredUnit.condIncorrect 420 # Nu
global.BPredUnit.condPredicted 1302 # Number of conditional branches predicted
global.BPredUnit.lookups 2254 # Number of BP lookups
global.BPredUnit.usedRAS 291 # Number of times the RAS was used to get a target.
-host_inst_rate 47059 # Simulator instruction rate (inst/s)
-host_mem_usage 160380 # Number of bytes of host memory used
+host_inst_rate 46995 # Simulator instruction rate (inst/s)
+host_mem_usage 160420 # Number of bytes of host memory used
host_seconds 0.12 # Real time elapsed on the host
-host_tick_rate 57322 # Simulator tick rate (ticks/s)
+host_tick_rate 57256 # Simulator tick rate (ticks/s)
memdepunit.memDep.conflictingLoads 12 # Number of conflicting loads.
memdepunit.memDep.conflictingStores 259 # Number of conflicting stores.
memdepunit.memDep.insertedLoads 2049 # Number of loads inserted to the mem dependence unit.
@@ -334,41 +334,39 @@ system.cpu.l2cache.ReadReq_misses 492 # nu
system.cpu.l2cache.ReadReq_mshr_miss_latency 492 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.995951 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 492 # number of ReadReq MSHR misses
-system.cpu.l2cache.WriteReq_accesses 2 # number of WriteReq accesses(hits+misses)
-system.cpu.l2cache.WriteReq_hits 2 # number of WriteReq hits
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs 0.008130 # Average number of references to valid blocks.
+system.cpu.l2cache.avg_refs 0.004065 # Average number of references to valid blocks.
system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.demand_accesses 496 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses 494 # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency 2.071138 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 1 # average overall mshr miss latency
-system.cpu.l2cache.demand_hits 4 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency 1019 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate 0.991935 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate 0.995951 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 492 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_miss_latency 492 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate 0.991935 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate 0.995951 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 492 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.overall_accesses 496 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses 494 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 2.071138 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 1 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits 4 # number of overall hits
+system.cpu.l2cache.overall_hits 2 # number of overall hits
system.cpu.l2cache.overall_miss_latency 1019 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate 0.991935 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate 0.995951 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 492 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_miss_latency 492 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate 0.991935 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate 0.995951 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 492 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
@@ -385,7 +383,7 @@ system.cpu.l2cache.replacements 0 # nu
system.cpu.l2cache.sampled_refs 492 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.tagsinuse 290.948901 # Cycle average of tags in use
-system.cpu.l2cache.total_refs 4 # Total number of references to valid blocks.
+system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 0 # number of writebacks
system.cpu.numCycles 6869 # number of cpu cycles simulated
diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/stderr b/tests/quick/00.hello/ref/alpha/linux/o3-timing/stderr
index 8893caac8..558105896 100644
--- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/stderr
+++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/stderr
@@ -1,3 +1,12 @@
warn: Entering event queue @ 0. Starting simulation...
warn: cycle 0: fault (page_table_fault) detected @ PC 0x000000
warn: Increasing stack 0x11ff92000:0x11ff9b000 to 0x11ff90000:0x11ff9b000 because of access to 0x11ff91ff0
+warn: Default fetch doesn't update it's state from a functional call.
+warn: Default fetch doesn't update it's state from a functional call.
+warn: Default fetch doesn't update it's state from a functional call.
+warn: Default fetch doesn't update it's state from a functional call.
+warn: Default fetch doesn't update it's state from a functional call.
+warn: Default fetch doesn't update it's state from a functional call.
+warn: Default fetch doesn't update it's state from a functional call.
+warn: Default fetch doesn't update it's state from a functional call.
+warn: Default fetch doesn't update it's state from a functional call.
diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/stdout b/tests/quick/00.hello/ref/alpha/linux/o3-timing/stdout
index 14ef519e9..f2a1151c4 100644
--- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/stdout
+++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/stdout
@@ -6,8 +6,8 @@ The Regents of The University of Michigan
All Rights Reserved
-M5 compiled Oct 7 2006 12:38:12
-M5 started Sat Oct 7 12:38:34 2006
+M5 compiled Oct 8 2006 20:54:51
+M5 started Sun Oct 8 20:55:10 2006
M5 executing on zizzer.eecs.umich.edu
command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/o3-timing tests/run.py quick/00.hello/alpha/linux/o3-timing
Exiting @ tick 6868 because target called exit()
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.ini b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.ini
index f7e73950d..7340cc079 100644
--- a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.ini
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.ini
@@ -56,6 +56,7 @@ physmem=system.physmem
type=AtomicSimpleCPU
children=workload
clock=1
+cpu_id=0
defer_registration=false
function_trace=false
function_trace_start=0
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.out b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.out
index 198d7df5e..73f91ff61 100644
--- a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.out
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.out
@@ -44,6 +44,7 @@ max_loads_all_threads=0
progress_interval=0
mem=system.physmem
system=system
+cpu_id=0
workload=system.cpu.workload
clock=1
defer_registration=false
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/m5stats.txt b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/m5stats.txt
index e3cd05fb0..875e55644 100644
--- a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/m5stats.txt
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/m5stats.txt
@@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 74000 # Simulator instruction rate (inst/s)
-host_mem_usage 148088 # Number of bytes of host memory used
-host_seconds 0.08 # Real time elapsed on the host
-host_tick_rate 73591 # Simulator tick rate (ticks/s)
+host_inst_rate 172802 # Simulator instruction rate (inst/s)
+host_mem_usage 148116 # Number of bytes of host memory used
+host_seconds 0.03 # Real time elapsed on the host
+host_tick_rate 170614 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 5642 # Number of instructions simulated
sim_seconds 0.000000 # Number of seconds simulated
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stdout b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stdout
index e26480539..59f571aaf 100644
--- a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stdout
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stdout
@@ -6,8 +6,8 @@ The Regents of The University of Michigan
All Rights Reserved
-M5 compiled Oct 7 2006 11:12:49
-M5 started Sat Oct 7 11:13:02 2006
+M5 compiled Oct 8 2006 14:00:39
+M5 started Sun Oct 8 14:00:50 2006
M5 executing on zizzer.eecs.umich.edu
command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/simple-atomic tests/run.py quick/00.hello/alpha/linux/simple-atomic
Exiting @ tick 5641 because target called exit()
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini b/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini
index cefcf7f11..7b517abc8 100644
--- a/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini
@@ -56,6 +56,7 @@ physmem=system.physmem
type=TimingSimpleCPU
children=dcache icache l2cache toL2Bus workload
clock=1
+cpu_id=0
defer_registration=false
function_trace=false
function_trace_start=0
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.out b/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.out
index 1ed18ff71..5c4c7fb14 100644
--- a/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.out
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.out
@@ -83,6 +83,7 @@ max_loads_all_threads=0
progress_interval=0
mem=system.cpu.dcache
system=system
+cpu_id=0
workload=system.cpu.workload
clock=1
defer_registration=false
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt b/tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt
index 97d39456e..2ee3181d8 100644
--- a/tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt
@@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 286207 # Simulator instruction rate (inst/s)
-host_mem_usage 159648 # Number of bytes of host memory used
+host_inst_rate 292635 # Simulator instruction rate (inst/s)
+host_mem_usage 159688 # Number of bytes of host memory used
host_seconds 0.02 # Real time elapsed on the host
-host_tick_rate 413300 # Simulator tick rate (ticks/s)
+host_tick_rate 422303 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 5642 # Number of instructions simulated
sim_seconds 0.000000 # Number of seconds simulated
@@ -153,41 +153,39 @@ system.cpu.l2cache.ReadReq_misses 441 # nu
system.cpu.l2cache.ReadReq_mshr_miss_latency 441 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.997738 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 441 # number of ReadReq MSHR misses
-system.cpu.l2cache.WriteReq_accesses 2 # number of WriteReq accesses(hits+misses)
-system.cpu.l2cache.WriteReq_hits 2 # number of WriteReq hits
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs 0.006803 # Average number of references to valid blocks.
+system.cpu.l2cache.avg_refs 0.002268 # Average number of references to valid blocks.
system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.demand_accesses 444 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses 442 # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency 2 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 1 # average overall mshr miss latency
-system.cpu.l2cache.demand_hits 3 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits 1 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency 882 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate 0.993243 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate 0.997738 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 441 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_miss_latency 441 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate 0.993243 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate 0.997738 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 441 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.overall_accesses 444 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses 442 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 2 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 1 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits 3 # number of overall hits
+system.cpu.l2cache.overall_hits 1 # number of overall hits
system.cpu.l2cache.overall_miss_latency 882 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate 0.993243 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate 0.997738 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 441 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_miss_latency 441 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate 0.993243 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate 0.997738 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 441 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
@@ -204,7 +202,7 @@ system.cpu.l2cache.replacements 0 # nu
system.cpu.l2cache.sampled_refs 441 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.tagsinuse 240.276061 # Cycle average of tags in use
-system.cpu.l2cache.total_refs 3 # Total number of references to valid blocks.
+system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 0 # number of writebacks
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing/stdout b/tests/quick/00.hello/ref/alpha/linux/simple-timing/stdout
index a9c37a14d..be8eccb38 100644
--- a/tests/quick/00.hello/ref/alpha/linux/simple-timing/stdout
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing/stdout
@@ -6,8 +6,8 @@ The Regents of The University of Michigan
All Rights Reserved
-M5 compiled Oct 7 2006 12:38:12
-M5 started Sat Oct 7 12:38:38 2006
+M5 compiled Oct 8 2006 14:00:39
+M5 started Sun Oct 8 14:00:50 2006
M5 executing on zizzer.eecs.umich.edu
command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/simple-timing tests/run.py quick/00.hello/alpha/linux/simple-timing
Exiting @ tick 8316 because target called exit()
diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/m5stats.txt b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/m5stats.txt
index 53d94a43f..41348bbfb 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/m5stats.txt
+++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/m5stats.txt
@@ -8,10 +8,10 @@ global.BPredUnit.condIncorrect 222 # Nu
global.BPredUnit.condPredicted 441 # Number of conditional branches predicted
global.BPredUnit.lookups 888 # Number of BP lookups
global.BPredUnit.usedRAS 160 # Number of times the RAS was used to get a target.
-host_inst_rate 45832 # Simulator instruction rate (inst/s)
-host_mem_usage 159900 # Number of bytes of host memory used
-host_seconds 0.05 # Real time elapsed on the host
-host_tick_rate 55090 # Simulator tick rate (ticks/s)
+host_inst_rate 26386 # Simulator instruction rate (inst/s)
+host_mem_usage 159884 # Number of bytes of host memory used
+host_seconds 0.09 # Real time elapsed on the host
+host_tick_rate 31792 # Simulator tick rate (ticks/s)
memdepunit.memDep.conflictingLoads 9 # Number of conflicting loads.
memdepunit.memDep.conflictingStores 7 # Number of conflicting stores.
memdepunit.memDep.insertedLoads 675 # Number of loads inserted to the mem dependence unit.
diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stdout b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stdout
index fa94f7eb9..c51631489 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stdout
+++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stdout
@@ -6,8 +6,8 @@ The Regents of The University of Michigan
All Rights Reserved
-M5 compiled Oct 7 2006 12:38:12
-M5 started Sat Oct 7 12:38:40 2006
+M5 compiled Oct 8 2006 14:00:39
+M5 started Sun Oct 8 14:00:52 2006
M5 executing on zizzer.eecs.umich.edu
command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/tru64/o3-timing tests/run.py quick/00.hello/alpha/tru64/o3-timing
Exiting @ tick 2886 because target called exit()
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.ini b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.ini
index 34f5c0b32..f248945b1 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.ini
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.ini
@@ -56,6 +56,7 @@ physmem=system.physmem
type=AtomicSimpleCPU
children=workload
clock=1
+cpu_id=0
defer_registration=false
function_trace=false
function_trace_start=0
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.out b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.out
index a474765ae..58ae0d9df 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.out
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.out
@@ -44,6 +44,7 @@ max_loads_all_threads=0
progress_interval=0
mem=system.physmem
system=system
+cpu_id=0
workload=system.cpu.workload
clock=1
defer_registration=false
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/m5stats.txt b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/m5stats.txt
index b120e12b9..e3f845135 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/m5stats.txt
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/m5stats.txt
@@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 548861 # Simulator instruction rate (inst/s)
-host_mem_usage 147820 # Number of bytes of host memory used
-host_seconds 0.01 # Real time elapsed on the host
-host_tick_rate 504404 # Simulator tick rate (ticks/s)
+host_inst_rate 60702 # Simulator instruction rate (inst/s)
+host_mem_usage 147692 # Number of bytes of host memory used
+host_seconds 0.04 # Real time elapsed on the host
+host_tick_rate 60102 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 2578 # Number of instructions simulated
sim_seconds 0.000000 # Number of seconds simulated
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stdout b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stdout
index 0c9b00960..2ee4e0a08 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stdout
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stdout
@@ -6,8 +6,8 @@ The Regents of The University of Michigan
All Rights Reserved
-M5 compiled Oct 7 2006 11:12:49
-M5 started Sat Oct 7 11:13:09 2006
+M5 compiled Oct 8 2006 14:00:39
+M5 started Sun Oct 8 14:00:54 2006
M5 executing on zizzer.eecs.umich.edu
command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/tru64/simple-atomic tests/run.py quick/00.hello/alpha/tru64/simple-atomic
Exiting @ tick 2577 because target called exit()
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini
index 0d7d34e64..5616cf909 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini
@@ -56,6 +56,7 @@ physmem=system.physmem
type=TimingSimpleCPU
children=dcache icache l2cache toL2Bus workload
clock=1
+cpu_id=0
defer_registration=false
function_trace=false
function_trace_start=0
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.out b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.out
index 9b44f8ddd..c76e14e2c 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.out
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.out
@@ -83,6 +83,7 @@ max_loads_all_threads=0
progress_interval=0
mem=system.cpu.dcache
system=system
+cpu_id=0
workload=system.cpu.workload
clock=1
defer_registration=false
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/m5stats.txt b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/m5stats.txt
index 916f9dad8..39ef8ead8 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/m5stats.txt
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/m5stats.txt
@@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 196989 # Simulator instruction rate (inst/s)
-host_mem_usage 159172 # Number of bytes of host memory used
-host_seconds 0.01 # Real time elapsed on the host
-host_tick_rate 279840 # Simulator tick rate (ticks/s)
+host_inst_rate 69262 # Simulator instruction rate (inst/s)
+host_mem_usage 159156 # Number of bytes of host memory used
+host_seconds 0.04 # Real time elapsed on the host
+host_tick_rate 100319 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 2578 # Number of instructions simulated
sim_seconds 0.000000 # Number of seconds simulated
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stdout b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stdout
index d152dc89c..27e317357 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stdout
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stdout
@@ -6,8 +6,8 @@ The Regents of The University of Michigan
All Rights Reserved
-M5 compiled Oct 7 2006 12:38:12
-M5 started Sat Oct 7 12:38:45 2006
+M5 compiled Oct 8 2006 14:00:39
+M5 started Sun Oct 8 14:00:54 2006
M5 executing on zizzer.eecs.umich.edu
command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/tru64/simple-timing tests/run.py quick/00.hello/alpha/tru64/simple-timing
Exiting @ tick 3777 because target called exit()