summaryrefslogtreecommitdiff
path: root/tests/quick/00.hello/ref/alpha
diff options
context:
space:
mode:
Diffstat (limited to 'tests/quick/00.hello/ref/alpha')
-rw-r--r--tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini12
-rwxr-xr-xtests/quick/00.hello/ref/alpha/linux/o3-timing/simerr4
-rwxr-xr-xtests/quick/00.hello/ref/alpha/linux/o3-timing/simout10
-rw-r--r--tests/quick/00.hello/ref/alpha/linux/o3-timing/stats.txt35
-rw-r--r--tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.ini3
-rwxr-xr-xtests/quick/00.hello/ref/alpha/linux/simple-atomic/simerr4
-rwxr-xr-xtests/quick/00.hello/ref/alpha/linux/simple-atomic/simout10
-rw-r--r--tests/quick/00.hello/ref/alpha/linux/simple-atomic/stats.txt8
-rw-r--r--tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini12
-rwxr-xr-xtests/quick/00.hello/ref/alpha/linux/simple-timing/simerr4
-rwxr-xr-xtests/quick/00.hello/ref/alpha/linux/simple-timing/simout10
-rw-r--r--tests/quick/00.hello/ref/alpha/linux/simple-timing/stats.txt35
-rw-r--r--tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini12
-rwxr-xr-xtests/quick/00.hello/ref/alpha/tru64/o3-timing/simerr5
-rwxr-xr-xtests/quick/00.hello/ref/alpha/tru64/o3-timing/simout10
-rw-r--r--tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt35
-rw-r--r--tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.ini3
-rwxr-xr-xtests/quick/00.hello/ref/alpha/tru64/simple-atomic/simerr5
-rwxr-xr-xtests/quick/00.hello/ref/alpha/tru64/simple-atomic/simout10
-rw-r--r--tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stats.txt8
-rw-r--r--tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini12
-rwxr-xr-xtests/quick/00.hello/ref/alpha/tru64/simple-timing/simerr5
-rwxr-xr-xtests/quick/00.hello/ref/alpha/tru64/simple-timing/simout10
-rw-r--r--tests/quick/00.hello/ref/alpha/tru64/simple-timing/stats.txt33
24 files changed, 98 insertions, 197 deletions
diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini b/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini
index 3764c941e..46ef9d2b9 100644
--- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini
+++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini
@@ -22,6 +22,7 @@ SSITSize=1024
activity=0
backComSize=5
cachePorts=200
+checker=Null
choiceCtrBits=2
choicePredictorSize=8192
clock=500
@@ -36,6 +37,8 @@ decodeToRenameDelay=1
decodeWidth=8
defer_registration=false
dispatchWidth=8
+do_checkpoint_insts=true
+do_statistics_insts=true
dtb=system.cpu.dtb
fetchToDecodeDelay=1
fetchTrapLatency=1
@@ -107,12 +110,11 @@ latency=1000
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
-prefetch_access=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10000
-prefetch_miss=false
+prefetch_on_access=false
prefetch_past_page=false
prefetch_policy=none
prefetch_serial_squash=false
@@ -281,12 +283,11 @@ latency=1000
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
-prefetch_access=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10000
-prefetch_miss=false
+prefetch_on_access=false
prefetch_past_page=false
prefetch_policy=none
prefetch_serial_squash=false
@@ -318,12 +319,11 @@ latency=1000
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
-prefetch_access=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10000
-prefetch_miss=false
+prefetch_on_access=false
prefetch_past_page=false
prefetch_policy=none
prefetch_serial_squash=false
diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/simerr b/tests/quick/00.hello/ref/alpha/linux/o3-timing/simerr
index 5ff857a03..eabe42249 100755
--- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/simerr
+++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/simerr
@@ -1,3 +1,3 @@
warn: Sockets disabled, not accepting gdb connections
-warn: Increasing stack size by one page.
-warn: be nice to actually delete the event here
+For more information see: http://www.m5sim.org/warn/d946bea6
+hack: be nice to actually delete the event here
diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/simout b/tests/quick/00.hello/ref/alpha/linux/o3-timing/simout
index b502697af..0d9f81ac8 100755
--- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/simout
+++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/simout
@@ -5,13 +5,13 @@ The Regents of The University of Michigan
All Rights Reserved
-M5 compiled Dec 4 2008 21:21:43
-M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652
-M5 commit date Thu Dec 04 18:04:32 2008 -0500
-M5 started Dec 4 2008 21:21:44
+M5 compiled Feb 16 2009 00:22:05
+M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase
+M5 started Feb 16 2009 00:22:12
M5 executing on zizzer
-command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/o3-timing -re --stdout-file stdout --stderr-file stderr tests/run.py quick/00.hello/alpha/linux/o3-timing
+command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/o3-timing -re tests/run.py quick/00.hello/alpha/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
+info: Increasing stack size by one page.
Hello world!
Exiting @ tick 12474500 because target called exit()
diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/00.hello/ref/alpha/linux/o3-timing/stats.txt
index 93747295c..b0c4635e4 100644
--- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/stats.txt
+++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/stats.txt
@@ -8,10 +8,10 @@ global.BPredUnit.condIncorrect 440 # Nu
global.BPredUnit.condPredicted 1370 # Number of conditional branches predicted
global.BPredUnit.lookups 2263 # Number of BP lookups
global.BPredUnit.usedRAS 304 # Number of times the RAS was used to get a target.
-host_inst_rate 7058 # Simulator instruction rate (inst/s)
-host_mem_usage 199016 # Number of bytes of host memory used
-host_seconds 0.90 # Real time elapsed on the host
-host_tick_rate 13784618 # Simulator tick rate (ticks/s)
+host_inst_rate 68343 # Simulator instruction rate (inst/s)
+host_mem_usage 200684 # Number of bytes of host memory used
+host_seconds 0.09 # Real time elapsed on the host
+host_tick_rate 133183507 # Simulator tick rate (ticks/s)
memdepunit.memDep.conflictingLoads 36 # Number of conflicting loads.
memdepunit.memDep.conflictingStores 29 # Number of conflicting stores.
memdepunit.memDep.insertedLoads 2287 # Number of loads inserted to the mem dependence unit.
@@ -109,15 +109,6 @@ system.cpu.dcache.overall_mshr_miss_rate 0.070730 # ms
system.cpu.dcache.overall_mshr_misses 188 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.dcache.replacements 0 # number of replacements
system.cpu.dcache.sampled_refs 174 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
@@ -218,15 +209,6 @@ system.cpu.icache.overall_mshr_miss_rate 0.170366 # ms
system.cpu.icache.overall_mshr_misses 307 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.icache.replacements 0 # number of replacements
system.cpu.icache.sampled_refs 307 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
@@ -405,15 +387,6 @@ system.cpu.l2cache.overall_mshr_miss_rate 0.997921 # m
system.cpu.l2cache.overall_mshr_misses 480 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.sampled_refs 393 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.ini b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.ini
index f3b922bb8..5b4a31473 100644
--- a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.ini
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.ini
@@ -12,9 +12,12 @@ physmem=system.physmem
[system.cpu]
type=AtomicSimpleCPU
children=dtb itb tracer workload
+checker=Null
clock=500
cpu_id=0
defer_registration=false
+do_checkpoint_insts=true
+do_statistics_insts=true
dtb=system.cpu.dtb
function_trace=false
function_trace_start=0
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/simerr b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/simerr
index 5ff857a03..eabe42249 100755
--- a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/simerr
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/simerr
@@ -1,3 +1,3 @@
warn: Sockets disabled, not accepting gdb connections
-warn: Increasing stack size by one page.
-warn: be nice to actually delete the event here
+For more information see: http://www.m5sim.org/warn/d946bea6
+hack: be nice to actually delete the event here
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/simout b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/simout
index 9a255c446..8975ff812 100755
--- a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/simout
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/simout
@@ -5,13 +5,13 @@ The Regents of The University of Michigan
All Rights Reserved
-M5 compiled Dec 4 2008 21:21:43
-M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652
-M5 commit date Thu Dec 04 18:04:32 2008 -0500
-M5 started Dec 4 2008 21:21:44
+M5 compiled Feb 16 2009 00:22:05
+M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase
+M5 started Feb 16 2009 00:22:12
M5 executing on zizzer
-command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py quick/00.hello/alpha/linux/simple-atomic
+command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-atomic -re tests/run.py quick/00.hello/alpha/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
+info: Increasing stack size by one page.
Hello world!
Exiting @ tick 3215000 because target called exit()
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stats.txt b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stats.txt
index 712fc898c..93917b1eb 100644
--- a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stats.txt
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stats.txt
@@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 6758 # Simulator instruction rate (inst/s)
-host_mem_usage 190848 # Number of bytes of host memory used
-host_seconds 0.95 # Real time elapsed on the host
-host_tick_rate 3391912 # Simulator tick rate (ticks/s)
+host_inst_rate 122377 # Simulator instruction rate (inst/s)
+host_mem_usage 192524 # Number of bytes of host memory used
+host_seconds 0.05 # Real time elapsed on the host
+host_tick_rate 61135620 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 6404 # Number of instructions simulated
sim_seconds 0.000003 # Number of seconds simulated
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini b/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini
index 0b9f96b2e..26edcc7cf 100644
--- a/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini
@@ -12,9 +12,12 @@ physmem=system.physmem
[system.cpu]
type=TimingSimpleCPU
children=dcache dtb icache itb l2cache toL2Bus tracer workload
+checker=Null
clock=500
cpu_id=0
defer_registration=false
+do_checkpoint_insts=true
+do_statistics_insts=true
dtb=system.cpu.dtb
function_trace=false
function_trace_start=0
@@ -43,12 +46,11 @@ latency=1000
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
-prefetch_access=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10000
-prefetch_miss=false
+prefetch_on_access=false
prefetch_past_page=false
prefetch_policy=none
prefetch_serial_squash=false
@@ -80,12 +82,11 @@ latency=1000
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
-prefetch_access=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10000
-prefetch_miss=false
+prefetch_on_access=false
prefetch_past_page=false
prefetch_policy=none
prefetch_serial_squash=false
@@ -117,12 +118,11 @@ latency=10000
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
-prefetch_access=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=100000
-prefetch_miss=false
+prefetch_on_access=false
prefetch_past_page=false
prefetch_policy=none
prefetch_serial_squash=false
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing/simerr b/tests/quick/00.hello/ref/alpha/linux/simple-timing/simerr
index 5ff857a03..eabe42249 100755
--- a/tests/quick/00.hello/ref/alpha/linux/simple-timing/simerr
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing/simerr
@@ -1,3 +1,3 @@
warn: Sockets disabled, not accepting gdb connections
-warn: Increasing stack size by one page.
-warn: be nice to actually delete the event here
+For more information see: http://www.m5sim.org/warn/d946bea6
+hack: be nice to actually delete the event here
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing/simout b/tests/quick/00.hello/ref/alpha/linux/simple-timing/simout
index c3d847e3f..22d348b2d 100755
--- a/tests/quick/00.hello/ref/alpha/linux/simple-timing/simout
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing/simout
@@ -5,13 +5,13 @@ The Regents of The University of Michigan
All Rights Reserved
-M5 compiled Dec 4 2008 21:21:43
-M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652
-M5 commit date Thu Dec 04 18:04:32 2008 -0500
-M5 started Dec 4 2008 21:21:46
+M5 compiled Feb 16 2009 00:22:05
+M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase
+M5 started Feb 16 2009 00:22:12
M5 executing on zizzer
-command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py quick/00.hello/alpha/linux/simple-timing
+command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-timing -re tests/run.py quick/00.hello/alpha/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
+info: Increasing stack size by one page.
Hello world!
Exiting @ tick 33777000 because target called exit()
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing/stats.txt b/tests/quick/00.hello/ref/alpha/linux/simple-timing/stats.txt
index f97f1c530..dc4411624 100644
--- a/tests/quick/00.hello/ref/alpha/linux/simple-timing/stats.txt
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing/stats.txt
@@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 68165 # Simulator instruction rate (inst/s)
-host_mem_usage 198212 # Number of bytes of host memory used
-host_seconds 0.09 # Real time elapsed on the host
-host_tick_rate 358563073 # Simulator tick rate (ticks/s)
+host_inst_rate 344098 # Simulator instruction rate (inst/s)
+host_mem_usage 199968 # Number of bytes of host memory used
+host_seconds 0.02 # Real time elapsed on the host
+host_tick_rate 1795121173 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 6404 # Number of instructions simulated
sim_seconds 0.000034 # Number of seconds simulated
@@ -64,15 +64,6 @@ system.cpu.dcache.overall_mshr_miss_rate 0.088780 # ms
system.cpu.dcache.overall_mshr_misses 182 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.dcache.replacements 0 # number of replacements
system.cpu.dcache.sampled_refs 168 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
@@ -138,15 +129,6 @@ system.cpu.icache.overall_mshr_miss_rate 0.043492 # ms
system.cpu.icache.overall_mshr_misses 279 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.icache.replacements 0 # number of replacements
system.cpu.icache.sampled_refs 279 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
@@ -223,15 +205,6 @@ system.cpu.l2cache.overall_mshr_miss_rate 0.997763 # m
system.cpu.l2cache.overall_mshr_misses 446 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.sampled_refs 359 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini
index 21f8bc603..9abe15dfc 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini
+++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini
@@ -22,6 +22,7 @@ SSITSize=1024
activity=0
backComSize=5
cachePorts=200
+checker=Null
choiceCtrBits=2
choicePredictorSize=8192
clock=500
@@ -36,6 +37,8 @@ decodeToRenameDelay=1
decodeWidth=8
defer_registration=false
dispatchWidth=8
+do_checkpoint_insts=true
+do_statistics_insts=true
dtb=system.cpu.dtb
fetchToDecodeDelay=1
fetchTrapLatency=1
@@ -107,12 +110,11 @@ latency=1000
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
-prefetch_access=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10000
-prefetch_miss=false
+prefetch_on_access=false
prefetch_past_page=false
prefetch_policy=none
prefetch_serial_squash=false
@@ -281,12 +283,11 @@ latency=1000
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
-prefetch_access=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10000
-prefetch_miss=false
+prefetch_on_access=false
prefetch_past_page=false
prefetch_policy=none
prefetch_serial_squash=false
@@ -318,12 +319,11 @@ latency=1000
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
-prefetch_access=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10000
-prefetch_miss=false
+prefetch_on_access=false
prefetch_past_page=false
prefetch_policy=none
prefetch_serial_squash=false
diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/simerr b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/simerr
index 28251ddf8..bb8489f81 100755
--- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/simerr
+++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/simerr
@@ -1,4 +1,5 @@
warn: Sockets disabled, not accepting gdb connections
-warn: Increasing stack size by one page.
+For more information see: http://www.m5sim.org/warn/d946bea6
warn: ignoring syscall sigprocmask(1, 18446744073709547831, ...)
-warn: be nice to actually delete the event here
+For more information see: http://www.m5sim.org/warn/5c5b547f
+hack: be nice to actually delete the event here
diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/simout b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/simout
index e4872d461..d373e353b 100755
--- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/simout
+++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/simout
@@ -5,13 +5,13 @@ The Regents of The University of Michigan
All Rights Reserved
-M5 compiled Dec 4 2008 21:21:43
-M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652
-M5 commit date Thu Dec 04 18:04:32 2008 -0500
-M5 started Dec 4 2008 21:29:52
+M5 compiled Feb 16 2009 00:22:05
+M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase
+M5 started Feb 16 2009 00:22:12
M5 executing on zizzer
-command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/o3-timing -re --stdout-file stdout --stderr-file stderr tests/run.py quick/00.hello/alpha/tru64/o3-timing
+command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/o3-timing -re tests/run.py quick/00.hello/alpha/tru64/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
+info: Increasing stack size by one page.
Hello world!
Exiting @ tick 7183000 because target called exit()
diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt
index 12af7d1b2..af633c5e8 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt
+++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt
@@ -8,10 +8,10 @@ global.BPredUnit.condIncorrect 209 # Nu
global.BPredUnit.condPredicted 447 # Number of conditional branches predicted
global.BPredUnit.lookups 859 # Number of BP lookups
global.BPredUnit.usedRAS 165 # Number of times the RAS was used to get a target.
-host_inst_rate 31288 # Simulator instruction rate (inst/s)
-host_mem_usage 198012 # Number of bytes of host memory used
-host_seconds 0.08 # Real time elapsed on the host
-host_tick_rate 93885607 # Simulator tick rate (ticks/s)
+host_inst_rate 22600 # Simulator instruction rate (inst/s)
+host_mem_usage 199684 # Number of bytes of host memory used
+host_seconds 0.11 # Real time elapsed on the host
+host_tick_rate 67889683 # Simulator tick rate (ticks/s)
memdepunit.memDep.conflictingLoads 7 # Number of conflicting loads.
memdepunit.memDep.conflictingStores 7 # Number of conflicting stores.
memdepunit.memDep.insertedLoads 738 # Number of loads inserted to the mem dependence unit.
@@ -109,15 +109,6 @@ system.cpu.dcache.overall_mshr_miss_rate 0.113033 # ms
system.cpu.dcache.overall_mshr_misses 98 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.dcache.replacements 0 # number of replacements
system.cpu.dcache.sampled_refs 85 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
@@ -218,15 +209,6 @@ system.cpu.icache.overall_mshr_miss_rate 0.242303 # ms
system.cpu.icache.overall_mshr_misses 181 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.icache.replacements 0 # number of replacements
system.cpu.icache.sampled_refs 181 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
@@ -404,15 +386,6 @@ system.cpu.l2cache.overall_mshr_miss_rate 1 # m
system.cpu.l2cache.overall_mshr_misses 266 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.sampled_refs 228 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.ini b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.ini
index bbdfaa101..8ca1fff45 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.ini
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.ini
@@ -12,9 +12,12 @@ physmem=system.physmem
[system.cpu]
type=AtomicSimpleCPU
children=dtb itb tracer workload
+checker=Null
clock=500
cpu_id=0
defer_registration=false
+do_checkpoint_insts=true
+do_statistics_insts=true
dtb=system.cpu.dtb
function_trace=false
function_trace_start=0
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/simerr b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/simerr
index 28251ddf8..bb8489f81 100755
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/simerr
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/simerr
@@ -1,4 +1,5 @@
warn: Sockets disabled, not accepting gdb connections
-warn: Increasing stack size by one page.
+For more information see: http://www.m5sim.org/warn/d946bea6
warn: ignoring syscall sigprocmask(1, 18446744073709547831, ...)
-warn: be nice to actually delete the event here
+For more information see: http://www.m5sim.org/warn/5c5b547f
+hack: be nice to actually delete the event here
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/simout b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/simout
index 55a4a98f7..7c13e1d4c 100755
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/simout
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/simout
@@ -5,13 +5,13 @@ The Regents of The University of Michigan
All Rights Reserved
-M5 compiled Dec 4 2008 21:21:43
-M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652
-M5 commit date Thu Dec 04 18:04:32 2008 -0500
-M5 started Dec 4 2008 21:24:43
+M5 compiled Feb 16 2009 00:22:05
+M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase
+M5 started Feb 16 2009 00:22:12
M5 executing on zizzer
-command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py quick/00.hello/alpha/tru64/simple-atomic
+command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-atomic -re tests/run.py quick/00.hello/alpha/tru64/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
+info: Increasing stack size by one page.
Hello world!
Exiting @ tick 1297500 because target called exit()
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stats.txt b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stats.txt
index 051f6dec4..ddfd1ad69 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stats.txt
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stats.txt
@@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 334328 # Simulator instruction rate (inst/s)
-host_mem_usage 189900 # Number of bytes of host memory used
-host_seconds 0.01 # Real time elapsed on the host
-host_tick_rate 162370166 # Simulator tick rate (ticks/s)
+host_inst_rate 147781 # Simulator instruction rate (inst/s)
+host_mem_usage 191596 # Number of bytes of host memory used
+host_seconds 0.02 # Real time elapsed on the host
+host_tick_rate 73371409 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 2577 # Number of instructions simulated
sim_seconds 0.000001 # Number of seconds simulated
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini
index 6a2eadca9..f0bdf09de 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini
@@ -12,9 +12,12 @@ physmem=system.physmem
[system.cpu]
type=TimingSimpleCPU
children=dcache dtb icache itb l2cache toL2Bus tracer workload
+checker=Null
clock=500
cpu_id=0
defer_registration=false
+do_checkpoint_insts=true
+do_statistics_insts=true
dtb=system.cpu.dtb
function_trace=false
function_trace_start=0
@@ -43,12 +46,11 @@ latency=1000
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
-prefetch_access=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10000
-prefetch_miss=false
+prefetch_on_access=false
prefetch_past_page=false
prefetch_policy=none
prefetch_serial_squash=false
@@ -80,12 +82,11 @@ latency=1000
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
-prefetch_access=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10000
-prefetch_miss=false
+prefetch_on_access=false
prefetch_past_page=false
prefetch_policy=none
prefetch_serial_squash=false
@@ -117,12 +118,11 @@ latency=10000
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
-prefetch_access=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=100000
-prefetch_miss=false
+prefetch_on_access=false
prefetch_past_page=false
prefetch_policy=none
prefetch_serial_squash=false
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/simerr b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/simerr
index 28251ddf8..bb8489f81 100755
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/simerr
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/simerr
@@ -1,4 +1,5 @@
warn: Sockets disabled, not accepting gdb connections
-warn: Increasing stack size by one page.
+For more information see: http://www.m5sim.org/warn/d946bea6
warn: ignoring syscall sigprocmask(1, 18446744073709547831, ...)
-warn: be nice to actually delete the event here
+For more information see: http://www.m5sim.org/warn/5c5b547f
+hack: be nice to actually delete the event here
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/simout b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/simout
index 779993228..3560f6496 100755
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/simout
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/simout
@@ -5,13 +5,13 @@ The Regents of The University of Michigan
All Rights Reserved
-M5 compiled Dec 4 2008 21:21:43
-M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652
-M5 commit date Thu Dec 04 18:04:32 2008 -0500
-M5 started Dec 4 2008 21:21:46
+M5 compiled Feb 16 2009 00:22:05
+M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase
+M5 started Feb 16 2009 00:22:12
M5 executing on zizzer
-command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py quick/00.hello/alpha/tru64/simple-timing
+command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-timing -re tests/run.py quick/00.hello/alpha/tru64/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
+info: Increasing stack size by one page.
Hello world!
Exiting @ tick 17374000 because target called exit()
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stats.txt b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stats.txt
index af7d3609f..5c25b785f 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stats.txt
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stats.txt
@@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 59950 # Simulator instruction rate (inst/s)
-host_mem_usage 197352 # Number of bytes of host memory used
+host_inst_rate 73131 # Simulator instruction rate (inst/s)
+host_mem_usage 199016 # Number of bytes of host memory used
host_seconds 0.04 # Real time elapsed on the host
-host_tick_rate 402241104 # Simulator tick rate (ticks/s)
+host_tick_rate 490513834 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 2577 # Number of instructions simulated
sim_seconds 0.000017 # Number of seconds simulated
@@ -64,15 +64,6 @@ system.cpu.dcache.overall_mshr_miss_rate 0.131171 # ms
system.cpu.dcache.overall_mshr_misses 93 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.dcache.replacements 0 # number of replacements
system.cpu.dcache.sampled_refs 82 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
@@ -138,15 +129,6 @@ system.cpu.icache.overall_mshr_miss_rate 0.063032 # ms
system.cpu.icache.overall_mshr_misses 163 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.icache.replacements 0 # number of replacements
system.cpu.icache.sampled_refs 163 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
@@ -222,15 +204,6 @@ system.cpu.l2cache.overall_mshr_miss_rate 1 # m
system.cpu.l2cache.overall_mshr_misses 245 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.sampled_refs 207 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions