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-rw-r--r--tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini6
-rw-r--r--tests/quick/00.hello/ref/alpha/linux/o3-timing/config.out6
-rw-r--r--tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt14
-rw-r--r--tests/quick/00.hello/ref/alpha/linux/o3-timing/stderr1
-rw-r--r--tests/quick/00.hello/ref/alpha/linux/o3-timing/stdout8
-rw-r--r--tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini6
-rw-r--r--tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.out6
-rw-r--r--tests/quick/00.hello/ref/alpha/tru64/o3-timing/m5stats.txt12
-rw-r--r--tests/quick/00.hello/ref/alpha/tru64/o3-timing/stderr1
-rw-r--r--tests/quick/00.hello/ref/alpha/tru64/o3-timing/stdout8
10 files changed, 35 insertions, 33 deletions
diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini b/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini
index 4b0687180..2296e2545 100644
--- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini
+++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini
@@ -7,9 +7,6 @@ max_tick=0
output_file=cout
progress_interval=0
-[debug]
-break_cycles=
-
[exetrace]
intel_format=false
legion_lockstep=false
@@ -109,6 +106,7 @@ numPhysIntRegs=256
numROBEntries=192
numRobs=1
numThreads=1
+phase=0
predType=tournament
progress_interval=0
renameToDecodeDelay=1
@@ -390,6 +388,7 @@ port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cp
[system.cpu.workload]
type=LiveProcess
cmd=hello
+cwd=
egid=100
env=
euid=100
@@ -415,6 +414,7 @@ type=PhysicalMemory
file=
latency=1
range=0:134217727
+zero=false
port=system.membus.port[0]
[trace]
diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.out b/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.out
index e593f63c8..1b1b58f1b 100644
--- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.out
+++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.out
@@ -10,6 +10,7 @@ type=PhysicalMemory
file=
range=[0,134217727]
latency=1
+zero=false
[system]
type=System
@@ -30,6 +31,7 @@ executable=tests/test-progs/hello/bin/alpha/linux/hello
input=cin
output=cout
env=
+cwd=
system=system
uid=100
euid=100
@@ -169,6 +171,7 @@ FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUL
[system.cpu]
type=DerivO3CPU
clock=1
+phase=0
numThreads=1
activity=0
workload=system.cpu.workload
@@ -409,9 +412,6 @@ intel_format=false
legion_lockstep=false
trace_system=client
-[debug]
-break_cycles=
-
[statsreset]
reset_cycle=0
diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt b/tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt
index 8b8a25405..4e3fdbcd2 100644
--- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt
+++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt
@@ -8,10 +8,10 @@ global.BPredUnit.condIncorrect 437 # Nu
global.BPredUnit.condPredicted 1563 # Number of conditional branches predicted
global.BPredUnit.lookups 5229 # Number of BP lookups
global.BPredUnit.usedRAS 2821 # Number of times the RAS was used to get a target.
-host_inst_rate 15743 # Simulator instruction rate (inst/s)
-host_mem_usage 180184 # Number of bytes of host memory used
-host_seconds 0.36 # Real time elapsed on the host
-host_tick_rate 3916768 # Simulator tick rate (ticks/s)
+host_inst_rate 11609 # Simulator instruction rate (inst/s)
+host_mem_usage 177052 # Number of bytes of host memory used
+host_seconds 0.48 # Real time elapsed on the host
+host_tick_rate 2887871 # Simulator tick rate (ticks/s)
memdepunit.memDep.conflictingLoads 23 # Number of conflicting loads.
memdepunit.memDep.conflictingStores 117 # Number of conflicting stores.
memdepunit.memDep.insertedLoads 3775 # Number of loads inserted to the mem dependence unit.
@@ -73,7 +73,7 @@ system.cpu.dcache.WriteReq_mshr_hits 181 # nu
system.cpu.dcache.WriteReq_mshr_miss_latency 375299 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.089901 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 73 # number of WriteReq MSHR misses
-system.cpu.dcache.avg_blocked_cycles_no_mshrs no value # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles_no_targets 3366.651163 # average number of cycles each access was blocked
system.cpu.dcache.avg_refs 11.587209 # Average number of references to valid blocks.
system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
@@ -263,8 +263,8 @@ system.cpu.iew.lsq.thread.0.rescheduledLoads 1
system.cpu.iew.lsq.thread.0.squashedLoads 2796 # Number of loads squashed
system.cpu.iew.lsq.thread.0.squashedStores 2922 # Number of stores squashed
system.cpu.iew.memOrderViolationEvents 40 # Number of memory order violations
-system.cpu.iew.predictedNotTakenIncorrect 281 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.predictedTakenIncorrect 120 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 279 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.predictedTakenIncorrect 122 # Number of branches that were predicted taken incorrectly
system.cpu.ipc 0.004016 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.004016 # IPC: Total IPC of All Threads
system.cpu.iq.ISSUE:FU_type_0 13840 # Type of FU issued
diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/stderr b/tests/quick/00.hello/ref/alpha/linux/o3-timing/stderr
index 87866a2a5..eb1796ead 100644
--- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/stderr
+++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/stderr
@@ -1 +1,2 @@
+0: system.remote_gdb.listener: listening for remote gdb on port 7000
warn: Entering event queue @ 0. Starting simulation...
diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/stdout b/tests/quick/00.hello/ref/alpha/linux/o3-timing/stdout
index 4c2593f2a..511bc594d 100644
--- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/stdout
+++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/stdout
@@ -6,8 +6,8 @@ The Regents of The University of Michigan
All Rights Reserved
-M5 compiled Nov 12 2006 23:25:38
-M5 started Sun Nov 12 23:25:46 2006
-M5 executing on zizzer.eecs.umich.edu
-command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/o3-timing tests/run.py quick/00.hello/alpha/linux/o3-timing
+M5 compiled Jan 22 2007 23:06:52
+M5 started Mon Jan 22 23:06:54 2007
+M5 executing on ewok
+command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/o3-timing tests/run.py quick/00.hello/alpha/linux/o3-timing
Exiting @ tick 1400135 because target called exit()
diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini
index 724e28225..db88e7673 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini
+++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini
@@ -7,9 +7,6 @@ max_tick=0
output_file=cout
progress_interval=0
-[debug]
-break_cycles=
-
[exetrace]
intel_format=false
legion_lockstep=false
@@ -109,6 +106,7 @@ numPhysIntRegs=256
numROBEntries=192
numRobs=1
numThreads=1
+phase=0
predType=tournament
progress_interval=0
renameToDecodeDelay=1
@@ -390,6 +388,7 @@ port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cp
[system.cpu.workload]
type=LiveProcess
cmd=hello
+cwd=
egid=100
env=
euid=100
@@ -415,6 +414,7 @@ type=PhysicalMemory
file=
latency=1
range=0:134217727
+zero=false
port=system.membus.port[0]
[trace]
diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.out b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.out
index 83eecc303..9ee1931ca 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.out
+++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.out
@@ -10,6 +10,7 @@ type=PhysicalMemory
file=
range=[0,134217727]
latency=1
+zero=false
[system]
type=System
@@ -30,6 +31,7 @@ executable=tests/test-progs/hello/bin/alpha/tru64/hello
input=cin
output=cout
env=
+cwd=
system=system
uid=100
euid=100
@@ -169,6 +171,7 @@ FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUL
[system.cpu]
type=DerivO3CPU
clock=1
+phase=0
numThreads=1
activity=0
workload=system.cpu.workload
@@ -409,9 +412,6 @@ intel_format=false
legion_lockstep=false
trace_system=client
-[debug]
-break_cycles=
-
[statsreset]
reset_cycle=0
diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/m5stats.txt b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/m5stats.txt
index ce44cab28..3aae57d12 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/m5stats.txt
+++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/m5stats.txt
@@ -8,10 +8,10 @@ global.BPredUnit.condIncorrect 218 # Nu
global.BPredUnit.condPredicted 459 # Number of conditional branches predicted
global.BPredUnit.lookups 898 # Number of BP lookups
global.BPredUnit.usedRAS 171 # Number of times the RAS was used to get a target.
-host_inst_rate 19676 # Simulator instruction rate (inst/s)
-host_mem_usage 179796 # Number of bytes of host memory used
-host_seconds 0.12 # Real time elapsed on the host
-host_tick_rate 6183068 # Simulator tick rate (ticks/s)
+host_inst_rate 22132 # Simulator instruction rate (inst/s)
+host_mem_usage 176684 # Number of bytes of host memory used
+host_seconds 0.11 # Real time elapsed on the host
+host_tick_rate 6945216 # Simulator tick rate (ticks/s)
memdepunit.memDep.conflictingLoads 10 # Number of conflicting loads.
memdepunit.memDep.conflictingStores 8 # Number of conflicting stores.
memdepunit.memDep.insertedLoads 783 # Number of loads inserted to the mem dependence unit.
@@ -263,8 +263,8 @@ system.cpu.iew.lsq.thread.0.rescheduledLoads 0
system.cpu.iew.lsq.thread.0.squashedLoads 368 # Number of loads squashed
system.cpu.iew.lsq.thread.0.squashedStores 87 # Number of stores squashed
system.cpu.iew.memOrderViolationEvents 12 # Number of memory order violations
-system.cpu.iew.predictedNotTakenIncorrect 96 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.predictedTakenIncorrect 56 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 95 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.predictedTakenIncorrect 57 # Number of branches that were predicted taken incorrectly
system.cpu.ipc 0.003174 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.003174 # IPC: Total IPC of All Threads
system.cpu.iq.ISSUE:FU_type_0 3491 # Type of FU issued
diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stderr b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stderr
index b3cdfe967..fb2137f1e 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stderr
+++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stderr
@@ -1,2 +1,3 @@
+0: system.remote_gdb.listener: listening for remote gdb on port 7000
warn: Entering event queue @ 0. Starting simulation...
warn: ignoring syscall sigprocmask(1, 18446744073709547831, ...)
diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stdout b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stdout
index ccb6a0e46..6436baf8f 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stdout
+++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stdout
@@ -6,8 +6,8 @@ The Regents of The University of Michigan
All Rights Reserved
-M5 compiled Nov 12 2006 23:25:38
-M5 started Sun Nov 12 23:25:54 2006
-M5 executing on zizzer.eecs.umich.edu
-command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/tru64/o3-timing tests/run.py quick/00.hello/alpha/tru64/o3-timing
+M5 compiled Jan 22 2007 23:06:52
+M5 started Mon Jan 22 23:07:09 2007
+M5 executing on ewok
+command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/o3-timing tests/run.py quick/00.hello/alpha/tru64/o3-timing
Exiting @ tick 752028 because target called exit()