diff options
Diffstat (limited to 'tests/quick/00.hello/ref/arm/linux/o3-timing/stats.txt')
| -rw-r--r-- | tests/quick/00.hello/ref/arm/linux/o3-timing/stats.txt | 332 |
1 files changed, 166 insertions, 166 deletions
diff --git a/tests/quick/00.hello/ref/arm/linux/o3-timing/stats.txt b/tests/quick/00.hello/ref/arm/linux/o3-timing/stats.txt index bb000db1d..d620e2c6d 100644 --- a/tests/quick/00.hello/ref/arm/linux/o3-timing/stats.txt +++ b/tests/quick/00.hello/ref/arm/linux/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 51112 # Simulator instruction rate (inst/s) -host_mem_usage 254432 # Number of bytes of host memory used -host_seconds 0.11 # Real time elapsed on the host -host_tick_rate 95982480 # Simulator tick rate (ticks/s) +host_inst_rate 117635 # Simulator instruction rate (inst/s) +host_mem_usage 212912 # Number of bytes of host memory used +host_seconds 0.05 # Real time elapsed on the host +host_tick_rate 220680920 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 5739 # Number of instructions simulated sim_seconds 0.000011 # Number of seconds simulated @@ -16,38 +16,38 @@ system.cpu.BPredUnit.condIncorrect 406 # Nu system.cpu.BPredUnit.condPredicted 1671 # Number of conditional branches predicted system.cpu.BPredUnit.lookups 2180 # Number of BP lookups system.cpu.BPredUnit.usedRAS 242 # Number of times the RAS was used to get a target. -system.cpu.commit.COM:branches 945 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 62 # number cycles where commit BW limit reached -system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle::samples 11008 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::mean 0.521348 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::stdev 1.245214 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::0 8442 76.69% 76.69% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::1 1229 11.16% 87.85% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::2 550 5.00% 92.85% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::3 321 2.92% 95.77% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::4 184 1.67% 97.44% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::5 137 1.24% 98.68% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::6 51 0.46% 99.15% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::7 32 0.29% 99.44% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::8 62 0.56% 100.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::total 11008 # Number of insts commited each cycle -system.cpu.commit.COM:count 5739 # Number of instructions committed -system.cpu.commit.COM:fp_insts 16 # Number of committed floating point instructions. -system.cpu.commit.COM:function_calls 82 # Number of function calls committed. -system.cpu.commit.COM:int_insts 4985 # Number of committed integer instructions. -system.cpu.commit.COM:loads 1201 # Number of loads committed -system.cpu.commit.COM:membars 12 # Number of memory barriers committed -system.cpu.commit.COM:refs 2139 # Number of memory references committed -system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed system.cpu.commit.branchMispredicts 317 # The number of times a branch was mispredicted +system.cpu.commit.branches 945 # Number of branches committed +system.cpu.commit.bw_lim_events 62 # number cycles where commit BW limit reached +system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits system.cpu.commit.commitCommittedInsts 5739 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 24 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.commitSquashedInsts 4490 # The number of squashed insts skipped by commit +system.cpu.commit.committed_per_cycle::samples 11008 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.521348 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.245214 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 8442 76.69% 76.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1229 11.16% 87.85% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 550 5.00% 92.85% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 321 2.92% 95.77% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 184 1.67% 97.44% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 137 1.24% 98.68% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 51 0.46% 99.15% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 32 0.29% 99.44% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 62 0.56% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 11008 # Number of insts commited each cycle +system.cpu.commit.count 5739 # Number of instructions committed +system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. +system.cpu.commit.function_calls 82 # Number of function calls committed. +system.cpu.commit.int_insts 4985 # Number of committed integer instructions. +system.cpu.commit.loads 1201 # Number of loads committed +system.cpu.commit.membars 12 # Number of memory barriers committed +system.cpu.commit.refs 2139 # Number of memory references committed +system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.committedInsts 5739 # Number of Instructions Simulated system.cpu.committedInsts_total 5739 # Number of Instructions Simulated system.cpu.cpi 3.765116 # CPI: Cycles Per Instruction @@ -105,8 +105,8 @@ system.cpu.dcache.demand_mshr_misses 147 # nu system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.021822 # Average percentage of cache occupancy system.cpu.dcache.occ_blocks::0 89.381733 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.021822 # Average percentage of cache occupancy system.cpu.dcache.overall_accesses 2731 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 34928.411633 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 31969.387755 # average overall mshr miss latency @@ -128,15 +128,15 @@ system.cpu.dcache.tagsinuse 89.381733 # Cy system.cpu.dcache.total_refs 2304 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 1281 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 158 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 346 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 12207 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 7419 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 2259 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 770 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 557 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 48 # Number of cycles decode is unblocking +system.cpu.decode.BlockedCycles 1281 # Number of cycles decode is blocked +system.cpu.decode.BranchMispred 158 # Number of times decode detected a branch misprediction +system.cpu.decode.BranchResolved 346 # Number of times decode resolved a branch +system.cpu.decode.DecodedInsts 12207 # Number of instructions handled by decode +system.cpu.decode.IdleCycles 7419 # Number of cycles decode is idle +system.cpu.decode.RunCycles 2259 # Number of cycles decode is running +system.cpu.decode.SquashCycles 770 # Number of cycles decode is squashing +system.cpu.decode.SquashedInsts 557 # Number of squashed instructions handled by decode +system.cpu.decode.UnblockCycles 48 # Number of cycles decode is unblocking system.cpu.dtb.accesses 0 # DTB accesses system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions @@ -220,8 +220,8 @@ system.cpu.icache.demand_mshr_misses 287 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.071283 # Average percentage of cache occupancy system.cpu.icache.occ_blocks::0 145.986730 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.071283 # Average percentage of cache occupancy system.cpu.icache.overall_accesses 1601 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 34737.313433 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 33334.494774 # average overall mshr miss latency @@ -244,21 +244,13 @@ system.cpu.icache.total_refs 1266 # To system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idleCycles 9831 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 1296 # Number of branches executed -system.cpu.iew.EXEC:nop 3 # number of nop insts executed -system.cpu.iew.EXEC:rate 0.372316 # Inst execution rate -system.cpu.iew.EXEC:refs 3091 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 1139 # Number of stores executed -system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 7215 # num instructions consuming a value -system.cpu.iew.WB:count 7676 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.492862 # average fanout of values written-back -system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 3556 # num instructions producing a value -system.cpu.iew.WB:rate 0.355239 # insts written-back per cycle -system.cpu.iew.WB:sent 7793 # cumulative count of insts sent to commit system.cpu.iew.branchMispredicts 365 # Number of branch mispredicts detected at execute +system.cpu.iew.exec_branches 1296 # Number of branches executed +system.cpu.iew.exec_nop 3 # number of nop insts executed +system.cpu.iew.exec_rate 0.372316 # Inst execution rate +system.cpu.iew.exec_refs 3091 # number of memory reference insts executed +system.cpu.iew.exec_stores 1139 # Number of stores executed +system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.iewBlockCycles 209 # Number of cycles IEW is blocking system.cpu.iew.iewDispLoadInsts 2372 # Number of dispatched load instructions system.cpu.iew.iewDispNonSpecInsts 13 # Number of dispatched non-speculative instructions @@ -286,103 +278,93 @@ system.cpu.iew.lsq.thread.0.squashedStores 560 # system.cpu.iew.memOrderViolationEvents 12 # Number of memory order violations system.cpu.iew.predictedNotTakenIncorrect 246 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedTakenIncorrect 119 # Number of branches that were predicted taken incorrectly +system.cpu.iew.wb_consumers 7215 # num instructions consuming a value +system.cpu.iew.wb_count 7676 # cumulative count of insts written-back +system.cpu.iew.wb_fanout 0.492862 # average fanout of values written-back +system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ +system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ +system.cpu.iew.wb_producers 3556 # num instructions producing a value +system.cpu.iew.wb_rate 0.355239 # insts written-back per cycle +system.cpu.iew.wb_sent 7793 # cumulative count of insts sent to commit system.cpu.int_regfile_reads 18334 # number of integer regfile reads system.cpu.int_regfile_writes 5503 # number of integer regfile writes system.cpu.ipc 0.265596 # IPC: Instructions Per Cycle system.cpu.ipc_total 0.265596 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntAlu 5116 61.06% 61.06% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntMult 6 0.07% 61.13% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 61.13% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 61.13% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 61.13% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 61.13% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 61.13% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 61.13% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 61.13% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 61.13% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 61.13% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 61.13% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 61.13% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 61.13% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 61.13% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 61.13% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 61.13% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 61.13% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 61.13% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 61.13% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 61.13% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 61.13% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 61.13% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 61.13% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 61.13% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 3 0.04% 61.16% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 61.16% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 61.16% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 61.16% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemRead 2082 24.85% 86.01% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemWrite 1172 13.99% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::total 8379 # Type of FU issued -system.cpu.iq.ISSUE:fu_busy_cnt 180 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.021482 # FU busy rate (busy events/executed inst) -system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntAlu 2 1.11% 1.11% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 1.11% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 1.11% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 1.11% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 1.11% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 1.11% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 1.11% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 1.11% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 1.11% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 1.11% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 1.11% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 1.11% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 1.11% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 1.11% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 1.11% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 1.11% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 1.11% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 1.11% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 1.11% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 1.11% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 1.11% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 1.11% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 1.11% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 1.11% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 1.11% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 1.11% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 1.11% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 1.11% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 1.11% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemRead 119 66.11% 67.22% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemWrite 59 32.78% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:issued_per_cycle::samples 11777 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::mean 0.711472 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.348484 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::0 8190 69.54% 69.54% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::1 1436 12.19% 81.74% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::2 830 7.05% 88.78% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::3 533 4.53% 93.31% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::4 422 3.58% 96.89% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::5 239 2.03% 98.92% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::6 96 0.82% 99.74% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::7 23 0.20% 99.93% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::8 8 0.07% 100.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::total 11777 # Number of insts issued each cycle -system.cpu.iq.ISSUE:rate 0.387773 # Inst issue rate +system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 5116 61.06% 61.06% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 6 0.07% 61.13% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.13% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 61.13% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.13% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.13% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.13% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.13% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 61.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.04% 61.16% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.16% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.16% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.16% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2082 24.85% 86.01% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1172 13.99% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::total 8379 # Type of FU issued system.cpu.iq.fp_alu_accesses 20 # Number of floating point alu accesses system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_writes 16 # Number of floating instruction queue writes +system.cpu.iq.fu_busy_cnt 180 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.021482 # FU busy rate (busy events/executed inst) +system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 2 1.11% 1.11% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 1.11% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 1.11% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.11% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.11% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.11% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 1.11% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.11% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 1.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 1.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.11% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 119 66.11% 67.22% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 59 32.78% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.int_alu_accesses 8539 # Number of integer alu accesses system.cpu.iq.int_inst_queue_reads 28698 # Number of integer instruction queue reads system.cpu.iq.int_inst_queue_wakeup_accesses 7660 # Number of integer instruction queue wakeup accesses @@ -394,6 +376,24 @@ system.cpu.iq.iqSquashedInstsExamined 4207 # Nu system.cpu.iq.iqSquashedInstsIssued 19 # Number of squashed instructions issued system.cpu.iq.iqSquashedNonSpecRemoved 1 # Number of squashed non-spec instructions that were removed system.cpu.iq.iqSquashedOperandsExamined 6956 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.issued_per_cycle::samples 11777 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.711472 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.348484 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 8190 69.54% 69.54% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1436 12.19% 81.74% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 830 7.05% 88.78% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 533 4.53% 93.31% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 422 3.58% 96.89% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 239 2.03% 98.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 96 0.82% 99.74% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 23 0.20% 99.93% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 8 0.07% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 11777 # Number of insts issued each cycle +system.cpu.iq.rate 0.387773 # Inst issue rate system.cpu.itb.accesses 0 # DTB accesses system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions @@ -457,8 +457,8 @@ system.cpu.l2cache.demand_mshr_misses 391 # nu system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.005656 # Average percentage of cache occupancy system.cpu.l2cache.occ_blocks::0 185.350735 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.005656 # Average percentage of cache occupancy system.cpu.l2cache.overall_accesses 434 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 34368.090452 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 31251.918159 # average overall mshr miss latency @@ -489,27 +489,27 @@ system.cpu.misc_regfile_writes 24 # nu system.cpu.numCycles 21608 # number of cpu cycles simulated system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.rename.RENAME:BlockCycles 329 # Number of cycles rename is blocking -system.cpu.rename.RENAME:CommittedMaps 4124 # Number of HB maps that are committed -system.cpu.rename.RENAME:IQFullEvents 48 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 7684 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 118 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:RenameLookups 30009 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 11406 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 8239 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 2041 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 770 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 193 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 4112 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:fp_rename_lookups 390 # Number of floating rename lookups -system.cpu.rename.RENAME:int_rename_lookups 29619 # Number of integer rename lookups -system.cpu.rename.RENAME:serializeStallCycles 760 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 16 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 508 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 14 # count of temporary serializing insts renamed +system.cpu.rename.BlockCycles 329 # Number of cycles rename is blocking +system.cpu.rename.CommittedMaps 4124 # Number of HB maps that are committed +system.cpu.rename.IQFullEvents 48 # Number of times rename has blocked due to IQ full +system.cpu.rename.IdleCycles 7684 # Number of cycles rename is idle +system.cpu.rename.LSQFullEvents 118 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenameLookups 30009 # Number of register rename lookups that rename has made +system.cpu.rename.RenamedInsts 11406 # Number of instructions processed by rename +system.cpu.rename.RenamedOperands 8239 # Number of destination operands rename has renamed +system.cpu.rename.RunCycles 2041 # Number of cycles rename is running +system.cpu.rename.SquashCycles 770 # Number of cycles rename is squashing +system.cpu.rename.UnblockCycles 193 # Number of cycles rename is unblocking +system.cpu.rename.UndoneMaps 4112 # Number of HB maps that are undone due to squashing +system.cpu.rename.fp_rename_lookups 390 # Number of floating rename lookups +system.cpu.rename.int_rename_lookups 29619 # Number of integer rename lookups +system.cpu.rename.serializeStallCycles 760 # count of cycles rename stalled for serializing inst +system.cpu.rename.serializingInsts 16 # count of serializing insts renamed +system.cpu.rename.skidInsts 508 # count of insts added to the skid buffer +system.cpu.rename.tempSerializingInsts 14 # count of temporary serializing insts renamed system.cpu.rob.rob_reads 21018 # The number of ROB reads system.cpu.rob.rob_writes 21240 # The number of ROB writes system.cpu.timesIdled 200 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.workload.PROG:num_syscalls 13 # Number of system calls +system.cpu.workload.num_syscalls 13 # Number of system calls ---------- End Simulation Statistics ---------- |