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Diffstat (limited to 'tests/quick/00.hello/ref/mips/linux/inorder-timing')
-rw-r--r--tests/quick/00.hello/ref/mips/linux/inorder-timing/config.ini13
-rwxr-xr-xtests/quick/00.hello/ref/mips/linux/inorder-timing/simout8
-rw-r--r--tests/quick/00.hello/ref/mips/linux/inorder-timing/stats.txt10
3 files changed, 10 insertions, 21 deletions
diff --git a/tests/quick/00.hello/ref/mips/linux/inorder-timing/config.ini b/tests/quick/00.hello/ref/mips/linux/inorder-timing/config.ini
index 6b7ff5873..d479ef8bf 100644
--- a/tests/quick/00.hello/ref/mips/linux/inorder-timing/config.ini
+++ b/tests/quick/00.hello/ref/mips/linux/inorder-timing/config.ini
@@ -1,22 +1,13 @@
[root]
type=Root
children=system
-time_sync_enable=false
-time_sync_period=100000000000
-time_sync_spin_threshold=100000000
+dummy=0
[system]
type=System
children=cpu membus physmem
mem_mode=atomic
physmem=system.physmem
-work_begin_ckpt_count=0
-work_begin_cpu_id_exit=-1
-work_begin_exit_count=0
-work_cpus_ckpt_count=0
-work_end_ckpt_count=0
-work_end_exit_count=0
-work_item_id=-1
[system.cpu]
type=InOrderCPU
@@ -255,7 +246,7 @@ egid=100
env=
errout=cerr
euid=100
-executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/mips/linux/hello
+executable=tests/test-progs/hello/bin/mips/linux/hello
gid=100
input=cin
max_stack_size=67108864
diff --git a/tests/quick/00.hello/ref/mips/linux/inorder-timing/simout b/tests/quick/00.hello/ref/mips/linux/inorder-timing/simout
index c56b70ea3..dc388ddae 100755
--- a/tests/quick/00.hello/ref/mips/linux/inorder-timing/simout
+++ b/tests/quick/00.hello/ref/mips/linux/inorder-timing/simout
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
All Rights Reserved
-M5 compiled Feb 6 2011 15:20:27
-M5 revision b885adc82ab4+ 7924+ default tip qtip brad/regress_updates
-M5 started Feb 6 2011 20:46:02
-M5 executing on SC2B0617
+M5 compiled Jan 24 2011 18:37:16
+M5 revision 09e8ac96522d+ 7823+ default regression_updates qtip tip
+M5 started Jan 24 2011 18:37:18
+M5 executing on zooks
command line: build/MIPS_SE/m5.fast -d build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/inorder-timing -re tests/run.py build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/inorder-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
diff --git a/tests/quick/00.hello/ref/mips/linux/inorder-timing/stats.txt b/tests/quick/00.hello/ref/mips/linux/inorder-timing/stats.txt
index ab040cd9f..170c01854 100644
--- a/tests/quick/00.hello/ref/mips/linux/inorder-timing/stats.txt
+++ b/tests/quick/00.hello/ref/mips/linux/inorder-timing/stats.txt
@@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 42279 # Simulator instruction rate (inst/s)
-host_mem_usage 206292 # Number of bytes of host memory used
-host_seconds 0.14 # Real time elapsed on the host
-host_tick_rate 155948553 # Simulator tick rate (ticks/s)
+host_inst_rate 32637 # Simulator instruction rate (inst/s)
+host_mem_usage 156860 # Number of bytes of host memory used
+host_seconds 0.18 # Real time elapsed on the host
+host_tick_rate 120410651 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 5827 # Number of instructions simulated
sim_seconds 0.000022 # Number of seconds simulated
@@ -253,8 +253,6 @@ system.cpu.l2cache.total_refs 2 # To
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 0 # number of writebacks
system.cpu.numCycles 43069 # number of cpu cycles simulated
-system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.runCycles 6002 # Number of cycles cpu stages are processed.
system.cpu.smtCommittedInsts 0 # Number of SMT Instructions Simulated (Per-Thread)
system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode