diff options
Diffstat (limited to 'tests/quick/00.hello/ref/mips/linux/o3-timing/stats.txt')
| -rw-r--r-- | tests/quick/00.hello/ref/mips/linux/o3-timing/stats.txt | 406 |
1 files changed, 203 insertions, 203 deletions
diff --git a/tests/quick/00.hello/ref/mips/linux/o3-timing/stats.txt b/tests/quick/00.hello/ref/mips/linux/o3-timing/stats.txt index eb0ece35d..d3b5afd1a 100644 --- a/tests/quick/00.hello/ref/mips/linux/o3-timing/stats.txt +++ b/tests/quick/00.hello/ref/mips/linux/o3-timing/stats.txt @@ -1,12 +1,12 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000012 # Number of seconds simulated -sim_ticks 12273500 # Number of ticks simulated +sim_ticks 12272500 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 39169 # Simulator instruction rate (inst/s) -host_tick_rate 92983194 # Simulator tick rate (ticks/s) -host_mem_usage 242872 # Number of bytes of host memory used -host_seconds 0.13 # Real time elapsed on the host +host_inst_rate 4036 # Simulator instruction rate (inst/s) +host_tick_rate 9581124 # Simulator tick rate (ticks/s) +host_mem_usage 250068 # Number of bytes of host memory used +host_seconds 1.28 # Real time elapsed on the host sim_insts 5169 # Number of instructions simulated system.cpu.dtb.read_hits 0 # DTB read hits system.cpu.dtb.read_misses 0 # DTB read misses @@ -27,101 +27,101 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 8 # Number of system calls -system.cpu.numCycles 24548 # number of cpu cycles simulated +system.cpu.numCycles 24546 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 1977 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 1345 # Number of conditional branches predicted +system.cpu.BPredUnit.lookups 1975 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 1343 # Number of conditional branches predicted system.cpu.BPredUnit.condIncorrect 399 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 1580 # Number of BTB lookups +system.cpu.BPredUnit.BTBLookups 1578 # Number of BTB lookups system.cpu.BPredUnit.BTBHits 493 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.usedRAS 251 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 71 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 7914 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 12271 # Number of instructions fetch has processed -system.cpu.fetch.Branches 1977 # Number of branches that fetch encountered +system.cpu.fetch.icacheStallCycles 7903 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 12258 # Number of instructions fetch has processed +system.cpu.fetch.Branches 1975 # Number of branches that fetch encountered system.cpu.fetch.predictedBranches 744 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 3026 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1189 # Number of cycles fetch has spent squashing +system.cpu.fetch.Cycles 3024 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1186 # Number of cycles fetch has spent squashing system.cpu.fetch.BlockedCycles 756 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 145 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 1783 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 230 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 12623 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.972114 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.277844 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 1781 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 229 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 12608 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.972240 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.277843 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 9597 76.03% 76.03% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1250 9.90% 85.93% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 9584 76.02% 76.02% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1250 9.91% 85.93% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::2 108 0.86% 86.79% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::3 139 1.10% 87.89% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::4 289 2.29% 90.18% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 93 0.74% 90.91% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 92 0.73% 90.91% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::6 132 1.05% 91.96% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::7 145 1.15% 93.11% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 870 6.89% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 869 6.89% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 12623 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.080536 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.499878 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 8103 # Number of cycles decode is idle +system.cpu.fetch.rateDist::total 12608 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.080461 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.499389 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 8092 # Number of cycles decode is idle system.cpu.decode.BlockedCycles 871 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 2859 # Number of cycles decode is running +system.cpu.decode.RunCycles 2857 # Number of cycles decode is running system.cpu.decode.UnblockCycles 51 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 739 # Number of cycles decode is squashing +system.cpu.decode.SquashCycles 737 # Number of cycles decode is squashing system.cpu.decode.BranchResolved 107 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 43 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 11438 # Number of instructions handled by decode +system.cpu.decode.DecodedInsts 11425 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 162 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 739 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 8274 # Number of cycles rename is idle +system.cpu.rename.SquashCycles 737 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 8263 # Number of cycles rename is idle system.cpu.rename.BlockCycles 258 # Number of cycles rename is blocking system.cpu.rename.serializeStallCycles 499 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 2742 # Number of cycles rename is running +system.cpu.rename.RunCycles 2740 # Number of cycles rename is running system.cpu.rename.UnblockCycles 111 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 11017 # Number of instructions processed by rename +system.cpu.rename.RenamedInsts 11004 # Number of instructions processed by rename system.cpu.rename.LSQFullEvents 101 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 6705 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 13124 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 13120 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 4 # Number of floating rename lookups +system.cpu.rename.RenamedOperands 6697 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 13110 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 13105 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 5 # Number of floating rename lookups system.cpu.rename.CommittedMaps 3410 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 3295 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 3287 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 18 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 11 # count of temporary serializing insts renamed system.cpu.rename.skidInsts 281 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2349 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1175 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.insertedLoads 2346 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1174 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 1 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 1 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 8651 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsAdded 8640 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 13 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 7822 # Number of instructions issued +system.cpu.iq.iqInstsIssued 7815 # Number of instructions issued system.cpu.iq.iqSquashedInstsIssued 50 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 2995 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 1815 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedInstsExamined 2984 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 1806 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 3 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 12623 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.619663 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.285161 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 12608 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.619845 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.285923 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 9267 73.41% 73.41% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1321 10.47% 83.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 831 6.58% 90.46% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 511 4.05% 94.51% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 357 2.83% 97.34% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 203 1.61% 98.95% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 83 0.66% 99.60% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 9257 73.42% 73.42% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1317 10.45% 83.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 832 6.60% 90.47% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 510 4.05% 94.51% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 356 2.82% 97.34% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 201 1.59% 98.93% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 85 0.67% 99.60% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 35 0.28% 99.88% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 15 0.12% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 12623 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 12608 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu.iq.fu_full::IntAlu 3 2.05% 2.05% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 2.05% # attempts to use FU when none available @@ -157,104 +157,104 @@ system.cpu.iq.fu_full::MemWrite 52 35.62% 100.00% # at system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 4598 58.78% 58.78% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 4 0.05% 58.83% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 2 0.03% 58.86% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2 0.03% 58.89% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 58.89% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 58.89% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 58.89% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 58.89% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 58.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 58.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 58.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 58.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 58.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 58.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 58.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 58.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 58.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 58.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 58.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 58.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 58.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 58.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 58.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 58.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 58.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 58.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 58.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 58.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 58.89% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2131 27.24% 86.13% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1085 13.87% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 4596 58.81% 58.81% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 4 0.05% 58.86% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 2 0.03% 58.89% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2 0.03% 58.91% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 58.91% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 58.91% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 58.91% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 58.91% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 58.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 58.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 58.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 58.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 58.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 58.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 58.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 58.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 58.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 58.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 58.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 58.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 58.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 58.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 58.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 58.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 58.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 58.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 58.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 58.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 58.91% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2128 27.23% 86.14% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1083 13.86% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 7822 # Type of FU issued -system.cpu.iq.rate 0.318641 # Inst issue rate +system.cpu.iq.FU_type_0::total 7815 # Type of FU issued +system.cpu.iq.rate 0.318382 # Inst issue rate system.cpu.iq.fu_busy_cnt 146 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.018665 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 28459 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 11666 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 7121 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fu_busy_rate 0.018682 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 28430 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 11643 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 7116 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 4 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 2 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 2 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 7966 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 7959 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 2 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 65 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1185 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 1182 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 4 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 9 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 250 # Number of stores squashed +system.cpu.iew.lsq.thread0.memOrderViolation 8 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 249 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 739 # Number of cycles IEW is squashing +system.cpu.iew.iewSquashCycles 737 # Number of cycles IEW is squashing system.cpu.iew.iewBlockCycles 165 # Number of cycles IEW is blocking system.cpu.iew.iewUnblockCycles 13 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 10044 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispatchedInsts 10031 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 128 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2349 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1175 # Number of dispatched store instructions +system.cpu.iew.iewDispLoadInsts 2346 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1174 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 13 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 6 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 9 # Number of memory order violations +system.cpu.iew.memOrderViolationEvents 8 # Number of memory order violations system.cpu.iew.predictedTakenIncorrect 107 # Number of branches that were predicted taken incorrectly system.cpu.iew.predictedNotTakenIncorrect 309 # Number of branches that were predicted not taken incorrectly system.cpu.iew.branchMispredicts 416 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 7537 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 2031 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 285 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 7531 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 2028 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 284 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 1380 # number of nop insts executed -system.cpu.iew.exec_refs 3091 # number of memory reference insts executed +system.cpu.iew.exec_nop 1378 # number of nop insts executed +system.cpu.iew.exec_refs 3087 # number of memory reference insts executed system.cpu.iew.exec_branches 1271 # Number of branches executed -system.cpu.iew.exec_stores 1060 # Number of stores executed -system.cpu.iew.exec_rate 0.307031 # Inst execution rate -system.cpu.iew.wb_sent 7215 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 7123 # cumulative count of insts written-back -system.cpu.iew.wb_producers 2761 # num instructions producing a value -system.cpu.iew.wb_consumers 3949 # num instructions consuming a value +system.cpu.iew.exec_stores 1059 # Number of stores executed +system.cpu.iew.exec_rate 0.306812 # Inst execution rate +system.cpu.iew.wb_sent 7210 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 7118 # cumulative count of insts written-back +system.cpu.iew.wb_producers 2758 # num instructions producing a value +system.cpu.iew.wb_consumers 3946 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.290166 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.699164 # average fanout of values written-back +system.cpu.iew.wb_rate 0.289986 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.698936 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 5826 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 4210 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 4197 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 10 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 357 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 11884 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.490239 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.276602 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::samples 11871 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.490776 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.277197 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 9485 79.81% 79.81% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 966 8.13% 87.94% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 656 5.52% 93.46% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 9472 79.79% 79.79% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 966 8.14% 87.93% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 656 5.53% 93.45% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::3 321 2.70% 96.16% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::4 147 1.24% 97.40% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::5 102 0.86% 98.26% # Number of insts commited each cycle @@ -264,7 +264,7 @@ system.cpu.commit.committed_per_cycle::8 102 0.86% 100.00% # Nu system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 11884 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 11871 # Number of insts commited each cycle system.cpu.commit.count 5826 # Number of instructions committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.commit.refs 2089 # Number of memory references committed @@ -276,47 +276,47 @@ system.cpu.commit.int_insts 5124 # Nu system.cpu.commit.function_calls 87 # Number of function calls committed. system.cpu.commit.bw_lim_events 102 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 21805 # The number of ROB reads -system.cpu.rob.rob_writes 20822 # The number of ROB writes +system.cpu.rob.rob_reads 21779 # The number of ROB reads +system.cpu.rob.rob_writes 20794 # The number of ROB writes system.cpu.timesIdled 251 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 11925 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.idleCycles 11938 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 5169 # Number of Instructions Simulated system.cpu.committedInsts_total 5169 # Number of Instructions Simulated -system.cpu.cpi 4.749081 # CPI: Cycles Per Instruction -system.cpu.cpi_total 4.749081 # CPI: Total CPI of All Threads -system.cpu.ipc 0.210567 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.210567 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 10287 # number of integer regfile reads -system.cpu.int_regfile_writes 4991 # number of integer regfile writes +system.cpu.cpi 4.748694 # CPI: Cycles Per Instruction +system.cpu.cpi_total 4.748694 # CPI: Total CPI of All Threads +system.cpu.ipc 0.210584 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.210584 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 10280 # number of integer regfile reads +system.cpu.int_regfile_writes 4987 # number of integer regfile writes system.cpu.fp_regfile_reads 3 # number of floating regfile reads system.cpu.fp_regfile_writes 1 # number of floating regfile writes -system.cpu.misc_regfile_reads 153 # number of misc regfile reads +system.cpu.misc_regfile_reads 154 # number of misc regfile reads system.cpu.icache.replacements 17 # number of replacements -system.cpu.icache.tagsinuse 161.223747 # Cycle average of tags in use -system.cpu.icache.total_refs 1364 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 161.224498 # Cycle average of tags in use +system.cpu.icache.total_refs 1363 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 336 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 4.059524 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 4.056548 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 161.223747 # Average occupied blocks per context +system.cpu.icache.occ_blocks::0 161.224498 # Average occupied blocks per context system.cpu.icache.occ_percent::0 0.078723 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 1364 # number of ReadReq hits -system.cpu.icache.demand_hits 1364 # number of demand (read+write) hits -system.cpu.icache.overall_hits 1364 # number of overall hits -system.cpu.icache.ReadReq_misses 419 # number of ReadReq misses -system.cpu.icache.demand_misses 419 # number of demand (read+write) misses -system.cpu.icache.overall_misses 419 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 15179500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 15179500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 15179500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 1783 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 1783 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 1783 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.234997 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.234997 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.234997 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 36227.923628 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 36227.923628 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 36227.923628 # average overall miss latency +system.cpu.icache.ReadReq_hits 1363 # number of ReadReq hits +system.cpu.icache.demand_hits 1363 # number of demand (read+write) hits +system.cpu.icache.overall_hits 1363 # number of overall hits +system.cpu.icache.ReadReq_misses 418 # number of ReadReq misses +system.cpu.icache.demand_misses 418 # number of demand (read+write) misses +system.cpu.icache.overall_misses 418 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 15148000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 15148000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 15148000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses 1781 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 1781 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 1781 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate 0.234700 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate 0.234700 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate 0.234700 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency 36239.234450 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency 36239.234450 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 36239.234450 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -326,9 +326,9 @@ system.cpu.icache.avg_blocked_cycles::no_targets no_value system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 83 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 83 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 83 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits 82 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits 82 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 82 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses 336 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses 336 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses 336 # number of overall MSHR misses @@ -337,9 +337,9 @@ system.cpu.icache.ReadReq_mshr_miss_latency 11784000 # system.cpu.icache.demand_mshr_miss_latency 11784000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency 11784000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.188446 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.188446 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.188446 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_mshr_miss_rate 0.188658 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate 0.188658 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate 0.188658 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency 35071.428571 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency 35071.428571 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency 35071.428571 # average overall mshr miss latency @@ -348,37 +348,37 @@ system.cpu.icache.mshr_cap_events 0 # nu system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 92.122056 # Cycle average of tags in use -system.cpu.dcache.total_refs 2382 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 92.121984 # Cycle average of tags in use +system.cpu.dcache.total_refs 2380 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 142 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 16.774648 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 16.760563 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 92.122056 # Average occupied blocks per context +system.cpu.dcache.occ_blocks::0 92.121984 # Average occupied blocks per context system.cpu.dcache.occ_percent::0 0.022491 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 1804 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits 1802 # number of ReadReq hits system.cpu.dcache.WriteReq_hits 578 # number of WriteReq hits -system.cpu.dcache.demand_hits 2382 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 2382 # number of overall hits -system.cpu.dcache.ReadReq_misses 134 # number of ReadReq misses +system.cpu.dcache.demand_hits 2380 # number of demand (read+write) hits +system.cpu.dcache.overall_hits 2380 # number of overall hits +system.cpu.dcache.ReadReq_misses 133 # number of ReadReq misses system.cpu.dcache.WriteReq_misses 347 # number of WriteReq misses -system.cpu.dcache.demand_misses 481 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 481 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 4801000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 11505500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency 16306500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 16306500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 1938 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses 480 # number of demand (read+write) misses +system.cpu.dcache.overall_misses 480 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 4767500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 11508000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency 16275500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 16275500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses 1935 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses 925 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 2863 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 2863 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.069143 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses 2860 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses 2860 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate 0.068734 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate 0.375135 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate 0.168006 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.168006 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 35828.358209 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 33157.060519 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency 33901.247401 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 33901.247401 # average overall miss latency +system.cpu.dcache.demand_miss_rate 0.167832 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate 0.167832 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency 35845.864662 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 33164.265130 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency 33907.291667 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 33907.291667 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -388,39 +388,39 @@ system.cpu.dcache.avg_blocked_cycles::no_targets no_value system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 43 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits 42 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits 296 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits 339 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 339 # number of overall MSHR hits +system.cpu.dcache.demand_mshr_hits 338 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 338 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses 91 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses 51 # number of WriteReq MSHR misses system.cpu.dcache.demand_mshr_misses 142 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses 142 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.ReadReq_mshr_miss_latency 3272000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 1835500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 5107500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 5107500 # number of overall MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 1836000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 5108000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 5108000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.046956 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate 0.047028 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate 0.055135 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.049598 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.049598 # mshr miss rate for overall accesses +system.cpu.dcache.demand_mshr_miss_rate 0.049650 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate 0.049650 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency 35956.043956 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35990.196078 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 35968.309859 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 35968.309859 # average overall mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 36000 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 35971.830986 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 35971.830986 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 221.520650 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 221.521956 # Cycle average of tags in use system.cpu.l2cache.total_refs 3 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 424 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.007075 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 221.520650 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::0 221.521956 # Average occupied blocks per context system.cpu.l2cache.occ_percent::0 0.006760 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits 3 # number of ReadReq hits system.cpu.l2cache.demand_hits 3 # number of demand (read+write) hits @@ -429,8 +429,8 @@ system.cpu.l2cache.ReadReq_misses 424 # nu system.cpu.l2cache.ReadExReq_misses 51 # number of ReadExReq misses system.cpu.l2cache.demand_misses 475 # number of demand (read+write) misses system.cpu.l2cache.overall_misses 475 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 14561500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 1760000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency 14561000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 1760500 # number of ReadExReq miss cycles system.cpu.l2cache.demand_miss_latency 16321500 # number of demand (read+write) miss cycles system.cpu.l2cache.overall_miss_latency 16321500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses 427 # number of ReadReq accesses(hits+misses) @@ -441,8 +441,8 @@ system.cpu.l2cache.ReadReq_miss_rate 0.992974 # mi system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate 0.993724 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate 0.993724 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 34343.160377 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 34509.803922 # average ReadExReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency 34341.981132 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 34519.607843 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency 34361.052632 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency 34361.052632 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked |