diff options
Diffstat (limited to 'tests/quick/00.hello/ref/mips/linux/o3-timing/stats.txt')
-rw-r--r-- | tests/quick/00.hello/ref/mips/linux/o3-timing/stats.txt | 14 |
1 files changed, 10 insertions, 4 deletions
diff --git a/tests/quick/00.hello/ref/mips/linux/o3-timing/stats.txt b/tests/quick/00.hello/ref/mips/linux/o3-timing/stats.txt index 85a5a75dd..e79cbdaa4 100644 --- a/tests/quick/00.hello/ref/mips/linux/o3-timing/stats.txt +++ b/tests/quick/00.hello/ref/mips/linux/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 48407 # Simulator instruction rate (inst/s) -host_mem_usage 206048 # Number of bytes of host memory used -host_seconds 0.11 # Real time elapsed on the host -host_tick_rate 131379529 # Simulator tick rate (ticks/s) +host_inst_rate 82851 # Simulator instruction rate (inst/s) +host_mem_usage 191760 # Number of bytes of host memory used +host_seconds 0.06 # Real time elapsed on the host +host_tick_rate 224354167 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 5169 # Number of instructions simulated sim_seconds 0.000014 # Number of seconds simulated @@ -93,6 +93,8 @@ system.cpu.dcache.demand_mshr_misses 155 # nu system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.occ_%::0 0.022292 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 91.308954 # Average occupied blocks per context system.cpu.dcache.overall_accesses 3246 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 29592.807425 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 36045.161290 # average overall mshr miss latency @@ -191,6 +193,8 @@ system.cpu.icache.demand_mshr_misses 329 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.icache.occ_%::0 0.076179 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 156.015053 # Average occupied blocks per context system.cpu.icache.overall_accesses 2220 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 35681.279621 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 34902.735562 # average overall mshr miss latency @@ -372,6 +376,8 @@ system.cpu.l2cache.demand_mshr_misses 466 # nu system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.occ_%::0 0.006413 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 210.151573 # Average occupied blocks per context system.cpu.l2cache.overall_accesses 470 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 34356.223176 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 31162.017167 # average overall mshr miss latency |