diff options
Diffstat (limited to 'tests/quick/00.hello/ref/mips/linux/o3-timing/stats.txt')
-rw-r--r-- | tests/quick/00.hello/ref/mips/linux/o3-timing/stats.txt | 76 |
1 files changed, 38 insertions, 38 deletions
diff --git a/tests/quick/00.hello/ref/mips/linux/o3-timing/stats.txt b/tests/quick/00.hello/ref/mips/linux/o3-timing/stats.txt index f4a13baba..abebc01ef 100644 --- a/tests/quick/00.hello/ref/mips/linux/o3-timing/stats.txt +++ b/tests/quick/00.hello/ref/mips/linux/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 49036 # Simulator instruction rate (inst/s) -host_mem_usage 153428 # Number of bytes of host memory used -host_seconds 0.10 # Real time elapsed on the host -host_tick_rate 135151055 # Simulator tick rate (ticks/s) +host_inst_rate 62820 # Simulator instruction rate (inst/s) +host_mem_usage 202152 # Number of bytes of host memory used +host_seconds 0.08 # Real time elapsed on the host +host_tick_rate 173066613 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 5024 # Number of instructions simulated sim_seconds 0.000014 # Number of seconds simulated @@ -19,23 +19,23 @@ system.cpu.BPredUnit.usedRAS 384 # Nu system.cpu.commit.COM:branches 879 # Number of branches committed system.cpu.commit.COM:bw_lim_events 63 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle::samples 14165 -system.cpu.commit.COM:committed_per_cycle::min_value 0 -system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% -system.cpu.commit.COM:committed_per_cycle::0-1 11701 82.61% -system.cpu.commit.COM:committed_per_cycle::1-2 1166 8.23% -system.cpu.commit.COM:committed_per_cycle::2-3 493 3.48% -system.cpu.commit.COM:committed_per_cycle::3-4 279 1.97% -system.cpu.commit.COM:committed_per_cycle::4-5 290 2.05% -system.cpu.commit.COM:committed_per_cycle::5-6 74 0.52% -system.cpu.commit.COM:committed_per_cycle::6-7 61 0.43% -system.cpu.commit.COM:committed_per_cycle::7-8 38 0.27% -system.cpu.commit.COM:committed_per_cycle::8 63 0.44% -system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% -system.cpu.commit.COM:committed_per_cycle::total 14165 -system.cpu.commit.COM:committed_per_cycle::max_value 8 -system.cpu.commit.COM:committed_per_cycle::mean 0.399223 -system.cpu.commit.COM:committed_per_cycle::stdev 1.126414 +system.cpu.commit.COM:committed_per_cycle::samples 14165 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::0-1 11701 82.61% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::1-2 1166 8.23% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::2-3 493 3.48% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::3-4 279 1.97% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::4-5 290 2.05% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::5-6 74 0.52% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::6-7 61 0.43% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::7-8 38 0.27% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::8 63 0.44% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::total 14165 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::mean 0.399223 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::stdev 1.126414 # Number of insts commited each cycle system.cpu.commit.COM:count 5655 # Number of instructions committed system.cpu.commit.COM:loads 1130 # Number of loads committed system.cpu.commit.COM:membars 0 # Number of memory barriers committed @@ -141,23 +141,23 @@ system.cpu.fetch.branchRate 0.084246 # Nu system.cpu.fetch.icacheStallCycles 2162 # Number of cycles fetch is stalled on an Icache miss system.cpu.fetch.predictedBranches 933 # Number of branches that fetch has predicted taken system.cpu.fetch.rate 0.549669 # Number of inst fetches per cycle -system.cpu.fetch.rateDist::samples 15217 -system.cpu.fetch.rateDist::min_value 0 -system.cpu.fetch.rateDist::underflows 0 0.00% -system.cpu.fetch.rateDist::0-1 11225 73.77% -system.cpu.fetch.rateDist::1-2 1766 11.61% -system.cpu.fetch.rateDist::2-3 196 1.29% -system.cpu.fetch.rateDist::3-4 137 0.90% -system.cpu.fetch.rateDist::4-5 314 2.06% -system.cpu.fetch.rateDist::5-6 113 0.74% -system.cpu.fetch.rateDist::6-7 304 2.00% -system.cpu.fetch.rateDist::7-8 249 1.64% -system.cpu.fetch.rateDist::8 913 6.00% -system.cpu.fetch.rateDist::overflows 0 0.00% -system.cpu.fetch.rateDist::total 15217 -system.cpu.fetch.rateDist::max_value 8 -system.cpu.fetch.rateDist::mean 1.002892 -system.cpu.fetch.rateDist::stdev 2.262712 +system.cpu.fetch.rateDist::samples 15217 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::underflows 0 0.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0-1 11225 73.77% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1-2 1766 11.61% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2-3 196 1.29% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3-4 137 0.90% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4-5 314 2.06% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5-6 113 0.74% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6-7 304 2.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7-8 249 1.64% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 913 6.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::overflows 0 0.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 15217 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.002892 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.262712 # Number of instructions fetched each cycle (Total) system.cpu.icache.ReadReq_accesses 2162 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_avg_miss_latency 35500 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 34915.151515 # average ReadReq mshr miss latency |