diff options
Diffstat (limited to 'tests/quick/00.hello/ref/mips/linux/simple-timing-ruby')
4 files changed, 107 insertions, 91 deletions
diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/config.ini b/tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/config.ini index 39758d41d..41938cc87 100644 --- a/tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/config.ini +++ b/tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/config.ini @@ -9,6 +9,7 @@ time_sync_spin_threshold=100000 type=System children=cpu dir_cntrl0 l1_cntrl0 physmem ruby mem_mode=timing +memories=system.physmem physmem=system.physmem work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 @@ -41,8 +42,8 @@ progress_interval=0 system=system tracer=system.cpu.tracer workload=system.cpu.workload -dcache_port=system.ruby.cpu_ruby_ports.port[1] -icache_port=system.ruby.cpu_ruby_ports.port[0] +dcache_port=system.l1_cntrl0.sequencer.port[1] +icache_port=system.l1_cntrl0.sequencer.port[0] [system.cpu.dtb] type=MipsTLB @@ -78,11 +79,13 @@ uid=100 type=Directory_Controller children=directory memBuffer buffer_size=0 +cntrl_id=1 directory=system.dir_cntrl0.directory directory_latency=12 memBuffer=system.dir_cntrl0.memBuffer number_of_TBEs=256 recycle_latency=10 +ruby_system=system.ruby transitions_per_cycle=32 version=0 @@ -117,16 +120,42 @@ version=0 [system.l1_cntrl0] type=L1Cache_Controller +children=cacheMemory sequencer buffer_size=0 -cacheMemory=system.ruby.cpu_ruby_ports.dcache +cacheMemory=system.l1_cntrl0.cacheMemory cache_response_latency=12 +cntrl_id=0 issue_latency=2 number_of_TBEs=256 recycle_latency=10 -sequencer=system.ruby.cpu_ruby_ports +ruby_system=system.ruby +sequencer=system.l1_cntrl0.sequencer transitions_per_cycle=32 version=0 +[system.l1_cntrl0.cacheMemory] +type=RubyCache +assoc=2 +latency=3 +replacement_policy=PSEUDO_LRU +size=256 +start_index_bit=6 + +[system.l1_cntrl0.sequencer] +type=RubySequencer +access_phys_mem=true +dcache=system.l1_cntrl0.cacheMemory +deadlock_threshold=500000 +icache=system.l1_cntrl0.cacheMemory +max_outstanding_requests=16 +physmem=system.physmem +ruby_system=system.ruby +using_network_tester=false +using_ruby_tester=false +version=0 +physMemPort=system.physmem.port[0] +port=system.cpu.icache_port system.cpu.dcache_port + [system.physmem] type=PhysicalMemory file= @@ -135,44 +164,18 @@ latency_var=0 null=false range=0:134217727 zero=false -port=system.ruby.cpu_ruby_ports.physMemPort +port=system.l1_cntrl0.sequencer.physMemPort [system.ruby] type=RubySystem -children=cpu_ruby_ports network profiler tracer +children=network profiler tracer block_size_bytes=64 clock=1 mem_size=134217728 -network=system.ruby.network no_mem_vec=false -profiler=system.ruby.profiler random_seed=1234 randomization=false stats_filename=ruby.stats -tracer=system.ruby.tracer - -[system.ruby.cpu_ruby_ports] -type=RubySequencer -children=dcache -access_phys_mem=true -dcache=system.ruby.cpu_ruby_ports.dcache -deadlock_threshold=500000 -icache=system.ruby.cpu_ruby_ports.dcache -max_outstanding_requests=16 -physmem=system.physmem -using_network_tester=false -using_ruby_tester=false -version=0 -physMemPort=system.physmem.port[0] -port=system.cpu.icache_port system.cpu.dcache_port - -[system.ruby.cpu_ruby_ports.dcache] -type=RubyCache -assoc=2 -latency=3 -replacement_policy=PSEUDO_LRU -size=256 -start_index_bit=6 [system.ruby.network] type=SimpleNetwork @@ -180,59 +183,77 @@ children=topology adaptive_routing=false buffer_size=0 control_msg_size=8 -endpoint_bandwidth=10000 -link_latency=1 +endpoint_bandwidth=1000 number_of_virtual_networks=10 +ruby_system=system.ruby topology=system.ruby.network.topology [system.ruby.network.topology] type=Topology -children=ext_links0 ext_links1 int_links0 int_links1 +children=ext_links0 ext_links1 int_links0 int_links1 routers0 routers1 routers2 description=Crossbar ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1 int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1 -num_int_nodes=3 print_config=false +routers=system.ruby.network.topology.routers0 system.ruby.network.topology.routers1 system.ruby.network.topology.routers2 [system.ruby.network.topology.ext_links0] -type=ExtLink -bw_multiplier=64 +type=SimpleExtLink +bandwidth_factor=16 ext_node=system.l1_cntrl0 -int_node=0 +int_node=system.ruby.network.topology.routers0 latency=1 +link_id=0 weight=1 [system.ruby.network.topology.ext_links1] -type=ExtLink -bw_multiplier=64 +type=SimpleExtLink +bandwidth_factor=16 ext_node=system.dir_cntrl0 -int_node=1 +int_node=system.ruby.network.topology.routers1 latency=1 +link_id=1 weight=1 [system.ruby.network.topology.int_links0] -type=IntLink -bw_multiplier=16 +type=SimpleIntLink +bandwidth_factor=16 latency=1 -node_a=0 -node_b=2 +link_id=2 +node_a=system.ruby.network.topology.routers0 +node_b=system.ruby.network.topology.routers2 weight=1 [system.ruby.network.topology.int_links1] -type=IntLink -bw_multiplier=16 +type=SimpleIntLink +bandwidth_factor=16 latency=1 -node_a=1 -node_b=2 +link_id=3 +node_a=system.ruby.network.topology.routers1 +node_b=system.ruby.network.topology.routers2 weight=1 +[system.ruby.network.topology.routers0] +type=BasicRouter +router_id=0 + +[system.ruby.network.topology.routers1] +type=BasicRouter +router_id=1 + +[system.ruby.network.topology.routers2] +type=BasicRouter +router_id=2 + [system.ruby.profiler] type=RubyProfiler all_instructions=false hot_lines=false num_of_sequencers=1 +ruby_system=system.ruby [system.ruby.tracer] type=RubyTracer +ruby_system=system.ruby warmup_length=100000 diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/simerr b/tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/simerr index eabe42249..e45cd058f 100755 --- a/tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/simerr +++ b/tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/simerr @@ -1,3 +1,2 @@ warn: Sockets disabled, not accepting gdb connections -For more information see: http://www.m5sim.org/warn/d946bea6 hack: be nice to actually delete the event here diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/simout b/tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/simout index e7dec82e9..12fac784c 100755 --- a/tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/simout +++ b/tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/simout @@ -1,14 +1,10 @@ -M5 Simulator System +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. -Copyright (c) 2001-2008 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled Apr 19 2011 12:18:54 -M5 started Apr 19 2011 12:18:57 -M5 executing on maize -command line: build/MIPS_SE/m5.fast -d build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-timing-ruby -re tests/run.py build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-timing-ruby +gem5 compiled Sep 9 2011 01:24:08 +gem5 started Sep 9 2011 01:24:15 +gem5 executing on chips +command line: build/MIPS_SE/gem5.opt -d build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/simple-timing-ruby -re tests/run.py build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/simple-timing-ruby Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt b/tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt index 12dfdb011..0e750eb72 100644 --- a/tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt +++ b/tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt @@ -1,52 +1,52 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 81519 # Simulator instruction rate (inst/s) -host_mem_usage 213976 # Number of bytes of host memory used -host_seconds 0.07 # Real time elapsed on the host -host_tick_rate 4090793 # Simulator tick rate (ticks/s) -sim_freq 1000000000 # Frequency of simulated ticks -sim_insts 5827 # Number of instructions simulated sim_seconds 0.000293 # Number of seconds simulated sim_ticks 292960 # Number of ticks simulated -system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.dtb.hits 0 # DTB hits -system.cpu.dtb.misses 0 # DTB misses -system.cpu.dtb.read_accesses 0 # DTB read accesses +sim_freq 1000000000 # Frequency of simulated ticks +host_inst_rate 24172 # Simulator instruction rate (inst/s) +host_tick_rate 1215173 # Simulator tick rate (ticks/s) +host_mem_usage 251116 # Number of bytes of host memory used +host_seconds 0.24 # Real time elapsed on the host +sim_insts 5827 # Number of instructions simulated system.cpu.dtb.read_hits 0 # DTB read hits system.cpu.dtb.read_misses 0 # DTB read misses -system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.read_accesses 0 # DTB read accesses system.cpu.dtb.write_hits 0 # DTB write hits system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.itb.accesses 0 # DTB accesses -system.cpu.itb.hits 0 # DTB hits -system.cpu.itb.misses 0 # DTB misses -system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.accesses 0 # DTB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 8 # Number of system calls system.cpu.numCycles 292960 # number of cpu cycles simulated -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.num_busy_cycles 292960 # Number of busy cycles -system.cpu.num_conditional_control_insts 677 # number of instructions that are conditional controls -system.cpu.num_fp_alu_accesses 2 # Number of float alu accesses -system.cpu.num_fp_insts 2 # number of float instructions -system.cpu.num_fp_register_reads 3 # number of times the floating registers were read -system.cpu.num_fp_register_writes 1 # number of times the floating registers were written -system.cpu.num_func_calls 194 # number of times a function call or return occured -system.cpu.num_idle_cycles 0 # Number of idle cycles +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.num_insts 5827 # Number of instructions executed system.cpu.num_int_alu_accesses 5126 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 2 # Number of float alu accesses +system.cpu.num_func_calls 194 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 677 # number of instructions that are conditional controls system.cpu.num_int_insts 5126 # number of integer instructions -system.cpu.num_int_register_reads 7301 # number of times the integer registers were read +system.cpu.num_fp_insts 2 # number of float instructions +system.cpu.num_int_register_reads 7300 # number of times the integer registers were read system.cpu.num_int_register_writes 3409 # number of times the integer registers were written -system.cpu.num_load_insts 1164 # Number of load instructions +system.cpu.num_fp_register_reads 3 # number of times the floating registers were read +system.cpu.num_fp_register_writes 1 # number of times the floating registers were written system.cpu.num_mem_refs 2090 # number of memory refs +system.cpu.num_load_insts 1164 # Number of load instructions system.cpu.num_store_insts 926 # Number of store instructions -system.cpu.workload.num_syscalls 8 # Number of system calls +system.cpu.num_idle_cycles 0 # Number of idle cycles +system.cpu.num_busy_cycles 292960 # Number of busy cycles +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.idle_fraction 0 # Percentage of idle cycles ---------- End Simulation Statistics ---------- |