diff options
Diffstat (limited to 'tests/quick/00.hello/ref/mips/linux/simple-timing/m5stats.txt')
| -rw-r--r-- | tests/quick/00.hello/ref/mips/linux/simple-timing/m5stats.txt | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing/m5stats.txt b/tests/quick/00.hello/ref/mips/linux/simple-timing/m5stats.txt index a9c46636a..cb408c2ca 100644 --- a/tests/quick/00.hello/ref/mips/linux/simple-timing/m5stats.txt +++ b/tests/quick/00.hello/ref/mips/linux/simple-timing/m5stats.txt @@ -1,11 +1,11 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 269189 # Simulator instruction rate (inst/s) -host_mem_usage 197500 # Number of bytes of host memory used -host_seconds 0.02 # Real time elapsed on the host -host_tick_rate 866482072 # Simulator tick rate (ticks/s) +host_inst_rate 186969 # Simulator instruction rate (inst/s) +host_mem_usage 180780 # Number of bytes of host memory used +host_seconds 0.03 # Real time elapsed on the host +host_tick_rate 602814418 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 5657 # Number of instructions simulated +sim_insts 5656 # Number of instructions simulated sim_seconds 0.000018 # Number of seconds simulated sim_ticks 18463000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 1130 # number of ReadReq accesses(hits+misses) @@ -225,7 +225,7 @@ system.cpu.l2cache.warmup_cycle 0 # Cy system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.numCycles 18463000 # number of cpu cycles simulated -system.cpu.num_insts 5657 # Number of instructions executed +system.cpu.num_insts 5656 # Number of instructions executed system.cpu.num_refs 2055 # Number of memory references system.cpu.workload.PROG:num_syscalls 13 # Number of system calls |