diff options
Diffstat (limited to 'tests/quick/00.hello/ref/mips/linux/simple-timing')
3 files changed, 19 insertions, 11 deletions
diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini b/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini index f2dee3856..7da6cb048 100644 --- a/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini +++ b/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini @@ -11,12 +11,14 @@ physmem=system.physmem [system.cpu] type=TimingSimpleCPU -children=dcache icache l2cache toL2Bus tracer workload +children=dcache dtb icache itb l2cache toL2Bus tracer workload clock=500 cpu_id=0 defer_registration=false +dtb=system.cpu.dtb function_trace=false function_trace_start=0 +itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 @@ -65,6 +67,9 @@ write_buffers=8 cpu_side=system.cpu.dcache_port mem_side=system.cpu.toL2Bus.port[1] +[system.cpu.dtb] +type=MipsDTB + [system.cpu.icache] type=BaseCache addr_range=0:18446744073709551615 @@ -101,6 +106,9 @@ write_buffers=8 cpu_side=system.cpu.icache_port mem_side=system.cpu.toL2Bus.port[0] +[system.cpu.itb] +type=MipsITB + [system.cpu.l2cache] type=BaseCache addr_range=0:18446744073709551615 @@ -156,7 +164,7 @@ cwd= egid=100 env= euid=100 -executable=tests/test-progs/hello/bin/mips/linux/hello +executable=/dist/m5/regression/test-progs/hello/bin/mips/linux/hello gid=100 input=cin output=cout diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing/m5stats.txt b/tests/quick/00.hello/ref/mips/linux/simple-timing/m5stats.txt index a9c46636a..cb408c2ca 100644 --- a/tests/quick/00.hello/ref/mips/linux/simple-timing/m5stats.txt +++ b/tests/quick/00.hello/ref/mips/linux/simple-timing/m5stats.txt @@ -1,11 +1,11 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 269189 # Simulator instruction rate (inst/s) -host_mem_usage 197500 # Number of bytes of host memory used -host_seconds 0.02 # Real time elapsed on the host -host_tick_rate 866482072 # Simulator tick rate (ticks/s) +host_inst_rate 186969 # Simulator instruction rate (inst/s) +host_mem_usage 180780 # Number of bytes of host memory used +host_seconds 0.03 # Real time elapsed on the host +host_tick_rate 602814418 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 5657 # Number of instructions simulated +sim_insts 5656 # Number of instructions simulated sim_seconds 0.000018 # Number of seconds simulated sim_ticks 18463000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 1130 # number of ReadReq accesses(hits+misses) @@ -225,7 +225,7 @@ system.cpu.l2cache.warmup_cycle 0 # Cy system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.numCycles 18463000 # number of cpu cycles simulated -system.cpu.num_insts 5657 # Number of instructions executed +system.cpu.num_insts 5656 # Number of instructions executed system.cpu.num_refs 2055 # Number of memory references system.cpu.workload.PROG:num_syscalls 13 # Number of system calls diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing/stdout b/tests/quick/00.hello/ref/mips/linux/simple-timing/stdout index ad6e002b5..08628c4d1 100644 --- a/tests/quick/00.hello/ref/mips/linux/simple-timing/stdout +++ b/tests/quick/00.hello/ref/mips/linux/simple-timing/stdout @@ -6,9 +6,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Aug 12 2007 17:11:48 -M5 started Sun Aug 12 17:11:50 2007 -M5 executing on zeep +M5 compiled Aug 14 2007 22:02:23 +M5 started Tue Aug 14 22:02:25 2007 +M5 executing on nacho command line: build/MIPS_SE/m5.fast -d build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-timing tests/run.py quick/00.hello/mips/linux/simple-timing Global frequency set at 1000000000000 ticks per second Exiting @ tick 18463000 because target called exit() |