diff options
Diffstat (limited to 'tests/quick/00.hello/ref/mips/linux')
6 files changed, 24 insertions, 72 deletions
diff --git a/tests/quick/00.hello/ref/mips/linux/simple-atomic/config.ini b/tests/quick/00.hello/ref/mips/linux/simple-atomic/config.ini index 766c4f486..5d677c743 100644 --- a/tests/quick/00.hello/ref/mips/linux/simple-atomic/config.ini +++ b/tests/quick/00.hello/ref/mips/linux/simple-atomic/config.ini @@ -11,7 +11,7 @@ physmem=system.physmem [system.cpu] type=AtomicSimpleCPU -children=dtb itb tlb tracer workload +children=dtb itb tracer workload CP0_Config=0 CP0_Config1=0 CP0_Config1_C2=false @@ -66,7 +66,6 @@ CP0_PerfCtr_M=false CP0_PerfCtr_W=false CP0_SrsCtl_HSS=0 CP0_WatchHi_M=false -UnifiedTLB=true checker=Null clock=500 cpu_id=0 @@ -87,7 +86,6 @@ progress_interval=0 simulate_data_stalls=false simulate_inst_stalls=false system=system -tlb=system.cpu.tlb tracer=system.cpu.tracer width=1 workload=system.cpu.workload @@ -95,15 +93,11 @@ dcache_port=system.membus.port[2] icache_port=system.membus.port[1] [system.cpu.dtb] -type=MipsDTB +type=MipsTLB size=64 [system.cpu.itb] -type=MipsITB -size=64 - -[system.cpu.tlb] -type=MipsUTB +type=MipsTLB size=64 [system.cpu.tracer] diff --git a/tests/quick/00.hello/ref/mips/linux/simple-atomic/simout b/tests/quick/00.hello/ref/mips/linux/simple-atomic/simout index 7b1955a4b..4fee53c4d 100755 --- a/tests/quick/00.hello/ref/mips/linux/simple-atomic/simout +++ b/tests/quick/00.hello/ref/mips/linux/simple-atomic/simout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 16 2009 00:16:15 -M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase -M5 started Feb 16 2009 00:16:42 -M5 executing on zizzer -command line: build/MIPS_SE/m5.fast -d build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-atomic -re tests/run.py quick/00.hello/mips/linux/simple-atomic +M5 compiled Apr 8 2009 12:30:01 +M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff +M5 started Apr 8 2009 12:33:27 +M5 executing on maize +command line: build/MIPS_SE/m5.fast -d build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-atomic -re tests/run.py build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/quick/00.hello/ref/mips/linux/simple-atomic/stats.txt b/tests/quick/00.hello/ref/mips/linux/simple-atomic/stats.txt index 20921ce17..a50f65423 100644 --- a/tests/quick/00.hello/ref/mips/linux/simple-atomic/stats.txt +++ b/tests/quick/00.hello/ref/mips/linux/simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 24803 # Simulator instruction rate (inst/s) -host_mem_usage 193824 # Number of bytes of host memory used -host_seconds 0.23 # Real time elapsed on the host -host_tick_rate 12384497 # Simulator tick rate (ticks/s) +host_inst_rate 113529 # Simulator instruction rate (inst/s) +host_mem_usage 195572 # Number of bytes of host memory used +host_seconds 0.05 # Real time elapsed on the host +host_tick_rate 56492209 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 5656 # Number of instructions simulated sim_seconds 0.000003 # Number of seconds simulated @@ -31,24 +31,6 @@ system.cpu.not_idle_fraction 1 # Pe system.cpu.numCycles 5657 # number of cpu cycles simulated system.cpu.num_insts 5656 # Number of instructions executed system.cpu.num_refs 2055 # Number of memory references -system.cpu.tlb.accesses 0 # DTB accesses -system.cpu.tlb.accesses 0 # DTB accesses -system.cpu.tlb.hits 0 # DTB hits -system.cpu.tlb.hits 0 # DTB hits -system.cpu.tlb.misses 0 # DTB misses -system.cpu.tlb.misses 0 # DTB misses -system.cpu.tlb.read_accesses 0 # DTB read accesses -system.cpu.tlb.read_accesses 0 # DTB read accesses -system.cpu.tlb.read_hits 0 # DTB read hits -system.cpu.tlb.read_hits 0 # DTB read hits -system.cpu.tlb.read_misses 0 # DTB read misses -system.cpu.tlb.read_misses 0 # DTB read misses -system.cpu.tlb.write_accesses 0 # DTB write accesses -system.cpu.tlb.write_accesses 0 # DTB write accesses -system.cpu.tlb.write_hits 0 # DTB write hits -system.cpu.tlb.write_hits 0 # DTB write hits -system.cpu.tlb.write_misses 0 # DTB write misses -system.cpu.tlb.write_misses 0 # DTB write misses system.cpu.workload.PROG:num_syscalls 13 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini b/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini index d6fb3e91a..ac73fcc0d 100644 --- a/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini +++ b/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini @@ -11,7 +11,7 @@ physmem=system.physmem [system.cpu] type=TimingSimpleCPU -children=dcache dtb icache itb l2cache tlb toL2Bus tracer workload +children=dcache dtb icache itb l2cache toL2Bus tracer workload CP0_Config=0 CP0_Config1=0 CP0_Config1_C2=false @@ -66,7 +66,6 @@ CP0_PerfCtr_M=false CP0_PerfCtr_W=false CP0_SrsCtl_HSS=0 CP0_WatchHi_M=false -UnifiedTLB=true checker=Null clock=500 cpu_id=0 @@ -85,7 +84,6 @@ numThreads=1 phase=0 progress_interval=0 system=system -tlb=system.cpu.tlb tracer=system.cpu.tracer workload=system.cpu.workload dcache_port=system.cpu.dcache.cpu_side @@ -124,7 +122,7 @@ cpu_side=system.cpu.dcache_port mem_side=system.cpu.toL2Bus.port[1] [system.cpu.dtb] -type=MipsDTB +type=MipsTLB size=64 [system.cpu.icache] @@ -160,7 +158,7 @@ cpu_side=system.cpu.icache_port mem_side=system.cpu.toL2Bus.port[0] [system.cpu.itb] -type=MipsITB +type=MipsTLB size=64 [system.cpu.l2cache] @@ -195,10 +193,6 @@ write_buffers=8 cpu_side=system.cpu.toL2Bus.port[2] mem_side=system.membus.port[1] -[system.cpu.tlb] -type=MipsUTB -size=64 - [system.cpu.toL2Bus] type=Bus block_size=64 diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing/simout b/tests/quick/00.hello/ref/mips/linux/simple-timing/simout index a5bd2cd4d..77ad52898 100755 --- a/tests/quick/00.hello/ref/mips/linux/simple-timing/simout +++ b/tests/quick/00.hello/ref/mips/linux/simple-timing/simout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 16 2009 00:16:15 -M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase -M5 started Feb 16 2009 00:16:42 -M5 executing on zizzer -command line: build/MIPS_SE/m5.fast -d build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-timing -re tests/run.py quick/00.hello/mips/linux/simple-timing +M5 compiled Apr 8 2009 12:30:01 +M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff +M5 started Apr 8 2009 12:30:04 +M5 executing on maize +command line: build/MIPS_SE/m5.fast -d build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-timing -re tests/run.py build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing/stats.txt b/tests/quick/00.hello/ref/mips/linux/simple-timing/stats.txt index de10d4a74..c7fdc027e 100644 --- a/tests/quick/00.hello/ref/mips/linux/simple-timing/stats.txt +++ b/tests/quick/00.hello/ref/mips/linux/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 26568 # Simulator instruction rate (inst/s) -host_mem_usage 201268 # Number of bytes of host memory used -host_seconds 0.21 # Real time elapsed on the host -host_tick_rate 151609105 # Simulator tick rate (ticks/s) +host_inst_rate 6063 # Simulator instruction rate (inst/s) +host_mem_usage 203244 # Number of bytes of host memory used +host_seconds 0.93 # Real time elapsed on the host +host_tick_rate 34635885 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 5656 # Number of instructions simulated sim_seconds 0.000032 # Number of seconds simulated @@ -218,24 +218,6 @@ system.cpu.not_idle_fraction 1 # Pe system.cpu.numCycles 64644 # number of cpu cycles simulated system.cpu.num_insts 5656 # Number of instructions executed system.cpu.num_refs 2055 # Number of memory references -system.cpu.tlb.accesses 0 # DTB accesses -system.cpu.tlb.accesses 0 # DTB accesses -system.cpu.tlb.hits 0 # DTB hits -system.cpu.tlb.hits 0 # DTB hits -system.cpu.tlb.misses 0 # DTB misses -system.cpu.tlb.misses 0 # DTB misses -system.cpu.tlb.read_accesses 0 # DTB read accesses -system.cpu.tlb.read_accesses 0 # DTB read accesses -system.cpu.tlb.read_hits 0 # DTB read hits -system.cpu.tlb.read_hits 0 # DTB read hits -system.cpu.tlb.read_misses 0 # DTB read misses -system.cpu.tlb.read_misses 0 # DTB read misses -system.cpu.tlb.write_accesses 0 # DTB write accesses -system.cpu.tlb.write_accesses 0 # DTB write accesses -system.cpu.tlb.write_hits 0 # DTB write hits -system.cpu.tlb.write_hits 0 # DTB write hits -system.cpu.tlb.write_misses 0 # DTB write misses -system.cpu.tlb.write_misses 0 # DTB write misses system.cpu.workload.PROG:num_syscalls 13 # Number of system calls ---------- End Simulation Statistics ---------- |