diff options
Diffstat (limited to 'tests/quick/00.hello/ref/mips/linux')
4 files changed, 547 insertions, 0 deletions
diff --git a/tests/quick/00.hello/ref/mips/linux/inorder-timing/config.ini b/tests/quick/00.hello/ref/mips/linux/inorder-timing/config.ini new file mode 100644 index 000000000..cf8b99da8 --- /dev/null +++ b/tests/quick/00.hello/ref/mips/linux/inorder-timing/config.ini @@ -0,0 +1,277 @@ +[root] +type=Root +children=system +dummy=0 + +[system] +type=System +children=cpu membus physmem +mem_mode=atomic +physmem=system.physmem + +[system.cpu] +type=InOrderCPU +children=dcache dtb icache itb l2cache toL2Bus tracer workload +BTBEntries=4096 +BTBTagSize=16 +CP0_Config=0 +CP0_Config1=0 +CP0_Config1_C2=false +CP0_Config1_CA=false +CP0_Config1_DA=0 +CP0_Config1_DL=0 +CP0_Config1_DS=0 +CP0_Config1_EP=false +CP0_Config1_FP=false +CP0_Config1_IA=0 +CP0_Config1_IL=0 +CP0_Config1_IS=0 +CP0_Config1_M=0 +CP0_Config1_MD=false +CP0_Config1_MMU=0 +CP0_Config1_PC=false +CP0_Config1_WR=false +CP0_Config2=0 +CP0_Config2_M=false +CP0_Config2_SA=0 +CP0_Config2_SL=0 +CP0_Config2_SS=0 +CP0_Config2_SU=0 +CP0_Config2_TA=0 +CP0_Config2_TL=0 +CP0_Config2_TS=0 +CP0_Config2_TU=0 +CP0_Config3=0 +CP0_Config3_DSPP=false +CP0_Config3_LPA=false +CP0_Config3_M=false +CP0_Config3_MT=false +CP0_Config3_SM=false +CP0_Config3_SP=false +CP0_Config3_TL=false +CP0_Config3_VEIC=false +CP0_Config3_VInt=false +CP0_Config_AR=0 +CP0_Config_AT=0 +CP0_Config_BE=0 +CP0_Config_MT=0 +CP0_Config_VI=0 +CP0_EBase_CPUNum=0 +CP0_IntCtl_IPPCI=0 +CP0_IntCtl_IPTI=0 +CP0_PRId=0 +CP0_PRId_CompanyID=0 +CP0_PRId_CompanyOptions=0 +CP0_PRId_ProcessorID=1 +CP0_PRId_Revision=0 +CP0_PerfCtr_M=false +CP0_PerfCtr_W=false +CP0_SrsCtl_HSS=0 +CP0_WatchHi_M=false +RASSize=16 +activity=0 +cachePorts=2 +checker=Null +choiceCtrBits=2 +choicePredictorSize=8192 +clock=500 +cpu_id=0 +dataMemPort=dcache_port +defer_registration=false +div16Latency=1 +div16RepeatRate=1 +div24Latency=1 +div24RepeatRate=1 +div32Latency=1 +div32RepeatRate=1 +div8Latency=1 +div8RepeatRate=1 +do_checkpoint_insts=true +do_statistics_insts=true +dtb=system.cpu.dtb +fetchMemPort=icache_port +functionTrace=false +functionTraceStart=0 +function_trace=false +function_trace_start=0 +globalCtrBits=2 +globalHistoryBits=13 +globalPredictorSize=8192 +instShiftAmt=2 +itb=system.cpu.itb +localCtrBits=2 +localHistoryBits=11 +localHistoryTableSize=2048 +localPredictorSize=2048 +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +memBlockSize=64 +multLatency=1 +multRepeatRate=1 +numThreads=1 +phase=0 +predType=tournament +progress_interval=0 +stageTracing=false +stageWidth=1 +system=system +tracer=system.cpu.tracer +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.dcache] +type=BaseCache +addr_range=0:18446744073709551615 +assoc=2 +block_size=64 +forward_snoops=true +hash_delay=1 +latency=1000 +max_miss_count=0 +mshrs=10 +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10000 +prefetch_on_access=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +repl=Null +size=262144 +subblock_size=0 +tgts_per_mshr=5 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.dcache_port +mem_side=system.cpu.toL2Bus.port[1] + +[system.cpu.dtb] +type=MipsTLB +size=64 + +[system.cpu.icache] +type=BaseCache +addr_range=0:18446744073709551615 +assoc=2 +block_size=64 +forward_snoops=true +hash_delay=1 +latency=1000 +max_miss_count=0 +mshrs=10 +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10000 +prefetch_on_access=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +repl=Null +size=131072 +subblock_size=0 +tgts_per_mshr=5 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.icache_port +mem_side=system.cpu.toL2Bus.port[0] + +[system.cpu.itb] +type=MipsTLB +size=64 + +[system.cpu.l2cache] +type=BaseCache +addr_range=0:18446744073709551615 +assoc=2 +block_size=64 +forward_snoops=true +hash_delay=1 +latency=10000 +max_miss_count=0 +mshrs=10 +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=100000 +prefetch_on_access=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +repl=Null +size=2097152 +subblock_size=0 +tgts_per_mshr=5 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.toL2Bus.port[2] +mem_side=system.membus.port[1] + +[system.cpu.toL2Bus] +type=Bus +block_size=64 +bus_id=0 +clock=1000 +header_cycles=1 +responder_set=false +width=64 +port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side + +[system.cpu.tracer] +type=ExeTracer + +[system.cpu.workload] +type=LiveProcess +cmd=hello +cwd= +egid=100 +env= +errout=cerr +euid=100 +executable=tests/test-progs/hello/bin/mips/linux/hello +gid=100 +input=cin +max_stack_size=67108864 +output=cout +pid=100 +ppid=99 +simpoint=0 +system=system +uid=100 + +[system.membus] +type=Bus +block_size=64 +bus_id=0 +clock=1000 +header_cycles=1 +responder_set=false +width=64 +port=system.physmem.port[0] system.cpu.l2cache.mem_side + +[system.physmem] +type=PhysicalMemory +file= +latency=30000 +latency_var=0 +null=false +range=0:134217727 +zero=false +port=system.membus.port[0] + diff --git a/tests/quick/00.hello/ref/mips/linux/inorder-timing/simerr b/tests/quick/00.hello/ref/mips/linux/inorder-timing/simerr new file mode 100755 index 000000000..eabe42249 --- /dev/null +++ b/tests/quick/00.hello/ref/mips/linux/inorder-timing/simerr @@ -0,0 +1,3 @@ +warn: Sockets disabled, not accepting gdb connections +For more information see: http://www.m5sim.org/warn/d946bea6 +hack: be nice to actually delete the event here diff --git a/tests/quick/00.hello/ref/mips/linux/inorder-timing/simout b/tests/quick/00.hello/ref/mips/linux/inorder-timing/simout new file mode 100755 index 000000000..56a68daea --- /dev/null +++ b/tests/quick/00.hello/ref/mips/linux/inorder-timing/simout @@ -0,0 +1,17 @@ +M5 Simulator System + +Copyright (c) 2001-2008 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled May 13 2009 01:40:41 +M5 revision 4c418376e894 6202 default tip +M5 started May 13 2009 01:40:42 +M5 executing on zooks +command line: build/MIPS_SE/m5.fast -d build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/inorder-timing -re tests/run.py build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/inorder-timing +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. +Hello World! +Exiting @ tick 29437500 because target called exit() diff --git a/tests/quick/00.hello/ref/mips/linux/inorder-timing/stats.txt b/tests/quick/00.hello/ref/mips/linux/inorder-timing/stats.txt new file mode 100644 index 000000000..577875f3a --- /dev/null +++ b/tests/quick/00.hello/ref/mips/linux/inorder-timing/stats.txt @@ -0,0 +1,250 @@ + +---------- Begin Simulation Statistics ---------- +host_inst_rate 23976 # Simulator instruction rate (inst/s) +host_mem_usage 152688 # Number of bytes of host memory used +host_seconds 0.24 # Real time elapsed on the host +host_tick_rate 124659634 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 5656 # Number of instructions simulated +sim_seconds 0.000029 # Number of seconds simulated +sim_ticks 29437500 # Number of ticks simulated +system.cpu.AGEN-Unit.instReqsProcessed 2055 # Number of Instructions Requests that completed in this resource. +system.cpu.Branch-Predictor.instReqsProcessed 5657 # Number of Instructions Requests that completed in this resource. +system.cpu.Branch-Predictor.predictedNotTaken 783 # Number of Branches Predicted As Not Taken (False). +system.cpu.Branch-Predictor.predictedTaken 96 # Number of Branches Predicted As Taken (True). +system.cpu.Decode-Unit.instReqsProcessed 5657 # Number of Instructions Requests that completed in this resource. +system.cpu.Execution-Unit.instReqsProcessed 3598 # Number of Instructions Requests that completed in this resource. +system.cpu.Execution-Unit.predictedNotTakenIncorrect 515 # Number of Branches Incorrectly Predicted As Not Taken). +system.cpu.Execution-Unit.predictedTakenIncorrect 34 # Number of Branches Incorrectly Predicted As Taken. +system.cpu.Fetch-Buffer-T0.instReqsProcessed 0 # Number of Instructions Requests that completed in this resource. +system.cpu.Fetch-Buffer-T0.instsBypassed 0 # Number of Instructions Bypassed. +system.cpu.Fetch-Buffer-T1.instReqsProcessed 0 # Number of Instructions Requests that completed in this resource. +system.cpu.Fetch-Buffer-T1.instsBypassed 0 # Number of Instructions Bypassed. +system.cpu.Fetch-Seq-Unit.instReqsProcessed 11315 # Number of Instructions Requests that completed in this resource. +system.cpu.Graduation-Unit.instReqsProcessed 5656 # Number of Instructions Requests that completed in this resource. +system.cpu.Mult-Div-Unit.divInstReqsProcessed 1 # Number of Divide Requests Processed. +system.cpu.Mult-Div-Unit.instReqsProcessed 8 # Number of Instructions Requests that completed in this resource. +system.cpu.Mult-Div-Unit.multInstReqsProcessed 3 # Number of Multiply Requests Processed. +system.cpu.RegFile-Manager.instReqsProcessed 10420 # Number of Instructions Requests that completed in this resource. +system.cpu.committedInsts 5656 # Number of Instructions Simulated (Per-Thread) +system.cpu.committedInsts_total 5656 # Number of Instructions Simulated (Total) +system.cpu.cpi 10.409477 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi_total 10.409477 # CPI: Total CPI of All Threads +system.cpu.dcache.ReadReq_accesses 1131 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 56207.317073 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53207.317073 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 1049 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 4609000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.072502 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 82 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_miss_latency 4363000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.072502 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 82 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_accesses 924 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 56554.687500 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53554.687500 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 860 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 3619500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.069264 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 64 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_miss_latency 3427500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.069264 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 64 # number of WriteReq MSHR misses +system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.dcache.avg_refs 14.568182 # Average number of references to valid blocks. +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.demand_accesses 2055 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 56359.589041 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 53359.589041 # average overall mshr miss latency +system.cpu.dcache.demand_hits 1909 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 8228500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.071046 # miss rate for demand accesses +system.cpu.dcache.demand_misses 146 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 7790500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.071046 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 146 # number of demand (read+write) MSHR misses +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.overall_accesses 2055 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 56359.589041 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 53359.589041 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.cpu.dcache.overall_hits 1909 # number of overall hits +system.cpu.dcache.overall_miss_latency 8228500 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.071046 # miss rate for overall accesses +system.cpu.dcache.overall_misses 146 # number of overall misses +system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 7790500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.071046 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 146 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.dcache.replacements 0 # number of replacements +system.cpu.dcache.sampled_refs 132 # Sample count of references to valid blocks. +system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.tagsinuse 84.205216 # Cycle average of tags in use +system.cpu.dcache.total_refs 1923 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 0 # number of writebacks +system.cpu.dcache_port.instReqsProcessed 2054 # Number of Instructions Requests that completed in this resource. +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.icache.ReadReq_accesses 5658 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 55772.277228 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 52772.277228 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 5355 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 16899000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.053552 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 303 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_miss_latency 15990000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.053552 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 303 # number of ReadReq MSHR misses +system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.icache.avg_refs 17.673267 # Average number of references to valid blocks. +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.demand_accesses 5658 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 55772.277228 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 52772.277228 # average overall mshr miss latency +system.cpu.icache.demand_hits 5355 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 16899000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.053552 # miss rate for demand accesses +system.cpu.icache.demand_misses 303 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 15990000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.053552 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 303 # number of demand (read+write) MSHR misses +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.icache.overall_accesses 5658 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 55772.277228 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 52772.277228 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.cpu.icache.overall_hits 5355 # number of overall hits +system.cpu.icache.overall_miss_latency 16899000 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.053552 # miss rate for overall accesses +system.cpu.icache.overall_misses 303 # number of overall misses +system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 15990000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.053552 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 303 # number of overall MSHR misses +system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.icache.replacements 13 # number of replacements +system.cpu.icache.sampled_refs 303 # Sample count of references to valid blocks. +system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.tagsinuse 135.958324 # Cycle average of tags in use +system.cpu.icache.total_refs 5355 # Total number of references to valid blocks. +system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.writebacks 0 # number of writebacks +system.cpu.icache_port.instReqsProcessed 5657 # Number of Instructions Requests that completed in this resource. +system.cpu.ipc 0.096066 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.ipc_total 0.096066 # IPC: Total IPC of All Threads +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.l2cache.ReadExReq_accesses 50 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_avg_miss_latency 52500 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40080 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_miss_latency 2625000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_misses 50 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 2004000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_misses 50 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_accesses 385 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 52052.219321 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40026.109661 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 19936000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.994805 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 383 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 15330000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.994805 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 383 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_accesses 14 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_avg_miss_latency 52535.714286 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40071.428571 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_miss_latency 735500 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_misses 14 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 561000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_misses 14 # number of UpgradeReq MSHR misses +system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.l2cache.avg_refs 0.005420 # Average number of references to valid blocks. +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.cache_copies 0 # number of cache copies performed +system.cpu.l2cache.demand_accesses 435 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 52103.926097 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 40032.332564 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 22561000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.995402 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 433 # number of demand (read+write) misses +system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_miss_latency 17334000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.995402 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 433 # number of demand (read+write) MSHR misses +system.cpu.l2cache.fast_writes 0 # number of fast writes performed +system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.overall_accesses 435 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 52103.926097 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 40032.332564 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.cpu.l2cache.overall_hits 2 # number of overall hits +system.cpu.l2cache.overall_miss_latency 22561000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.995402 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 433 # number of overall misses +system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_miss_latency 17334000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.995402 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 433 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.l2cache.replacements 0 # number of replacements +system.cpu.l2cache.sampled_refs 369 # Sample count of references to valid blocks. +system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.tagsinuse 183.249501 # Cycle average of tags in use +system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.writebacks 0 # number of writebacks +system.cpu.numCycles 58876 # number of cpu cycles simulated +system.cpu.smtCommittedInsts 0 # Number of SMT Instructions Simulated (Per-Thread) +system.cpu.smtCycles 0 # Total number of cycles that the CPU was simultaneous multithreading.(SMT) +system.cpu.smt_cpi no_value # CPI: Total SMT-CPI +system.cpu.smt_ipc no_value # IPC: Total SMT-IPC +system.cpu.threadCycles 58876 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.workload.PROG:num_syscalls 13 # Number of system calls + +---------- End Simulation Statistics ---------- |