diff options
Diffstat (limited to 'tests/quick/00.hello/ref/mips/linux')
20 files changed, 0 insertions, 2579 deletions
diff --git a/tests/quick/00.hello/ref/mips/linux/inorder-timing/config.ini b/tests/quick/00.hello/ref/mips/linux/inorder-timing/config.ini deleted file mode 100644 index 1ccb30b9c..000000000 --- a/tests/quick/00.hello/ref/mips/linux/inorder-timing/config.ini +++ /dev/null @@ -1,240 +0,0 @@ -[root] -type=Root -children=system -time_sync_enable=false -time_sync_period=100000000000 -time_sync_spin_threshold=100000000 - -[system] -type=System -children=cpu membus physmem -mem_mode=atomic -memories=system.physmem -num_work_ids=16 -physmem=system.physmem -work_begin_ckpt_count=0 -work_begin_cpu_id_exit=-1 -work_begin_exit_count=0 -work_cpus_ckpt_count=0 -work_end_ckpt_count=0 -work_end_exit_count=0 -work_item_id=-1 -system_port=system.membus.port[0] - -[system.cpu] -type=InOrderCPU -children=dcache dtb icache itb l2cache toL2Bus tracer workload -BTBEntries=4096 -BTBTagSize=16 -RASSize=16 -activity=0 -cachePorts=2 -checker=Null -choiceCtrBits=2 -choicePredictorSize=8192 -clock=500 -cpu_id=0 -dataMemPort=dcache_port -defer_registration=false -div16Latency=1 -div16RepeatRate=1 -div24Latency=1 -div24RepeatRate=1 -div32Latency=1 -div32RepeatRate=1 -div8Latency=1 -div8RepeatRate=1 -do_checkpoint_insts=true -do_statistics_insts=true -dtb=system.cpu.dtb -fetchBuffSize=4 -fetchMemPort=icache_port -functionTrace=false -functionTraceStart=0 -function_trace=false -function_trace_start=0 -globalCtrBits=2 -globalHistoryBits=13 -globalPredictorSize=8192 -instShiftAmt=2 -itb=system.cpu.itb -localCtrBits=2 -localHistoryBits=11 -localHistoryTableSize=2048 -localPredictorSize=2048 -max_insts_all_threads=0 -max_insts_any_thread=0 -max_loads_all_threads=0 -max_loads_any_thread=0 -memBlockSize=64 -multLatency=1 -multRepeatRate=1 -numThreads=1 -phase=0 -predType=tournament -progress_interval=0 -stageTracing=false -stageWidth=4 -system=system -threadModel=SMT -tracer=system.cpu.tracer -workload=system.cpu.workload -dcache_port=system.cpu.dcache.cpu_side -icache_port=system.cpu.icache.cpu_side - -[system.cpu.dcache] -type=BaseCache -addr_range=0:18446744073709551615 -assoc=2 -block_size=64 -forward_snoops=true -hash_delay=1 -is_top_level=true -latency=1000 -max_miss_count=0 -mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 -prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 -prioritizeRequests=false -repl=Null -size=262144 -subblock_size=0 -tgts_per_mshr=5 -trace_addr=0 -two_queue=false -write_buffers=8 -cpu_side=system.cpu.dcache_port -mem_side=system.cpu.toL2Bus.port[1] - -[system.cpu.dtb] -type=MipsTLB -size=64 - -[system.cpu.icache] -type=BaseCache -addr_range=0:18446744073709551615 -assoc=2 -block_size=64 -forward_snoops=true -hash_delay=1 -is_top_level=true -latency=1000 -max_miss_count=0 -mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 -prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 -prioritizeRequests=false -repl=Null -size=131072 -subblock_size=0 -tgts_per_mshr=5 -trace_addr=0 -two_queue=false -write_buffers=8 -cpu_side=system.cpu.icache_port -mem_side=system.cpu.toL2Bus.port[0] - -[system.cpu.itb] -type=MipsTLB -size=64 - -[system.cpu.l2cache] -type=BaseCache -addr_range=0:18446744073709551615 -assoc=2 -block_size=64 -forward_snoops=true -hash_delay=1 -is_top_level=false -latency=10000 -max_miss_count=0 -mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=100000 -prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 -prioritizeRequests=false -repl=Null -size=2097152 -subblock_size=0 -tgts_per_mshr=5 -trace_addr=0 -two_queue=false -write_buffers=8 -cpu_side=system.cpu.toL2Bus.port[2] -mem_side=system.membus.port[2] - -[system.cpu.toL2Bus] -type=Bus -block_size=64 -bus_id=0 -clock=1000 -header_cycles=1 -use_default_range=false -width=64 -port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side - -[system.cpu.tracer] -type=ExeTracer - -[system.cpu.workload] -type=LiveProcess -cmd=hello -cwd= -egid=100 -env= -errout=cerr -euid=100 -executable=/dist/m5/regression/test-progs/hello/bin/mips/linux/hello -gid=100 -input=cin -max_stack_size=67108864 -output=cout -pid=100 -ppid=99 -simpoint=0 -system=system -uid=100 - -[system.membus] -type=Bus -block_size=64 -bus_id=0 -clock=1000 -header_cycles=1 -use_default_range=false -width=64 -port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side - -[system.physmem] -type=PhysicalMemory -file= -latency=30000 -latency_var=0 -null=false -range=0:134217727 -zero=false -port=system.membus.port[1] - diff --git a/tests/quick/00.hello/ref/mips/linux/inorder-timing/simerr b/tests/quick/00.hello/ref/mips/linux/inorder-timing/simerr deleted file mode 100755 index e45cd058f..000000000 --- a/tests/quick/00.hello/ref/mips/linux/inorder-timing/simerr +++ /dev/null @@ -1,2 +0,0 @@ -warn: Sockets disabled, not accepting gdb connections -hack: be nice to actually delete the event here diff --git a/tests/quick/00.hello/ref/mips/linux/inorder-timing/simout b/tests/quick/00.hello/ref/mips/linux/inorder-timing/simout deleted file mode 100755 index 677598e87..000000000 --- a/tests/quick/00.hello/ref/mips/linux/inorder-timing/simout +++ /dev/null @@ -1,12 +0,0 @@ -gem5 Simulator System. http://gem5.org -gem5 is copyrighted software; use the --copyright option for details. - -gem5 compiled Jan 23 2012 03:56:13 -gem5 started Jan 23 2012 04:23:29 -gem5 executing on zizzer -command line: build/MIPS_SE/gem5.opt -d build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/inorder-timing -re tests/run.py build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/inorder-timing -Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -info: Increasing stack size by one page. -Hello World! -Exiting @ tick 19785000 because target called exit() diff --git a/tests/quick/00.hello/ref/mips/linux/inorder-timing/stats.txt b/tests/quick/00.hello/ref/mips/linux/inorder-timing/stats.txt deleted file mode 100644 index 78172e7b6..000000000 --- a/tests/quick/00.hello/ref/mips/linux/inorder-timing/stats.txt +++ /dev/null @@ -1,295 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 0.000020 # Number of seconds simulated -sim_ticks 19785000 # Number of ticks simulated -final_tick 19785000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 71616 # Simulator instruction rate (inst/s) -host_tick_rate 243111037 # Simulator tick rate (ticks/s) -host_mem_usage 208328 # Number of bytes of host memory used -host_seconds 0.08 # Real time elapsed on the host -sim_insts 5827 # Number of instructions simulated -system.physmem.bytes_read 29120 # Number of bytes read from this memory -system.physmem.bytes_inst_read 20288 # Number of instructions bytes read from this memory -system.physmem.bytes_written 0 # Number of bytes written to this memory -system.physmem.num_reads 455 # Number of read requests responded to by this memory -system.physmem.num_writes 0 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 1471822087 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 1025423300 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total 1471822087 # Total bandwidth to/from this memory (bytes/s) -system.cpu.dtb.read_hits 0 # DTB read hits -system.cpu.dtb.read_misses 0 # DTB read misses -system.cpu.dtb.read_accesses 0 # DTB read accesses -system.cpu.dtb.write_hits 0 # DTB write hits -system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.dtb.write_accesses 0 # DTB write accesses -system.cpu.dtb.hits 0 # DTB hits -system.cpu.dtb.misses 0 # DTB misses -system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.hits 0 # DTB hits -system.cpu.itb.misses 0 # DTB misses -system.cpu.itb.accesses 0 # DTB accesses -system.cpu.workload.num_syscalls 8 # Number of system calls -system.cpu.numCycles 39571 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 9159 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) -system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 403 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 34166 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 5405 # Number of cycles cpu stages are processed. -system.cpu.activity 13.658993 # Percentage of cycles cpu is active -system.cpu.comLoads 1164 # Number of Load instructions committed -system.cpu.comStores 925 # Number of Store instructions committed -system.cpu.comBranches 916 # Number of Branches instructions committed -system.cpu.comNops 657 # Number of Nop instructions committed -system.cpu.comNonSpec 10 # Number of Non-Speculative instructions committed -system.cpu.comInts 2155 # Number of Integer instructions committed -system.cpu.comFloats 0 # Number of Floating Point instructions committed -system.cpu.committedInsts 5827 # Number of Instructions Simulated (Per-Thread) -system.cpu.smtCommittedInsts 0 # Number of SMT Instructions Simulated (Per-Thread) -system.cpu.committedInsts_total 5827 # Number of Instructions Simulated (Total) -system.cpu.cpi 6.790973 # CPI: Cycles Per Instruction (Per-Thread) -system.cpu.smt_cpi no_value # CPI: Total SMT-CPI -system.cpu.cpi_total 6.790973 # CPI: Total CPI of All Threads -system.cpu.ipc 0.147254 # IPC: Instructions Per Cycle (Per-Thread) -system.cpu.smt_ipc no_value # IPC: Total SMT-IPC -system.cpu.ipc_total 0.147254 # IPC: Total IPC of All Threads -system.cpu.branch_predictor.lookups 1185 # Number of BP lookups -system.cpu.branch_predictor.condPredicted 896 # Number of conditional branches predicted -system.cpu.branch_predictor.condIncorrect 611 # Number of conditional branches incorrect -system.cpu.branch_predictor.BTBLookups 1035 # Number of BTB lookups -system.cpu.branch_predictor.BTBHits 443 # Number of BTB hits -system.cpu.branch_predictor.usedRAS 86 # Number of times the RAS was used to get a target. -system.cpu.branch_predictor.RASInCorrect 32 # Number of incorrect RAS predictions. -system.cpu.branch_predictor.BTBHitPct 42.801932 # BTB Hit Percentage -system.cpu.branch_predictor.predictedTaken 536 # Number of Branches Predicted As Taken (True). -system.cpu.branch_predictor.predictedNotTaken 649 # Number of Branches Predicted As Not Taken (False). -system.cpu.regfile_manager.intRegFileReads 5108 # Number of Reads from Int. Register File -system.cpu.regfile_manager.intRegFileWrites 3408 # Number of Writes to Int. Register File -system.cpu.regfile_manager.intRegFileAccesses 8516 # Total Accesses (Read+Write) to the Int. Register File -system.cpu.regfile_manager.floatRegFileReads 3 # Number of Reads from FP Register File -system.cpu.regfile_manager.floatRegFileWrites 1 # Number of Writes to FP Register File -system.cpu.regfile_manager.floatRegFileAccesses 4 # Total Accesses (Read+Write) to the FP Register File -system.cpu.regfile_manager.regForwards 1344 # Number of Registers Read Through Forwarding Logic -system.cpu.agen_unit.agens 2228 # Number of Address Generations -system.cpu.execution_unit.predictedTakenIncorrect 317 # Number of Branches Incorrectly Predicted As Taken. -system.cpu.execution_unit.predictedNotTakenIncorrect 285 # Number of Branches Incorrectly Predicted As Not Taken). -system.cpu.execution_unit.mispredicted 602 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.predicted 314 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.mispredictPct 65.720524 # Percentage of Incorrect Branches Predicts -system.cpu.execution_unit.executions 3132 # Number of Instructions Executed. -system.cpu.mult_div_unit.multiplies 3 # Number of Multipy Operations Executed -system.cpu.mult_div_unit.divides 1 # Number of Divide Operations Executed -system.cpu.stage0.idleCycles 35846 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 3725 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 9.413459 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 36723 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 2848 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 7.197190 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 36778 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 2793 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 7.058199 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 38328 # Number of cycles 0 instructions are processed. -system.cpu.stage3.runCycles 1243 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 3.141189 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 36666 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 2905 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 7.341235 # Percentage of cycles stage was utilized (processing insts). -system.cpu.icache.replacements 13 # number of replacements -system.cpu.icache.tagsinuse 148.138598 # Cycle average of tags in use -system.cpu.icache.total_refs 443 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 319 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 1.388715 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 148.138598 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.072333 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 443 # number of ReadReq hits -system.cpu.icache.demand_hits 443 # number of demand (read+write) hits -system.cpu.icache.overall_hits 443 # number of overall hits -system.cpu.icache.ReadReq_misses 341 # number of ReadReq misses -system.cpu.icache.demand_misses 341 # number of demand (read+write) misses -system.cpu.icache.overall_misses 341 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 19027500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 19027500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 19027500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 784 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 784 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 784 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.434949 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.434949 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.434949 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 55799.120235 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 55799.120235 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 55799.120235 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 29000 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 29000 # average number of cycles each access was blocked -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 22 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 22 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 22 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 319 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 319 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 319 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 16952500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 16952500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 16952500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.406888 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.406888 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.406888 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 53142.633229 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 53142.633229 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 53142.633229 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 89.732679 # Cycle average of tags in use -system.cpu.dcache.total_refs 1838 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 138 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 13.318841 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 89.732679 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.021907 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 1075 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 763 # number of WriteReq hits -system.cpu.dcache.demand_hits 1838 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 1838 # number of overall hits -system.cpu.dcache.ReadReq_misses 89 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 162 # number of WriteReq misses -system.cpu.dcache.demand_misses 251 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 251 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 5072500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 8912000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency 13984500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 13984500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 1164 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses 925 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 2089 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 2089 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.076460 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.175135 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate 0.120153 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.120153 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 56994.382022 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 55012.345679 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency 55715.139442 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 55715.139442 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 1153500 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 23 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 50152.173913 # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 2 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 111 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits 113 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 113 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 87 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 51 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 138 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 138 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 4702500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 2746000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 7448500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 7448500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.074742 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate 0.055135 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.066060 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.066060 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 54051.724138 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53843.137255 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 53974.637681 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 53974.637681 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 205.469583 # Cycle average of tags in use -system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 404 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.004950 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 205.469583 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.006270 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits -system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 2 # number of overall hits -system.cpu.l2cache.ReadReq_misses 404 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses 51 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 455 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 455 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 21170500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 2682500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 23853000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 23853000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 406 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 51 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 457 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 457 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.995074 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.995624 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.995624 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 52402.227723 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 52598.039216 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 52424.175824 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 52424.175824 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 404 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 51 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 455 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 455 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 16247000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 2058000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 18305000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 18305000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.995074 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.995624 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.995624 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40215.346535 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40352.941176 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 40230.769231 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 40230.769231 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate - ----------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/mips/linux/o3-timing/config.ini b/tests/quick/00.hello/ref/mips/linux/o3-timing/config.ini deleted file mode 100644 index 508c3cad4..000000000 --- a/tests/quick/00.hello/ref/mips/linux/o3-timing/config.ini +++ /dev/null @@ -1,535 +0,0 @@ -[root] -type=Root -children=system -time_sync_enable=false -time_sync_period=100000000000 -time_sync_spin_threshold=100000000 - -[system] -type=System -children=cpu membus physmem -mem_mode=atomic -memories=system.physmem -num_work_ids=16 -physmem=system.physmem -work_begin_ckpt_count=0 -work_begin_cpu_id_exit=-1 -work_begin_exit_count=0 -work_cpus_ckpt_count=0 -work_end_ckpt_count=0 -work_end_exit_count=0 -work_item_id=-1 -system_port=system.membus.port[0] - -[system.cpu] -type=DerivO3CPU -children=dcache dtb fuPool icache itb l2cache toL2Bus tracer workload -BTBEntries=4096 -BTBTagSize=16 -LFSTSize=1024 -LQEntries=32 -LSQCheckLoads=true -LSQDepCheckShift=4 -RASSize=16 -SQEntries=32 -SSITSize=1024 -activity=0 -backComSize=5 -cachePorts=200 -checker=Null -choiceCtrBits=2 -choicePredictorSize=8192 -clock=500 -commitToDecodeDelay=1 -commitToFetchDelay=1 -commitToIEWDelay=1 -commitToRenameDelay=1 -commitWidth=8 -cpu_id=0 -decodeToFetchDelay=1 -decodeToRenameDelay=1 -decodeWidth=8 -defer_registration=false -dispatchWidth=8 -do_checkpoint_insts=true -do_statistics_insts=true -dtb=system.cpu.dtb -fetchToDecodeDelay=1 -fetchTrapLatency=1 -fetchWidth=8 -forwardComSize=5 -fuPool=system.cpu.fuPool -function_trace=false -function_trace_start=0 -globalCtrBits=2 -globalHistoryBits=13 -globalPredictorSize=8192 -iewToCommitDelay=1 -iewToDecodeDelay=1 -iewToFetchDelay=1 -iewToRenameDelay=1 -instShiftAmt=2 -issueToExecuteDelay=1 -issueWidth=8 -itb=system.cpu.itb -localCtrBits=2 -localHistoryBits=11 -localHistoryTableSize=2048 -localPredictorSize=2048 -max_insts_all_threads=0 -max_insts_any_thread=0 -max_loads_all_threads=0 -max_loads_any_thread=0 -numIQEntries=64 -numPhysFloatRegs=256 -numPhysIntRegs=256 -numROBEntries=192 -numRobs=1 -numThreads=1 -phase=0 -predType=tournament -progress_interval=0 -renameToDecodeDelay=1 -renameToFetchDelay=1 -renameToIEWDelay=2 -renameToROBDelay=1 -renameWidth=8 -smtCommitPolicy=RoundRobin -smtFetchPolicy=SingleThread -smtIQPolicy=Partitioned -smtIQThreshold=100 -smtLSQPolicy=Partitioned -smtLSQThreshold=100 -smtNumFetchingThreads=1 -smtROBPolicy=Partitioned -smtROBThreshold=100 -squashWidth=8 -store_set_clear_period=250000 -system=system -tracer=system.cpu.tracer -trapLatency=13 -wbDepth=1 -wbWidth=8 -workload=system.cpu.workload -dcache_port=system.cpu.dcache.cpu_side -icache_port=system.cpu.icache.cpu_side - -[system.cpu.dcache] -type=BaseCache -addr_range=0:18446744073709551615 -assoc=2 -block_size=64 -forward_snoops=true -hash_delay=1 -is_top_level=true -latency=1000 -max_miss_count=0 -mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 -prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 -prioritizeRequests=false -repl=Null -size=262144 -subblock_size=0 -tgts_per_mshr=20 -trace_addr=0 -two_queue=false -write_buffers=8 -cpu_side=system.cpu.dcache_port -mem_side=system.cpu.toL2Bus.port[1] - -[system.cpu.dtb] -type=MipsTLB -size=64 - -[system.cpu.fuPool] -type=FUPool -children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 -FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 - -[system.cpu.fuPool.FUList0] -type=FUDesc -children=opList -count=6 -opList=system.cpu.fuPool.FUList0.opList - -[system.cpu.fuPool.FUList0.opList] -type=OpDesc -issueLat=1 -opClass=IntAlu -opLat=1 - -[system.cpu.fuPool.FUList1] -type=FUDesc -children=opList0 opList1 -count=2 -opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 - -[system.cpu.fuPool.FUList1.opList0] -type=OpDesc -issueLat=1 -opClass=IntMult -opLat=3 - -[system.cpu.fuPool.FUList1.opList1] -type=OpDesc -issueLat=19 -opClass=IntDiv -opLat=20 - -[system.cpu.fuPool.FUList2] -type=FUDesc -children=opList0 opList1 opList2 -count=4 -opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 - -[system.cpu.fuPool.FUList2.opList0] -type=OpDesc -issueLat=1 -opClass=FloatAdd -opLat=2 - -[system.cpu.fuPool.FUList2.opList1] -type=OpDesc -issueLat=1 -opClass=FloatCmp -opLat=2 - -[system.cpu.fuPool.FUList2.opList2] -type=OpDesc -issueLat=1 -opClass=FloatCvt -opLat=2 - -[system.cpu.fuPool.FUList3] -type=FUDesc -children=opList0 opList1 opList2 -count=2 -opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 - -[system.cpu.fuPool.FUList3.opList0] -type=OpDesc -issueLat=1 -opClass=FloatMult -opLat=4 - -[system.cpu.fuPool.FUList3.opList1] -type=OpDesc -issueLat=12 -opClass=FloatDiv -opLat=12 - -[system.cpu.fuPool.FUList3.opList2] -type=OpDesc -issueLat=24 -opClass=FloatSqrt -opLat=24 - -[system.cpu.fuPool.FUList4] -type=FUDesc -children=opList -count=0 -opList=system.cpu.fuPool.FUList4.opList - -[system.cpu.fuPool.FUList4.opList] -type=OpDesc -issueLat=1 -opClass=MemRead -opLat=1 - -[system.cpu.fuPool.FUList5] -type=FUDesc -children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 -count=4 -opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 - -[system.cpu.fuPool.FUList5.opList00] -type=OpDesc -issueLat=1 -opClass=SimdAdd -opLat=1 - -[system.cpu.fuPool.FUList5.opList01] -type=OpDesc -issueLat=1 -opClass=SimdAddAcc -opLat=1 - -[system.cpu.fuPool.FUList5.opList02] -type=OpDesc -issueLat=1 -opClass=SimdAlu -opLat=1 - -[system.cpu.fuPool.FUList5.opList03] -type=OpDesc -issueLat=1 -opClass=SimdCmp -opLat=1 - -[system.cpu.fuPool.FUList5.opList04] -type=OpDesc -issueLat=1 -opClass=SimdCvt -opLat=1 - -[system.cpu.fuPool.FUList5.opList05] -type=OpDesc -issueLat=1 -opClass=SimdMisc -opLat=1 - -[system.cpu.fuPool.FUList5.opList06] -type=OpDesc -issueLat=1 -opClass=SimdMult -opLat=1 - -[system.cpu.fuPool.FUList5.opList07] -type=OpDesc -issueLat=1 -opClass=SimdMultAcc -opLat=1 - -[system.cpu.fuPool.FUList5.opList08] -type=OpDesc -issueLat=1 -opClass=SimdShift -opLat=1 - -[system.cpu.fuPool.FUList5.opList09] -type=OpDesc -issueLat=1 -opClass=SimdShiftAcc -opLat=1 - -[system.cpu.fuPool.FUList5.opList10] -type=OpDesc -issueLat=1 -opClass=SimdSqrt -opLat=1 - -[system.cpu.fuPool.FUList5.opList11] -type=OpDesc -issueLat=1 -opClass=SimdFloatAdd -opLat=1 - -[system.cpu.fuPool.FUList5.opList12] -type=OpDesc -issueLat=1 -opClass=SimdFloatAlu -opLat=1 - -[system.cpu.fuPool.FUList5.opList13] -type=OpDesc -issueLat=1 -opClass=SimdFloatCmp -opLat=1 - -[system.cpu.fuPool.FUList5.opList14] -type=OpDesc -issueLat=1 -opClass=SimdFloatCvt -opLat=1 - -[system.cpu.fuPool.FUList5.opList15] -type=OpDesc -issueLat=1 -opClass=SimdFloatDiv -opLat=1 - -[system.cpu.fuPool.FUList5.opList16] -type=OpDesc -issueLat=1 -opClass=SimdFloatMisc -opLat=1 - -[system.cpu.fuPool.FUList5.opList17] -type=OpDesc -issueLat=1 -opClass=SimdFloatMult -opLat=1 - -[system.cpu.fuPool.FUList5.opList18] -type=OpDesc -issueLat=1 -opClass=SimdFloatMultAcc -opLat=1 - -[system.cpu.fuPool.FUList5.opList19] -type=OpDesc -issueLat=1 -opClass=SimdFloatSqrt -opLat=1 - -[system.cpu.fuPool.FUList6] -type=FUDesc -children=opList -count=0 -opList=system.cpu.fuPool.FUList6.opList - -[system.cpu.fuPool.FUList6.opList] -type=OpDesc -issueLat=1 -opClass=MemWrite -opLat=1 - -[system.cpu.fuPool.FUList7] -type=FUDesc -children=opList0 opList1 -count=4 -opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 - -[system.cpu.fuPool.FUList7.opList0] -type=OpDesc -issueLat=1 -opClass=MemRead -opLat=1 - -[system.cpu.fuPool.FUList7.opList1] -type=OpDesc -issueLat=1 -opClass=MemWrite -opLat=1 - -[system.cpu.fuPool.FUList8] -type=FUDesc -children=opList -count=1 -opList=system.cpu.fuPool.FUList8.opList - -[system.cpu.fuPool.FUList8.opList] -type=OpDesc -issueLat=3 -opClass=IprAccess -opLat=3 - -[system.cpu.icache] -type=BaseCache -addr_range=0:18446744073709551615 -assoc=2 -block_size=64 -forward_snoops=true -hash_delay=1 -is_top_level=true -latency=1000 -max_miss_count=0 -mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 -prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 -prioritizeRequests=false -repl=Null -size=131072 -subblock_size=0 -tgts_per_mshr=20 -trace_addr=0 -two_queue=false -write_buffers=8 -cpu_side=system.cpu.icache_port -mem_side=system.cpu.toL2Bus.port[0] - -[system.cpu.itb] -type=MipsTLB -size=64 - -[system.cpu.l2cache] -type=BaseCache -addr_range=0:18446744073709551615 -assoc=2 -block_size=64 -forward_snoops=true -hash_delay=1 -is_top_level=false -latency=1000 -max_miss_count=0 -mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 -prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 -prioritizeRequests=false -repl=Null -size=2097152 -subblock_size=0 -tgts_per_mshr=5 -trace_addr=0 -two_queue=false -write_buffers=8 -cpu_side=system.cpu.toL2Bus.port[2] -mem_side=system.membus.port[2] - -[system.cpu.toL2Bus] -type=Bus -block_size=64 -bus_id=0 -clock=1000 -header_cycles=1 -use_default_range=false -width=64 -port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side - -[system.cpu.tracer] -type=ExeTracer - -[system.cpu.workload] -type=LiveProcess -cmd=hello -cwd= -egid=100 -env= -errout=cerr -euid=100 -executable=/dist/m5/regression/test-progs/hello/bin/mips/linux/hello -gid=100 -input=cin -max_stack_size=67108864 -output=cout -pid=100 -ppid=99 -simpoint=0 -system=system -uid=100 - -[system.membus] -type=Bus -block_size=64 -bus_id=0 -clock=1000 -header_cycles=1 -use_default_range=false -width=64 -port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side - -[system.physmem] -type=PhysicalMemory -file= -latency=30000 -latency_var=0 -null=false -range=0:134217727 -zero=false -port=system.membus.port[1] - diff --git a/tests/quick/00.hello/ref/mips/linux/o3-timing/simerr b/tests/quick/00.hello/ref/mips/linux/o3-timing/simerr deleted file mode 100755 index e45cd058f..000000000 --- a/tests/quick/00.hello/ref/mips/linux/o3-timing/simerr +++ /dev/null @@ -1,2 +0,0 @@ -warn: Sockets disabled, not accepting gdb connections -hack: be nice to actually delete the event here diff --git a/tests/quick/00.hello/ref/mips/linux/o3-timing/simout b/tests/quick/00.hello/ref/mips/linux/o3-timing/simout deleted file mode 100755 index eb1e6f70f..000000000 --- a/tests/quick/00.hello/ref/mips/linux/o3-timing/simout +++ /dev/null @@ -1,12 +0,0 @@ -gem5 Simulator System. http://gem5.org -gem5 is copyrighted software; use the --copyright option for details. - -gem5 compiled Jan 23 2012 03:56:13 -gem5 started Jan 23 2012 04:23:41 -gem5 executing on zizzer -command line: build/MIPS_SE/gem5.opt -d build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/o3-timing -re tests/run.py build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/o3-timing -Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -info: Increasing stack size by one page. -Hello World! -Exiting @ tick 12272500 because target called exit() diff --git a/tests/quick/00.hello/ref/mips/linux/o3-timing/stats.txt b/tests/quick/00.hello/ref/mips/linux/o3-timing/stats.txt deleted file mode 100644 index e49d82dd9..000000000 --- a/tests/quick/00.hello/ref/mips/linux/o3-timing/stats.txt +++ /dev/null @@ -1,492 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 0.000012 # Number of seconds simulated -sim_ticks 12272500 # Number of ticks simulated -final_tick 12272500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 65845 # Simulator instruction rate (inst/s) -host_tick_rate 156294886 # Simulator tick rate (ticks/s) -host_mem_usage 208908 # Number of bytes of host memory used -host_seconds 0.08 # Real time elapsed on the host -sim_insts 5169 # Number of instructions simulated -system.physmem.bytes_read 30400 # Number of bytes read from this memory -system.physmem.bytes_inst_read 21312 # Number of instructions bytes read from this memory -system.physmem.bytes_written 0 # Number of bytes written to this memory -system.physmem.num_reads 475 # Number of read requests responded to by this memory -system.physmem.num_writes 0 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 2477082909 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 1736565492 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total 2477082909 # Total bandwidth to/from this memory (bytes/s) -system.cpu.dtb.read_hits 0 # DTB read hits -system.cpu.dtb.read_misses 0 # DTB read misses -system.cpu.dtb.read_accesses 0 # DTB read accesses -system.cpu.dtb.write_hits 0 # DTB write hits -system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.dtb.write_accesses 0 # DTB write accesses -system.cpu.dtb.hits 0 # DTB hits -system.cpu.dtb.misses 0 # DTB misses -system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.hits 0 # DTB hits -system.cpu.itb.misses 0 # DTB misses -system.cpu.itb.accesses 0 # DTB accesses -system.cpu.workload.num_syscalls 8 # Number of system calls -system.cpu.numCycles 24546 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 1975 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 1343 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 399 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 1578 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 493 # Number of BTB hits -system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 251 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 71 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 7903 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 12258 # Number of instructions fetch has processed -system.cpu.fetch.Branches 1975 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 744 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 3024 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1186 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 756 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 145 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 1781 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 229 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 12608 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.972240 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.277843 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 9584 76.02% 76.02% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1250 9.91% 85.93% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 108 0.86% 86.79% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 139 1.10% 87.89% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 289 2.29% 90.18% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 92 0.73% 90.91% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 132 1.05% 91.96% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 145 1.15% 93.11% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 869 6.89% 100.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 12608 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.080461 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.499389 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 8092 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 871 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 2857 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 51 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 737 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 107 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 43 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 11425 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 162 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 737 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 8263 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 258 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 499 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 2740 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 111 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 11004 # Number of instructions processed by rename -system.cpu.rename.LSQFullEvents 101 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 6697 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 13109 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 13105 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 4 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 3410 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 3287 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 18 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 11 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 281 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2346 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1174 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 1 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 8640 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 13 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 7815 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 50 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 2984 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 1806 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 3 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 12608 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.619845 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.285923 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 9257 73.42% 73.42% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1317 10.45% 83.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 832 6.60% 90.47% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 510 4.05% 94.51% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 356 2.82% 97.34% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 201 1.59% 98.93% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 85 0.67% 99.60% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 35 0.28% 99.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 15 0.12% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 12608 # Number of insts issued each cycle -system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 3 2.05% 2.05% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 2.05% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 2.05% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.05% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.05% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.05% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 2.05% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.05% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 2.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 2.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.05% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 91 62.33% 64.38% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 52 35.62% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 4596 58.81% 58.81% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 4 0.05% 58.86% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 2 0.03% 58.89% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2 0.03% 58.91% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 58.91% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 58.91% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 58.91% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 58.91% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 58.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 58.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 58.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 58.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 58.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 58.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 58.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 58.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 58.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 58.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 58.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 58.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 58.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 58.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 58.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 58.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 58.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 58.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 58.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 58.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 58.91% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2128 27.23% 86.14% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1083 13.86% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 7815 # Type of FU issued -system.cpu.iq.rate 0.318382 # Inst issue rate -system.cpu.iq.fu_busy_cnt 146 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.018682 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 28430 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 11643 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 7116 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 4 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 2 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 2 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 7959 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 2 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 65 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1182 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 4 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 8 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 249 # Number of stores squashed -system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 737 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 165 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 13 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 10031 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 128 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2346 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1174 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 13 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 6 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 8 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 107 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 309 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 416 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 7531 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 2028 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 284 # Number of squashed instructions skipped in execute -system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 1378 # number of nop insts executed -system.cpu.iew.exec_refs 3087 # number of memory reference insts executed -system.cpu.iew.exec_branches 1271 # Number of branches executed -system.cpu.iew.exec_stores 1059 # Number of stores executed -system.cpu.iew.exec_rate 0.306812 # Inst execution rate -system.cpu.iew.wb_sent 7210 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 7118 # cumulative count of insts written-back -system.cpu.iew.wb_producers 2758 # num instructions producing a value -system.cpu.iew.wb_consumers 3946 # num instructions consuming a value -system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.289986 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.698936 # average fanout of values written-back -system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 5826 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 4197 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 10 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 357 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 11871 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.490776 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.277197 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 9472 79.79% 79.79% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 966 8.14% 87.93% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 656 5.53% 93.45% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 321 2.70% 96.16% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 147 1.24% 97.40% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 102 0.86% 98.26% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 64 0.54% 98.80% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 41 0.35% 99.14% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 102 0.86% 100.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 11871 # Number of insts commited each cycle -system.cpu.commit.count 5826 # Number of instructions committed -system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 2089 # Number of memory references committed -system.cpu.commit.loads 1164 # Number of loads committed -system.cpu.commit.membars 0 # Number of memory barriers committed -system.cpu.commit.branches 916 # Number of branches committed -system.cpu.commit.fp_insts 2 # Number of committed floating point instructions. -system.cpu.commit.int_insts 5124 # Number of committed integer instructions. -system.cpu.commit.function_calls 87 # Number of function calls committed. -system.cpu.commit.bw_lim_events 102 # number cycles where commit BW limit reached -system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 21779 # The number of ROB reads -system.cpu.rob.rob_writes 20794 # The number of ROB writes -system.cpu.timesIdled 251 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 11938 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 5169 # Number of Instructions Simulated -system.cpu.committedInsts_total 5169 # Number of Instructions Simulated -system.cpu.cpi 4.748694 # CPI: Cycles Per Instruction -system.cpu.cpi_total 4.748694 # CPI: Total CPI of All Threads -system.cpu.ipc 0.210584 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.210584 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 10280 # number of integer regfile reads -system.cpu.int_regfile_writes 4987 # number of integer regfile writes -system.cpu.fp_regfile_reads 3 # number of floating regfile reads -system.cpu.fp_regfile_writes 1 # number of floating regfile writes -system.cpu.misc_regfile_reads 153 # number of misc regfile reads -system.cpu.icache.replacements 17 # number of replacements -system.cpu.icache.tagsinuse 161.224498 # Cycle average of tags in use -system.cpu.icache.total_refs 1363 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 336 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 4.056548 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 161.224498 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.078723 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 1363 # number of ReadReq hits -system.cpu.icache.demand_hits 1363 # number of demand (read+write) hits -system.cpu.icache.overall_hits 1363 # number of overall hits -system.cpu.icache.ReadReq_misses 418 # number of ReadReq misses -system.cpu.icache.demand_misses 418 # number of demand (read+write) misses -system.cpu.icache.overall_misses 418 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 15148000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 15148000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 15148000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 1781 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 1781 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 1781 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.234700 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.234700 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.234700 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 36239.234450 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 36239.234450 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 36239.234450 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 82 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 82 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 82 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 336 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 336 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 336 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 11784000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 11784000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 11784000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.188658 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.188658 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.188658 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 35071.428571 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 35071.428571 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 35071.428571 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 92.121984 # Cycle average of tags in use -system.cpu.dcache.total_refs 2380 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 142 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 16.760563 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 92.121984 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.022491 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 1802 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 578 # number of WriteReq hits -system.cpu.dcache.demand_hits 2380 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 2380 # number of overall hits -system.cpu.dcache.ReadReq_misses 133 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 347 # number of WriteReq misses -system.cpu.dcache.demand_misses 480 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 480 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 4767500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 11508000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency 16275500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 16275500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 1935 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses 925 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 2860 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 2860 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.068734 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.375135 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate 0.167832 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.167832 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 35845.864662 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 33164.265130 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency 33907.291667 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 33907.291667 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 42 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 296 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits 338 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 338 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 91 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 51 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 142 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 142 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 3272000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 1836000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 5108000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 5108000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.047028 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate 0.055135 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.049650 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.049650 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 35956.043956 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 36000 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 35971.830986 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 35971.830986 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 221.521956 # Cycle average of tags in use -system.cpu.l2cache.total_refs 3 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 424 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.007075 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 221.521956 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.006760 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 3 # number of ReadReq hits -system.cpu.l2cache.demand_hits 3 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 3 # number of overall hits -system.cpu.l2cache.ReadReq_misses 424 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses 51 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 475 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 475 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 14561000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 1760500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 16321500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 16321500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 427 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 51 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 478 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 478 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.992974 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.993724 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.993724 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 34341.981132 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 34519.607843 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 34361.052632 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 34361.052632 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 424 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 51 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 475 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 475 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 13198000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 1598500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 14796500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 14796500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.992974 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.993724 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.993724 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31127.358491 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31343.137255 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31150.526316 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31150.526316 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate - ----------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/mips/linux/simple-atomic/config.ini b/tests/quick/00.hello/ref/mips/linux/simple-atomic/config.ini deleted file mode 100644 index 8bad8df13..000000000 --- a/tests/quick/00.hello/ref/mips/linux/simple-atomic/config.ini +++ /dev/null @@ -1,102 +0,0 @@ -[root] -type=Root -children=system -time_sync_enable=false -time_sync_period=100000000000 -time_sync_spin_threshold=100000000 - -[system] -type=System -children=cpu membus physmem -mem_mode=atomic -memories=system.physmem -num_work_ids=16 -physmem=system.physmem -work_begin_ckpt_count=0 -work_begin_cpu_id_exit=-1 -work_begin_exit_count=0 -work_cpus_ckpt_count=0 -work_end_ckpt_count=0 -work_end_exit_count=0 -work_item_id=-1 -system_port=system.membus.port[0] - -[system.cpu] -type=AtomicSimpleCPU -children=dtb itb tracer workload -checker=Null -clock=500 -cpu_id=0 -defer_registration=false -do_checkpoint_insts=true -do_statistics_insts=true -dtb=system.cpu.dtb -function_trace=false -function_trace_start=0 -itb=system.cpu.itb -max_insts_all_threads=0 -max_insts_any_thread=0 -max_loads_all_threads=0 -max_loads_any_thread=0 -numThreads=1 -phase=0 -progress_interval=0 -simulate_data_stalls=false -simulate_inst_stalls=false -system=system -tracer=system.cpu.tracer -width=1 -workload=system.cpu.workload -dcache_port=system.membus.port[3] -icache_port=system.membus.port[2] - -[system.cpu.dtb] -type=MipsTLB -size=64 - -[system.cpu.itb] -type=MipsTLB -size=64 - -[system.cpu.tracer] -type=ExeTracer - -[system.cpu.workload] -type=LiveProcess -cmd=hello -cwd= -egid=100 -env= -errout=cerr -euid=100 -executable=/dist/m5/regression/test-progs/hello/bin/mips/linux/hello -gid=100 -input=cin -max_stack_size=67108864 -output=cout -pid=100 -ppid=99 -simpoint=0 -system=system -uid=100 - -[system.membus] -type=Bus -block_size=64 -bus_id=0 -clock=1000 -header_cycles=1 -use_default_range=false -width=64 -port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port - -[system.physmem] -type=PhysicalMemory -file= -latency=30000 -latency_var=0 -null=false -range=0:134217727 -zero=false -port=system.membus.port[1] - diff --git a/tests/quick/00.hello/ref/mips/linux/simple-atomic/simerr b/tests/quick/00.hello/ref/mips/linux/simple-atomic/simerr deleted file mode 100755 index e45cd058f..000000000 --- a/tests/quick/00.hello/ref/mips/linux/simple-atomic/simerr +++ /dev/null @@ -1,2 +0,0 @@ -warn: Sockets disabled, not accepting gdb connections -hack: be nice to actually delete the event here diff --git a/tests/quick/00.hello/ref/mips/linux/simple-atomic/simout b/tests/quick/00.hello/ref/mips/linux/simple-atomic/simout deleted file mode 100755 index 4b9270f18..000000000 --- a/tests/quick/00.hello/ref/mips/linux/simple-atomic/simout +++ /dev/null @@ -1,12 +0,0 @@ -gem5 Simulator System. http://gem5.org -gem5 is copyrighted software; use the --copyright option for details. - -gem5 compiled Jan 23 2012 03:56:13 -gem5 started Jan 23 2012 04:23:47 -gem5 executing on zizzer -command line: build/MIPS_SE/gem5.opt -d build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/simple-atomic -re tests/run.py build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/simple-atomic -Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -info: Increasing stack size by one page. -Hello World! -Exiting @ tick 2913500 because target called exit() diff --git a/tests/quick/00.hello/ref/mips/linux/simple-atomic/stats.txt b/tests/quick/00.hello/ref/mips/linux/simple-atomic/stats.txt deleted file mode 100644 index 397c3f1f6..000000000 --- a/tests/quick/00.hello/ref/mips/linux/simple-atomic/stats.txt +++ /dev/null @@ -1,63 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 0.000003 # Number of seconds simulated -sim_ticks 2913500 # Number of ticks simulated -final_tick 2913500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 231601 # Simulator instruction rate (inst/s) -host_tick_rate 115720913 # Simulator tick rate (ticks/s) -host_mem_usage 199128 # Number of bytes of host memory used -host_seconds 0.03 # Real time elapsed on the host -sim_insts 5827 # Number of instructions simulated -system.physmem.bytes_read 27687 # Number of bytes read from this memory -system.physmem.bytes_inst_read 23312 # Number of instructions bytes read from this memory -system.physmem.bytes_written 3658 # Number of bytes written to this memory -system.physmem.num_reads 6992 # Number of read requests responded to by this memory -system.physmem.num_writes 925 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 9503003261 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 8001372919 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 1255534580 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 10758537841 # Total bandwidth to/from this memory (bytes/s) -system.cpu.dtb.read_hits 0 # DTB read hits -system.cpu.dtb.read_misses 0 # DTB read misses -system.cpu.dtb.read_accesses 0 # DTB read accesses -system.cpu.dtb.write_hits 0 # DTB write hits -system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.dtb.write_accesses 0 # DTB write accesses -system.cpu.dtb.hits 0 # DTB hits -system.cpu.dtb.misses 0 # DTB misses -system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.hits 0 # DTB hits -system.cpu.itb.misses 0 # DTB misses -system.cpu.itb.accesses 0 # DTB accesses -system.cpu.workload.num_syscalls 8 # Number of system calls -system.cpu.numCycles 5828 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.num_insts 5827 # Number of instructions executed -system.cpu.num_int_alu_accesses 5126 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 2 # Number of float alu accesses -system.cpu.num_func_calls 194 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 677 # number of instructions that are conditional controls -system.cpu.num_int_insts 5126 # number of integer instructions -system.cpu.num_fp_insts 2 # number of float instructions -system.cpu.num_int_register_reads 7300 # number of times the integer registers were read -system.cpu.num_int_register_writes 3409 # number of times the integer registers were written -system.cpu.num_fp_register_reads 3 # number of times the floating registers were read -system.cpu.num_fp_register_writes 1 # number of times the floating registers were written -system.cpu.num_mem_refs 2090 # number of memory refs -system.cpu.num_load_insts 1164 # Number of load instructions -system.cpu.num_store_insts 926 # Number of store instructions -system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 5828 # Number of busy cycles -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.idle_fraction 0 # Percentage of idle cycles - ----------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/config.ini b/tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/config.ini deleted file mode 100644 index e5b4b16c8..000000000 --- a/tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/config.ini +++ /dev/null @@ -1,268 +0,0 @@ -[root] -type=Root -children=system -time_sync_enable=false -time_sync_period=100000000 -time_sync_spin_threshold=100000 - -[system] -type=System -children=cpu dir_cntrl0 l1_cntrl0 physmem ruby sys_port_proxy -mem_mode=timing -memories=system.physmem -num_work_ids=16 -physmem=system.physmem -work_begin_ckpt_count=0 -work_begin_cpu_id_exit=-1 -work_begin_exit_count=0 -work_cpus_ckpt_count=0 -work_end_ckpt_count=0 -work_end_exit_count=0 -work_item_id=-1 -system_port=system.sys_port_proxy.port[0] - -[system.cpu] -type=TimingSimpleCPU -children=dtb itb tracer workload -checker=Null -clock=1 -cpu_id=0 -defer_registration=false -do_checkpoint_insts=true -do_statistics_insts=true -dtb=system.cpu.dtb -function_trace=false -function_trace_start=0 -itb=system.cpu.itb -max_insts_all_threads=0 -max_insts_any_thread=0 -max_loads_all_threads=0 -max_loads_any_thread=0 -numThreads=1 -phase=0 -progress_interval=0 -system=system -tracer=system.cpu.tracer -workload=system.cpu.workload -dcache_port=system.l1_cntrl0.sequencer.port[1] -icache_port=system.l1_cntrl0.sequencer.port[0] - -[system.cpu.dtb] -type=MipsTLB -size=64 - -[system.cpu.itb] -type=MipsTLB -size=64 - -[system.cpu.tracer] -type=ExeTracer - -[system.cpu.workload] -type=LiveProcess -cmd=hello -cwd= -egid=100 -env= -errout=cerr -euid=100 -executable=/dist/m5/regression/test-progs/hello/bin/mips/linux/hello -gid=100 -input=cin -max_stack_size=67108864 -output=cout -pid=100 -ppid=99 -simpoint=0 -system=system -uid=100 - -[system.dir_cntrl0] -type=Directory_Controller -children=directory memBuffer -buffer_size=0 -cntrl_id=1 -directory=system.dir_cntrl0.directory -directory_latency=12 -memBuffer=system.dir_cntrl0.memBuffer -number_of_TBEs=256 -recycle_latency=10 -ruby_system=system.ruby -transitions_per_cycle=32 -version=0 - -[system.dir_cntrl0.directory] -type=RubyDirectoryMemory -map_levels=4 -numa_high_bit=6 -size=134217728 -use_map=false -version=0 - -[system.dir_cntrl0.memBuffer] -type=RubyMemoryControl -bank_bit_0=8 -bank_busy_time=11 -bank_queue_size=12 -banks_per_rank=8 -basic_bus_busy_time=2 -dimm_bit_0=12 -dimms_per_channel=2 -mem_bus_cycle_multiplier=10 -mem_ctl_latency=12 -mem_fixed_delay=0 -mem_random_arbitrate=0 -rank_bit_0=11 -rank_rank_delay=1 -ranks_per_dimm=2 -read_write_delay=2 -refresh_period=1560 -tFaw=0 -version=0 - -[system.l1_cntrl0] -type=L1Cache_Controller -children=cacheMemory sequencer -buffer_size=0 -cacheMemory=system.l1_cntrl0.cacheMemory -cache_response_latency=12 -cntrl_id=0 -issue_latency=2 -number_of_TBEs=256 -recycle_latency=10 -ruby_system=system.ruby -sequencer=system.l1_cntrl0.sequencer -transitions_per_cycle=32 -version=0 - -[system.l1_cntrl0.cacheMemory] -type=RubyCache -assoc=2 -is_icache=false -latency=3 -replacement_policy=PSEUDO_LRU -size=256 -start_index_bit=6 - -[system.l1_cntrl0.sequencer] -type=RubySequencer -access_phys_mem=true -dcache=system.l1_cntrl0.cacheMemory -deadlock_threshold=500000 -icache=system.l1_cntrl0.cacheMemory -max_outstanding_requests=16 -physmem=system.physmem -ruby_system=system.ruby -using_network_tester=false -using_ruby_tester=false -version=0 -physMemPort=system.physmem.port[0] -port=system.cpu.icache_port system.cpu.dcache_port - -[system.physmem] -type=PhysicalMemory -file= -latency=30 -latency_var=0 -null=false -range=0:134217727 -zero=false -port=system.l1_cntrl0.sequencer.physMemPort system.sys_port_proxy.physMemPort - -[system.ruby] -type=RubySystem -children=network profiler -block_size_bytes=64 -clock=1 -mem_size=134217728 -no_mem_vec=false -random_seed=1234 -randomization=false -stats_filename=ruby.stats - -[system.ruby.network] -type=SimpleNetwork -children=topology -adaptive_routing=false -buffer_size=0 -control_msg_size=8 -endpoint_bandwidth=1000 -number_of_virtual_networks=10 -ruby_system=system.ruby -topology=system.ruby.network.topology - -[system.ruby.network.topology] -type=Topology -children=ext_links0 ext_links1 int_links0 int_links1 routers0 routers1 routers2 -description=Crossbar -ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1 -int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1 -print_config=false -routers=system.ruby.network.topology.routers0 system.ruby.network.topology.routers1 system.ruby.network.topology.routers2 - -[system.ruby.network.topology.ext_links0] -type=SimpleExtLink -bandwidth_factor=16 -ext_node=system.l1_cntrl0 -int_node=system.ruby.network.topology.routers0 -latency=1 -link_id=0 -weight=1 - -[system.ruby.network.topology.ext_links1] -type=SimpleExtLink -bandwidth_factor=16 -ext_node=system.dir_cntrl0 -int_node=system.ruby.network.topology.routers1 -latency=1 -link_id=1 -weight=1 - -[system.ruby.network.topology.int_links0] -type=SimpleIntLink -bandwidth_factor=16 -latency=1 -link_id=2 -node_a=system.ruby.network.topology.routers0 -node_b=system.ruby.network.topology.routers2 -weight=1 - -[system.ruby.network.topology.int_links1] -type=SimpleIntLink -bandwidth_factor=16 -latency=1 -link_id=3 -node_a=system.ruby.network.topology.routers1 -node_b=system.ruby.network.topology.routers2 -weight=1 - -[system.ruby.network.topology.routers0] -type=BasicRouter -router_id=0 - -[system.ruby.network.topology.routers1] -type=BasicRouter -router_id=1 - -[system.ruby.network.topology.routers2] -type=BasicRouter -router_id=2 - -[system.ruby.profiler] -type=RubyProfiler -all_instructions=false -hot_lines=false -num_of_sequencers=1 -ruby_system=system.ruby - -[system.sys_port_proxy] -type=RubyPortProxy -access_phys_mem=true -physmem=system.physmem -ruby_system=system.ruby -using_network_tester=false -using_ruby_tester=false -version=0 -physMemPort=system.physmem.port[1] -port=system.system_port - diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/simerr b/tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/simerr deleted file mode 100755 index e45cd058f..000000000 --- a/tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/simerr +++ /dev/null @@ -1,2 +0,0 @@ -warn: Sockets disabled, not accepting gdb connections -hack: be nice to actually delete the event here diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/simout b/tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/simout deleted file mode 100755 index f6eaf03f7..000000000 --- a/tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/simout +++ /dev/null @@ -1,12 +0,0 @@ -gem5 Simulator System. http://gem5.org -gem5 is copyrighted software; use the --copyright option for details. - -gem5 compiled Jan 23 2012 03:56:13 -gem5 started Jan 23 2012 04:23:56 -gem5 executing on zizzer -command line: build/MIPS_SE/gem5.opt -d build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/simple-timing-ruby -re tests/run.py build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/simple-timing-ruby -Global frequency set at 1000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -info: Increasing stack size by one page. -Hello World! -Exiting @ tick 292960 because target called exit() diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt b/tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt deleted file mode 100644 index 65d0aed82..000000000 --- a/tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt +++ /dev/null @@ -1,63 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 0.000293 # Number of seconds simulated -sim_ticks 292960 # Number of ticks simulated -final_tick 292960 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 55801 # Simulator instruction rate (inst/s) -host_tick_rate 2804966 # Simulator tick rate (ticks/s) -host_mem_usage 220172 # Number of bytes of host memory used -host_seconds 0.10 # Real time elapsed on the host -sim_insts 5827 # Number of instructions simulated -system.physmem.bytes_read 27687 # Number of bytes read from this memory -system.physmem.bytes_inst_read 23312 # Number of instructions bytes read from this memory -system.physmem.bytes_written 3658 # Number of bytes written to this memory -system.physmem.num_reads 6992 # Number of read requests responded to by this memory -system.physmem.num_writes 925 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 94507783 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 79574003 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 12486346 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 106994129 # Total bandwidth to/from this memory (bytes/s) -system.cpu.dtb.read_hits 0 # DTB read hits -system.cpu.dtb.read_misses 0 # DTB read misses -system.cpu.dtb.read_accesses 0 # DTB read accesses -system.cpu.dtb.write_hits 0 # DTB write hits -system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.dtb.write_accesses 0 # DTB write accesses -system.cpu.dtb.hits 0 # DTB hits -system.cpu.dtb.misses 0 # DTB misses -system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.hits 0 # DTB hits -system.cpu.itb.misses 0 # DTB misses -system.cpu.itb.accesses 0 # DTB accesses -system.cpu.workload.num_syscalls 8 # Number of system calls -system.cpu.numCycles 292960 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.num_insts 5827 # Number of instructions executed -system.cpu.num_int_alu_accesses 5126 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 2 # Number of float alu accesses -system.cpu.num_func_calls 194 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 677 # number of instructions that are conditional controls -system.cpu.num_int_insts 5126 # number of integer instructions -system.cpu.num_fp_insts 2 # number of float instructions -system.cpu.num_int_register_reads 7300 # number of times the integer registers were read -system.cpu.num_int_register_writes 3409 # number of times the integer registers were written -system.cpu.num_fp_register_reads 3 # number of times the floating registers were read -system.cpu.num_fp_register_writes 1 # number of times the floating registers were written -system.cpu.num_mem_refs 2090 # number of memory refs -system.cpu.num_load_insts 1164 # Number of load instructions -system.cpu.num_store_insts 926 # Number of store instructions -system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 292960 # Number of busy cycles -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.idle_fraction 0 # Percentage of idle cycles - ----------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini b/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini deleted file mode 100644 index 36444e22d..000000000 --- a/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini +++ /dev/null @@ -1,205 +0,0 @@ -[root] -type=Root -children=system -time_sync_enable=false -time_sync_period=100000000000 -time_sync_spin_threshold=100000000 - -[system] -type=System -children=cpu membus physmem -mem_mode=atomic -memories=system.physmem -num_work_ids=16 -physmem=system.physmem -work_begin_ckpt_count=0 -work_begin_cpu_id_exit=-1 -work_begin_exit_count=0 -work_cpus_ckpt_count=0 -work_end_ckpt_count=0 -work_end_exit_count=0 -work_item_id=-1 -system_port=system.membus.port[0] - -[system.cpu] -type=TimingSimpleCPU -children=dcache dtb icache itb l2cache toL2Bus tracer workload -checker=Null -clock=500 -cpu_id=0 -defer_registration=false -do_checkpoint_insts=true -do_statistics_insts=true -dtb=system.cpu.dtb -function_trace=false -function_trace_start=0 -itb=system.cpu.itb -max_insts_all_threads=0 -max_insts_any_thread=0 -max_loads_all_threads=0 -max_loads_any_thread=0 -numThreads=1 -phase=0 -progress_interval=0 -system=system -tracer=system.cpu.tracer -workload=system.cpu.workload -dcache_port=system.cpu.dcache.cpu_side -icache_port=system.cpu.icache.cpu_side - -[system.cpu.dcache] -type=BaseCache -addr_range=0:18446744073709551615 -assoc=2 -block_size=64 -forward_snoops=true -hash_delay=1 -is_top_level=true -latency=1000 -max_miss_count=0 -mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 -prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 -prioritizeRequests=false -repl=Null -size=262144 -subblock_size=0 -tgts_per_mshr=5 -trace_addr=0 -two_queue=false -write_buffers=8 -cpu_side=system.cpu.dcache_port -mem_side=system.cpu.toL2Bus.port[1] - -[system.cpu.dtb] -type=MipsTLB -size=64 - -[system.cpu.icache] -type=BaseCache -addr_range=0:18446744073709551615 -assoc=2 -block_size=64 -forward_snoops=true -hash_delay=1 -is_top_level=true -latency=1000 -max_miss_count=0 -mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 -prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 -prioritizeRequests=false -repl=Null -size=131072 -subblock_size=0 -tgts_per_mshr=5 -trace_addr=0 -two_queue=false -write_buffers=8 -cpu_side=system.cpu.icache_port -mem_side=system.cpu.toL2Bus.port[0] - -[system.cpu.itb] -type=MipsTLB -size=64 - -[system.cpu.l2cache] -type=BaseCache -addr_range=0:18446744073709551615 -assoc=2 -block_size=64 -forward_snoops=true -hash_delay=1 -is_top_level=false -latency=10000 -max_miss_count=0 -mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=100000 -prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 -prioritizeRequests=false -repl=Null -size=2097152 -subblock_size=0 -tgts_per_mshr=5 -trace_addr=0 -two_queue=false -write_buffers=8 -cpu_side=system.cpu.toL2Bus.port[2] -mem_side=system.membus.port[2] - -[system.cpu.toL2Bus] -type=Bus -block_size=64 -bus_id=0 -clock=1000 -header_cycles=1 -use_default_range=false -width=64 -port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side - -[system.cpu.tracer] -type=ExeTracer - -[system.cpu.workload] -type=LiveProcess -cmd=hello -cwd= -egid=100 -env= -errout=cerr -euid=100 -executable=/dist/m5/regression/test-progs/hello/bin/mips/linux/hello -gid=100 -input=cin -max_stack_size=67108864 -output=cout -pid=100 -ppid=99 -simpoint=0 -system=system -uid=100 - -[system.membus] -type=Bus -block_size=64 -bus_id=0 -clock=1000 -header_cycles=1 -use_default_range=false -width=64 -port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side - -[system.physmem] -type=PhysicalMemory -file= -latency=30000 -latency_var=0 -null=false -range=0:134217727 -zero=false -port=system.membus.port[1] - diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing/simerr b/tests/quick/00.hello/ref/mips/linux/simple-timing/simerr deleted file mode 100755 index e45cd058f..000000000 --- a/tests/quick/00.hello/ref/mips/linux/simple-timing/simerr +++ /dev/null @@ -1,2 +0,0 @@ -warn: Sockets disabled, not accepting gdb connections -hack: be nice to actually delete the event here diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing/simout b/tests/quick/00.hello/ref/mips/linux/simple-timing/simout deleted file mode 100755 index 7525d1ad5..000000000 --- a/tests/quick/00.hello/ref/mips/linux/simple-timing/simout +++ /dev/null @@ -1,12 +0,0 @@ -gem5 Simulator System. http://gem5.org -gem5 is copyrighted software; use the --copyright option for details. - -gem5 compiled Jan 23 2012 03:56:13 -gem5 started Jan 23 2012 04:23:52 -gem5 executing on zizzer -command line: build/MIPS_SE/gem5.opt -d build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/simple-timing -re tests/run.py build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/simple-timing -Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -info: Increasing stack size by one page. -Hello World! -Exiting @ tick 32088000 because target called exit() diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing/stats.txt b/tests/quick/00.hello/ref/mips/linux/simple-timing/stats.txt deleted file mode 100644 index 566ce19a4..000000000 --- a/tests/quick/00.hello/ref/mips/linux/simple-timing/stats.txt +++ /dev/null @@ -1,246 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 0.000032 # Number of seconds simulated -sim_ticks 32088000 # Number of ticks simulated -final_tick 32088000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 263412 # Simulator instruction rate (inst/s) -host_tick_rate 1449372115 # Simulator tick rate (ticks/s) -host_mem_usage 207940 # Number of bytes of host memory used -host_seconds 0.02 # Real time elapsed on the host -sim_insts 5827 # Number of instructions simulated -system.physmem.bytes_read 28096 # Number of bytes read from this memory -system.physmem.bytes_inst_read 19264 # Number of instructions bytes read from this memory -system.physmem.bytes_written 0 # Number of bytes written to this memory -system.physmem.num_reads 439 # Number of read requests responded to by this memory -system.physmem.num_writes 0 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 875592122 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 600349040 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total 875592122 # Total bandwidth to/from this memory (bytes/s) -system.cpu.dtb.read_hits 0 # DTB read hits -system.cpu.dtb.read_misses 0 # DTB read misses -system.cpu.dtb.read_accesses 0 # DTB read accesses -system.cpu.dtb.write_hits 0 # DTB write hits -system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.dtb.write_accesses 0 # DTB write accesses -system.cpu.dtb.hits 0 # DTB hits -system.cpu.dtb.misses 0 # DTB misses -system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.hits 0 # DTB hits -system.cpu.itb.misses 0 # DTB misses -system.cpu.itb.accesses 0 # DTB accesses -system.cpu.workload.num_syscalls 8 # Number of system calls -system.cpu.numCycles 64176 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.num_insts 5827 # Number of instructions executed -system.cpu.num_int_alu_accesses 5126 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 2 # Number of float alu accesses -system.cpu.num_func_calls 194 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 677 # number of instructions that are conditional controls -system.cpu.num_int_insts 5126 # number of integer instructions -system.cpu.num_fp_insts 2 # number of float instructions -system.cpu.num_int_register_reads 7300 # number of times the integer registers were read -system.cpu.num_int_register_writes 3409 # number of times the integer registers were written -system.cpu.num_fp_register_reads 3 # number of times the floating registers were read -system.cpu.num_fp_register_writes 1 # number of times the floating registers were written -system.cpu.num_mem_refs 2090 # number of memory refs -system.cpu.num_load_insts 1164 # Number of load instructions -system.cpu.num_store_insts 926 # Number of store instructions -system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 64176 # Number of busy cycles -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.icache.replacements 13 # number of replacements -system.cpu.icache.tagsinuse 132.493866 # Cycle average of tags in use -system.cpu.icache.total_refs 5526 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 303 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 18.237624 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 132.493866 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.064694 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 5526 # number of ReadReq hits -system.cpu.icache.demand_hits 5526 # number of demand (read+write) hits -system.cpu.icache.overall_hits 5526 # number of overall hits -system.cpu.icache.ReadReq_misses 303 # number of ReadReq misses -system.cpu.icache.demand_misses 303 # number of demand (read+write) misses -system.cpu.icache.overall_misses 303 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 16884000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 16884000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 16884000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 5829 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 5829 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 5829 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.051981 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.051981 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.051981 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 55722.772277 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 55722.772277 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 55722.772277 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 303 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 303 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 303 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 15975000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 15975000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 15975000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.051981 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.051981 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.051981 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 52722.772277 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 52722.772277 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 52722.772277 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 87.458397 # Cycle average of tags in use -system.cpu.dcache.total_refs 1951 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 138 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 14.137681 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 87.458397 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.021352 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 1077 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 874 # number of WriteReq hits -system.cpu.dcache.demand_hits 1951 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 1951 # number of overall hits -system.cpu.dcache.ReadReq_misses 87 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 51 # number of WriteReq misses -system.cpu.dcache.demand_misses 138 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 138 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 4872000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 2856000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency 7728000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 7728000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 1164 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses 925 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 2089 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 2089 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.074742 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.055135 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate 0.066060 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.066060 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency 56000 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 56000 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 87 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 51 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 138 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 138 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 4611000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 2703000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 7314000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 7314000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.074742 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate 0.055135 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.066060 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.066060 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 188.045319 # Cycle average of tags in use -system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 388 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.005155 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 188.045319 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.005739 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits -system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 2 # number of overall hits -system.cpu.l2cache.ReadReq_misses 388 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses 51 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 439 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 439 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 20176000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 2652000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 22828000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 22828000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 390 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 51 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 441 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 441 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.994872 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.995465 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.995465 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 388 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 51 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 439 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 439 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 15520000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 2040000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 17560000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 17560000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.994872 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.995465 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.995465 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate - ----------- End Simulation Statistics ---------- |