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-rw-r--r--tests/quick/00.hello/ref/mips/linux/inorder-timing/config.ini13
-rwxr-xr-xtests/quick/00.hello/ref/mips/linux/inorder-timing/simout8
-rw-r--r--tests/quick/00.hello/ref/mips/linux/inorder-timing/stats.txt10
-rw-r--r--tests/quick/00.hello/ref/mips/linux/o3-timing/config.ini13
-rwxr-xr-xtests/quick/00.hello/ref/mips/linux/o3-timing/simout8
-rw-r--r--tests/quick/00.hello/ref/mips/linux/o3-timing/stats.txt30
-rw-r--r--tests/quick/00.hello/ref/mips/linux/simple-atomic/config.ini11
-rwxr-xr-xtests/quick/00.hello/ref/mips/linux/simple-atomic/simout8
-rw-r--r--tests/quick/00.hello/ref/mips/linux/simple-atomic/stats.txt24
-rw-r--r--tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/config.ini189
-rwxr-xr-xtests/quick/00.hello/ref/mips/linux/simple-timing-ruby/simout8
-rw-r--r--tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt26
-rw-r--r--tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini13
-rwxr-xr-xtests/quick/00.hello/ref/mips/linux/simple-timing/simout12
-rw-r--r--tests/quick/00.hello/ref/mips/linux/simple-timing/stats.txt26
15 files changed, 145 insertions, 254 deletions
diff --git a/tests/quick/00.hello/ref/mips/linux/inorder-timing/config.ini b/tests/quick/00.hello/ref/mips/linux/inorder-timing/config.ini
index 6b7ff5873..d479ef8bf 100644
--- a/tests/quick/00.hello/ref/mips/linux/inorder-timing/config.ini
+++ b/tests/quick/00.hello/ref/mips/linux/inorder-timing/config.ini
@@ -1,22 +1,13 @@
[root]
type=Root
children=system
-time_sync_enable=false
-time_sync_period=100000000000
-time_sync_spin_threshold=100000000
+dummy=0
[system]
type=System
children=cpu membus physmem
mem_mode=atomic
physmem=system.physmem
-work_begin_ckpt_count=0
-work_begin_cpu_id_exit=-1
-work_begin_exit_count=0
-work_cpus_ckpt_count=0
-work_end_ckpt_count=0
-work_end_exit_count=0
-work_item_id=-1
[system.cpu]
type=InOrderCPU
@@ -255,7 +246,7 @@ egid=100
env=
errout=cerr
euid=100
-executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/mips/linux/hello
+executable=tests/test-progs/hello/bin/mips/linux/hello
gid=100
input=cin
max_stack_size=67108864
diff --git a/tests/quick/00.hello/ref/mips/linux/inorder-timing/simout b/tests/quick/00.hello/ref/mips/linux/inorder-timing/simout
index c56b70ea3..dc388ddae 100755
--- a/tests/quick/00.hello/ref/mips/linux/inorder-timing/simout
+++ b/tests/quick/00.hello/ref/mips/linux/inorder-timing/simout
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
All Rights Reserved
-M5 compiled Feb 6 2011 15:20:27
-M5 revision b885adc82ab4+ 7924+ default tip qtip brad/regress_updates
-M5 started Feb 6 2011 20:46:02
-M5 executing on SC2B0617
+M5 compiled Jan 24 2011 18:37:16
+M5 revision 09e8ac96522d+ 7823+ default regression_updates qtip tip
+M5 started Jan 24 2011 18:37:18
+M5 executing on zooks
command line: build/MIPS_SE/m5.fast -d build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/inorder-timing -re tests/run.py build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/inorder-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
diff --git a/tests/quick/00.hello/ref/mips/linux/inorder-timing/stats.txt b/tests/quick/00.hello/ref/mips/linux/inorder-timing/stats.txt
index ab040cd9f..170c01854 100644
--- a/tests/quick/00.hello/ref/mips/linux/inorder-timing/stats.txt
+++ b/tests/quick/00.hello/ref/mips/linux/inorder-timing/stats.txt
@@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 42279 # Simulator instruction rate (inst/s)
-host_mem_usage 206292 # Number of bytes of host memory used
-host_seconds 0.14 # Real time elapsed on the host
-host_tick_rate 155948553 # Simulator tick rate (ticks/s)
+host_inst_rate 32637 # Simulator instruction rate (inst/s)
+host_mem_usage 156860 # Number of bytes of host memory used
+host_seconds 0.18 # Real time elapsed on the host
+host_tick_rate 120410651 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 5827 # Number of instructions simulated
sim_seconds 0.000022 # Number of seconds simulated
@@ -253,8 +253,6 @@ system.cpu.l2cache.total_refs 2 # To
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 0 # number of writebacks
system.cpu.numCycles 43069 # number of cpu cycles simulated
-system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.runCycles 6002 # Number of cycles cpu stages are processed.
system.cpu.smtCommittedInsts 0 # Number of SMT Instructions Simulated (Per-Thread)
system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
diff --git a/tests/quick/00.hello/ref/mips/linux/o3-timing/config.ini b/tests/quick/00.hello/ref/mips/linux/o3-timing/config.ini
index 74ab46a47..a9c72ed3e 100644
--- a/tests/quick/00.hello/ref/mips/linux/o3-timing/config.ini
+++ b/tests/quick/00.hello/ref/mips/linux/o3-timing/config.ini
@@ -1,22 +1,13 @@
[root]
type=Root
children=system
-time_sync_enable=false
-time_sync_period=100000000000
-time_sync_spin_threshold=100000000
+dummy=0
[system]
type=System
children=cpu membus physmem
mem_mode=atomic
physmem=system.physmem
-work_begin_ckpt_count=0
-work_begin_cpu_id_exit=-1
-work_begin_exit_count=0
-work_cpus_ckpt_count=0
-work_end_ckpt_count=0
-work_end_exit_count=0
-work_item_id=-1
[system.cpu]
type=DerivO3CPU
@@ -547,7 +538,7 @@ egid=100
env=
errout=cerr
euid=100
-executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/mips/linux/hello
+executable=/dist/m5/regression/test-progs/hello/bin/mips/linux/hello
gid=100
input=cin
max_stack_size=67108864
diff --git a/tests/quick/00.hello/ref/mips/linux/o3-timing/simout b/tests/quick/00.hello/ref/mips/linux/o3-timing/simout
index c91e0bbc6..6b2281542 100755
--- a/tests/quick/00.hello/ref/mips/linux/o3-timing/simout
+++ b/tests/quick/00.hello/ref/mips/linux/o3-timing/simout
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
All Rights Reserved
-M5 compiled Feb 6 2011 15:20:27
-M5 revision b885adc82ab4+ 7924+ default tip qtip brad/regress_updates
-M5 started Feb 6 2011 20:46:02
-M5 executing on SC2B0617
+M5 compiled Jan 17 2011 21:17:36
+M5 revision f72d94f8c275 7839 default qtip tip outgoing.patch qbase
+M5 started Jan 17 2011 21:17:39
+M5 executing on zizzer
command line: build/MIPS_SE/m5.fast -d build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/o3-timing -re tests/run.py build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
diff --git a/tests/quick/00.hello/ref/mips/linux/o3-timing/stats.txt b/tests/quick/00.hello/ref/mips/linux/o3-timing/stats.txt
index 22735f5ae..a5f35787b 100644
--- a/tests/quick/00.hello/ref/mips/linux/o3-timing/stats.txt
+++ b/tests/quick/00.hello/ref/mips/linux/o3-timing/stats.txt
@@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 88897 # Simulator instruction rate (inst/s)
-host_mem_usage 206716 # Number of bytes of host memory used
-host_seconds 0.06 # Real time elapsed on the host
-host_tick_rate 218871445 # Simulator tick rate (ticks/s)
+host_inst_rate 35741 # Simulator instruction rate (inst/s)
+host_mem_usage 204488 # Number of bytes of host memory used
+host_seconds 0.14 # Real time elapsed on the host
+host_tick_rate 88262097 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 5169 # Number of instructions simulated
sim_seconds 0.000013 # Number of seconds simulated
@@ -37,9 +37,6 @@ system.cpu.commit.COM:committed_per_cycle::min_value 0
system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::total 12273 # Number of insts commited each cycle
system.cpu.commit.COM:count 5826 # Number of instructions committed
-system.cpu.commit.COM:fp_insts 2 # Number of committed floating point instructions.
-system.cpu.commit.COM:function_calls 87 # Number of function calls committed.
-system.cpu.commit.COM:int_insts 5124 # Number of committed integer instructions.
system.cpu.commit.COM:loads 1164 # Number of loads committed
system.cpu.commit.COM:membars 0 # Number of memory barriers committed
system.cpu.commit.COM:refs 2089 # Number of memory references committed
@@ -165,8 +162,6 @@ system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Nu
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 12922 # Number of instructions fetched each cycle (Total)
-system.cpu.fp_regfile_reads 3 # number of floating regfile reads
-system.cpu.fp_regfile_writes 1 # number of floating regfile writes
system.cpu.icache.ReadReq_accesses 1555 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 36274.074074 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 35024.316109 # average ReadReq mshr miss latency
@@ -266,8 +261,6 @@ system.cpu.iew.lsq.thread.0.squashedStores 210 #
system.cpu.iew.memOrderViolationEvents 16 # Number of memory order violations
system.cpu.iew.predictedNotTakenIncorrect 259 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.predictedTakenIncorrect 118 # Number of branches that were predicted taken incorrectly
-system.cpu.int_regfile_reads 9780 # number of integer regfile reads
-system.cpu.int_regfile_writes 4751 # number of integer regfile writes
system.cpu.ipc 0.202151 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.202151 # IPC: Total IPC of All Threads
system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
@@ -359,14 +352,6 @@ system.cpu.iq.ISSUE:issued_per_cycle::min_value 0
system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::total 12922 # Number of insts issued each cycle
system.cpu.iq.ISSUE:rate 0.288346 # Inst issue rate
-system.cpu.iq.fp_alu_accesses 2 # Number of floating point alu accesses
-system.cpu.iq.fp_inst_queue_reads 4 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_wakeup_accesses 2 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_writes 2 # Number of floating instruction queue writes
-system.cpu.iq.int_alu_accesses 7513 # Number of integer alu accesses
-system.cpu.iq.int_inst_queue_reads 27837 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_wakeup_accesses 6791 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.int_inst_queue_writes 10538 # Number of integer instruction queue writes
system.cpu.iq.iqInstsAdded 8058 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqInstsIssued 7373 # Number of instructions issued
system.cpu.iq.iqNonSpecInstsAdded 11 # Number of non-speculative instructions added to the IQ
@@ -451,10 +436,7 @@ system.cpu.memDep0.conflictingLoads 5 # Nu
system.cpu.memDep0.conflictingStores 1 # Number of conflicting stores.
system.cpu.memDep0.insertedLoads 2139 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 1135 # Number of stores inserted to the mem dependence unit.
-system.cpu.misc_regfile_reads 136 # number of misc regfile reads
system.cpu.numCycles 25570 # number of cpu cycles simulated
-system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.rename.RENAME:BlockCycles 238 # Number of cycles rename is blocking
system.cpu.rename.RENAME:CommittedMaps 3410 # Number of HB maps that are committed
system.cpu.rename.RENAME:IdleCycles 8931 # Number of cycles rename is idle
@@ -466,14 +448,10 @@ system.cpu.rename.RENAME:RunCycles 2609 # Nu
system.cpu.rename.RENAME:SquashCycles 649 # Number of cycles rename is squashing
system.cpu.rename.RENAME:UnblockCycles 81 # Number of cycles rename is unblocking
system.cpu.rename.RENAME:UndoneMaps 2709 # Number of HB maps that are undone due to squashing
-system.cpu.rename.RENAME:fp_rename_lookups 5 # Number of floating rename lookups
-system.cpu.rename.RENAME:int_rename_lookups 12083 # Number of integer rename lookups
system.cpu.rename.RENAME:serializeStallCycles 414 # count of cycles rename stalled for serializing inst
system.cpu.rename.RENAME:serializingInsts 16 # count of serializing insts renamed
system.cpu.rename.RENAME:skidInsts 196 # count of insts added to the skid buffer
system.cpu.rename.RENAME:tempSerializingInsts 11 # count of temporary serializing insts renamed
-system.cpu.rob.rob_reads 21491 # The number of ROB reads
-system.cpu.rob.rob_writes 19268 # The number of ROB writes
system.cpu.timesIdled 259 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.workload.PROG:num_syscalls 8 # Number of system calls
diff --git a/tests/quick/00.hello/ref/mips/linux/simple-atomic/config.ini b/tests/quick/00.hello/ref/mips/linux/simple-atomic/config.ini
index 23ffe531a..6242699da 100644
--- a/tests/quick/00.hello/ref/mips/linux/simple-atomic/config.ini
+++ b/tests/quick/00.hello/ref/mips/linux/simple-atomic/config.ini
@@ -1,22 +1,13 @@
[root]
type=Root
children=system
-time_sync_enable=false
-time_sync_period=100000000000
-time_sync_spin_threshold=100000000
+dummy=0
[system]
type=System
children=cpu membus physmem
mem_mode=atomic
physmem=system.physmem
-work_begin_ckpt_count=0
-work_begin_cpu_id_exit=-1
-work_begin_exit_count=0
-work_cpus_ckpt_count=0
-work_end_ckpt_count=0
-work_end_exit_count=0
-work_item_id=-1
[system.cpu]
type=AtomicSimpleCPU
diff --git a/tests/quick/00.hello/ref/mips/linux/simple-atomic/simout b/tests/quick/00.hello/ref/mips/linux/simple-atomic/simout
index e35105442..5dbd10419 100755
--- a/tests/quick/00.hello/ref/mips/linux/simple-atomic/simout
+++ b/tests/quick/00.hello/ref/mips/linux/simple-atomic/simout
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
All Rights Reserved
-M5 compiled Feb 6 2011 15:20:27
-M5 revision b885adc82ab4+ 7924+ default tip qtip brad/regress_updates
-M5 started Feb 6 2011 20:46:02
-M5 executing on SC2B0617
+M5 compiled Feb 24 2010 23:13:04
+M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip
+M5 started Feb 25 2010 03:11:22
+M5 executing on SC2B0619
command line: build/MIPS_SE/m5.fast -d build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-atomic -re tests/run.py build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
diff --git a/tests/quick/00.hello/ref/mips/linux/simple-atomic/stats.txt b/tests/quick/00.hello/ref/mips/linux/simple-atomic/stats.txt
index 5f3d27685..a6694501e 100644
--- a/tests/quick/00.hello/ref/mips/linux/simple-atomic/stats.txt
+++ b/tests/quick/00.hello/ref/mips/linux/simple-atomic/stats.txt
@@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 930385 # Simulator instruction rate (inst/s)
-host_mem_usage 197752 # Number of bytes of host memory used
+host_inst_rate 1101929 # Simulator instruction rate (inst/s)
+host_mem_usage 183300 # Number of bytes of host memory used
host_seconds 0.01 # Real time elapsed on the host
-host_tick_rate 445693743 # Simulator tick rate (ticks/s)
+host_tick_rate 525428314 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 5827 # Number of instructions simulated
sim_seconds 0.000003 # Number of seconds simulated
@@ -29,24 +29,8 @@ system.cpu.itb.write_hits 0 # DT
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.numCycles 5828 # number of cpu cycles simulated
-system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu.num_busy_cycles 5828 # Number of busy cycles
-system.cpu.num_conditional_control_insts 677 # number of instructions that are conditional controls
-system.cpu.num_fp_alu_accesses 2 # Number of float alu accesses
-system.cpu.num_fp_insts 2 # number of float instructions
-system.cpu.num_fp_register_reads 3 # number of times the floating registers were read
-system.cpu.num_fp_register_writes 1 # number of times the floating registers were written
-system.cpu.num_func_calls 194 # number of times a function call or return occured
-system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_insts 5827 # Number of instructions executed
-system.cpu.num_int_alu_accesses 5126 # Number of integer alu accesses
-system.cpu.num_int_insts 5126 # number of integer instructions
-system.cpu.num_int_register_reads 7301 # number of times the integer registers were read
-system.cpu.num_int_register_writes 3409 # number of times the integer registers were written
-system.cpu.num_load_insts 1164 # Number of load instructions
-system.cpu.num_mem_refs 2090 # number of memory refs
-system.cpu.num_store_insts 926 # Number of store instructions
+system.cpu.num_refs 2090 # Number of memory references
system.cpu.workload.PROG:num_syscalls 8 # Number of system calls
---------- End Simulation Statistics ----------
diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/config.ini b/tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/config.ini
index 7f769242f..b37edc581 100644
--- a/tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/config.ini
+++ b/tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/config.ini
@@ -1,22 +1,13 @@
[root]
type=Root
children=system
-time_sync_enable=false
-time_sync_period=100000000
-time_sync_spin_threshold=100000
+dummy=0
[system]
type=System
-children=cpu dir_cntrl0 l1_cntrl0 physmem ruby
-mem_mode=timing
+children=cpu physmem ruby
+mem_mode=atomic
physmem=system.physmem
-work_begin_ckpt_count=0
-work_begin_cpu_id_exit=-1
-work_begin_exit_count=0
-work_cpus_ckpt_count=0
-work_end_ckpt_count=0
-work_end_exit_count=0
-work_item_id=-1
[system.cpu]
type=TimingSimpleCPU
@@ -95,8 +86,8 @@ progress_interval=0
system=system
tracer=system.cpu.tracer
workload=system.cpu.workload
-dcache_port=system.ruby.cpu_ruby_ports.port[1]
-icache_port=system.ruby.cpu_ruby_ports.port[0]
+dcache_port=system.ruby.network.topology.ext_links0.ext_node.sequencer.port[1]
+icache_port=system.ruby.network.topology.ext_links0.ext_node.sequencer.port[0]
[system.cpu.dtb]
type=MipsTLB
@@ -117,7 +108,7 @@ egid=100
env=
errout=cerr
euid=100
-executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/mips/linux/hello
+executable=tests/test-progs/hello/bin/mips/linux/hello
gid=100
input=cin
max_stack_size=67108864
@@ -128,59 +119,6 @@ simpoint=0
system=system
uid=100
-[system.dir_cntrl0]
-type=Directory_Controller
-children=directory memBuffer
-buffer_size=0
-directory=system.dir_cntrl0.directory
-directory_latency=12
-memBuffer=system.dir_cntrl0.memBuffer
-number_of_TBEs=256
-recycle_latency=10
-transitions_per_cycle=32
-version=0
-
-[system.dir_cntrl0.directory]
-type=RubyDirectoryMemory
-map_levels=4
-numa_high_bit=6
-size=134217728
-use_map=false
-version=0
-
-[system.dir_cntrl0.memBuffer]
-type=RubyMemoryControl
-bank_bit_0=8
-bank_busy_time=11
-bank_queue_size=12
-banks_per_rank=8
-basic_bus_busy_time=2
-dimm_bit_0=12
-dimms_per_channel=2
-mem_bus_cycle_multiplier=10
-mem_ctl_latency=12
-mem_fixed_delay=0
-mem_random_arbitrate=0
-rank_bit_0=11
-rank_rank_delay=1
-ranks_per_dimm=2
-read_write_delay=2
-refresh_period=1560
-tFaw=0
-version=0
-
-[system.l1_cntrl0]
-type=L1Cache_Controller
-buffer_size=0
-cacheMemory=system.ruby.cpu_ruby_ports.dcache
-cache_response_latency=12
-issue_latency=2
-number_of_TBEs=256
-recycle_latency=10
-sequencer=system.ruby.cpu_ruby_ports
-transitions_per_cycle=32
-version=0
-
[system.physmem]
type=PhysicalMemory
file=
@@ -189,48 +127,35 @@ latency_var=0
null=false
range=0:134217727
zero=false
-port=system.ruby.cpu_ruby_ports.physMemPort
+port=system.ruby.network.topology.ext_links0.ext_node.sequencer.physMemPort
[system.ruby]
type=RubySystem
-children=cpu_ruby_ports network profiler tracer
+children=debug network profiler tracer
block_size_bytes=64
clock=1
+debug=system.ruby.debug
mem_size=134217728
network=system.ruby.network
-no_mem_vec=false
profiler=system.ruby.profiler
random_seed=1234
randomization=false
stats_filename=ruby.stats
+tech_nm=45
tracer=system.ruby.tracer
-[system.ruby.cpu_ruby_ports]
-type=RubySequencer
-children=dcache
-access_phys_mem=true
-dcache=system.ruby.cpu_ruby_ports.dcache
-deadlock_threshold=500000
-icache=system.ruby.cpu_ruby_ports.dcache
-max_outstanding_requests=16
-physmem=system.physmem
-using_ruby_tester=false
-version=0
-physMemPort=system.physmem.port[0]
-port=system.cpu.icache_port system.cpu.dcache_port
-
-[system.ruby.cpu_ruby_ports.dcache]
-type=RubyCache
-assoc=2
-latency=3
-replacement_policy=PSEUDO_LRU
-size=256
-start_index_bit=6
+[system.ruby.debug]
+type=RubyDebug
+filter_string=none
+output_filename=none
+protocol_trace=false
+start_time=1
+verbosity_string=none
[system.ruby.network]
type=SimpleNetwork
children=topology
-adaptive_routing=false
+adaptive_routing=true
buffer_size=0
control_msg_size=8
endpoint_bandwidth=10000
@@ -241,7 +166,6 @@ topology=system.ruby.network.topology
[system.ruby.network.topology]
type=Topology
children=ext_links0 ext_links1 int_links0 int_links1
-description=Crossbar
ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1
int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1
num_int_nodes=3
@@ -249,20 +173,93 @@ print_config=false
[system.ruby.network.topology.ext_links0]
type=ExtLink
+children=ext_node
bw_multiplier=64
-ext_node=system.l1_cntrl0
+ext_node=system.ruby.network.topology.ext_links0.ext_node
int_node=0
latency=1
weight=1
+[system.ruby.network.topology.ext_links0.ext_node]
+type=L1Cache_Controller
+children=sequencer
+buffer_size=0
+cacheMemory=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
+cache_response_latency=12
+issue_latency=2
+number_of_TBEs=256
+recycle_latency=10
+sequencer=system.ruby.network.topology.ext_links0.ext_node.sequencer
+transitions_per_cycle=32
+version=0
+
+[system.ruby.network.topology.ext_links0.ext_node.sequencer]
+type=RubySequencer
+children=icache
+dcache=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
+deadlock_threshold=500000
+icache=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
+max_outstanding_requests=16
+physmem=system.physmem
+using_ruby_tester=false
+version=0
+physMemPort=system.physmem.port[0]
+port=system.cpu.icache_port system.cpu.dcache_port
+
+[system.ruby.network.topology.ext_links0.ext_node.sequencer.icache]
+type=RubyCache
+assoc=2
+latency=3
+replacement_policy=PSEUDO_LRU
+size=256
+
[system.ruby.network.topology.ext_links1]
type=ExtLink
+children=ext_node
bw_multiplier=64
-ext_node=system.dir_cntrl0
+ext_node=system.ruby.network.topology.ext_links1.ext_node
int_node=1
latency=1
weight=1
+[system.ruby.network.topology.ext_links1.ext_node]
+type=Directory_Controller
+children=directory memBuffer
+buffer_size=0
+directory=system.ruby.network.topology.ext_links1.ext_node.directory
+directory_latency=12
+memBuffer=system.ruby.network.topology.ext_links1.ext_node.memBuffer
+number_of_TBEs=256
+recycle_latency=10
+transitions_per_cycle=32
+version=0
+
+[system.ruby.network.topology.ext_links1.ext_node.directory]
+type=RubyDirectoryMemory
+size=134217728
+version=0
+
+[system.ruby.network.topology.ext_links1.ext_node.memBuffer]
+type=RubyMemoryControl
+bank_bit_0=8
+bank_busy_time=11
+bank_queue_size=12
+banks_per_rank=8
+basic_bus_busy_time=2
+dimm_bit_0=12
+dimms_per_channel=2
+mem_bus_cycle_multiplier=10
+mem_ctl_latency=12
+mem_fixed_delay=0
+mem_random_arbitrate=0
+rank_bit_0=11
+rank_rank_delay=1
+ranks_per_dimm=2
+read_write_delay=2
+refresh_period=1560
+tFaw=0
+version=0
+
[system.ruby.network.topology.int_links0]
type=IntLink
bw_multiplier=16
diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/simout b/tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/simout
index 1196b3dac..87d5c1036 100755
--- a/tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/simout
+++ b/tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/simout
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
All Rights Reserved
-M5 compiled Feb 6 2011 15:20:27
-M5 revision b885adc82ab4+ 7924+ default tip qtip brad/regress_updates
-M5 started Feb 6 2011 20:46:13
-M5 executing on SC2B0617
+M5 compiled Jan 21 2010 11:12:15
+M5 revision a2fac757fb31+ 6860+ default qtip brad/rubycfg_orion_update tip
+M5 started Jan 21 2010 11:12:51
+M5 executing on svvint07
command line: build/MIPS_SE/m5.fast -d build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-timing-ruby -re tests/run.py build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-timing-ruby
Global frequency set at 1000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt b/tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt
index 5e4d0048f..c0deed77b 100644
--- a/tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt
+++ b/tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt
@@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 54057 # Simulator instruction rate (inst/s)
-host_mem_usage 215848 # Number of bytes of host memory used
-host_seconds 0.11 # Real time elapsed on the host
-host_tick_rate 2713497 # Simulator tick rate (ticks/s)
+host_inst_rate 24278 # Simulator instruction rate (inst/s)
+host_mem_usage 347460 # Number of bytes of host memory used
+host_seconds 0.24 # Real time elapsed on the host
+host_tick_rate 1220626 # Simulator tick rate (ticks/s)
sim_freq 1000000000 # Frequency of simulated ticks
sim_insts 5827 # Number of instructions simulated
sim_seconds 0.000293 # Number of seconds simulated
@@ -29,24 +29,8 @@ system.cpu.itb.write_hits 0 # DT
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.numCycles 292960 # number of cpu cycles simulated
-system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu.num_busy_cycles 292960 # Number of busy cycles
-system.cpu.num_conditional_control_insts 677 # number of instructions that are conditional controls
-system.cpu.num_fp_alu_accesses 2 # Number of float alu accesses
-system.cpu.num_fp_insts 2 # number of float instructions
-system.cpu.num_fp_register_reads 3 # number of times the floating registers were read
-system.cpu.num_fp_register_writes 1 # number of times the floating registers were written
-system.cpu.num_func_calls 194 # number of times a function call or return occured
-system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_insts 5827 # Number of instructions executed
-system.cpu.num_int_alu_accesses 5126 # Number of integer alu accesses
-system.cpu.num_int_insts 5126 # number of integer instructions
-system.cpu.num_int_register_reads 7301 # number of times the integer registers were read
-system.cpu.num_int_register_writes 3409 # number of times the integer registers were written
-system.cpu.num_load_insts 1164 # Number of load instructions
-system.cpu.num_mem_refs 2090 # number of memory refs
-system.cpu.num_store_insts 926 # Number of store instructions
+system.cpu.num_refs 2090 # Number of memory references
system.cpu.workload.PROG:num_syscalls 8 # Number of system calls
---------- End Simulation Statistics ----------
diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini b/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini
index fbed8c837..e2f4de6ac 100644
--- a/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini
+++ b/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini
@@ -1,22 +1,13 @@
[root]
type=Root
children=system
-time_sync_enable=false
-time_sync_period=100000000000
-time_sync_spin_threshold=100000000
+dummy=0
[system]
type=System
children=cpu membus physmem
mem_mode=atomic
physmem=system.physmem
-work_begin_ckpt_count=0
-work_begin_cpu_id_exit=-1
-work_begin_exit_count=0
-work_cpus_ckpt_count=0
-work_end_ckpt_count=0
-work_end_exit_count=0
-work_item_id=-1
[system.cpu]
type=TimingSimpleCPU
@@ -220,7 +211,7 @@ egid=100
env=
errout=cerr
euid=100
-executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/mips/linux/hello
+executable=/dist/m5/regression/test-progs/hello/bin/mips/linux/hello
gid=100
input=cin
max_stack_size=67108864
diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing/simout b/tests/quick/00.hello/ref/mips/linux/simple-timing/simout
index b10b0a832..bfd8a31fc 100755
--- a/tests/quick/00.hello/ref/mips/linux/simple-timing/simout
+++ b/tests/quick/00.hello/ref/mips/linux/simple-timing/simout
@@ -1,3 +1,5 @@
+Redirecting stdout to build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/simple-timing/simout
+Redirecting stderr to build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/simple-timing/simerr
M5 Simulator System
Copyright (c) 2001-2008
@@ -5,11 +7,11 @@ The Regents of The University of Michigan
All Rights Reserved
-M5 compiled Feb 6 2011 15:20:27
-M5 revision b885adc82ab4+ 7924+ default tip qtip brad/regress_updates
-M5 started Feb 6 2011 20:46:12
-M5 executing on SC2B0617
-command line: build/MIPS_SE/m5.fast -d build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-timing -re tests/run.py build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-timing
+M5 compiled Aug 26 2010 12:56:28
+M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix
+M5 started Aug 26 2010 12:56:30
+M5 executing on zizzer
+command line: build/MIPS_SE/m5.opt -d build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/simple-timing -re tests/run.py build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing/stats.txt b/tests/quick/00.hello/ref/mips/linux/simple-timing/stats.txt
index 5ad70ef1f..f4ea21892 100644
--- a/tests/quick/00.hello/ref/mips/linux/simple-timing/stats.txt
+++ b/tests/quick/00.hello/ref/mips/linux/simple-timing/stats.txt
@@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 499743 # Simulator instruction rate (inst/s)
-host_mem_usage 205480 # Number of bytes of host memory used
-host_seconds 0.01 # Real time elapsed on the host
-host_tick_rate 2679135009 # Simulator tick rate (ticks/s)
+host_inst_rate 5098 # Simulator instruction rate (inst/s)
+host_mem_usage 204896 # Number of bytes of host memory used
+host_seconds 1.14 # Real time elapsed on the host
+host_tick_rate 28066026 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 5827 # Number of instructions simulated
sim_seconds 0.000032 # Number of seconds simulated
@@ -213,24 +213,8 @@ system.cpu.l2cache.warmup_cycle 0 # Cy
system.cpu.l2cache.writebacks 0 # number of writebacks
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.numCycles 64176 # number of cpu cycles simulated
-system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu.num_busy_cycles 64176 # Number of busy cycles
-system.cpu.num_conditional_control_insts 677 # number of instructions that are conditional controls
-system.cpu.num_fp_alu_accesses 2 # Number of float alu accesses
-system.cpu.num_fp_insts 2 # number of float instructions
-system.cpu.num_fp_register_reads 3 # number of times the floating registers were read
-system.cpu.num_fp_register_writes 1 # number of times the floating registers were written
-system.cpu.num_func_calls 194 # number of times a function call or return occured
-system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_insts 5827 # Number of instructions executed
-system.cpu.num_int_alu_accesses 5126 # Number of integer alu accesses
-system.cpu.num_int_insts 5126 # number of integer instructions
-system.cpu.num_int_register_reads 7301 # number of times the integer registers were read
-system.cpu.num_int_register_writes 3409 # number of times the integer registers were written
-system.cpu.num_load_insts 1164 # Number of load instructions
-system.cpu.num_mem_refs 2090 # number of memory refs
-system.cpu.num_store_insts 926 # Number of store instructions
+system.cpu.num_refs 2090 # Number of memory references
system.cpu.workload.PROG:num_syscalls 8 # Number of system calls
---------- End Simulation Statistics ----------