diff options
Diffstat (limited to 'tests/quick/00.hello/ref/mips')
| -rwxr-xr-x | tests/quick/00.hello/ref/mips/linux/o3-timing/simout | 6 | ||||
| -rw-r--r-- | tests/quick/00.hello/ref/mips/linux/o3-timing/stats.txt | 9 |
2 files changed, 8 insertions, 7 deletions
diff --git a/tests/quick/00.hello/ref/mips/linux/o3-timing/simout b/tests/quick/00.hello/ref/mips/linux/o3-timing/simout index ac792f6c6..6b2281542 100755 --- a/tests/quick/00.hello/ref/mips/linux/o3-timing/simout +++ b/tests/quick/00.hello/ref/mips/linux/o3-timing/simout @@ -5,9 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Nov 14 2010 23:58:18 -M5 revision f440cdaf1c2d+ 7743+ default tip -M5 started Nov 14 2010 23:58:34 +M5 compiled Jan 17 2011 21:17:36 +M5 revision f72d94f8c275 7839 default qtip tip outgoing.patch qbase +M5 started Jan 17 2011 21:17:39 M5 executing on zizzer command line: build/MIPS_SE/m5.fast -d build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/o3-timing -re tests/run.py build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/o3-timing Global frequency set at 1000000000000 ticks per second diff --git a/tests/quick/00.hello/ref/mips/linux/o3-timing/stats.txt b/tests/quick/00.hello/ref/mips/linux/o3-timing/stats.txt index 8e9b6a4ca..a5f35787b 100644 --- a/tests/quick/00.hello/ref/mips/linux/o3-timing/stats.txt +++ b/tests/quick/00.hello/ref/mips/linux/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 72923 # Simulator instruction rate (inst/s) +host_inst_rate 35741 # Simulator instruction rate (inst/s) host_mem_usage 204488 # Number of bytes of host memory used -host_seconds 0.07 # Real time elapsed on the host -host_tick_rate 179666090 # Simulator tick rate (ticks/s) +host_seconds 0.14 # Real time elapsed on the host +host_tick_rate 88262097 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 5169 # Number of instructions simulated sim_seconds 0.000013 # Number of seconds simulated @@ -136,9 +136,10 @@ system.cpu.dtb.write_hits 0 # DT system.cpu.dtb.write_misses 0 # DTB write misses system.cpu.fetch.Branches 1744 # Number of branches that fetch encountered system.cpu.fetch.CacheLines 1555 # Number of cache lines fetched -system.cpu.fetch.Cycles 4407 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.Cycles 2837 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.IcacheSquashes 219 # Number of outstanding Icache misses that were squashed system.cpu.fetch.Insts 11052 # Number of instructions fetch has processed +system.cpu.fetch.MiscStallCycles 15 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.SquashCycles 393 # Number of cycles fetch has spent squashing system.cpu.fetch.branchRate 0.068205 # Number of branch fetches per cycle system.cpu.fetch.icacheStallCycles 1555 # Number of cycles fetch is stalled on an Icache miss |