diff options
Diffstat (limited to 'tests/quick/00.hello/ref/power/linux/o3-timing/stats.txt')
| -rw-r--r-- | tests/quick/00.hello/ref/power/linux/o3-timing/stats.txt | 610 |
1 files changed, 305 insertions, 305 deletions
diff --git a/tests/quick/00.hello/ref/power/linux/o3-timing/stats.txt b/tests/quick/00.hello/ref/power/linux/o3-timing/stats.txt index eed636458..6e32b0c6c 100644 --- a/tests/quick/00.hello/ref/power/linux/o3-timing/stats.txt +++ b/tests/quick/00.hello/ref/power/linux/o3-timing/stats.txt @@ -1,41 +1,41 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 32835 # Simulator instruction rate (inst/s) -host_mem_usage 222408 # Number of bytes of host memory used -host_seconds 0.18 # Real time elapsed on the host -host_tick_rate 66311402 # Simulator tick rate (ticks/s) +host_inst_rate 15140 # Simulator instruction rate (inst/s) +host_mem_usage 204452 # Number of bytes of host memory used +host_seconds 0.38 # Real time elapsed on the host +host_tick_rate 30510356 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 5800 # Number of instructions simulated sim_seconds 0.000012 # Number of seconds simulated -sim_ticks 11733000 # Number of ticks simulated +sim_ticks 11695000 # Number of ticks simulated system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.BTBHits 687 # Number of BTB hits -system.cpu.BPredUnit.BTBLookups 1888 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 679 # Number of BTB hits +system.cpu.BPredUnit.BTBLookups 1865 # Number of BTB lookups system.cpu.BPredUnit.RASInCorrect 31 # Number of incorrect RAS predictions. -system.cpu.BPredUnit.condIncorrect 387 # Number of conditional branches incorrect -system.cpu.BPredUnit.condPredicted 1757 # Number of conditional branches predicted -system.cpu.BPredUnit.lookups 2100 # Number of BP lookups -system.cpu.BPredUnit.usedRAS 189 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.condIncorrect 388 # Number of conditional branches incorrect +system.cpu.BPredUnit.condPredicted 1734 # Number of conditional branches predicted +system.cpu.BPredUnit.lookups 2075 # Number of BP lookups +system.cpu.BPredUnit.usedRAS 187 # Number of times the RAS was used to get a target. system.cpu.commit.COM:branches 1038 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 51 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_lim_events 42 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle::samples 10473 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::mean 0.553805 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::stdev 1.272090 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::samples 10395 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::mean 0.557961 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::stdev 1.275569 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::0 7930 75.72% 75.72% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::1 1118 10.68% 86.39% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::2 663 6.33% 92.72% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::3 256 2.44% 95.17% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::4 224 2.14% 97.31% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::5 123 1.17% 98.48% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::6 87 0.83% 99.31% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::7 21 0.20% 99.51% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::8 51 0.49% 100.00% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::0 7869 75.70% 75.70% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::1 1103 10.61% 86.31% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::2 649 6.24% 92.55% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::3 257 2.47% 95.03% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::4 223 2.15% 97.17% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::5 132 1.27% 98.44% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::6 100 0.96% 99.40% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::7 20 0.19% 99.60% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::8 42 0.40% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::total 10473 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::total 10395 # Number of insts commited each cycle system.cpu.commit.COM:count 5800 # Number of instructions committed system.cpu.commit.COM:fp_insts 22 # Number of committed floating point instructions. system.cpu.commit.COM:function_calls 103 # Number of function calls committed. @@ -47,86 +47,86 @@ system.cpu.commit.COM:swp_count 0 # Nu system.cpu.commit.branchMispredicts 240 # The number of times a branch was mispredicted system.cpu.commit.commitCommittedInsts 5800 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 16 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 3389 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 3301 # The number of squashed insts skipped by commit system.cpu.committedInsts 5800 # Number of Instructions Simulated system.cpu.committedInsts_total 5800 # Number of Instructions Simulated -system.cpu.cpi 4.046034 # CPI: Cycles Per Instruction -system.cpu.cpi_total 4.046034 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 1444 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 33681.818182 # average ReadReq miss latency +system.cpu.cpi 4.032931 # CPI: Cycles Per Instruction +system.cpu.cpi_total 4.032931 # CPI: Total CPI of All Threads +system.cpu.dcache.ReadReq_accesses 1431 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 33954.022989 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34464.285714 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 1356 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 2964000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.060942 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 88 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 32 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_hits 1344 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 2954000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.060797 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 87 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 31 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_miss_latency 1930000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.038781 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate 0.039133 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 56 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 1046 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 33737.864078 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 36302.083333 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 33770.226537 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 36291.666667 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_hits 737 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 10425000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 10435000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.295411 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses 309 # number of WriteReq misses system.cpu.dcache.WriteReq_mshr_hits 261 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 1742500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 1742000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.045889 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 48 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 20.125000 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 20.009615 # Average number of references to valid blocks. system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 2490 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 33725.440806 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 35312.500000 # average overall mshr miss latency -system.cpu.dcache.demand_hits 2093 # number of demand (read+write) hits +system.cpu.dcache.demand_accesses 2477 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 33810.606061 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 35307.692308 # average overall mshr miss latency +system.cpu.dcache.demand_hits 2081 # number of demand (read+write) hits system.cpu.dcache.demand_miss_latency 13389000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.159438 # miss rate for demand accesses -system.cpu.dcache.demand_misses 397 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 293 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 3672500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.041767 # mshr miss rate for demand accesses +system.cpu.dcache.demand_miss_rate 0.159871 # miss rate for demand accesses +system.cpu.dcache.demand_misses 396 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 292 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 3672000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.041986 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 104 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.016245 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 66.538229 # Average occupied blocks per context -system.cpu.dcache.overall_accesses 2490 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 33725.440806 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 35312.500000 # average overall mshr miss latency +system.cpu.dcache.occ_%::0 0.016225 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 66.459259 # Average occupied blocks per context +system.cpu.dcache.overall_accesses 2477 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 33810.606061 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 35307.692308 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 2093 # number of overall hits +system.cpu.dcache.overall_hits 2081 # number of overall hits system.cpu.dcache.overall_miss_latency 13389000 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.159438 # miss rate for overall accesses -system.cpu.dcache.overall_misses 397 # number of overall misses -system.cpu.dcache.overall_mshr_hits 293 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 3672500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.041767 # mshr miss rate for overall accesses +system.cpu.dcache.overall_miss_rate 0.159871 # miss rate for overall accesses +system.cpu.dcache.overall_misses 396 # number of overall misses +system.cpu.dcache.overall_mshr_hits 292 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 3672000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.041986 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 104 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.sampled_refs 104 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 66.538229 # Cycle average of tags in use -system.cpu.dcache.total_refs 2093 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 66.459259 # Cycle average of tags in use +system.cpu.dcache.total_refs 2081 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 885 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 150 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 267 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 10406 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 7574 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 1944 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 570 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 416 # Number of squashed instructions handled by decode +system.cpu.decode.DECODE:BlockedCycles 887 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BranchMispred 151 # Number of times decode detected a branch misprediction +system.cpu.decode.DECODE:BranchResolved 265 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 10261 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 7524 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 1914 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 549 # Number of cycles decode is squashing +system.cpu.decode.DECODE:SquashedInsts 421 # Number of squashed instructions handled by decode system.cpu.decode.DECODE:UnblockCycles 70 # Number of cycles decode is unblocking system.cpu.dtb.accesses 0 # DTB accesses system.cpu.dtb.hits 0 # DTB hits @@ -137,243 +137,243 @@ system.cpu.dtb.read_misses 0 # DT system.cpu.dtb.write_accesses 0 # DTB write accesses system.cpu.dtb.write_hits 0 # DTB write hits system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.fetch.Branches 2100 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 1490 # Number of cache lines fetched -system.cpu.fetch.Cycles 2070 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 225 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 11687 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2075 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 1460 # Number of cache lines fetched +system.cpu.fetch.Cycles 2040 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 218 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 11548 # Number of instructions fetch has processed system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.SquashCycles 410 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.089487 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 1490 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 876 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 0.498018 # Number of inst fetches per cycle -system.cpu.fetch.rateDist::samples 11043 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.058317 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.450976 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.SquashCycles 402 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.088709 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 1460 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 866 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 0.493694 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 10944 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.055190 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.449465 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 8973 81.26% 81.26% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 161 1.46% 82.71% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 189 1.71% 84.42% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 155 1.40% 85.83% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 202 1.83% 87.66% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 136 1.23% 88.89% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 272 2.46% 91.35% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 77 0.70% 92.05% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 878 7.95% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 8904 81.36% 81.36% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 156 1.43% 82.79% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 186 1.70% 84.48% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 150 1.37% 85.86% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 199 1.82% 87.67% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 133 1.22% 88.89% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 272 2.49% 91.37% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 75 0.69% 92.06% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 869 7.94% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 11043 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 10944 # Number of instructions fetched each cycle (Total) system.cpu.fp_regfile_reads 25 # number of floating regfile reads system.cpu.fp_regfile_writes 2 # number of floating regfile writes -system.cpu.icache.ReadReq_accesses 1490 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 36422.279793 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 34777.108434 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 1104 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 14059000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.259060 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 386 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 54 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 11546000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.222819 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 332 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_accesses 1460 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 36594.488189 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 34774.774775 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 1079 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 13942500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.260959 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 381 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 48 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 11580000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.228082 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 333 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 3.325301 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 3.240240 # Average number of references to valid blocks. system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 1490 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 36422.279793 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 34777.108434 # average overall mshr miss latency -system.cpu.icache.demand_hits 1104 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 14059000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.259060 # miss rate for demand accesses -system.cpu.icache.demand_misses 386 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 54 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 11546000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.222819 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 332 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_accesses 1460 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 36594.488189 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 34774.774775 # average overall mshr miss latency +system.cpu.icache.demand_hits 1079 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 13942500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.260959 # miss rate for demand accesses +system.cpu.icache.demand_misses 381 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 48 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 11580000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.228082 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 333 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.078715 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 161.207549 # Average occupied blocks per context -system.cpu.icache.overall_accesses 1490 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 36422.279793 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 34777.108434 # average overall mshr miss latency +system.cpu.icache.occ_%::0 0.078664 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 161.104076 # Average occupied blocks per context +system.cpu.icache.overall_accesses 1460 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 36594.488189 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 34774.774775 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 1104 # number of overall hits -system.cpu.icache.overall_miss_latency 14059000 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.259060 # miss rate for overall accesses -system.cpu.icache.overall_misses 386 # number of overall misses -system.cpu.icache.overall_mshr_hits 54 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 11546000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.222819 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 332 # number of overall MSHR misses +system.cpu.icache.overall_hits 1079 # number of overall hits +system.cpu.icache.overall_miss_latency 13942500 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.260959 # miss rate for overall accesses +system.cpu.icache.overall_misses 381 # number of overall misses +system.cpu.icache.overall_mshr_hits 48 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 11580000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.228082 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 333 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.sampled_refs 332 # Sample count of references to valid blocks. +system.cpu.icache.sampled_refs 333 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 161.207549 # Cycle average of tags in use -system.cpu.icache.total_refs 1104 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 161.104076 # Cycle average of tags in use +system.cpu.icache.total_refs 1079 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 12424 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 1261 # Number of branches executed +system.cpu.idleCycles 12447 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 1262 # Number of branches executed system.cpu.iew.EXEC:nop 0 # number of nop insts executed -system.cpu.iew.EXEC:rate 0.331998 # Inst execution rate -system.cpu.iew.EXEC:refs 2813 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 1315 # Number of stores executed +system.cpu.iew.EXEC:rate 0.332008 # Inst execution rate +system.cpu.iew.EXEC:refs 2790 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 1305 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 5926 # num instructions consuming a value -system.cpu.iew.WB:count 7582 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.645461 # average fanout of values written-back +system.cpu.iew.WB:consumers 5916 # num instructions consuming a value +system.cpu.iew.WB:count 7563 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.645030 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 3825 # num instructions producing a value -system.cpu.iew.WB:rate 0.323092 # insts written-back per cycle -system.cpu.iew.WB:sent 7642 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 277 # Number of branch mispredicts detected at execute +system.cpu.iew.WB:producers 3816 # num instructions producing a value +system.cpu.iew.WB:rate 0.323329 # insts written-back per cycle +system.cpu.iew.WB:sent 7623 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 279 # Number of branch mispredicts detected at execute system.cpu.iew.iewBlockCycles 130 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 1681 # Number of dispatched load instructions +system.cpu.iew.iewDispLoadInsts 1666 # Number of dispatched load instructions system.cpu.iew.iewDispNonSpecInsts 14 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 97 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 1450 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 9185 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 1498 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 298 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 7791 # Number of executed instructions +system.cpu.iew.iewDispSquashedInsts 100 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 1436 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 9097 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 1485 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 289 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 7766 # Number of executed instructions system.cpu.iew.iewIQFullEvents 4 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 570 # Number of cycles IEW is squashing +system.cpu.iew.iewSquashCycles 549 # Number of cycles IEW is squashing system.cpu.iew.iewUnblockCycles 12 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 30 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.forwLoads 29 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 1 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 42 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.memOrderViolation 13 # Number of memory ordering violations system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 719 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 404 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 42 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 201 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 76 # Number of branches that were predicted taken incorrectly -system.cpu.int_regfile_reads 12419 # number of integer regfile reads -system.cpu.int_regfile_writes 6594 # number of integer regfile writes -system.cpu.ipc 0.247156 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.247156 # IPC: Total IPC of All Threads +system.cpu.iew.lsq.thread.0.squashedLoads 704 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 390 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 13 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 202 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 77 # Number of branches that were predicted taken incorrectly +system.cpu.int_regfile_reads 12407 # number of integer regfile reads +system.cpu.int_regfile_writes 6585 # number of integer regfile writes +system.cpu.ipc 0.247959 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.247959 # IPC: Total IPC of All Threads system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntAlu 5126 63.37% 63.37% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntMult 0 0.00% 63.37% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 63.37% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatAdd 2 0.02% 63.39% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 63.39% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 63.39% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 63.39% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 63.39% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 63.39% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 63.39% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 63.39% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 63.39% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 63.39% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 63.39% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 63.39% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 63.39% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 63.39% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 63.39% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 63.39% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 63.39% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 63.39% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 63.39% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 63.39% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 63.39% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 63.39% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 63.39% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 63.39% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 63.39% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 63.39% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemRead 1593 19.69% 83.09% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemWrite 1368 16.91% 100.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntAlu 5116 63.51% 63.51% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntMult 0 0.00% 63.51% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 63.51% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatAdd 2 0.02% 63.54% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 63.54% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 63.54% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 63.54% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 63.54% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 63.54% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 63.54% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 63.54% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 63.54% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 63.54% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 63.54% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 63.54% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 63.54% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 63.54% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 63.54% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 63.54% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 63.54% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 63.54% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 63.54% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 63.54% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 63.54% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 63.54% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 63.54% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 63.54% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 63.54% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 63.54% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemRead 1580 19.62% 83.15% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemWrite 1357 16.85% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::total 8089 # Type of FU issued -system.cpu.iq.ISSUE:fu_busy_cnt 153 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.018915 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:FU_type_0::total 8055 # Type of FU issued +system.cpu.iq.ISSUE:fu_busy_cnt 152 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.018870 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntAlu 11 7.19% 7.19% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 7.19% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 7.19% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 7.19% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 7.19% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 7.19% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 7.19% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 7.19% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 7.19% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 7.19% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 7.19% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 7.19% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 7.19% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 7.19% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 7.19% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 7.19% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 7.19% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 7.19% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 7.19% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 7.19% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 7.19% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 7.19% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 7.19% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 7.19% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 7.19% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 7.19% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 7.19% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 7.19% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 7.19% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemRead 73 47.71% 54.90% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemWrite 69 45.10% 100.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntAlu 11 7.24% 7.24% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 7.24% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 7.24% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 7.24% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 7.24% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 7.24% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 7.24% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 7.24% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 7.24% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 7.24% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 7.24% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 7.24% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 7.24% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 7.24% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 7.24% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 7.24% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 7.24% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 7.24% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 7.24% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 7.24% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 7.24% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 7.24% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 7.24% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 7.24% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 7.24% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 7.24% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 7.24% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 7.24% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 7.24% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemRead 72 47.37% 54.61% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemWrite 69 45.39% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:issued_per_cycle::samples 11043 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::mean 0.732500 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.410424 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::samples 10944 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::mean 0.736020 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.423307 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::0 7773 70.39% 70.39% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::1 1167 10.57% 80.96% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::2 813 7.36% 88.32% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::3 500 4.53% 92.85% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::4 391 3.54% 96.39% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::5 222 2.01% 98.40% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::6 124 1.12% 99.52% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::7 46 0.42% 99.94% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::0 7700 70.36% 70.36% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::1 1176 10.75% 81.10% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::2 793 7.25% 88.35% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::3 485 4.43% 92.78% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::4 365 3.34% 96.12% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::5 233 2.13% 98.25% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::6 138 1.26% 99.51% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::7 47 0.43% 99.94% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::8 7 0.06% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::total 11043 # Number of insts issued each cycle -system.cpu.iq.ISSUE:rate 0.344697 # Inst issue rate +system.cpu.iq.ISSUE:issued_per_cycle::total 10944 # Number of insts issued each cycle +system.cpu.iq.ISSUE:rate 0.344363 # Inst issue rate system.cpu.iq.fp_alu_accesses 31 # Number of floating point alu accesses system.cpu.iq.fp_inst_queue_reads 59 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_wakeup_accesses 27 # Number of floating instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_writes 36 # Number of floating instruction queue writes -system.cpu.iq.int_alu_accesses 8211 # Number of integer alu accesses -system.cpu.iq.int_inst_queue_reads 27329 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_wakeup_accesses 7555 # Number of integer instruction queue wakeup accesses -system.cpu.iq.int_inst_queue_writes 12158 # Number of integer instruction queue writes -system.cpu.iq.iqInstsAdded 9163 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 8089 # Number of instructions issued +system.cpu.iq.int_alu_accesses 8176 # Number of integer alu accesses +system.cpu.iq.int_inst_queue_reads 27162 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_wakeup_accesses 7536 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_writes 11998 # Number of integer instruction queue writes +system.cpu.iq.iqInstsAdded 9075 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 8055 # Number of instructions issued system.cpu.iq.iqNonSpecInstsAdded 22 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 2985 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 14 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 2924 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 15 # Number of squashed instructions issued system.cpu.iq.iqSquashedNonSpecRemoved 6 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 2761 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedOperandsExamined 2633 # Number of squashed operands that are examined and possibly removed from graph system.cpu.itb.accesses 0 # DTB accesses system.cpu.itb.hits 0 # DTB hits system.cpu.itb.misses 0 # DTB misses @@ -384,97 +384,97 @@ system.cpu.itb.write_accesses 0 # DT system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses system.cpu.l2cache.ReadExReq_accesses 48 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 34947.916667 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 34937.500000 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31770.833333 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 1677500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 1677000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_misses 48 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_mshr_miss_latency 1525000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_misses 48 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 388 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 34326.315789 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31147.368421 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_accesses 389 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 34322.834646 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31146.981627 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 8 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 13044000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.979381 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 380 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 11836000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.979381 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 380 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_miss_latency 13077000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.979434 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 381 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 11867000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.979434 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 381 # number of ReadReq MSHR misses system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.021053 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 0.020997 # Average number of references to valid blocks. system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 436 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 34396.028037 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31217.289720 # average overall mshr miss latency +system.cpu.l2cache.demand_accesses 437 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 34391.608392 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31216.783217 # average overall mshr miss latency system.cpu.l2cache.demand_hits 8 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 14721500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.981651 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 428 # number of demand (read+write) misses +system.cpu.l2cache.demand_miss_latency 14754000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.981693 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 429 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 13361000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.981651 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 428 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 13392000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.981693 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 429 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.005863 # Average percentage of cache occupancy -system.cpu.l2cache.occ_blocks::0 192.111326 # Average occupied blocks per context -system.cpu.l2cache.overall_accesses 436 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 34396.028037 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31217.289720 # average overall mshr miss latency +system.cpu.l2cache.occ_%::0 0.005859 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 191.979751 # Average occupied blocks per context +system.cpu.l2cache.overall_accesses 437 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 34391.608392 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31216.783217 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 8 # number of overall hits -system.cpu.l2cache.overall_miss_latency 14721500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.981651 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 428 # number of overall misses +system.cpu.l2cache.overall_miss_latency 14754000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.981693 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 429 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 13361000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.981651 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 428 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 13392000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.981693 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 429 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 380 # Sample count of references to valid blocks. +system.cpu.l2cache.sampled_refs 381 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 192.111326 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 191.979751 # Cycle average of tags in use system.cpu.l2cache.total_refs 8 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.memDep0.conflictingLoads 67 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 29 # Number of conflicting stores. -system.cpu.memDep0.insertedLoads 1681 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1450 # Number of stores inserted to the mem dependence unit. -system.cpu.numCycles 23467 # number of cpu cycles simulated +system.cpu.memDep0.conflictingLoads 48 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 28 # Number of conflicting stores. +system.cpu.memDep0.insertedLoads 1666 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1436 # Number of stores inserted to the mem dependence unit. +system.cpu.numCycles 23391 # number of cpu cycles simulated system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.rename.RENAME:BlockCycles 312 # Number of cycles rename is blocking +system.cpu.rename.RENAME:BlockCycles 314 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 5007 # Number of HB maps that are committed system.cpu.rename.RENAME:IQFullEvents 7 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 7756 # Number of cycles rename is idle +system.cpu.rename.RENAME:IdleCycles 7703 # Number of cycles rename is idle system.cpu.rename.RENAME:LSQFullEvents 194 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:RenameLookups 16232 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 9925 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 8708 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 1825 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 570 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 243 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 3701 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:RenameLookups 16001 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 9789 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 8584 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 1797 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 549 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 244 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 3577 # Number of HB maps that are undone due to squashing system.cpu.rename.RENAME:fp_rename_lookups 55 # Number of floating rename lookups -system.cpu.rename.RENAME:int_rename_lookups 16177 # Number of integer rename lookups +system.cpu.rename.RENAME:int_rename_lookups 15946 # Number of integer rename lookups system.cpu.rename.RENAME:serializeStallCycles 337 # count of cycles rename stalled for serializing inst system.cpu.rename.RENAME:serializingInsts 22 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 473 # count of insts added to the skid buffer +system.cpu.rename.RENAME:skidInsts 471 # count of insts added to the skid buffer system.cpu.rename.RENAME:tempSerializingInsts 22 # count of temporary serializing insts renamed -system.cpu.rob.rob_reads 19611 # The number of ROB reads -system.cpu.rob.rob_writes 18950 # The number of ROB writes -system.cpu.timesIdled 230 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.rob.rob_reads 19454 # The number of ROB reads +system.cpu.rob.rob_writes 18753 # The number of ROB writes +system.cpu.timesIdled 229 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 9 # Number of system calls ---------- End Simulation Statistics ---------- |