diff options
Diffstat (limited to 'tests/quick/00.hello/ref/power/linux')
| -rwxr-xr-x | tests/quick/00.hello/ref/power/linux/o3-timing/simerr | 2 | ||||
| -rwxr-xr-x | tests/quick/00.hello/ref/power/linux/o3-timing/simout | 6 | ||||
| -rw-r--r-- | tests/quick/00.hello/ref/power/linux/o3-timing/stats.txt | 11 |
3 files changed, 10 insertions, 9 deletions
diff --git a/tests/quick/00.hello/ref/power/linux/o3-timing/simerr b/tests/quick/00.hello/ref/power/linux/o3-timing/simerr index 1fe8a27f7..29a71f392 100755 --- a/tests/quick/00.hello/ref/power/linux/o3-timing/simerr +++ b/tests/quick/00.hello/ref/power/linux/o3-timing/simerr @@ -1,5 +1,5 @@ warn: Sockets disabled, not accepting gdb connections For more information see: http://www.m5sim.org/warn/d946bea6 -warn: allowing mmap of file @ fd 17040520. This will break if not /dev/zero. +warn: allowing mmap of file @ fd 16206088. This will break if not /dev/zero. For more information see: http://www.m5sim.org/warn/3a2134f6 hack: be nice to actually delete the event here diff --git a/tests/quick/00.hello/ref/power/linux/o3-timing/simout b/tests/quick/00.hello/ref/power/linux/o3-timing/simout index d3bc761bb..6bd581433 100755 --- a/tests/quick/00.hello/ref/power/linux/o3-timing/simout +++ b/tests/quick/00.hello/ref/power/linux/o3-timing/simout @@ -5,9 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Nov 15 2010 00:01:15 -M5 revision f440cdaf1c2d+ 7743+ default tip -M5 started Nov 15 2010 00:01:17 +M5 compiled Jan 17 2011 17:18:01 +M5 revision f72d94f8c275 7839 default qtip tip outgoing.patch qbase +M5 started Jan 17 2011 17:18:03 M5 executing on zizzer command line: build/POWER_SE/m5.fast -d build/POWER_SE/tests/fast/quick/00.hello/power/linux/o3-timing -re tests/run.py build/POWER_SE/tests/fast/quick/00.hello/power/linux/o3-timing Global frequency set at 1000000000000 ticks per second diff --git a/tests/quick/00.hello/ref/power/linux/o3-timing/stats.txt b/tests/quick/00.hello/ref/power/linux/o3-timing/stats.txt index 6f780bef0..8b311d8d3 100644 --- a/tests/quick/00.hello/ref/power/linux/o3-timing/stats.txt +++ b/tests/quick/00.hello/ref/power/linux/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 15746 # Simulator instruction rate (inst/s) -host_mem_usage 202164 # Number of bytes of host memory used -host_seconds 0.37 # Real time elapsed on the host -host_tick_rate 31829526 # Simulator tick rate (ticks/s) +host_inst_rate 12762 # Simulator instruction rate (inst/s) +host_mem_usage 202140 # Number of bytes of host memory used +host_seconds 0.45 # Real time elapsed on the host +host_tick_rate 25804848 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 5800 # Number of instructions simulated sim_seconds 0.000012 # Number of seconds simulated @@ -136,9 +136,10 @@ system.cpu.dtb.write_hits 0 # DT system.cpu.dtb.write_misses 0 # DTB write misses system.cpu.fetch.Branches 2100 # Number of branches that fetch encountered system.cpu.fetch.CacheLines 1490 # Number of cache lines fetched -system.cpu.fetch.Cycles 3561 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.Cycles 2070 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.IcacheSquashes 225 # Number of outstanding Icache misses that were squashed system.cpu.fetch.Insts 11687 # Number of instructions fetch has processed +system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.SquashCycles 410 # Number of cycles fetch has spent squashing system.cpu.fetch.branchRate 0.089487 # Number of branch fetches per cycle system.cpu.fetch.icacheStallCycles 1490 # Number of cycles fetch is stalled on an Icache miss |