diff options
Diffstat (limited to 'tests/quick/00.hello/ref/sparc/linux/simple-timing-ruby/config.ini')
-rw-r--r-- | tests/quick/00.hello/ref/sparc/linux/simple-timing-ruby/config.ini | 95 |
1 files changed, 95 insertions, 0 deletions
diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-timing-ruby/config.ini b/tests/quick/00.hello/ref/sparc/linux/simple-timing-ruby/config.ini new file mode 100644 index 000000000..4d7c09664 --- /dev/null +++ b/tests/quick/00.hello/ref/sparc/linux/simple-timing-ruby/config.ini @@ -0,0 +1,95 @@ +[root] +type=Root +children=system +dummy=0 + +[system] +type=System +children=cpu membus physmem +mem_mode=atomic +physmem=system.physmem + +[system.cpu] +type=TimingSimpleCPU +children=dtb itb tracer workload +checker=Null +clock=500 +cpu_id=0 +defer_registration=false +do_checkpoint_insts=true +do_statistics_insts=true +dtb=system.cpu.dtb +function_trace=false +function_trace_start=0 +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +phase=0 +progress_interval=0 +system=system +tracer=system.cpu.tracer +workload=system.cpu.workload +dcache_port=system.membus.port[2] +icache_port=system.membus.port[1] + +[system.cpu.dtb] +type=SparcTLB +size=64 + +[system.cpu.itb] +type=SparcTLB +size=64 + +[system.cpu.tracer] +type=ExeTracer + +[system.cpu.workload] +type=LiveProcess +cmd=hello +cwd= +egid=100 +env= +errout=cerr +euid=100 +executable=/dist/m5/regression/test-progs/hello/bin/sparc/linux/hello +gid=100 +input=cin +max_stack_size=67108864 +output=cout +pid=100 +ppid=99 +simpoint=0 +system=system +uid=100 + +[system.membus] +type=Bus +block_size=64 +bus_id=0 +clock=1000 +header_cycles=1 +responder_set=false +width=64 +port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port + +[system.physmem] +type=RubyMemory +clock=1 +config_file= +config_options= +debug=false +debug_file= +file= +latency=30000 +latency_var=0 +null=false +num_cpus=1 +phase=0 +range=0:134217727 +stats_file=ruby.stats +zero=false +port=system.membus.port[0] + |