diff options
Diffstat (limited to 'tests/quick/00.hello/ref/sparc/linux/simple-timing/m5stats.txt')
| -rw-r--r-- | tests/quick/00.hello/ref/sparc/linux/simple-timing/m5stats.txt | 50 |
1 files changed, 25 insertions, 25 deletions
diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-timing/m5stats.txt b/tests/quick/00.hello/ref/sparc/linux/simple-timing/m5stats.txt index 8907d716d..ff4bd3dbe 100644 --- a/tests/quick/00.hello/ref/sparc/linux/simple-timing/m5stats.txt +++ b/tests/quick/00.hello/ref/sparc/linux/simple-timing/m5stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 277220 # Simulator instruction rate (inst/s) -host_mem_usage 197684 # Number of bytes of host memory used +host_inst_rate 198489 # Simulator instruction rate (inst/s) +host_mem_usage 181156 # Number of bytes of host memory used host_seconds 0.02 # Real time elapsed on the host -host_tick_rate 892278360 # Simulator tick rate (ticks/s) +host_tick_rate 645076356 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 4863 # Number of instructions simulated +sim_insts 4833 # Number of instructions simulated sim_seconds 0.000016 # Number of seconds simulated -sim_ticks 15912000 # Number of ticks simulated +sim_ticks 15925000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 608 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_avg_miss_latency 24777.777778 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency 22777.777778 # average ReadReq mshr miss latency @@ -76,53 +76,53 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.sampled_refs 138 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 83.464621 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 83.440192 # Cycle average of tags in use system.cpu.dcache.total_refs 1131 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_accesses 4864 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses 4877 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_avg_miss_latency 24906.250000 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 22906.250000 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 4608 # number of ReadReq hits +system.cpu.icache.ReadReq_hits 4621 # number of ReadReq hits system.cpu.icache.ReadReq_miss_latency 6376000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.052632 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate 0.052491 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 256 # number of ReadReq misses system.cpu.icache.ReadReq_mshr_miss_latency 5864000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.052632 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate 0.052491 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 256 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_refs 18 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 18.050781 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 4864 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses 4877 # number of demand (read+write) accesses system.cpu.icache.demand_avg_miss_latency 24906.250000 # average overall miss latency system.cpu.icache.demand_avg_mshr_miss_latency 22906.250000 # average overall mshr miss latency -system.cpu.icache.demand_hits 4608 # number of demand (read+write) hits +system.cpu.icache.demand_hits 4621 # number of demand (read+write) hits system.cpu.icache.demand_miss_latency 6376000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.052632 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate 0.052491 # miss rate for demand accesses system.cpu.icache.demand_misses 256 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.icache.demand_mshr_miss_latency 5864000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.052632 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate 0.052491 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 256 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 4864 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses 4877 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 24906.250000 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 22906.250000 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 4608 # number of overall hits +system.cpu.icache.overall_hits 4621 # number of overall hits system.cpu.icache.overall_miss_latency 6376000 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.052632 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate 0.052491 # miss rate for overall accesses system.cpu.icache.overall_misses 256 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits system.cpu.icache.overall_mshr_miss_latency 5864000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.052632 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate 0.052491 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 256 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses @@ -138,8 +138,8 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.icache.replacements 0 # number of replacements system.cpu.icache.sampled_refs 256 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 114.953503 # Cycle average of tags in use -system.cpu.icache.total_refs 4608 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 114.921642 # Cycle average of tags in use +system.cpu.icache.total_refs 4621 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles @@ -219,14 +219,14 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.sampled_refs 292 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 133.743977 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 133.706132 # Cycle average of tags in use system.cpu.l2cache.total_refs 3 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 15912000 # number of cpu cycles simulated -system.cpu.num_insts 4863 # Number of instructions executed -system.cpu.num_refs 1269 # Number of memory references +system.cpu.numCycles 15925000 # number of cpu cycles simulated +system.cpu.num_insts 4833 # Number of instructions executed +system.cpu.num_refs 1282 # Number of memory references system.cpu.workload.PROG:num_syscalls 11 # Number of system calls ---------- End Simulation Statistics ---------- |