diff options
Diffstat (limited to 'tests/quick/00.hello/ref/sparc/linux/simple-timing/m5stats.txt')
| -rw-r--r-- | tests/quick/00.hello/ref/sparc/linux/simple-timing/m5stats.txt | 116 |
1 files changed, 58 insertions, 58 deletions
diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-timing/m5stats.txt b/tests/quick/00.hello/ref/sparc/linux/simple-timing/m5stats.txt index 132891c92..39cffe2aa 100644 --- a/tests/quick/00.hello/ref/sparc/linux/simple-timing/m5stats.txt +++ b/tests/quick/00.hello/ref/sparc/linux/simple-timing/m5stats.txt @@ -1,31 +1,31 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 56962 # Simulator instruction rate (inst/s) -host_mem_usage 210220 # Number of bytes of host memory used -host_seconds 0.09 # Real time elapsed on the host -host_tick_rate 184294275 # Simulator tick rate (ticks/s) +host_inst_rate 288337 # Simulator instruction rate (inst/s) +host_mem_usage 198672 # Number of bytes of host memory used +host_seconds 0.02 # Real time elapsed on the host +host_tick_rate 1546587822 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 5340 # Number of instructions simulated -sim_seconds 0.000017 # Number of seconds simulated -sim_ticks 17315000 # Number of ticks simulated +sim_seconds 0.000029 # Number of seconds simulated +sim_ticks 29031000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 716 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 26759.259259 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 23759.259259 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_miss_latency 55222.222222 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 52222.222222 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_hits 662 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 1445000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency 2982000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.075419 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 54 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 1283000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 2820000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.075419 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 54 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 673 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 27000 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 24000 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_hits 577 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 2592000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 5376000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.142645 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses 96 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 2304000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 5088000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.142645 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 96 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked @@ -37,29 +37,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 1389 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 26913.333333 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 23913.333333 # average overall mshr miss latency +system.cpu.dcache.demand_avg_miss_latency 55720 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 52720 # average overall mshr miss latency system.cpu.dcache.demand_hits 1239 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 4037000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency 8358000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.107991 # miss rate for demand accesses system.cpu.dcache.demand_misses 150 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 3587000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 7908000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.107991 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 150 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.overall_accesses 1389 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 26913.333333 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 23913.333333 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 55720 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 52720 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 1239 # number of overall hits -system.cpu.dcache.overall_miss_latency 4037000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency 8358000 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.107991 # miss rate for overall accesses system.cpu.dcache.overall_misses 150 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 3587000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 7908000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.107991 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 150 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -76,18 +76,18 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.sampled_refs 135 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 83.359749 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 82.357482 # Cycle average of tags in use system.cpu.dcache.total_refs 1254 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks system.cpu.icache.ReadReq_accesses 5384 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 26898.832685 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 23898.832685 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_miss_latency 55673.151751 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 52673.151751 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_hits 5127 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 6913000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency 14308000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.047734 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 257 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 6142000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 13537000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.047734 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 257 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked @@ -99,29 +99,29 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.demand_accesses 5384 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 26898.832685 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 23898.832685 # average overall mshr miss latency +system.cpu.icache.demand_avg_miss_latency 55673.151751 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 52673.151751 # average overall mshr miss latency system.cpu.icache.demand_hits 5127 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 6913000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency 14308000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.047734 # miss rate for demand accesses system.cpu.icache.demand_misses 257 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 6142000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 13537000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.047734 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 257 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.overall_accesses 5384 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 26898.832685 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 23898.832685 # average overall mshr miss latency +system.cpu.icache.overall_avg_miss_latency 55673.151751 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 52673.151751 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.icache.overall_hits 5127 # number of overall hits -system.cpu.icache.overall_miss_latency 6913000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency 14308000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.047734 # miss rate for overall accesses system.cpu.icache.overall_misses 257 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 6142000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 13537000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.047734 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 257 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -138,37 +138,37 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.icache.replacements 0 # number of replacements system.cpu.icache.sampled_refs 257 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 118.738905 # Cycle average of tags in use +system.cpu.icache.tagsinuse 117.715481 # Cycle average of tags in use system.cpu.icache.total_refs 5127 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.l2cache.ReadExReq_accesses 81 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 23000 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 11000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 1863000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_miss_latency 4212000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_misses 81 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 891000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 3240000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_misses 81 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadReq_accesses 311 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 23000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 11000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 3 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 7084000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency 16016000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 0.990354 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_misses 308 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 3388000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 12320000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 0.990354 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 308 # number of ReadReq MSHR misses system.cpu.l2cache.UpgradeReq_accesses 15 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 23000 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 11000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 345000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_avg_miss_latency 52000 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_miss_latency 780000 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_misses 15 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 165000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 600000 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_misses 15 # number of UpgradeReq MSHR misses system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked @@ -180,29 +180,29 @@ system.cpu.l2cache.blocked_cycles_no_mshrs 0 # system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 392 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 23000 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 11000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency system.cpu.l2cache.demand_hits 3 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 8947000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency 20228000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate 0.992347 # miss rate for demand accesses system.cpu.l2cache.demand_misses 389 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 4279000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 15560000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_rate 0.992347 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_misses 389 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.overall_accesses 392 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 23000 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 11000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 3 # number of overall hits -system.cpu.l2cache.overall_miss_latency 8947000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency 20228000 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 0.992347 # miss rate for overall accesses system.cpu.l2cache.overall_misses 389 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 4279000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 15560000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_rate 0.992347 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_misses 389 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -219,12 +219,12 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.sampled_refs 293 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 138.022706 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 136.844792 # Cycle average of tags in use system.cpu.l2cache.total_refs 3 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 34630 # number of cpu cycles simulated +system.cpu.numCycles 58062 # number of cpu cycles simulated system.cpu.num_insts 5340 # Number of instructions executed system.cpu.num_refs 1402 # Number of memory references system.cpu.workload.PROG:num_syscalls 11 # Number of system calls |