diff options
Diffstat (limited to 'tests/quick/00.hello/ref/sparc/linux')
10 files changed, 351 insertions, 276 deletions
diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/config.ini b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/config.ini index de14f79c7..fe9f8a548 100644 --- a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/config.ini +++ b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/config.ini @@ -1,13 +1,22 @@ [root] type=Root children=system -dummy=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem mem_mode=atomic physmem=system.physmem +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 [system.cpu] type=AtomicSimpleCPU @@ -57,7 +66,7 @@ egid=100 env= errout=cerr euid=100 -executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/sparc/linux/hello +executable=/dist/m5/regression/test-progs/hello/bin/sparc/linux/hello gid=100 input=cin max_stack_size=67108864 diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/simout b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/simout index ec097652e..38db96c18 100755 --- a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/simout +++ b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 25 2010 03:11:27 -M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip -M5 started Feb 25 2010 03:37:59 -M5 executing on SC2B0619 +M5 compiled Feb 7 2011 02:13:30 +M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip +M5 started Feb 7 2011 02:14:08 +M5 executing on burrito command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/00.hello/sparc/linux/simple-atomic -re tests/run.py build/SPARC_SE/tests/fast/quick/00.hello/sparc/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/stats.txt b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/stats.txt index 01cd0d37d..2caa46c35 100644 --- a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/stats.txt +++ b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 897027 # Simulator instruction rate (inst/s) -host_mem_usage 182692 # Number of bytes of host memory used -host_seconds 0.01 # Real time elapsed on the host -host_tick_rate 434663663 # Simulator tick rate (ticks/s) +host_inst_rate 96674 # Simulator instruction rate (inst/s) +host_mem_usage 215848 # Number of bytes of host memory used +host_seconds 0.06 # Real time elapsed on the host +host_tick_rate 48656953 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 5340 # Number of instructions simulated sim_seconds 0.000003 # Number of seconds simulated @@ -11,8 +11,24 @@ sim_ticks 2701000 # Nu system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.numCycles 5403 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.num_busy_cycles 5403 # Number of busy cycles +system.cpu.num_conditional_control_insts 0 # number of instructions that are conditional controls +system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses +system.cpu.num_fp_insts 0 # number of float instructions +system.cpu.num_fp_register_reads 0 # number of times the floating registers were read +system.cpu.num_fp_register_writes 0 # number of times the floating registers were written +system.cpu.num_func_calls 0 # number of times a function call or return occured +system.cpu.num_idle_cycles 0 # Number of idle cycles system.cpu.num_insts 5340 # Number of instructions executed -system.cpu.num_refs 1402 # Number of memory references +system.cpu.num_int_alu_accesses 4517 # Number of integer alu accesses +system.cpu.num_int_insts 4517 # number of integer instructions +system.cpu.num_int_register_reads 10620 # number of times the integer registers were read +system.cpu.num_int_register_writes 4859 # number of times the integer registers were written +system.cpu.num_load_insts 724 # Number of load instructions +system.cpu.num_mem_refs 1402 # number of memory refs +system.cpu.num_store_insts 678 # Number of store instructions system.cpu.workload.PROG:num_syscalls 11 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-timing-ruby/config.ini b/tests/quick/00.hello/ref/sparc/linux/simple-timing-ruby/config.ini index eb5199f6d..6590fce9b 100644 --- a/tests/quick/00.hello/ref/sparc/linux/simple-timing-ruby/config.ini +++ b/tests/quick/00.hello/ref/sparc/linux/simple-timing-ruby/config.ini @@ -1,13 +1,22 @@ [root] type=Root children=system -dummy=0 +time_sync_enable=false +time_sync_period=100000000 +time_sync_spin_threshold=100000 [system] type=System -children=cpu physmem ruby -mem_mode=atomic +children=cpu dir_cntrl0 l1_cntrl0 physmem ruby +mem_mode=timing physmem=system.physmem +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 [system.cpu] type=TimingSimpleCPU @@ -32,8 +41,8 @@ progress_interval=0 system=system tracer=system.cpu.tracer workload=system.cpu.workload -dcache_port=system.ruby.network.topology.ext_links0.ext_node.sequencer.port[1] -icache_port=system.ruby.network.topology.ext_links0.ext_node.sequencer.port[0] +dcache_port=system.ruby.cpu_ruby_ports.port[1] +icache_port=system.ruby.cpu_ruby_ports.port[0] [system.cpu.dtb] type=SparcTLB @@ -54,7 +63,7 @@ egid=100 env= errout=cerr euid=100 -executable=tests/test-progs/hello/bin/sparc/linux/hello +executable=/dist/m5/regression/test-progs/hello/bin/sparc/linux/hello gid=100 input=cin max_stack_size=67108864 @@ -65,6 +74,59 @@ simpoint=0 system=system uid=100 +[system.dir_cntrl0] +type=Directory_Controller +children=directory memBuffer +buffer_size=0 +directory=system.dir_cntrl0.directory +directory_latency=12 +memBuffer=system.dir_cntrl0.memBuffer +number_of_TBEs=256 +recycle_latency=10 +transitions_per_cycle=32 +version=0 + +[system.dir_cntrl0.directory] +type=RubyDirectoryMemory +map_levels=4 +numa_high_bit=6 +size=134217728 +use_map=false +version=0 + +[system.dir_cntrl0.memBuffer] +type=RubyMemoryControl +bank_bit_0=8 +bank_busy_time=11 +bank_queue_size=12 +banks_per_rank=8 +basic_bus_busy_time=2 +dimm_bit_0=12 +dimms_per_channel=2 +mem_bus_cycle_multiplier=10 +mem_ctl_latency=12 +mem_fixed_delay=0 +mem_random_arbitrate=0 +rank_bit_0=11 +rank_rank_delay=1 +ranks_per_dimm=2 +read_write_delay=2 +refresh_period=1560 +tFaw=0 +version=0 + +[system.l1_cntrl0] +type=L1Cache_Controller +buffer_size=0 +cacheMemory=system.ruby.cpu_ruby_ports.dcache +cache_response_latency=12 +issue_latency=2 +number_of_TBEs=256 +recycle_latency=10 +sequencer=system.ruby.cpu_ruby_ports +transitions_per_cycle=32 +version=0 + [system.physmem] type=PhysicalMemory file= @@ -73,35 +135,48 @@ latency_var=0 null=false range=0:134217727 zero=false -port=system.ruby.network.topology.ext_links0.ext_node.sequencer.physMemPort +port=system.ruby.cpu_ruby_ports.physMemPort [system.ruby] type=RubySystem -children=debug network profiler tracer +children=cpu_ruby_ports network profiler tracer block_size_bytes=64 clock=1 -debug=system.ruby.debug mem_size=134217728 network=system.ruby.network +no_mem_vec=false profiler=system.ruby.profiler random_seed=1234 randomization=false stats_filename=ruby.stats -tech_nm=45 tracer=system.ruby.tracer -[system.ruby.debug] -type=RubyDebug -filter_string=none -output_filename=none -protocol_trace=false -start_time=1 -verbosity_string=none +[system.ruby.cpu_ruby_ports] +type=RubySequencer +children=dcache +access_phys_mem=true +dcache=system.ruby.cpu_ruby_ports.dcache +deadlock_threshold=500000 +icache=system.ruby.cpu_ruby_ports.dcache +max_outstanding_requests=16 +physmem=system.physmem +using_ruby_tester=false +version=0 +physMemPort=system.physmem.port[0] +port=system.cpu.icache_port system.cpu.dcache_port + +[system.ruby.cpu_ruby_ports.dcache] +type=RubyCache +assoc=2 +latency=3 +replacement_policy=PSEUDO_LRU +size=256 +start_index_bit=6 [system.ruby.network] type=SimpleNetwork children=topology -adaptive_routing=true +adaptive_routing=false buffer_size=0 control_msg_size=8 endpoint_bandwidth=10000 @@ -112,6 +187,7 @@ topology=system.ruby.network.topology [system.ruby.network.topology] type=Topology children=ext_links0 ext_links1 int_links0 int_links1 +description=Crossbar ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1 int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1 num_int_nodes=3 @@ -119,93 +195,20 @@ print_config=false [system.ruby.network.topology.ext_links0] type=ExtLink -children=ext_node bw_multiplier=64 -ext_node=system.ruby.network.topology.ext_links0.ext_node +ext_node=system.l1_cntrl0 int_node=0 latency=1 weight=1 -[system.ruby.network.topology.ext_links0.ext_node] -type=L1Cache_Controller -children=sequencer -buffer_size=0 -cacheMemory=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache -cache_response_latency=12 -issue_latency=2 -number_of_TBEs=256 -recycle_latency=10 -sequencer=system.ruby.network.topology.ext_links0.ext_node.sequencer -transitions_per_cycle=32 -version=0 - -[system.ruby.network.topology.ext_links0.ext_node.sequencer] -type=RubySequencer -children=icache -dcache=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache -deadlock_threshold=500000 -icache=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache -max_outstanding_requests=16 -physmem=system.physmem -using_ruby_tester=false -version=0 -physMemPort=system.physmem.port[0] -port=system.cpu.icache_port system.cpu.dcache_port - -[system.ruby.network.topology.ext_links0.ext_node.sequencer.icache] -type=RubyCache -assoc=2 -latency=3 -replacement_policy=PSEUDO_LRU -size=256 - [system.ruby.network.topology.ext_links1] type=ExtLink -children=ext_node bw_multiplier=64 -ext_node=system.ruby.network.topology.ext_links1.ext_node +ext_node=system.dir_cntrl0 int_node=1 latency=1 weight=1 -[system.ruby.network.topology.ext_links1.ext_node] -type=Directory_Controller -children=directory memBuffer -buffer_size=0 -directory=system.ruby.network.topology.ext_links1.ext_node.directory -directory_latency=12 -memBuffer=system.ruby.network.topology.ext_links1.ext_node.memBuffer -number_of_TBEs=256 -recycle_latency=10 -transitions_per_cycle=32 -version=0 - -[system.ruby.network.topology.ext_links1.ext_node.directory] -type=RubyDirectoryMemory -size=134217728 -version=0 - -[system.ruby.network.topology.ext_links1.ext_node.memBuffer] -type=RubyMemoryControl -bank_bit_0=8 -bank_busy_time=11 -bank_queue_size=12 -banks_per_rank=8 -basic_bus_busy_time=2 -dimm_bit_0=12 -dimms_per_channel=2 -mem_bus_cycle_multiplier=10 -mem_ctl_latency=12 -mem_fixed_delay=0 -mem_random_arbitrate=0 -rank_bit_0=11 -rank_rank_delay=1 -ranks_per_dimm=2 -read_write_delay=2 -refresh_period=1560 -tFaw=0 -version=0 - [system.ruby.network.topology.int_links0] type=IntLink bw_multiplier=16 diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-timing-ruby/ruby.stats b/tests/quick/00.hello/ref/sparc/linux/simple-timing-ruby/ruby.stats index 2464ac2ec..b11f8c789 100644 --- a/tests/quick/00.hello/ref/sparc/linux/simple-timing-ruby/ruby.stats +++ b/tests/quick/00.hello/ref/sparc/linux/simple-timing-ruby/ruby.stats @@ -4,16 +4,11 @@ RubySystem config: random_seed: 1234 randomization: 0 - tech_nm: 45 cycle_period: 1 block_size_bytes: 64 block_size_bits: 6 memory_size_bytes: 134217728 memory_size_bits: 27 -DirectoryMemory Global Config: - number of directory memories: 1 - total memory size bytes: 134217728 - total memory size bits: 27 Network Configuration --------------------- @@ -23,9 +18,9 @@ topology: virtual_net_0: active, ordered virtual_net_1: active, ordered virtual_net_2: active, ordered -virtual_net_3: inactive +virtual_net_3: active, ordered virtual_net_4: active, ordered -virtual_net_5: active, ordered +virtual_net_5: inactive virtual_net_6: inactive virtual_net_7: inactive virtual_net_8: inactive @@ -39,7 +34,7 @@ periodic_stats_period: 1000000 ================ End RubySystem Configuration Print ================ -Real time: Jan/21/2010 11:30:49 +Real time: Feb/07/2011 02:13:39 Profiler Stats -------------- @@ -48,31 +43,20 @@ Elapsed_time_in_minutes: 0.0166667 Elapsed_time_in_hours: 0.000277778 Elapsed_time_in_days: 1.15741e-05 -Virtual_time_in_seconds: 0.28 -Virtual_time_in_minutes: 0.00466667 -Virtual_time_in_hours: 7.77778e-05 -Virtual_time_in_days: 3.24074e-06 +Virtual_time_in_seconds: 0.34 +Virtual_time_in_minutes: 0.00566667 +Virtual_time_in_hours: 9.44444e-05 +Virtual_time_in_days: 3.93519e-06 Ruby_current_time: 253364 Ruby_start_time: 0 Ruby_cycles: 253364 -mbytes_resident: 34.3555 -mbytes_total: 34.5312 -resident_ratio: 0.995136 - -Total_misses: 0 -total_misses: 0 [ 0 ] -user_misses: 0 [ 0 ] -supervisor_misses: 0 [ 0 ] - -ruby_cycles_executed: 253365 [ 253365 ] - -transactions_started: 0 [ 0 ] -transactions_ended: 0 [ 0 ] -cycles_per_transaction: 0 [ 0 ] -misses_per_transaction: 0 [ 0 ] +mbytes_resident: 37.8555 +mbytes_total: 228.355 +resident_ratio: 0.165791 +ruby_cycles_executed: [ 253365 ] Busy Controller Counts: L1Cache-0:0 @@ -86,9 +70,27 @@ sequencer_requests_outstanding: [binsize: 1 max: 1 count: 6773 average: 1 | All Non-Zero Cycle Demand Cache Accesses ---------------------------------------- miss_latency: [binsize: 2 max: 371 count: 6772 average: 36.4135 | standard deviation: 69.5949 | 0 5483 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 2 4 2 2 10 2 309 224 133 323 144 9 3 1 0 0 11 11 1 16 4 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 1 25 14 6 15 3 1 1 1 0 0 1 1 0 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ] -miss_latency_1: [binsize: 2 max: 285 count: 5383 average: 26.3539 | standard deviation: 60.2129 | 0 4668 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 1 1 0 5 2 172 118 76 168 91 3 1 1 0 0 8 9 0 10 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 18 3 4 10 1 0 0 1 0 0 1 1 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_2: [binsize: 2 max: 285 count: 716 average: 98.7235 | standard deviation: 87.4535 | 0 321 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 3 1 2 3 0 110 62 31 116 36 4 1 0 0 0 1 0 1 6 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 5 2 2 3 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_3: [binsize: 2 max: 371 count: 673 average: 50.584 | standard deviation: 80.4924 | 0 494 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 27 44 26 39 17 2 1 0 0 0 2 2 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 9 0 2 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ] +miss_latency_IFETCH: [binsize: 2 max: 285 count: 5383 average: 26.3539 | standard deviation: 60.2129 | 0 4668 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 1 1 0 5 2 172 118 76 168 91 3 1 1 0 0 8 9 0 10 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 18 3 4 10 1 0 0 1 0 0 1 1 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_LD: [binsize: 2 max: 285 count: 716 average: 98.7235 | standard deviation: 87.4535 | 0 321 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 3 1 2 3 0 110 62 31 116 36 4 1 0 0 0 1 0 1 6 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 5 2 2 3 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_ST: [binsize: 2 max: 371 count: 673 average: 50.584 | standard deviation: 80.4924 | 0 494 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 27 44 26 39 17 2 1 0 0 0 2 2 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 9 0 2 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ] +miss_latency_L1Cache: [binsize: 1 max: 3 count: 5483 average: 3 | standard deviation: 0 | 0 0 0 5483 ] +miss_latency_Directory: [binsize: 2 max: 371 count: 1289 average: 178.544 | standard deviation: 22.1923 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 2 4 2 2 10 2 309 224 133 323 144 9 3 1 0 0 11 11 1 16 4 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 1 25 14 6 15 3 1 1 1 0 0 1 1 0 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ] +miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_wCC_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +imcomplete_wCC_Times: 0 +miss_latency_dir_issue_to_initial_request: [binsize: 1 max: 0 count: 1 average: 0 | standard deviation: 0 | 1 ] +miss_latency_dir_initial_forward_request: [binsize: 1 max: 0 count: 1 average: 0 | standard deviation: 0 | 1 ] +miss_latency_dir_forward_to_first_response: [binsize: 1 max: 0 count: 1 average: 0 | standard deviation: 0 | 1 ] +miss_latency_dir_first_response_to_completion: [binsize: 1 max: 159 count: 1 average: 159 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ] +imcomplete_dir_Times: 1288 +miss_latency_IFETCH_L1Cache: [binsize: 1 max: 3 count: 4668 average: 3 | standard deviation: 0 | 0 0 0 4668 ] +miss_latency_IFETCH_Directory: [binsize: 2 max: 285 count: 715 average: 178.824 | standard deviation: 21.9931 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 1 1 0 5 2 172 118 76 168 91 3 1 1 0 0 8 9 0 10 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 18 3 4 10 1 0 0 1 0 0 1 1 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_LD_L1Cache: [binsize: 1 max: 3 count: 321 average: 3 | standard deviation: 0 | 0 0 0 321 ] +miss_latency_LD_Directory: [binsize: 2 max: 285 count: 395 average: 176.514 | standard deviation: 18.6332 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 3 1 2 3 0 110 62 31 116 36 4 1 0 0 0 1 0 1 6 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 5 2 2 3 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_ST_L1Cache: [binsize: 1 max: 3 count: 494 average: 3 | standard deviation: 0 | 0 0 0 494 ] +miss_latency_ST_Directory: [binsize: 2 max: 371 count: 179 average: 181.905 | standard deviation: 28.882 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 27 44 26 39 17 2 1 0 0 0 2 2 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 9 0 2 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ] All Non-Zero Cycle SW Prefetch Requests ------------------------------------ @@ -120,25 +122,31 @@ Resource Usage page_size: 4096 user_time: 0 system_time: 0 -page_reclaims: 7494 -page_faults: 2200 +page_reclaims: 11225 +page_faults: 3 swaps: 0 -block_inputs: 0 -block_outputs: 0 +block_inputs: 1280 +block_outputs: 64 Network Stats ------------- +total_msg_count_Control: 3867 30936 +total_msg_count_Data: 3855 277560 +total_msg_count_Response_Data: 3867 278424 +total_msg_count_Writeback_Control: 3855 30840 +total_msgs: 15444 total_bytes: 617760 + switch_0_inlinks: 2 switch_0_outlinks: 2 links_utilized_percent_switch_0: 0.158621 links_utilized_percent_switch_0_link_0: 0.0635745 bw: 640000 base_latency: 1 links_utilized_percent_switch_0_link_1: 0.253667 bw: 160000 base_latency: 1 - outgoing_messages_switch_0_link_0_Response_Data: 1289 92808 [ 0 1289 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_0_Writeback_Control: 1285 10280 [ 0 0 1285 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Control: 1289 10312 [ 1289 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Data: 1285 92520 [ 1285 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_0_Response_Data: 1289 92808 [ 0 0 0 0 1289 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_0_Writeback_Control: 1285 10280 [ 0 0 0 1285 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Control: 1289 10312 [ 0 0 1289 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Data: 1285 92520 [ 0 0 1285 0 0 0 0 0 0 0 ] base_latency: 1 switch_1_inlinks: 2 switch_1_outlinks: 2 @@ -146,10 +154,10 @@ links_utilized_percent_switch_1: 0.158857 links_utilized_percent_switch_1_link_0: 0.0634167 bw: 640000 base_latency: 1 links_utilized_percent_switch_1_link_1: 0.254298 bw: 160000 base_latency: 1 - outgoing_messages_switch_1_link_0_Control: 1289 10312 [ 1289 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_0_Data: 1285 92520 [ 1285 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_Response_Data: 1289 92808 [ 0 1289 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_Writeback_Control: 1285 10280 [ 0 0 1285 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_Control: 1289 10312 [ 0 0 1289 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_Data: 1285 92520 [ 0 0 1285 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Response_Data: 1289 92808 [ 0 0 0 0 1289 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Writeback_Control: 1285 10280 [ 0 0 0 1285 0 0 0 0 0 0 ] base_latency: 1 switch_2_inlinks: 2 switch_2_outlinks: 2 @@ -157,63 +165,64 @@ links_utilized_percent_switch_2: 0.253982 links_utilized_percent_switch_2_link_0: 0.254298 bw: 160000 base_latency: 1 links_utilized_percent_switch_2_link_1: 0.253667 bw: 160000 base_latency: 1 - outgoing_messages_switch_2_link_0_Response_Data: 1289 92808 [ 0 1289 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_0_Writeback_Control: 1285 10280 [ 0 0 1285 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_1_Control: 1289 10312 [ 1289 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_1_Data: 1285 92520 [ 1285 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_0_Response_Data: 1289 92808 [ 0 0 0 0 1289 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_0_Writeback_Control: 1285 10280 [ 0 0 0 1285 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Control: 1289 10312 [ 0 0 1289 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Data: 1285 92520 [ 0 0 1285 0 0 0 0 0 0 0 ] base_latency: 1 -Cache Stats: system.ruby.network.topology.ext_links0.ext_node.sequencer.icache - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_misses: 1289 - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_demand_misses: 1289 - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_hw_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_misses_per_transaction: inf +Cache Stats: system.ruby.cpu_ruby_ports.dcache + system.ruby.cpu_ruby_ports.dcache_total_misses: 1289 + system.ruby.cpu_ruby_ports.dcache_total_demand_misses: 1289 + system.ruby.cpu_ruby_ports.dcache_total_prefetches: 0 + system.ruby.cpu_ruby_ports.dcache_total_sw_prefetches: 0 + system.ruby.cpu_ruby_ports.dcache_total_hw_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_type_LD: 30.6439% - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_type_ST: 13.8867% - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_type_IFETCH: 55.4694% + system.ruby.cpu_ruby_ports.dcache_request_type_LD: 30.6439% + system.ruby.cpu_ruby_ports.dcache_request_type_ST: 13.8867% + system.ruby.cpu_ruby_ports.dcache_request_type_IFETCH: 55.4694% - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_access_mode_type_SupervisorMode: 1289 100% - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_size: [binsize: 1 max: 8 count: 1289 average: 5.1249 | standard deviation: 2.01759 | 0 50 2 0 836 0 0 0 401 ] + system.ruby.cpu_ruby_ports.dcache_access_mode_type_SupervisorMode: 1289 100% - --- L1Cache 0 --- + --- L1Cache --- - Event Counts - -Load 716 -Ifetch 5383 -Store 673 -Data 1289 -Fwd_GETX 0 -Inv 0 -Replacement 1285 -Writeback_Ack 1285 -Writeback_Nack 0 +Load [716 ] 716 +Ifetch [5383 ] 5383 +Store [673 ] 673 +Data [1289 ] 1289 +Fwd_GETX [0 ] 0 +Inv [0 ] 0 +Replacement [1285 ] 1285 +Writeback_Ack [1285 ] 1285 +Writeback_Nack [0 ] 0 - Transitions - -I Load 395 -I Ifetch 715 -I Store 179 -I Inv 0 <-- -I Replacement 0 <-- +I Load [395 ] 395 +I Ifetch [715 ] 715 +I Store [179 ] 179 +I Inv [0 ] 0 +I Replacement [0 ] 0 + +II Writeback_Nack [0 ] 0 -II Writeback_Nack 0 <-- +M Load [321 ] 321 +M Ifetch [4668 ] 4668 +M Store [494 ] 494 +M Fwd_GETX [0 ] 0 +M Inv [0 ] 0 +M Replacement [1285 ] 1285 -M Load 321 -M Ifetch 4668 -M Store 494 -M Fwd_GETX 0 <-- -M Inv 0 <-- -M Replacement 1285 +MI Fwd_GETX [0 ] 0 +MI Inv [0 ] 0 +MI Writeback_Ack [1285 ] 1285 +MI Writeback_Nack [0 ] 0 -MI Fwd_GETX 0 <-- -MI Inv 0 <-- -MI Writeback_Ack 1285 +MII Fwd_GETX [0 ] 0 -IS Data 1110 +IS Data [1110 ] 1110 -IM Data 179 +IM Data [179 ] 179 -Memory controller: system.ruby.network.topology.ext_links1.ext_node.memBuffer: +Memory controller: system.dir_cntrl0.memBuffer: memory_total_requests: 2574 memory_reads: 1289 memory_writes: 1285 @@ -233,70 +242,69 @@ Memory controller: system.ruby.network.topology.ext_links1.ext_node.memBuffer: memory_stalls_for_read_read_turnaround: 0 accesses_per_bank: 166 40 36 48 109 42 63 241 50 34 16 26 60 64 38 46 30 88 202 144 40 58 22 20 60 120 136 125 84 134 166 66 - --- Directory 0 --- + --- Directory --- - Event Counts - -GETX 1289 -GETS 0 -PUTX 1285 -PUTX_NotOwner 0 -DMA_READ 0 -DMA_WRITE 0 -Memory_Data 1289 -Memory_Ack 1285 +GETX [1289 ] 1289 +GETS [0 ] 0 +PUTX [1285 ] 1285 +PUTX_NotOwner [0 ] 0 +DMA_READ [0 ] 0 +DMA_WRITE [0 ] 0 +Memory_Data [1289 ] 1289 +Memory_Ack [1285 ] 1285 - Transitions - -I GETX 1289 -I PUTX_NotOwner 0 <-- -I DMA_READ 0 <-- -I DMA_WRITE 0 <-- - -M GETX 0 <-- -M PUTX 1285 -M PUTX_NotOwner 0 <-- -M DMA_READ 0 <-- -M DMA_WRITE 0 <-- - -M_DRD GETX 0 <-- -M_DRD PUTX 0 <-- - -M_DWR GETX 0 <-- -M_DWR PUTX 0 <-- - -M_DWRI GETX 0 <-- -M_DWRI Memory_Ack 0 <-- - -M_DRDI GETX 0 <-- -M_DRDI Memory_Ack 0 <-- - -IM GETX 0 <-- -IM GETS 0 <-- -IM PUTX 0 <-- -IM PUTX_NotOwner 0 <-- -IM DMA_READ 0 <-- -IM DMA_WRITE 0 <-- -IM Memory_Data 1289 - -MI GETX 0 <-- -MI GETS 0 <-- -MI PUTX 0 <-- -MI PUTX_NotOwner 0 <-- -MI DMA_READ 0 <-- -MI DMA_WRITE 0 <-- -MI Memory_Ack 1285 - -ID GETX 0 <-- -ID GETS 0 <-- -ID PUTX 0 <-- -ID PUTX_NotOwner 0 <-- -ID DMA_READ 0 <-- -ID DMA_WRITE 0 <-- -ID Memory_Data 0 <-- - -ID_W GETX 0 <-- -ID_W GETS 0 <-- -ID_W PUTX 0 <-- -ID_W PUTX_NotOwner 0 <-- -ID_W DMA_READ 0 <-- -ID_W DMA_WRITE 0 <-- -ID_W Memory_Ack 0 <-- - +I GETX [1289 ] 1289 +I PUTX_NotOwner [0 ] 0 +I DMA_READ [0 ] 0 +I DMA_WRITE [0 ] 0 + +M GETX [0 ] 0 +M PUTX [1285 ] 1285 +M PUTX_NotOwner [0 ] 0 +M DMA_READ [0 ] 0 +M DMA_WRITE [0 ] 0 + +M_DRD GETX [0 ] 0 +M_DRD PUTX [0 ] 0 + +M_DWR GETX [0 ] 0 +M_DWR PUTX [0 ] 0 + +M_DWRI GETX [0 ] 0 +M_DWRI Memory_Ack [0 ] 0 + +M_DRDI GETX [0 ] 0 +M_DRDI Memory_Ack [0 ] 0 + +IM GETX [0 ] 0 +IM GETS [0 ] 0 +IM PUTX [0 ] 0 +IM PUTX_NotOwner [0 ] 0 +IM DMA_READ [0 ] 0 +IM DMA_WRITE [0 ] 0 +IM Memory_Data [1289 ] 1289 + +MI GETX [0 ] 0 +MI GETS [0 ] 0 +MI PUTX [0 ] 0 +MI PUTX_NotOwner [0 ] 0 +MI DMA_READ [0 ] 0 +MI DMA_WRITE [0 ] 0 +MI Memory_Ack [1285 ] 1285 + +ID GETX [0 ] 0 +ID GETS [0 ] 0 +ID PUTX [0 ] 0 +ID PUTX_NotOwner [0 ] 0 +ID DMA_READ [0 ] 0 +ID DMA_WRITE [0 ] 0 +ID Memory_Data [0 ] 0 + +ID_W GETX [0 ] 0 +ID_W GETS [0 ] 0 +ID_W PUTX [0 ] 0 +ID_W PUTX_NotOwner [0 ] 0 +ID_W DMA_READ [0 ] 0 +ID_W DMA_WRITE [0 ] 0 +ID_W Memory_Ack
\ No newline at end of file diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-timing-ruby/simout b/tests/quick/00.hello/ref/sparc/linux/simple-timing-ruby/simout index e4e5995ba..c97aaa4c9 100755 --- a/tests/quick/00.hello/ref/sparc/linux/simple-timing-ruby/simout +++ b/tests/quick/00.hello/ref/sparc/linux/simple-timing-ruby/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jan 21 2010 11:29:25 -M5 revision a2fac757fb31+ 6860+ default qtip brad/rubycfg_orion_update tip -M5 started Jan 21 2010 11:30:48 -M5 executing on svvint07 +M5 compiled Feb 7 2011 02:13:30 +M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip +M5 started Feb 7 2011 02:13:38 +M5 executing on burrito command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/00.hello/sparc/linux/simple-timing-ruby -re tests/run.py build/SPARC_SE/tests/fast/quick/00.hello/sparc/linux/simple-timing-ruby Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt b/tests/quick/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt index aa77d6897..5961a0ac8 100644 --- a/tests/quick/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt +++ b/tests/quick/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 59331 # Simulator instruction rate (inst/s) -host_mem_usage 347024 # Number of bytes of host memory used -host_seconds 0.09 # Real time elapsed on the host -host_tick_rate 2815062 # Simulator tick rate (ticks/s) +host_inst_rate 26190 # Simulator instruction rate (inst/s) +host_mem_usage 233840 # Number of bytes of host memory used +host_seconds 0.20 # Real time elapsed on the host +host_tick_rate 1241276 # Simulator tick rate (ticks/s) sim_freq 1000000000 # Frequency of simulated ticks sim_insts 5340 # Number of instructions simulated sim_seconds 0.000253 # Number of seconds simulated @@ -11,8 +11,24 @@ sim_ticks 253364 # Nu system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.numCycles 253364 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.num_busy_cycles 253364 # Number of busy cycles +system.cpu.num_conditional_control_insts 0 # number of instructions that are conditional controls +system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses +system.cpu.num_fp_insts 0 # number of float instructions +system.cpu.num_fp_register_reads 0 # number of times the floating registers were read +system.cpu.num_fp_register_writes 0 # number of times the floating registers were written +system.cpu.num_func_calls 0 # number of times a function call or return occured +system.cpu.num_idle_cycles 0 # Number of idle cycles system.cpu.num_insts 5340 # Number of instructions executed -system.cpu.num_refs 1402 # Number of memory references +system.cpu.num_int_alu_accesses 4517 # Number of integer alu accesses +system.cpu.num_int_insts 4517 # number of integer instructions +system.cpu.num_int_register_reads 10620 # number of times the integer registers were read +system.cpu.num_int_register_writes 4858 # number of times the integer registers were written +system.cpu.num_load_insts 724 # Number of load instructions +system.cpu.num_mem_refs 1402 # number of memory refs +system.cpu.num_store_insts 678 # Number of store instructions system.cpu.workload.PROG:num_syscalls 11 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-timing/config.ini b/tests/quick/00.hello/ref/sparc/linux/simple-timing/config.ini index 35f8386c3..d416eae87 100644 --- a/tests/quick/00.hello/ref/sparc/linux/simple-timing/config.ini +++ b/tests/quick/00.hello/ref/sparc/linux/simple-timing/config.ini @@ -1,13 +1,22 @@ [root] type=Root children=system -dummy=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem mem_mode=atomic physmem=system.physmem +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 [system.cpu] type=TimingSimpleCPU diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-timing/simout b/tests/quick/00.hello/ref/sparc/linux/simple-timing/simout index 9b5f99faf..1b1015662 100755 --- a/tests/quick/00.hello/ref/sparc/linux/simple-timing/simout +++ b/tests/quick/00.hello/ref/sparc/linux/simple-timing/simout @@ -1,5 +1,3 @@ -Redirecting stdout to build/SPARC_SE/tests/opt/quick/00.hello/sparc/linux/simple-timing/simout -Redirecting stderr to build/SPARC_SE/tests/opt/quick/00.hello/sparc/linux/simple-timing/simerr M5 Simulator System Copyright (c) 2001-2008 @@ -7,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Aug 26 2010 13:03:41 -M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix -M5 started Aug 26 2010 13:05:08 -M5 executing on zizzer -command line: build/SPARC_SE/m5.opt -d build/SPARC_SE/tests/opt/quick/00.hello/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/opt/quick/00.hello/sparc/linux/simple-timing +M5 compiled Feb 7 2011 02:13:30 +M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip +M5 started Feb 7 2011 02:14:00 +M5 executing on burrito +command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/00.hello/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/fast/quick/00.hello/sparc/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Hello World!Exiting @ tick 28206000 because target called exit() diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-timing/stats.txt b/tests/quick/00.hello/ref/sparc/linux/simple-timing/stats.txt index 49d0076df..d21947f29 100644 --- a/tests/quick/00.hello/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/quick/00.hello/ref/sparc/linux/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 369934 # Simulator instruction rate (inst/s) -host_mem_usage 207380 # Number of bytes of host memory used -host_seconds 0.01 # Real time elapsed on the host -host_tick_rate 1923223783 # Simulator tick rate (ticks/s) +host_inst_rate 87383 # Simulator instruction rate (inst/s) +host_mem_usage 223480 # Number of bytes of host memory used +host_seconds 0.06 # Real time elapsed on the host +host_tick_rate 459485360 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 5340 # Number of instructions simulated sim_seconds 0.000028 # Number of seconds simulated @@ -195,8 +195,24 @@ system.cpu.l2cache.warmup_cycle 0 # Cy system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.numCycles 56412 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.num_busy_cycles 56412 # Number of busy cycles +system.cpu.num_conditional_control_insts 0 # number of instructions that are conditional controls +system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses +system.cpu.num_fp_insts 0 # number of float instructions +system.cpu.num_fp_register_reads 0 # number of times the floating registers were read +system.cpu.num_fp_register_writes 0 # number of times the floating registers were written +system.cpu.num_func_calls 0 # number of times a function call or return occured +system.cpu.num_idle_cycles 0 # Number of idle cycles system.cpu.num_insts 5340 # Number of instructions executed -system.cpu.num_refs 1402 # Number of memory references +system.cpu.num_int_alu_accesses 4517 # Number of integer alu accesses +system.cpu.num_int_insts 4517 # number of integer instructions +system.cpu.num_int_register_reads 10620 # number of times the integer registers were read +system.cpu.num_int_register_writes 4858 # number of times the integer registers were written +system.cpu.num_load_insts 724 # Number of load instructions +system.cpu.num_mem_refs 1402 # number of memory refs +system.cpu.num_store_insts 678 # Number of store instructions system.cpu.workload.PROG:num_syscalls 11 # Number of system calls ---------- End Simulation Statistics ---------- |