diff options
Diffstat (limited to 'tests/quick/00.hello/ref/sparc')
10 files changed, 320 insertions, 852 deletions
diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-atomic-ruby/config.ini b/tests/quick/00.hello/ref/sparc/linux/simple-atomic-ruby/config.ini deleted file mode 100644 index aa19d3d6d..000000000 --- a/tests/quick/00.hello/ref/sparc/linux/simple-atomic-ruby/config.ini +++ /dev/null @@ -1,97 +0,0 @@ -[root] -type=Root -children=system -dummy=0 - -[system] -type=System -children=cpu membus physmem -mem_mode=atomic -physmem=system.physmem - -[system.cpu] -type=AtomicSimpleCPU -children=dtb itb tracer workload -checker=Null -clock=500 -cpu_id=0 -defer_registration=false -do_checkpoint_insts=true -do_statistics_insts=true -dtb=system.cpu.dtb -function_trace=false -function_trace_start=0 -itb=system.cpu.itb -max_insts_all_threads=0 -max_insts_any_thread=0 -max_loads_all_threads=0 -max_loads_any_thread=0 -numThreads=1 -phase=0 -progress_interval=0 -simulate_data_stalls=false -simulate_inst_stalls=false -system=system -tracer=system.cpu.tracer -width=1 -workload=system.cpu.workload -dcache_port=system.membus.port[2] -icache_port=system.membus.port[1] - -[system.cpu.dtb] -type=SparcTLB -size=64 - -[system.cpu.itb] -type=SparcTLB -size=64 - -[system.cpu.tracer] -type=ExeTracer - -[system.cpu.workload] -type=LiveProcess -cmd=hello -cwd= -egid=100 -env= -errout=cerr -euid=100 -executable=/dist/m5/regression/test-progs/hello/bin/sparc/linux/hello -gid=100 -input=cin -max_stack_size=67108864 -output=cout -pid=100 -ppid=99 -simpoint=0 -system=system -uid=100 - -[system.membus] -type=Bus -block_size=64 -bus_id=0 -clock=1000 -header_cycles=1 -responder_set=false -width=64 -port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port - -[system.physmem] -type=RubyMemory -clock=1 -config_file=build/SPARC_SE/tests/fast/quick/00.hello/sparc/linux/simple-atomic-ruby/ruby.config -debug=false -debug_file=ruby.debug -file= -latency=30000 -latency_var=0 -null=false -num_cpus=1 -phase=0 -range=0:134217727 -stats_file=ruby.stats -zero=false -port=system.membus.port[0] - diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-atomic-ruby/ruby.stats b/tests/quick/00.hello/ref/sparc/linux/simple-atomic-ruby/ruby.stats deleted file mode 100644 index 15198ed2d..000000000 --- a/tests/quick/00.hello/ref/sparc/linux/simple-atomic-ruby/ruby.stats +++ /dev/null @@ -1,382 +0,0 @@ - -================ Begin RubySystem Configuration Print ================ - -RubySystem config: - random_seed: 539659 - randomization: 0 - tech_nm: 45 - freq_mhz: 3000 - block_size_bytes: 64 - block_size_bits: 6 - memory_size_bytes: 1073741824 - memory_size_bits: 30 -DMA_Controller config: DMAController_0 - version: 0 - buffer_size: 32 - dma_sequencer: DMASequencer_0 - number_of_TBEs: 128 - transitions_per_cycle: 32 -Directory_Controller config: DirectoryController_0 - version: 0 - buffer_size: 32 - directory_latency: 6 - directory_name: DirectoryMemory_0 - memory_controller_name: MemoryControl_0 - memory_latency: 158 - number_of_TBEs: 128 - recycle_latency: 10 - to_mem_ctrl_latency: 1 - transitions_per_cycle: 32 -L1Cache_Controller config: L1CacheController_0 - version: 0 - buffer_size: 32 - cache: l1u_0 - cache_response_latency: 12 - issue_latency: 2 - number_of_TBEs: 128 - sequencer: Sequencer_0 - transitions_per_cycle: 32 -Cache config: l1u_0 - controller: L1CacheController_0 - cache_associativity: 8 - num_cache_sets_bits: 2 - num_cache_sets: 4 - cache_set_size_bytes: 256 - cache_set_size_Kbytes: 0.25 - cache_set_size_Mbytes: 0.000244141 - cache_size_bytes: 2048 - cache_size_Kbytes: 2 - cache_size_Mbytes: 0.00195312 -DirectoryMemory Global Config: - number of directory memories: 1 - total memory size bytes: 1073741824 - total memory size bits: 30 -DirectoryMemory module config: DirectoryMemory_0 - controller: DirectoryController_0 - version: 0 - memory_bits: 30 - memory_size_bytes: 1073741824 - memory_size_Kbytes: 1.04858e+06 - memory_size_Mbytes: 1024 - memory_size_Gbytes: 1 -Seqeuncer config: Sequencer_0 - controller: L1CacheController_0 - version: 0 - max_outstanding_requests: 16 - deadlock_threshold: 500000 - -Network Configuration ---------------------- -network: SIMPLE_NETWORK -topology: theTopology - -virtual_net_0: active, ordered -virtual_net_1: active, ordered -virtual_net_2: active, ordered -virtual_net_3: inactive -virtual_net_4: active, ordered -virtual_net_5: active, ordered - ---- Begin Topology Print --- - -Topology print ONLY indicates the _NETWORK_ latency between two machines -It does NOT include the latency within the machines - -L1Cache-0 Network Latencies - L1Cache-0 -> Directory-0 net_lat: 7 - L1Cache-0 -> DMA-0 net_lat: 7 - -Directory-0 Network Latencies - Directory-0 -> L1Cache-0 net_lat: 7 - Directory-0 -> DMA-0 net_lat: 7 - -DMA-0 Network Latencies - DMA-0 -> L1Cache-0 net_lat: 7 - DMA-0 -> Directory-0 net_lat: 7 - ---- End Topology Print --- - -Profiler Configuration ----------------------- -periodic_stats_period: 1000000 - -================ End RubySystem Configuration Print ================ - - -Real time: Jul/06/2009 11:11:24 - -Profiler Stats --------------- -Elapsed_time_in_seconds: 0 -Elapsed_time_in_minutes: 0 -Elapsed_time_in_hours: 0 -Elapsed_time_in_days: 0 - -Virtual_time_in_seconds: 0.23 -Virtual_time_in_minutes: 0.00383333 -Virtual_time_in_hours: 6.38889e-05 -Virtual_time_in_days: 6.38889e-05 - -Ruby_current_time: 2701001 -Ruby_start_time: 1 -Ruby_cycles: 2701000 - -mbytes_resident: 144.91 -mbytes_total: 1330.19 -resident_ratio: 0.108942 - -Total_misses: 0 -total_misses: 0 [ 0 ] -user_misses: 0 [ 0 ] -supervisor_misses: 0 [ 0 ] - -instruction_executed: 1 [ 1 ] -ruby_cycles_executed: 2701001 [ 2701001 ] -cycles_per_instruction: 2.701e+06 [ 2.701e+06 ] -misses_per_thousand_instructions: 0 [ 0 ] - -transactions_started: 0 [ 0 ] -transactions_ended: 0 [ 0 ] -instructions_per_transaction: 0 [ 0 ] -cycles_per_transaction: 0 [ 0 ] -misses_per_transaction: 0 [ 0 ] - -L1D_cache cache stats: - L1D_cache_total_misses: 0 - L1D_cache_total_demand_misses: 0 - L1D_cache_total_prefetches: 0 - L1D_cache_total_sw_prefetches: 0 - L1D_cache_total_hw_prefetches: 0 - L1D_cache_misses_per_transaction: 0 - L1D_cache_misses_per_instruction: 0 - L1D_cache_instructions_per_misses: NaN - - L1D_cache_request_size: [binsize: log2 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - -L1I_cache cache stats: - L1I_cache_total_misses: 0 - L1I_cache_total_demand_misses: 0 - L1I_cache_total_prefetches: 0 - L1I_cache_total_sw_prefetches: 0 - L1I_cache_total_hw_prefetches: 0 - L1I_cache_misses_per_transaction: 0 - L1I_cache_misses_per_instruction: 0 - L1I_cache_instructions_per_misses: NaN - - L1I_cache_request_size: [binsize: log2 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - -L2_cache cache stats: - L2_cache_total_misses: 0 - L2_cache_total_demand_misses: 0 - L2_cache_total_prefetches: 0 - L2_cache_total_sw_prefetches: 0 - L2_cache_total_hw_prefetches: 0 - L2_cache_misses_per_transaction: 0 - L2_cache_misses_per_instruction: 0 - L2_cache_instructions_per_misses: NaN - - L2_cache_request_size: [binsize: log2 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - - -Busy Controller Counts: -L1Cache-0:0 -Directory-0:0 -DMA-0:0 - -Busy Bank Count:0 - -L1TBE_usage: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] -L2TBE_usage: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] -StopTable_usage: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] -sequencer_requests_outstanding: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] -store_buffer_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] -unique_blocks_in_store_buffer: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - -All Non-Zero Cycle Demand Cache Accesses ----------------------------------------- -miss_latency: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] -miss_latency_L2Miss: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - -All Non-Zero Cycle SW Prefetch Requests ------------------------------------- -prefetch_latency: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] -prefetch_latency_L2Miss:[binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] -multicast_retries: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] -gets_mask_prediction_count: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] -getx_mask_prediction_count: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] -explicit_training_mask: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - -Request vs. RubySystem State Profile --------------------------------- - - -filter_action: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - -Message Delayed Cycles ----------------------- -Total_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] -Total_nonPF_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - virtual_network_0_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - virtual_network_1_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - virtual_network_2_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - virtual_network_3_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - virtual_network_4_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - virtual_network_5_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - -Resource Usage --------------- -page_size: 4096 -user_time: 0 -system_time: 0 -page_reclaims: 37843 -page_faults: 0 -swaps: 0 -block_inputs: 0 -block_outputs: 40 - -Network Stats -------------- - -switch_0_inlinks: 2 -switch_0_outlinks: 2 -links_utilized_percent_switch_0: 0 - links_utilized_percent_switch_0_link_0: 0 bw: 640000 base_latency: 1 - links_utilized_percent_switch_0_link_1: 0 bw: 160000 base_latency: 1 - - -switch_1_inlinks: 2 -switch_1_outlinks: 2 -links_utilized_percent_switch_1: 0 - links_utilized_percent_switch_1_link_0: 0 bw: 640000 base_latency: 1 - links_utilized_percent_switch_1_link_1: 0 bw: 160000 base_latency: 1 - - -switch_2_inlinks: 2 -switch_2_outlinks: 2 -links_utilized_percent_switch_2: 0 - links_utilized_percent_switch_2_link_0: 0 bw: 640000 base_latency: 1 - links_utilized_percent_switch_2_link_1: 0 bw: 160000 base_latency: 1 - - -switch_3_inlinks: 3 -switch_3_outlinks: 3 -links_utilized_percent_switch_3: 0 - links_utilized_percent_switch_3_link_0: 0 bw: 160000 base_latency: 1 - links_utilized_percent_switch_3_link_1: 0 bw: 160000 base_latency: 1 - links_utilized_percent_switch_3_link_2: 0 bw: 160000 base_latency: 1 - - - --- DMA --- - - Event Counts - -ReadRequest 0 -WriteRequest 0 -Data 0 -Ack 0 - - - Transitions - -READY ReadRequest 0 <-- -READY WriteRequest 0 <-- - -BUSY_RD Data 0 <-- - -BUSY_WR Ack 0 <-- - - --- Directory --- - - Event Counts - -GETX 0 -GETS 0 -PUTX 0 -PUTX_NotOwner 0 -DMA_READ 0 -DMA_WRITE 0 -Memory_Data 0 -Memory_Ack 0 - - - Transitions - -I GETX 0 <-- -I PUTX_NotOwner 0 <-- -I DMA_READ 0 <-- -I DMA_WRITE 0 <-- - -M GETX 0 <-- -M PUTX 0 <-- -M PUTX_NotOwner 0 <-- -M DMA_READ 0 <-- -M DMA_WRITE 0 <-- - -M_DRD GETX 0 <-- -M_DRD PUTX 0 <-- - -M_DWR GETX 0 <-- -M_DWR PUTX 0 <-- - -M_DWRI Memory_Ack 0 <-- - -IM GETX 0 <-- -IM GETS 0 <-- -IM PUTX 0 <-- -IM PUTX_NotOwner 0 <-- -IM DMA_READ 0 <-- -IM DMA_WRITE 0 <-- -IM Memory_Data 0 <-- - -MI GETX 0 <-- -MI GETS 0 <-- -MI PUTX 0 <-- -MI PUTX_NotOwner 0 <-- -MI DMA_READ 0 <-- -MI DMA_WRITE 0 <-- -MI Memory_Ack 0 <-- - -ID GETX 0 <-- -ID GETS 0 <-- -ID PUTX 0 <-- -ID PUTX_NotOwner 0 <-- -ID DMA_READ 0 <-- -ID DMA_WRITE 0 <-- -ID Memory_Data 0 <-- - -ID_W GETX 0 <-- -ID_W GETS 0 <-- -ID_W PUTX 0 <-- -ID_W PUTX_NotOwner 0 <-- -ID_W DMA_READ 0 <-- -ID_W DMA_WRITE 0 <-- -ID_W Memory_Ack 0 <-- - - --- L1Cache --- - - Event Counts - -Load 0 -Ifetch 0 -Store 0 -Data 0 -Fwd_GETX 0 -Inv 0 -Replacement 0 -Writeback_Ack 0 -Writeback_Nack 0 - - - Transitions - -I Load 0 <-- -I Ifetch 0 <-- -I Store 0 <-- -I Inv 0 <-- -I Replacement 0 <-- - -II Writeback_Nack 0 <-- - -M Load 0 <-- -M Ifetch 0 <-- -M Store 0 <-- -M Fwd_GETX 0 <-- -M Inv 0 <-- -M Replacement 0 <-- - -MI Fwd_GETX 0 <-- -MI Inv 0 <-- -MI Writeback_Ack 0 <-- - -IS Data 0 <-- - -IM Data 0 <-- - diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-atomic-ruby/simerr b/tests/quick/00.hello/ref/sparc/linux/simple-atomic-ruby/simerr deleted file mode 100755 index 187d1a0ac..000000000 --- a/tests/quick/00.hello/ref/sparc/linux/simple-atomic-ruby/simerr +++ /dev/null @@ -1,23 +0,0 @@ -["-r", "tests/configs/../../src/mem/ruby/config/MI_example-homogeneous.rb", "-p", "1", "-m", "1", "-s", "1024"] -print config: 1 -Creating new MessageBuffer for 0 0 -Creating new MessageBuffer for 0 1 -Creating new MessageBuffer for 0 2 -Creating new MessageBuffer for 0 3 -Creating new MessageBuffer for 0 4 -Creating new MessageBuffer for 0 5 -Creating new MessageBuffer for 1 0 -Creating new MessageBuffer for 1 1 -Creating new MessageBuffer for 1 2 -Creating new MessageBuffer for 1 3 -Creating new MessageBuffer for 1 4 -Creating new MessageBuffer for 1 5 -Creating new MessageBuffer for 2 0 -Creating new MessageBuffer for 2 1 -Creating new MessageBuffer for 2 2 -Creating new MessageBuffer for 2 3 -Creating new MessageBuffer for 2 4 -Creating new MessageBuffer for 2 5 -warn: Sockets disabled, not accepting gdb connections -For more information see: http://www.m5sim.org/warn/d946bea6 -hack: be nice to actually delete the event here diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-atomic-ruby/simout b/tests/quick/00.hello/ref/sparc/linux/simple-atomic-ruby/simout deleted file mode 100755 index 38357eb8b..000000000 --- a/tests/quick/00.hello/ref/sparc/linux/simple-atomic-ruby/simout +++ /dev/null @@ -1,16 +0,0 @@ -M5 Simulator System - -Copyright (c) 2001-2008 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled Jul 6 2009 11:07:18 -M5 revision d3635cac686a 6289 default ruby_refs.diff qtip tip -M5 started Jul 6 2009 11:11:24 -M5 executing on maize -command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/00.hello/sparc/linux/simple-atomic-ruby -re tests/run.py build/SPARC_SE/tests/fast/quick/00.hello/sparc/linux/simple-atomic-ruby -Global frequency set at 1000000000000 ticks per second - Debug: Adding to filter: 'q' (Queue) -info: Entering event queue @ 0. Starting simulation... -Hello World!Exiting @ tick 2701000 because target called exit() diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-atomic-ruby/stats.txt b/tests/quick/00.hello/ref/sparc/linux/simple-atomic-ruby/stats.txt deleted file mode 100644 index 8137d6a2a..000000000 --- a/tests/quick/00.hello/ref/sparc/linux/simple-atomic-ruby/stats.txt +++ /dev/null @@ -1,18 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -host_inst_rate 49084 # Simulator instruction rate (inst/s) -host_mem_usage 201040 # Number of bytes of host memory used -host_seconds 0.11 # Real time elapsed on the host -host_tick_rate 24773225 # Simulator tick rate (ticks/s) -sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 5340 # Number of instructions simulated -sim_seconds 0.000003 # Number of seconds simulated -sim_ticks 2701000 # Number of ticks simulated -system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 5403 # number of cpu cycles simulated -system.cpu.num_insts 5340 # Number of instructions executed -system.cpu.num_refs 1402 # Number of memory references -system.cpu.workload.PROG:num_syscalls 11 # Number of system calls - ----------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-timing-ruby/config.ini b/tests/quick/00.hello/ref/sparc/linux/simple-timing-ruby/config.ini index 780244072..eb5199f6d 100644 --- a/tests/quick/00.hello/ref/sparc/linux/simple-timing-ruby/config.ini +++ b/tests/quick/00.hello/ref/sparc/linux/simple-timing-ruby/config.ini @@ -5,7 +5,7 @@ dummy=0 [system] type=System -children=cpu membus physmem +children=cpu physmem ruby mem_mode=atomic physmem=system.physmem @@ -13,7 +13,7 @@ physmem=system.physmem type=TimingSimpleCPU children=dtb itb tracer workload checker=Null -clock=500 +clock=1 cpu_id=0 defer_registration=false do_checkpoint_insts=true @@ -32,8 +32,8 @@ progress_interval=0 system=system tracer=system.cpu.tracer workload=system.cpu.workload -dcache_port=system.membus.port[2] -icache_port=system.membus.port[1] +dcache_port=system.ruby.network.topology.ext_links0.ext_node.sequencer.port[1] +icache_port=system.ruby.network.topology.ext_links0.ext_node.sequencer.port[0] [system.cpu.dtb] type=SparcTLB @@ -54,7 +54,7 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/regression/test-progs/hello/bin/sparc/linux/hello +executable=tests/test-progs/hello/bin/sparc/linux/hello gid=100 input=cin max_stack_size=67108864 @@ -65,30 +65,170 @@ simpoint=0 system=system uid=100 -[system.membus] -type=Bus -block_size=64 -bus_id=0 -clock=1000 -header_cycles=1 -responder_set=false -width=64 -port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port - [system.physmem] -type=RubyMemory -clock=1 -config_file=build/SPARC_SE/tests/fast/quick/00.hello/sparc/linux/simple-timing-ruby/ruby.config -debug=false -debug_file=ruby.debug +type=PhysicalMemory file= -latency=30000 +latency=30 latency_var=0 null=false -num_cpus=1 -phase=0 range=0:134217727 -stats_file=ruby.stats zero=false -port=system.membus.port[0] +port=system.ruby.network.topology.ext_links0.ext_node.sequencer.physMemPort + +[system.ruby] +type=RubySystem +children=debug network profiler tracer +block_size_bytes=64 +clock=1 +debug=system.ruby.debug +mem_size=134217728 +network=system.ruby.network +profiler=system.ruby.profiler +random_seed=1234 +randomization=false +stats_filename=ruby.stats +tech_nm=45 +tracer=system.ruby.tracer + +[system.ruby.debug] +type=RubyDebug +filter_string=none +output_filename=none +protocol_trace=false +start_time=1 +verbosity_string=none + +[system.ruby.network] +type=SimpleNetwork +children=topology +adaptive_routing=true +buffer_size=0 +control_msg_size=8 +endpoint_bandwidth=10000 +link_latency=1 +number_of_virtual_networks=10 +topology=system.ruby.network.topology + +[system.ruby.network.topology] +type=Topology +children=ext_links0 ext_links1 int_links0 int_links1 +ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1 +int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1 +num_int_nodes=3 +print_config=false + +[system.ruby.network.topology.ext_links0] +type=ExtLink +children=ext_node +bw_multiplier=64 +ext_node=system.ruby.network.topology.ext_links0.ext_node +int_node=0 +latency=1 +weight=1 + +[system.ruby.network.topology.ext_links0.ext_node] +type=L1Cache_Controller +children=sequencer +buffer_size=0 +cacheMemory=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache +cache_response_latency=12 +issue_latency=2 +number_of_TBEs=256 +recycle_latency=10 +sequencer=system.ruby.network.topology.ext_links0.ext_node.sequencer +transitions_per_cycle=32 +version=0 + +[system.ruby.network.topology.ext_links0.ext_node.sequencer] +type=RubySequencer +children=icache +dcache=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache +deadlock_threshold=500000 +icache=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache +max_outstanding_requests=16 +physmem=system.physmem +using_ruby_tester=false +version=0 +physMemPort=system.physmem.port[0] +port=system.cpu.icache_port system.cpu.dcache_port + +[system.ruby.network.topology.ext_links0.ext_node.sequencer.icache] +type=RubyCache +assoc=2 +latency=3 +replacement_policy=PSEUDO_LRU +size=256 + +[system.ruby.network.topology.ext_links1] +type=ExtLink +children=ext_node +bw_multiplier=64 +ext_node=system.ruby.network.topology.ext_links1.ext_node +int_node=1 +latency=1 +weight=1 + +[system.ruby.network.topology.ext_links1.ext_node] +type=Directory_Controller +children=directory memBuffer +buffer_size=0 +directory=system.ruby.network.topology.ext_links1.ext_node.directory +directory_latency=12 +memBuffer=system.ruby.network.topology.ext_links1.ext_node.memBuffer +number_of_TBEs=256 +recycle_latency=10 +transitions_per_cycle=32 +version=0 + +[system.ruby.network.topology.ext_links1.ext_node.directory] +type=RubyDirectoryMemory +size=134217728 +version=0 + +[system.ruby.network.topology.ext_links1.ext_node.memBuffer] +type=RubyMemoryControl +bank_bit_0=8 +bank_busy_time=11 +bank_queue_size=12 +banks_per_rank=8 +basic_bus_busy_time=2 +dimm_bit_0=12 +dimms_per_channel=2 +mem_bus_cycle_multiplier=10 +mem_ctl_latency=12 +mem_fixed_delay=0 +mem_random_arbitrate=0 +rank_bit_0=11 +rank_rank_delay=1 +ranks_per_dimm=2 +read_write_delay=2 +refresh_period=1560 +tFaw=0 +version=0 + +[system.ruby.network.topology.int_links0] +type=IntLink +bw_multiplier=16 +latency=1 +node_a=0 +node_b=2 +weight=1 + +[system.ruby.network.topology.int_links1] +type=IntLink +bw_multiplier=16 +latency=1 +node_a=1 +node_b=2 +weight=1 + +[system.ruby.profiler] +type=RubyProfiler +all_instructions=false +hot_lines=false +num_of_sequencers=1 + +[system.ruby.tracer] +type=RubyTracer +warmup_length=100000 diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-timing-ruby/ruby.stats b/tests/quick/00.hello/ref/sparc/linux/simple-timing-ruby/ruby.stats index d69152c37..2464ac2ec 100644 --- a/tests/quick/00.hello/ref/sparc/linux/simple-timing-ruby/ruby.stats +++ b/tests/quick/00.hello/ref/sparc/linux/simple-timing-ruby/ruby.stats @@ -2,73 +2,23 @@ ================ Begin RubySystem Configuration Print ================ RubySystem config: - random_seed: 229628 + random_seed: 1234 randomization: 0 tech_nm: 45 - freq_mhz: 3000 + cycle_period: 1 block_size_bytes: 64 block_size_bits: 6 - memory_size_bytes: 1073741824 - memory_size_bits: 30 -DMA_Controller config: DMAController_0 - version: 0 - buffer_size: 32 - dma_sequencer: DMASequencer_0 - number_of_TBEs: 128 - transitions_per_cycle: 32 -Directory_Controller config: DirectoryController_0 - version: 0 - buffer_size: 32 - directory_latency: 6 - directory_name: DirectoryMemory_0 - memory_controller_name: MemoryControl_0 - memory_latency: 158 - number_of_TBEs: 128 - recycle_latency: 10 - to_mem_ctrl_latency: 1 - transitions_per_cycle: 32 -L1Cache_Controller config: L1CacheController_0 - version: 0 - buffer_size: 32 - cache: l1u_0 - cache_response_latency: 12 - issue_latency: 2 - number_of_TBEs: 128 - sequencer: Sequencer_0 - transitions_per_cycle: 32 -Cache config: l1u_0 - controller: L1CacheController_0 - cache_associativity: 8 - num_cache_sets_bits: 2 - num_cache_sets: 4 - cache_set_size_bytes: 256 - cache_set_size_Kbytes: 0.25 - cache_set_size_Mbytes: 0.000244141 - cache_size_bytes: 2048 - cache_size_Kbytes: 2 - cache_size_Mbytes: 0.00195312 + memory_size_bytes: 134217728 + memory_size_bits: 27 DirectoryMemory Global Config: number of directory memories: 1 - total memory size bytes: 1073741824 - total memory size bits: 30 -DirectoryMemory module config: DirectoryMemory_0 - controller: DirectoryController_0 - version: 0 - memory_bits: 30 - memory_size_bytes: 1073741824 - memory_size_Kbytes: 1.04858e+06 - memory_size_Mbytes: 1024 - memory_size_Gbytes: 1 -Seqeuncer config: Sequencer_0 - controller: L1CacheController_0 - version: 0 - max_outstanding_requests: 16 - deadlock_threshold: 500000 + total memory size bytes: 134217728 + total memory size bits: 27 Network Configuration --------------------- network: SIMPLE_NETWORK -topology: theTopology +topology: virtual_net_0: active, ordered virtual_net_1: active, ordered @@ -76,25 +26,11 @@ virtual_net_2: active, ordered virtual_net_3: inactive virtual_net_4: active, ordered virtual_net_5: active, ordered +virtual_net_6: inactive +virtual_net_7: inactive +virtual_net_8: inactive +virtual_net_9: inactive ---- Begin Topology Print --- - -Topology print ONLY indicates the _NETWORK_ latency between two machines -It does NOT include the latency within the machines - -L1Cache-0 Network Latencies - L1Cache-0 -> Directory-0 net_lat: 7 - L1Cache-0 -> DMA-0 net_lat: 7 - -Directory-0 Network Latencies - Directory-0 -> L1Cache-0 net_lat: 7 - Directory-0 -> DMA-0 net_lat: 7 - -DMA-0 Network Latencies - DMA-0 -> L1Cache-0 net_lat: 7 - DMA-0 -> Directory-0 net_lat: 7 - ---- End Topology Print --- Profiler Configuration ---------------------- @@ -103,7 +39,7 @@ periodic_stats_period: 1000000 ================ End RubySystem Configuration Print ================ -Real time: Jul/06/2009 11:11:36 +Real time: Jan/21/2010 11:30:49 Profiler Stats -------------- @@ -112,123 +48,52 @@ Elapsed_time_in_minutes: 0.0166667 Elapsed_time_in_hours: 0.000277778 Elapsed_time_in_days: 1.15741e-05 -Virtual_time_in_seconds: 0.71 -Virtual_time_in_minutes: 0.0118333 -Virtual_time_in_hours: 0.000197222 -Virtual_time_in_days: 0.000197222 +Virtual_time_in_seconds: 0.28 +Virtual_time_in_minutes: 0.00466667 +Virtual_time_in_hours: 7.77778e-05 +Virtual_time_in_days: 3.24074e-06 -Ruby_current_time: 20314001 -Ruby_start_time: 1 -Ruby_cycles: 20314000 +Ruby_current_time: 253364 +Ruby_start_time: 0 +Ruby_cycles: 253364 -mbytes_resident: 145.32 -mbytes_total: 1330.48 -resident_ratio: 0.109227 +mbytes_resident: 34.3555 +mbytes_total: 34.5312 +resident_ratio: 0.995136 Total_misses: 0 total_misses: 0 [ 0 ] user_misses: 0 [ 0 ] supervisor_misses: 0 [ 0 ] -instruction_executed: 1 [ 1 ] -ruby_cycles_executed: 20314001 [ 20314001 ] -cycles_per_instruction: 2.0314e+07 [ 2.0314e+07 ] -misses_per_thousand_instructions: 0 [ 0 ] +ruby_cycles_executed: 253365 [ 253365 ] transactions_started: 0 [ 0 ] transactions_ended: 0 [ 0 ] -instructions_per_transaction: 0 [ 0 ] cycles_per_transaction: 0 [ 0 ] misses_per_transaction: 0 [ 0 ] -L1D_cache cache stats: - L1D_cache_total_misses: 0 - L1D_cache_total_demand_misses: 0 - L1D_cache_total_prefetches: 0 - L1D_cache_total_sw_prefetches: 0 - L1D_cache_total_hw_prefetches: 0 - L1D_cache_misses_per_transaction: 0 - L1D_cache_misses_per_instruction: 0 - L1D_cache_instructions_per_misses: NaN - - L1D_cache_request_size: [binsize: log2 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - -L1I_cache cache stats: - L1I_cache_total_misses: 0 - L1I_cache_total_demand_misses: 0 - L1I_cache_total_prefetches: 0 - L1I_cache_total_sw_prefetches: 0 - L1I_cache_total_hw_prefetches: 0 - L1I_cache_misses_per_transaction: 0 - L1I_cache_misses_per_instruction: 0 - L1I_cache_instructions_per_misses: NaN - - L1I_cache_request_size: [binsize: log2 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - -L2_cache cache stats: - L2_cache_total_misses: 0 - L2_cache_total_demand_misses: 0 - L2_cache_total_prefetches: 0 - L2_cache_total_sw_prefetches: 0 - L2_cache_total_hw_prefetches: 0 - L2_cache_misses_per_transaction: 0 - L2_cache_misses_per_instruction: 0 - L2_cache_instructions_per_misses: NaN - - L2_cache_request_size: [binsize: log2 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - - -Memory control: - memory_total_requests: 1262 - memory_reads: 647 - memory_writes: 615 - memory_refreshes: 12114 - memory_total_request_delays: 1568 - memory_delays_per_request: 1.24247 - memory_delays_in_input_queue: 615 - memory_delays_behind_head_of_bank_queue: 1 - memory_delays_stalled_at_head_of_bank_queue: 952 - memory_stalls_for_bank_busy: 261 - memory_stalls_for_random_busy: 0 - memory_stalls_for_anti_starvation: 0 - memory_stalls_for_arbitration: 39 - memory_stalls_for_bus: 627 - memory_stalls_for_tfaw: 0 - memory_stalls_for_read_write_turnaround: 25 - memory_stalls_for_read_read_turnaround: 0 - accesses_per_bank: 90 30 28 38 62 36 45 47 17 28 13 18 28 22 6 14 12 27 39 28 18 42 13 12 41 72 76 92 62 79 86 41 Busy Controller Counts: L1Cache-0:0 Directory-0:0 -DMA-0:0 + Busy Bank Count:0 -L1TBE_usage: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] -L2TBE_usage: [binsize: 1 max: 1 count: 1262 average: 0.487322 | standard deviation: 0.500594 | 647 615 ] -StopTable_usage: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] -sequencer_requests_outstanding: [binsize: 1 max: 1 count: 6772 average: 1 | standard deviation: 0 | 0 6772 ] -store_buffer_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] -unique_blocks_in_store_buffer: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +sequencer_requests_outstanding: [binsize: 1 max: 1 count: 6773 average: 1 | standard deviation: 0 | 0 6773 ] All Non-Zero Cycle Demand Cache Accesses ---------------------------------------- -miss_latency: [binsize: 2 max: 270 count: 6772 average: 18.3048 | standard deviation: 50.462 | 0 6125 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 30 0 0 0 0 13 0 0 0 0 558 0 0 0 0 5 0 0 0 0 17 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 21 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_1: [binsize: 2 max: 270 count: 5383 average: 13.4873 | standard deviation: 43.0215 | 0 5021 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 0 0 0 0 3 0 0 0 0 316 0 0 0 0 4 0 0 0 0 10 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 11 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_2: [binsize: 2 max: 260 count: 716 average: 41.8128 | standard deviation: 72.7521 | 0 549 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7 0 0 0 0 7 0 0 0 0 141 0 0 0 0 1 0 0 0 0 4 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_3: [binsize: 2 max: 260 count: 673 average: 31.8276 | standard deviation: 65.1506 | 0 555 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7 0 0 0 0 3 0 0 0 0 101 0 0 0 0 0 0 0 0 0 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_L2Miss: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency: [binsize: 2 max: 371 count: 6772 average: 36.4135 | standard deviation: 69.5949 | 0 5483 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 2 4 2 2 10 2 309 224 133 323 144 9 3 1 0 0 11 11 1 16 4 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 1 25 14 6 15 3 1 1 1 0 0 1 1 0 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ] +miss_latency_1: [binsize: 2 max: 285 count: 5383 average: 26.3539 | standard deviation: 60.2129 | 0 4668 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 1 1 0 5 2 172 118 76 168 91 3 1 1 0 0 8 9 0 10 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 18 3 4 10 1 0 0 1 0 0 1 1 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_2: [binsize: 2 max: 285 count: 716 average: 98.7235 | standard deviation: 87.4535 | 0 321 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 3 1 2 3 0 110 62 31 116 36 4 1 0 0 0 1 0 1 6 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 5 2 2 3 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_3: [binsize: 2 max: 371 count: 673 average: 50.584 | standard deviation: 80.4924 | 0 494 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 27 44 26 39 17 2 1 0 0 0 2 2 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 9 0 2 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ] All Non-Zero Cycle SW Prefetch Requests ------------------------------------ prefetch_latency: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] prefetch_latency_L2Miss:[binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] -multicast_retries: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] -gets_mask_prediction_count: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] -getx_mask_prediction_count: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] -explicit_training_mask: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - Request vs. RubySystem State Profile -------------------------------- @@ -237,104 +102,156 @@ filter_action: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN Message Delayed Cycles ---------------------- -Total_delay_cycles: [binsize: 1 max: 0 count: 1262 average: 0 | standard deviation: 0 | 1262 ] -Total_nonPF_delay_cycles: [binsize: 1 max: 0 count: 1262 average: 0 | standard deviation: 0 | 1262 ] +Total_delay_cycles: [binsize: 1 max: 0 count: 2574 average: 0 | standard deviation: 0 | 2574 ] +Total_nonPF_delay_cycles: [binsize: 1 max: 0 count: 2574 average: 0 | standard deviation: 0 | 2574 ] virtual_network_0_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - virtual_network_1_delay_cycles: [binsize: 1 max: 0 count: 647 average: 0 | standard deviation: 0 | 647 ] - virtual_network_2_delay_cycles: [binsize: 1 max: 0 count: 615 average: 0 | standard deviation: 0 | 615 ] + virtual_network_1_delay_cycles: [binsize: 1 max: 0 count: 1289 average: 0 | standard deviation: 0 | 1289 ] + virtual_network_2_delay_cycles: [binsize: 1 max: 0 count: 1285 average: 0 | standard deviation: 0 | 1285 ] virtual_network_3_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] virtual_network_4_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] virtual_network_5_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + virtual_network_6_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + virtual_network_7_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + virtual_network_8_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + virtual_network_9_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] Resource Usage -------------- page_size: 4096 user_time: 0 system_time: 0 -page_reclaims: 37948 -page_faults: 0 +page_reclaims: 7494 +page_faults: 2200 swaps: 0 block_inputs: 0 -block_outputs: 48 +block_outputs: 0 Network Stats ------------- switch_0_inlinks: 2 switch_0_outlinks: 2 -links_utilized_percent_switch_0: 0.00019414 - links_utilized_percent_switch_0_link_0: 7.76558e-05 bw: 640000 base_latency: 1 - links_utilized_percent_switch_0_link_1: 0.000310623 bw: 160000 base_latency: 1 +links_utilized_percent_switch_0: 0.158621 + links_utilized_percent_switch_0_link_0: 0.0635745 bw: 640000 base_latency: 1 + links_utilized_percent_switch_0_link_1: 0.253667 bw: 160000 base_latency: 1 - outgoing_messages_switch_0_link_0_Response_Data: 647 5176 [ 0 647 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_0_Writeback_Control: 615 4920 [ 0 0 615 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Control: 647 5176 [ 647 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Data: 615 4920 [ 615 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_0_Response_Data: 1289 92808 [ 0 1289 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_0_Writeback_Control: 1285 10280 [ 0 0 1285 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Control: 1289 10312 [ 1289 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Data: 1285 92520 [ 1285 0 0 0 0 0 0 0 0 0 ] base_latency: 1 switch_1_inlinks: 2 switch_1_outlinks: 2 -links_utilized_percent_switch_1: 0.00019414 - links_utilized_percent_switch_1_link_0: 7.76558e-05 bw: 640000 base_latency: 1 - links_utilized_percent_switch_1_link_1: 0.000310623 bw: 160000 base_latency: 1 +links_utilized_percent_switch_1: 0.158857 + links_utilized_percent_switch_1_link_0: 0.0634167 bw: 640000 base_latency: 1 + links_utilized_percent_switch_1_link_1: 0.254298 bw: 160000 base_latency: 1 - outgoing_messages_switch_1_link_0_Control: 647 5176 [ 647 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_0_Data: 615 4920 [ 615 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_Response_Data: 647 5176 [ 0 647 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_Writeback_Control: 615 4920 [ 0 0 615 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_Control: 1289 10312 [ 1289 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_Data: 1285 92520 [ 1285 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Response_Data: 1289 92808 [ 0 1289 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Writeback_Control: 1285 10280 [ 0 0 1285 0 0 0 0 0 0 0 ] base_latency: 1 switch_2_inlinks: 2 switch_2_outlinks: 2 -links_utilized_percent_switch_2: 0 - links_utilized_percent_switch_2_link_0: 0 bw: 640000 base_latency: 1 - links_utilized_percent_switch_2_link_1: 0 bw: 160000 base_latency: 1 - - -switch_3_inlinks: 3 -switch_3_outlinks: 3 -links_utilized_percent_switch_3: 0.000207082 - links_utilized_percent_switch_3_link_0: 0.000310623 bw: 160000 base_latency: 1 - links_utilized_percent_switch_3_link_1: 0.000310623 bw: 160000 base_latency: 1 - links_utilized_percent_switch_3_link_2: 0 bw: 160000 base_latency: 1 - - outgoing_messages_switch_3_link_0_Response_Data: 647 5176 [ 0 647 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_0_Writeback_Control: 615 4920 [ 0 0 615 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_1_Control: 647 5176 [ 647 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_1_Data: 615 4920 [ 615 0 0 0 0 0 ] base_latency: 1 - - --- DMA --- +links_utilized_percent_switch_2: 0.253982 + links_utilized_percent_switch_2_link_0: 0.254298 bw: 160000 base_latency: 1 + links_utilized_percent_switch_2_link_1: 0.253667 bw: 160000 base_latency: 1 + + outgoing_messages_switch_2_link_0_Response_Data: 1289 92808 [ 0 1289 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_0_Writeback_Control: 1285 10280 [ 0 0 1285 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Control: 1289 10312 [ 1289 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Data: 1285 92520 [ 1285 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + +Cache Stats: system.ruby.network.topology.ext_links0.ext_node.sequencer.icache + system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_misses: 1289 + system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_demand_misses: 1289 + system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_prefetches: 0 + system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_sw_prefetches: 0 + system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_hw_prefetches: 0 + system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_misses_per_transaction: inf + + system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_type_LD: 30.6439% + system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_type_ST: 13.8867% + system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_type_IFETCH: 55.4694% + + system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_access_mode_type_SupervisorMode: 1289 100% + system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_size: [binsize: 1 max: 8 count: 1289 average: 5.1249 | standard deviation: 2.01759 | 0 50 2 0 836 0 0 0 401 ] + + --- L1Cache 0 --- - Event Counts - -ReadRequest 0 -WriteRequest 0 -Data 0 -Ack 0 +Load 716 +Ifetch 5383 +Store 673 +Data 1289 +Fwd_GETX 0 +Inv 0 +Replacement 1285 +Writeback_Ack 1285 +Writeback_Nack 0 - Transitions - -READY ReadRequest 0 <-- -READY WriteRequest 0 <-- +I Load 395 +I Ifetch 715 +I Store 179 +I Inv 0 <-- +I Replacement 0 <-- -BUSY_RD Data 0 <-- +II Writeback_Nack 0 <-- -BUSY_WR Ack 0 <-- +M Load 321 +M Ifetch 4668 +M Store 494 +M Fwd_GETX 0 <-- +M Inv 0 <-- +M Replacement 1285 + +MI Fwd_GETX 0 <-- +MI Inv 0 <-- +MI Writeback_Ack 1285 + +IS Data 1110 + +IM Data 179 + +Memory controller: system.ruby.network.topology.ext_links1.ext_node.memBuffer: + memory_total_requests: 2574 + memory_reads: 1289 + memory_writes: 1285 + memory_refreshes: 528 + memory_total_request_delays: 3552 + memory_delays_per_request: 1.37995 + memory_delays_in_input_queue: 1284 + memory_delays_behind_head_of_bank_queue: 3 + memory_delays_stalled_at_head_of_bank_queue: 2265 + memory_stalls_for_bank_busy: 847 + memory_stalls_for_random_busy: 0 + memory_stalls_for_anti_starvation: 0 + memory_stalls_for_arbitration: 88 + memory_stalls_for_bus: 1292 + memory_stalls_for_tfaw: 0 + memory_stalls_for_read_write_turnaround: 38 + memory_stalls_for_read_read_turnaround: 0 + accesses_per_bank: 166 40 36 48 109 42 63 241 50 34 16 26 60 64 38 46 30 88 202 144 40 58 22 20 60 120 136 125 84 134 166 66 - --- Directory --- + --- Directory 0 --- - Event Counts - -GETX 647 +GETX 1289 GETS 0 -PUTX 615 +PUTX 1285 PUTX_NotOwner 0 DMA_READ 0 DMA_WRITE 0 -Memory_Data 647 -Memory_Ack 615 +Memory_Data 1289 +Memory_Ack 1285 - Transitions - -I GETX 647 +I GETX 1289 I PUTX_NotOwner 0 <-- I DMA_READ 0 <-- I DMA_WRITE 0 <-- M GETX 0 <-- -M PUTX 615 +M PUTX 1285 M PUTX_NotOwner 0 <-- M DMA_READ 0 <-- M DMA_WRITE 0 <-- @@ -345,15 +262,19 @@ M_DRD PUTX 0 <-- M_DWR GETX 0 <-- M_DWR PUTX 0 <-- +M_DWRI GETX 0 <-- M_DWRI Memory_Ack 0 <-- +M_DRDI GETX 0 <-- +M_DRDI Memory_Ack 0 <-- + IM GETX 0 <-- IM GETS 0 <-- IM PUTX 0 <-- IM PUTX_NotOwner 0 <-- IM DMA_READ 0 <-- IM DMA_WRITE 0 <-- -IM Memory_Data 647 +IM Memory_Data 1289 MI GETX 0 <-- MI GETS 0 <-- @@ -361,7 +282,7 @@ MI PUTX 0 <-- MI PUTX_NotOwner 0 <-- MI DMA_READ 0 <-- MI DMA_WRITE 0 <-- -MI Memory_Ack 615 +MI Memory_Ack 1285 ID GETX 0 <-- ID GETS 0 <-- @@ -379,39 +300,3 @@ ID_W DMA_READ 0 <-- ID_W DMA_WRITE 0 <-- ID_W Memory_Ack 0 <-- - --- L1Cache --- - - Event Counts - -Load 716 -Ifetch 5383 -Store 673 -Data 647 -Fwd_GETX 0 -Inv 0 -Replacement 615 -Writeback_Ack 615 -Writeback_Nack 0 - - - Transitions - -I Load 167 -I Ifetch 362 -I Store 118 -I Inv 0 <-- -I Replacement 0 <-- - -II Writeback_Nack 0 <-- - -M Load 549 -M Ifetch 5021 -M Store 555 -M Fwd_GETX 0 <-- -M Inv 0 <-- -M Replacement 615 - -MI Fwd_GETX 0 <-- -MI Inv 0 <-- -MI Writeback_Ack 615 - -IS Data 529 - -IM Data 118 - diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-timing-ruby/simerr b/tests/quick/00.hello/ref/sparc/linux/simple-timing-ruby/simerr index 187d1a0ac..eabe42249 100755 --- a/tests/quick/00.hello/ref/sparc/linux/simple-timing-ruby/simerr +++ b/tests/quick/00.hello/ref/sparc/linux/simple-timing-ruby/simerr @@ -1,23 +1,3 @@ -["-r", "tests/configs/../../src/mem/ruby/config/MI_example-homogeneous.rb", "-p", "1", "-m", "1", "-s", "1024"] -print config: 1 -Creating new MessageBuffer for 0 0 -Creating new MessageBuffer for 0 1 -Creating new MessageBuffer for 0 2 -Creating new MessageBuffer for 0 3 -Creating new MessageBuffer for 0 4 -Creating new MessageBuffer for 0 5 -Creating new MessageBuffer for 1 0 -Creating new MessageBuffer for 1 1 -Creating new MessageBuffer for 1 2 -Creating new MessageBuffer for 1 3 -Creating new MessageBuffer for 1 4 -Creating new MessageBuffer for 1 5 -Creating new MessageBuffer for 2 0 -Creating new MessageBuffer for 2 1 -Creating new MessageBuffer for 2 2 -Creating new MessageBuffer for 2 3 -Creating new MessageBuffer for 2 4 -Creating new MessageBuffer for 2 5 warn: Sockets disabled, not accepting gdb connections For more information see: http://www.m5sim.org/warn/d946bea6 hack: be nice to actually delete the event here diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-timing-ruby/simout b/tests/quick/00.hello/ref/sparc/linux/simple-timing-ruby/simout index 1430a9707..e4e5995ba 100755 --- a/tests/quick/00.hello/ref/sparc/linux/simple-timing-ruby/simout +++ b/tests/quick/00.hello/ref/sparc/linux/simple-timing-ruby/simout @@ -5,12 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jul 6 2009 11:07:18 -M5 revision d3635cac686a 6289 default ruby_refs.diff qtip tip -M5 started Jul 6 2009 11:11:35 -M5 executing on maize +M5 compiled Jan 21 2010 11:29:25 +M5 revision a2fac757fb31+ 6860+ default qtip brad/rubycfg_orion_update tip +M5 started Jan 21 2010 11:30:48 +M5 executing on svvint07 command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/00.hello/sparc/linux/simple-timing-ruby -re tests/run.py build/SPARC_SE/tests/fast/quick/00.hello/sparc/linux/simple-timing-ruby -Global frequency set at 1000000000000 ticks per second - Debug: Adding to filter: 'q' (Queue) +Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... -Hello World!Exiting @ tick 20314000 because target called exit() +Hello World!Exiting @ tick 253364 because target called exit() diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt b/tests/quick/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt index bca92ee68..aa77d6897 100644 --- a/tests/quick/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt +++ b/tests/quick/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt @@ -1,16 +1,16 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 3344 # Simulator instruction rate (inst/s) -host_mem_usage 1362412 # Number of bytes of host memory used -host_seconds 1.60 # Real time elapsed on the host -host_tick_rate 12720005 # Simulator tick rate (ticks/s) -sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 59331 # Simulator instruction rate (inst/s) +host_mem_usage 347024 # Number of bytes of host memory used +host_seconds 0.09 # Real time elapsed on the host +host_tick_rate 2815062 # Simulator tick rate (ticks/s) +sim_freq 1000000000 # Frequency of simulated ticks sim_insts 5340 # Number of instructions simulated -sim_seconds 0.000020 # Number of seconds simulated -sim_ticks 20314000 # Number of ticks simulated +sim_seconds 0.000253 # Number of seconds simulated +sim_ticks 253364 # Number of ticks simulated system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 40628 # number of cpu cycles simulated +system.cpu.numCycles 253364 # number of cpu cycles simulated system.cpu.num_insts 5340 # Number of instructions executed system.cpu.num_refs 1402 # Number of memory references system.cpu.workload.PROG:num_syscalls 11 # Number of system calls |