diff options
Diffstat (limited to 'tests/quick/00.hello/ref/x86/linux/simple-timing-ruby')
4 files changed, 61 insertions, 34 deletions
diff --git a/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/config.ini b/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/config.ini index 5985e429a..d0926d8e6 100644 --- a/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/config.ini +++ b/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/config.ini @@ -10,6 +10,13 @@ type=System children=cpu dir_cntrl0 l1_cntrl0 physmem ruby mem_mode=timing physmem=system.physmem +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 [system.cpu] type=TimingSimpleCPU @@ -56,7 +63,7 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/regression/test-progs/hello/bin/x86/linux/hello +executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/x86/linux/hello gid=100 input=cin max_stack_size=67108864 @@ -147,6 +154,7 @@ tracer=system.ruby.tracer [system.ruby.cpu_ruby_ports] type=RubySequencer children=dcache +access_phys_mem=true dcache=system.ruby.cpu_ruby_ports.dcache deadlock_threshold=500000 icache=system.ruby.cpu_ruby_ports.dcache diff --git a/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/ruby.stats b/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/ruby.stats index adfa92f7c..27560c564 100644 --- a/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/ruby.stats +++ b/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/ruby.stats @@ -34,7 +34,7 @@ periodic_stats_period: 1000000 ================ End RubySystem Configuration Print ================ -Real time: Feb/04/2011 03:47:05 +Real time: Feb/06/2011 20:48:09 Profiler Stats -------------- @@ -43,18 +43,18 @@ Elapsed_time_in_minutes: 0 Elapsed_time_in_hours: 0 Elapsed_time_in_days: 0 -Virtual_time_in_seconds: 0.19 -Virtual_time_in_minutes: 0.00316667 -Virtual_time_in_hours: 5.27778e-05 -Virtual_time_in_days: 2.19907e-06 +Virtual_time_in_seconds: 0.36 +Virtual_time_in_minutes: 0.006 +Virtual_time_in_hours: 0.0001 +Virtual_time_in_days: 4.16667e-06 Ruby_current_time: 276484 Ruby_start_time: 0 Ruby_cycles: 276484 -mbytes_resident: 38.8594 -mbytes_total: 233.992 -resident_ratio: 0.166088 +mbytes_resident: 36.707 +mbytes_total: 212.684 +resident_ratio: 0.172627 ruby_cycles_executed: [ 276485 ] @@ -71,8 +71,9 @@ All Non-Zero Cycle Demand Cache Accesses ---------------------------------------- miss_latency: [binsize: 2 max: 371 count: 8900 average: 30.0656 | standard deviation: 63.8436 | 0 7523 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 9 4 1 3 2 328 243 178 299 187 7 4 1 3 0 8 6 4 9 5 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 6 11 19 16 9 0 1 0 1 1 0 1 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 ] miss_latency_IFETCH: [binsize: 2 max: 369 count: 6910 average: 18.6938 | standard deviation: 50.1996 | 0 6287 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 2 2 0 1 0 158 125 57 116 102 5 3 0 2 0 8 5 3 4 4 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 2 2 3 8 6 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ] -miss_latency_LD: [binsize: 2 max: 293 count: 1056 average: 86.3144 | standard deviation: 89.2896 | 0 556 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 5 1 1 1 1 104 47 87 151 61 1 0 0 1 0 0 1 0 4 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 3 1 14 8 2 0 0 0 1 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_LD: [binsize: 2 max: 293 count: 1048 average: 86.792 | standard deviation: 89.333 | 0 549 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 5 1 1 1 1 103 47 87 151 61 1 0 0 1 0 0 1 0 4 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 3 1 14 8 2 0 0 0 1 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] miss_latency_ST: [binsize: 2 max: 371 count: 934 average: 50.6017 | standard deviation: 78.9939 | 0 680 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 2 1 0 1 1 66 71 34 32 24 1 1 1 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 8 2 0 1 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ] +miss_latency_RMW_Read: [binsize: 1 max: 169 count: 8 average: 23.75 | standard deviation: 58.6905 | 0 0 0 7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ] miss_latency_L1Cache: [binsize: 1 max: 3 count: 7523 average: 3 | standard deviation: 0 | 0 0 0 7523 ] miss_latency_Directory: [binsize: 2 max: 371 count: 1377 average: 177.934 | standard deviation: 21.7881 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 9 4 1 3 2 328 243 178 299 187 7 4 1 3 0 8 6 4 9 5 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 6 11 19 16 9 0 1 0 1 1 0 1 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 ] miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] @@ -87,10 +88,12 @@ miss_latency_dir_first_response_to_completion: [binsize: 1 max: 159 count: 1 ave imcomplete_dir_Times: 1376 miss_latency_IFETCH_L1Cache: [binsize: 1 max: 3 count: 6287 average: 3 | standard deviation: 0 | 0 0 0 6287 ] miss_latency_IFETCH_Directory: [binsize: 2 max: 369 count: 623 average: 177.067 | standard deviation: 19.4782 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 2 2 0 1 0 158 125 57 116 102 5 3 0 2 0 8 5 3 4 4 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 2 2 3 8 6 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ] -miss_latency_LD_L1Cache: [binsize: 1 max: 3 count: 556 average: 3 | standard deviation: 0 | 0 0 0 556 ] -miss_latency_LD_Directory: [binsize: 2 max: 293 count: 500 average: 178.96 | standard deviation: 22.8334 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 5 1 1 1 1 104 47 87 151 61 1 0 0 1 0 0 1 0 4 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 3 1 14 8 2 0 0 0 1 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_LD_L1Cache: [binsize: 1 max: 3 count: 549 average: 3 | standard deviation: 0 | 0 0 0 549 ] +miss_latency_LD_Directory: [binsize: 2 max: 293 count: 499 average: 178.98 | standard deviation: 22.8519 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 5 1 1 1 1 103 47 87 151 61 1 0 0 1 0 0 1 0 4 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 3 1 14 8 2 0 0 0 1 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] miss_latency_ST_L1Cache: [binsize: 1 max: 3 count: 680 average: 3 | standard deviation: 0 | 0 0 0 680 ] miss_latency_ST_Directory: [binsize: 2 max: 371 count: 254 average: 178.039 | standard deviation: 24.8377 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 2 1 0 1 1 66 71 34 32 24 1 1 1 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 8 2 0 1 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ] +miss_latency_RMW_Read_L1Cache: [binsize: 1 max: 3 count: 7 average: 3 | standard deviation: 0 | 0 0 0 7 ] +miss_latency_RMW_Read_Directory: [binsize: 1 max: 169 count: 1 average: 169 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ] All Non-Zero Cycle SW Prefetch Requests ------------------------------------ @@ -122,11 +125,11 @@ Resource Usage page_size: 4096 user_time: 0 system_time: 0 -page_reclaims: 11021 +page_reclaims: 10563 page_faults: 0 swaps: 0 block_inputs: 0 -block_outputs: 64 +block_outputs: 0 Network Stats ------------- @@ -177,17 +180,17 @@ Cache Stats: system.ruby.cpu_ruby_ports.dcache system.ruby.cpu_ruby_ports.dcache_total_sw_prefetches: 0 system.ruby.cpu_ruby_ports.dcache_total_hw_prefetches: 0 - system.ruby.cpu_ruby_ports.dcache_request_type_LD: 36.3108% - system.ruby.cpu_ruby_ports.dcache_request_type_ST: 18.4459% + system.ruby.cpu_ruby_ports.dcache_request_type_LD: 36.2382% + system.ruby.cpu_ruby_ports.dcache_request_type_ST: 18.5185% system.ruby.cpu_ruby_ports.dcache_request_type_IFETCH: 45.2433% system.ruby.cpu_ruby_ports.dcache_access_mode_type_SupervisorMode: 1377 100% --- L1Cache --- - Event Counts - -Load [1056 ] 1056 +Load [1048 ] 1048 Ifetch [6910 ] 6910 -Store [934 ] 934 +Store [942 ] 942 Data [1377 ] 1377 Fwd_GETX [0 ] 0 Inv [0 ] 0 @@ -196,17 +199,17 @@ Writeback_Ack [1373 ] 1373 Writeback_Nack [0 ] 0 - Transitions - -I Load [500 ] 500 +I Load [499 ] 499 I Ifetch [623 ] 623 -I Store [254 ] 254 +I Store [255 ] 255 I Inv [0 ] 0 I Replacement [0 ] 0 II Writeback_Nack [0 ] 0 -M Load [556 ] 556 +M Load [549 ] 549 M Ifetch [6287 ] 6287 -M Store [680 ] 680 +M Store [687 ] 687 M Fwd_GETX [0 ] 0 M Inv [0 ] 0 M Replacement [1373 ] 1373 @@ -218,9 +221,9 @@ MI Writeback_Nack [0 ] 0 MII Fwd_GETX [0 ] 0 -IS Data [1123 ] 1123 +IS Data [1122 ] 1122 -IM Data [254 ] 254 +IM Data [255 ] 255 Memory controller: system.dir_cntrl0.memBuffer: memory_total_requests: 2750 diff --git a/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/simout b/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/simout index 4e5806bd6..58b226717 100755 --- a/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/simout +++ b/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/simout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 4 2011 03:47:02 -M5 revision afcc4492291f 7892 default qbase qtip rubystatupdate.patch tip -M5 started Feb 4 2011 03:47:05 -M5 executing on burrito -command line: build/X86_SE/m5.opt -d build/X86_SE/tests/opt/quick/00.hello/x86/linux/simple-timing-ruby -re tests/run.py build/X86_SE/tests/opt/quick/00.hello/x86/linux/simple-timing-ruby +M5 compiled Feb 6 2011 15:49:25 +M5 revision b885adc82ab4+ 7924+ default tip qtip brad/regress_updates +M5 started Feb 6 2011 20:48:09 +M5 executing on SC2B0617 +command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-timing-ruby -re tests/run.py build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-timing-ruby Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Hello world! diff --git a/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt b/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt index 806c6c56a..10481a15c 100644 --- a/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt +++ b/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 106685 # Simulator instruction rate (inst/s) -host_mem_usage 239612 # Number of bytes of host memory used -host_seconds 0.09 # Real time elapsed on the host -host_tick_rate 3002497 # Simulator tick rate (ticks/s) +host_inst_rate 86745 # Simulator instruction rate (inst/s) +host_mem_usage 217792 # Number of bytes of host memory used +host_seconds 0.11 # Real time elapsed on the host +host_tick_rate 2441144 # Simulator tick rate (ticks/s) sim_freq 1000000000 # Frequency of simulated ticks sim_insts 9810 # Number of instructions simulated sim_seconds 0.000276 # Number of seconds simulated @@ -11,8 +11,24 @@ sim_ticks 276484 # Nu system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.numCycles 276484 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.num_busy_cycles 276484 # Number of busy cycles +system.cpu.num_conditional_control_insts 904 # number of instructions that are conditional controls +system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses +system.cpu.num_fp_insts 0 # number of float instructions +system.cpu.num_fp_register_reads 0 # number of times the floating registers were read +system.cpu.num_fp_register_writes 0 # number of times the floating registers were written +system.cpu.num_func_calls 0 # number of times a function call or return occured +system.cpu.num_idle_cycles 0 # Number of idle cycles system.cpu.num_insts 9810 # Number of instructions executed -system.cpu.num_refs 1990 # Number of memory references +system.cpu.num_int_alu_accesses 9715 # Number of integer alu accesses +system.cpu.num_int_insts 9715 # number of integer instructions +system.cpu.num_int_register_reads 26194 # number of times the integer registers were read +system.cpu.num_int_register_writes 9368 # number of times the integer registers were written +system.cpu.num_load_insts 1056 # Number of load instructions +system.cpu.num_mem_refs 1990 # number of memory refs +system.cpu.num_store_insts 934 # Number of store instructions system.cpu.workload.PROG:num_syscalls 11 # Number of system calls ---------- End Simulation Statistics ---------- |