diff options
Diffstat (limited to 'tests/quick/00.hello/ref/x86/linux')
| -rwxr-xr-x | tests/quick/00.hello/ref/x86/linux/simple-timing/simout | 14 | ||||
| -rw-r--r-- | tests/quick/00.hello/ref/x86/linux/simple-timing/stats.txt | 87 |
2 files changed, 47 insertions, 54 deletions
diff --git a/tests/quick/00.hello/ref/x86/linux/simple-timing/simout b/tests/quick/00.hello/ref/x86/linux/simple-timing/simout index 2a02cd35e..f57480110 100755 --- a/tests/quick/00.hello/ref/x86/linux/simple-timing/simout +++ b/tests/quick/00.hello/ref/x86/linux/simple-timing/simout @@ -1,3 +1,5 @@ +Redirecting stdout to build/X86_SE/tests/opt/quick/00.hello/x86/linux/simple-timing/simout +Redirecting stderr to build/X86_SE/tests/opt/quick/00.hello/x86/linux/simple-timing/simerr M5 Simulator System Copyright (c) 2001-2008 @@ -5,12 +7,12 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled May 2 2010 23:23:01 -M5 revision 674289bfe108 7074 default qtip tip updateauxvectorsstats.patch -M5 started May 2 2010 23:23:02 -M5 executing on burrito -command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-timing +M5 compiled Aug 26 2010 13:20:12 +M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix +M5 started Aug 26 2010 13:33:02 +M5 executing on zizzer +command line: build/X86_SE/m5.opt -d build/X86_SE/tests/opt/quick/00.hello/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/opt/quick/00.hello/x86/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Hello world! -Exiting @ tick 29813000 because target called exit() +Exiting @ tick 28768000 because target called exit() diff --git a/tests/quick/00.hello/ref/x86/linux/simple-timing/stats.txt b/tests/quick/00.hello/ref/x86/linux/simple-timing/stats.txt index cc8de12ad..eecf4ab78 100644 --- a/tests/quick/00.hello/ref/x86/linux/simple-timing/stats.txt +++ b/tests/quick/00.hello/ref/x86/linux/simple-timing/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 734670 # Simulator instruction rate (inst/s) -host_mem_usage 220588 # Number of bytes of host memory used -host_seconds 0.01 # Real time elapsed on the host -host_tick_rate 2255655595 # Simulator tick rate (ticks/s) +host_inst_rate 397795 # Simulator instruction rate (inst/s) +host_mem_usage 205892 # Number of bytes of host memory used +host_seconds 0.02 # Real time elapsed on the host +host_tick_rate 1184355702 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 9561 # Number of instructions simulated -sim_seconds 0.000030 # Number of seconds simulated -sim_ticks 29813000 # Number of ticks simulated +sim_seconds 0.000029 # Number of seconds simulated +sim_ticks 28768000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 1056 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency @@ -21,13 +21,13 @@ system.cpu.dcache.ReadReq_mshr_misses 55 # nu system.cpu.dcache.WriteReq_accesses 934 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 836 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 5488000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.104925 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 98 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 5194000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.104925 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 98 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_hits 855 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 4424000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.084582 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 79 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_miss_latency 4187000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.084582 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 79 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.avg_refs 13.850746 # Average number of references to valid blocks. @@ -39,37 +39,37 @@ system.cpu.dcache.cache_copies 0 # nu system.cpu.dcache.demand_accesses 1990 # number of demand (read+write) accesses system.cpu.dcache.demand_avg_miss_latency 56000 # average overall miss latency system.cpu.dcache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency -system.cpu.dcache.demand_hits 1837 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 8568000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.076884 # miss rate for demand accesses -system.cpu.dcache.demand_misses 153 # number of demand (read+write) misses +system.cpu.dcache.demand_hits 1856 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 7504000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.067337 # miss rate for demand accesses +system.cpu.dcache.demand_misses 134 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 8109000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.076884 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 153 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_miss_latency 7102000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.067337 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 134 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.019841 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 81.267134 # Average occupied blocks per context +system.cpu.dcache.occ_%::0 0.019695 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 80.668870 # Average occupied blocks per context system.cpu.dcache.overall_accesses 1990 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 56000 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 1837 # number of overall hits -system.cpu.dcache.overall_miss_latency 8568000 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.076884 # miss rate for overall accesses -system.cpu.dcache.overall_misses 153 # number of overall misses +system.cpu.dcache.overall_hits 1856 # number of overall hits +system.cpu.dcache.overall_miss_latency 7504000 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.067337 # miss rate for overall accesses +system.cpu.dcache.overall_misses 134 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 8109000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.076884 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 153 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_miss_latency 7102000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.067337 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 134 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.sampled_refs 134 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 81.267134 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 80.668870 # Cycle average of tags in use system.cpu.dcache.total_refs 1856 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks @@ -105,8 +105,8 @@ system.cpu.icache.demand_mshr_misses 228 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.052030 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 106.557747 # Average occupied blocks per context +system.cpu.icache.occ_%::0 0.051447 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 105.363985 # Average occupied blocks per context system.cpu.icache.overall_accesses 6911 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 55815.789474 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 52815.789474 # average overall mshr miss latency @@ -124,7 +124,7 @@ system.cpu.icache.overall_mshr_uncacheable_misses 0 system.cpu.icache.replacements 0 # number of replacements system.cpu.icache.sampled_refs 228 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 106.557747 # Cycle average of tags in use +system.cpu.icache.tagsinuse 105.363985 # Cycle average of tags in use system.cpu.icache.total_refs 6683 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks @@ -148,18 +148,9 @@ system.cpu.l2cache.ReadReq_misses 282 # nu system.cpu.l2cache.ReadReq_mshr_miss_latency 11280000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 0.996466 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 282 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_accesses 19 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 52000 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 988000 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_misses 19 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 760000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_misses 19 # number of UpgradeReq MSHR misses system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.003802 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 0.003546 # Average number of references to valid blocks. system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked @@ -179,8 +170,8 @@ system.cpu.l2cache.demand_mshr_misses 361 # nu system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.003920 # Average percentage of cache occupancy -system.cpu.l2cache.occ_blocks::0 128.459536 # Average occupied blocks per context +system.cpu.l2cache.occ_%::0 0.004084 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 133.809342 # Average occupied blocks per context system.cpu.l2cache.overall_accesses 362 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency @@ -196,14 +187,14 @@ system.cpu.l2cache.overall_mshr_misses 361 # nu system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 263 # Sample count of references to valid blocks. +system.cpu.l2cache.sampled_refs 282 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 128.459536 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 133.809342 # Cycle average of tags in use system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 59626 # number of cpu cycles simulated +system.cpu.numCycles 57536 # number of cpu cycles simulated system.cpu.num_insts 9561 # Number of instructions executed system.cpu.num_refs 1990 # Number of memory references system.cpu.workload.PROG:num_syscalls 11 # Number of system calls |